System and method for probabilistic quadrature amplitude modulation (QAM)

Abstract

The invention relates to a system and method for probabilistic quadrature amplitude modulation (QAM). An apparatus may include: a transmitter; and one or more processors configured to: identify a code rate of a low density parity check (LDPC) code; receiving, by an LDPC encoder, a set of information bits and encoding the set of information bits using the code rate to generate a set of encoded bits and a set of parity bits; generating a bit array matrix from the set of encoded bits; discarding one or more parity bits from the set of parity bits to generate an array of parity bits having a size equal to the number of columns of the matrix; generating a bit array by cascading (1) one or more bit arrays selected from the matrix of bit arrays and (2) one or more bits corresponding to the one or more bit arrays selected from the parity bit array; and modulating the bit array by a modulator to generate modulated data.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of and priority to U.S. Provisional Patent Application No. 63 / 554,589, filed February 16, 2024, which is incorporated herein by reference in its entirety for all purposes. Technical Field

[0003] The present disclosure generally relates to systems and methods for improving the encoding / decoding process of a communication system and / or performing probability coded modulation / demodulation to improve the performance of quadrature amplitude modulation (QAM) through constellation shaping of the signal / code. Background Art

[0004] Error correction codes enable information data to be exchanged reliably between a transmitter communication system and a receiver communication system. The transmitter communication system encodes the information data to obtain a codeword. The codeword is the encoded information data. The transmitter communication system transmits the codeword to the receiver communication system. Due to noise in the communication channel, the transmission received by the receiver communication system may differ from the transmitted codeword. Encoding the information data allows a receiver communication system with appropriate decoding procedures to recover the information data from the received transmission even in the presence of such noise. For example, the transmitter communication system transmits parity bits to the receiver communication system. The parity bits allow the receiver communication system to verify whether the received transmission is a valid codeword and, if not, to correct errors in the transmission. In one approach, generating the parity bits involves a complex process. Summary of the Invention

[0005] In one aspect, the present disclosure provides an apparatus comprising: a transmitter and one or more processors, wherein the one or more processors are configured to: identify a code rate of a low-density parity-check (LDPC) code; receive a set of information bits by an LDPC encoder; encode the set of information bits by the LDPC encoder using the code rate to generate a set of coded bits and a set of parity bits; generate a bit array matrix from the set of coded bits; discard one or more parity bits from the set of parity bits to generate a parity bit array having a size equal to the number of columns of the matrix; generate a bit array by concatenating (1) one or more bit arrays selected from the bit array matrix and (2) one or more bits corresponding to the one or more bit arrays selected from the parity bit array; and modulate the bit array by a modulator to generate modulated data for transmission by the transmitter.

[0006] On the other hand, the present disclosure provides a method, which includes: identifying a code rate of a low-density parity-check (LDPC) code by one or more processors; receiving a set of information bits by an LDPC encoder; encoding the set of information bits by the LDPC encoder using the code rate to generate a set of coded bits and a set of parity bits; generating a bit array matrix from the set of coded bits; discarding one or more parity bits from the set of parity bits by the one or more processors to generate a parity bit array having a size equal to the number of columns of the matrix; generating a bit array by the one or more processors by cascading (1) one or more bit arrays selected from the bit array matrix and (2) one or more bits corresponding to the one or more bit arrays selected from the parity bit array; and modulating the bit array by a modulator to generate modulated data for transmission by the transmitter.

[0007] On the other hand, the present disclosure provides an apparatus comprising: a transmitter; and one or more processors configured to: identify a target code rate for encoding data; determine a code rate of a low-density parity-check (LDPC) code and a number of unshaped bits to encode the data at the target code rate; receive, by an LDPC encoder, the data comprising shaped bits generated by a shaping encoder and a set of unshaped bits of a size equal to the number, and encode the data using the code rate to generate an encoded bit matrix and a set of parity bits; discard one or more parity bits from the set of parity bits based on at least the number to generate a parity bit array; generate a bit array by concatenating (1) one or more bit arrays obtained from columns of the matrix and (2) one or more bits corresponding to the one or more bit arrays obtained from the parity bit array; and modulate, by the modulator, the bit array to generate modulated data for transmission by the transmitter. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The various objects, aspects, features and advantages of the present disclosure will become more apparent and better understood by referring to the detailed description taken in conjunction with the accompanying drawings, in which like reference characters identify corresponding elements throughout. In the drawings, like reference numerals generally indicate identical, functionally similar and / or structurally similar elements.

[0009] Figure 1 is a diagram depicting an example communication environment having a communication system in accordance with one or more embodiments.

[0010] Figure 2 is a schematic block diagram of a computing system according to an embodiment.

[0011] Figure 3A 、 Figure 3B and Figure 3CA diagram depicting an LDPC coded modulation system using a uniformly distributed QAM constellation and the information-theoretic limit of the uniformly distributed QAM constellation.

[0012] Figure 4A and Figure 4B is a diagram depicting geometric constellation shaping in accordance with one or more embodiments.

[0013] Figure 5A and Figure 5B is a diagram depicting probabilistic constellation shaping in accordance with one or more embodiments.

[0014] Figure 6A 、 Figure 6B and Figure 6C is a diagram depicting an example LDPC coded modulation system including a shaping encoder, an LDPC encoder, and / or a symbol mapper in accordance with one or more embodiments.

[0015] Figure 7 is a diagram depicting an example shaping code according to one or more embodiments.

[0016] Figure 8A 、 Figure 8B 、 Figure 8C and Figure 8D is a diagram depicting an example shaping code according to one or more embodiments.

[0017] Figure 9A 、 Figure 9B and Figure 9C is a graph depicting example simulation results using an LDPC coded modulation system in accordance with one or more embodiments.

[0018] Figure 10 is a diagram depicting an example LDPC coded demodulation system including a shaping decoder, an LDPC decoder, and / or a symbol demapper in accordance with one or more embodiments.

[0019] Figure 11 is a flowchart showing a method for encoding data using a shaping code and an LDPC code according to an embodiment.

[0020] Figure 12A and Figure 12B is a diagram depicting an example shaping code according to one or more embodiments.

[0021] Figure 13A and Figure 13B is a diagram depicting an example shaping code according to one or more embodiments.

[0022] Figure 14A and Figure 14B is a diagram depicting an example shaping code according to one or more embodiments.

[0023] Figure 15A and Figure 15B is a diagram depicting an example shaping code according to one or more embodiments.

[0024] Figure 16A and Figure 16B is a diagram depicting an example shaping code according to one or more embodiments.

[0025] The details of various embodiments of the methods and systems are set forth in the accompanying drawings and the description below. DETAILED DESCRIPTION

[0026] The following disclosure provides many different embodiments or examples for implementing the different features of the provided themes. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, a first feature that communicates with or is communicatively coupled to a second feature in the following description may include an embodiment in which the first feature directly communicates with or is directly coupled to the second feature, and may also include an embodiment in which an additional feature may be interposed between the first and second features so that the first feature indirectly communicates with or is indirectly coupled to the second feature. In addition, the disclosure may repeat reference numbers and / or letters in various examples. This repetition is for simplicity and clarity purposes and does not itself dictate the relationship between the various embodiments and / or configurations discussed.

[0027] refer to Figure 1 , which illustrates a diagram depicting an example communication environment 100 including communication systems (or communication devices) 105, 108 according to one or more embodiments. In one embodiment, the communication system 105 includes baseband circuitry 110 and transmitter circuitry 120, and the communication system 108 includes baseband circuitry 150 and receiver circuitry 140. In one aspect, the communication system 105 is considered a transmitter communication system, and the communication system 108 is considered a receiver communication system. These components operate together to exchange data (e.g., messages or frames) over a wireless medium. In one or more embodiments, these components are embodied as application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or any combination of these. In some embodiments, the communication systems 105, 108 include baseband circuitry 110 and transmitter circuitry 120. Figure 1 For example, each of the communication systems 105, 108 includes transceiver circuitry to allow two-way communication between the communication systems 105, 108 or with other communication systems. In some embodiments, each of the communication systems 105, 108 may have a Figure 2 The configuration of the computing system 2000 shown in FIG.

[0028] The baseband circuitry 110 of the communication system 105 is circuitry that generates baseband data 115 for transmission. Baseband data 115 includes information data (e.g., signal(s)) at a baseband frequency for transmission. In one approach, baseband circuitry 110 includes an encoder 130 that encodes the data and generates or outputs parity bits. A parity bit (or parity data) associated with a group of bits refers to an error detection code that indicates whether the total number of 1 bits in the group is even or odd. In one aspect, baseband circuitry 110 (or encoder 130) obtains a generator matrix or parity check matrix, or uses a previously generated generator matrix or previously generated parity check matrix, and encodes the information data by applying the generator matrix or parity check matrix to obtain a codeword. In some embodiments, baseband circuitry 110 stores one or more generator matrices or one or more parity check matrices that conform to any IEEE 802.11 standard for WLAN communication. Baseband circuitry 110 retrieves a stored generator matrix or a stored parity check matrix in response to detecting information data to be transmitted or in response to receiving an instruction to encode the information data. In one approach, baseband circuitry 110 generates parity bits based on a portion of the generator matrix or using the parity check matrix and appends the parity bits to the information bits to form a codeword. An information bit is any binary data input to an encoder to generate binary-encoded data based on binary input data. Baseband circuitry 110 generates baseband data 115 comprising a codeword for communication system 108 and provides baseband data 115 to transmitter circuitry 120.

[0029] Transmitter circuitry 120 of communication system 105 includes or corresponds to circuitry that receives baseband data 115 from baseband circuitry 110 and transmits a wireless signal 125 based on baseband data 115. In one configuration, transmitter circuitry 120 is coupled between baseband circuitry 110 and an antenna (not shown). In this configuration, transmitter circuitry 120 up-converts baseband data 115 from baseband circuitry 110 to a carrier signal to generate wireless signal 125 at an RF frequency (e.g., 10 MHz to 60 GHz), and transmits wireless signal 125 through the antenna.

[0030] Receiver circuitry 140 of communication system 108 is circuitry that receives wireless signal 125 from communication system 105 and obtains baseband data 145 from received wireless signal 125. In one configuration, receiver circuitry 140 is coupled between baseband circuitry 150 and an antenna (not shown). In this configuration, receiver circuitry 140 receives wireless signal 125 via the antenna and downconverts wireless signal 125 at an RF frequency according to a carrier signal to obtain baseband data 145 from wireless signal 125. Receiver circuitry 140 then provides baseband data 145 to baseband circuitry 150.

[0031] Baseband circuitry 150 of communication system 108 includes or corresponds to circuitry that receives baseband data 145 from receiver circuitry 140 and obtains information data from received baseband data 145. In one embodiment, baseband circuitry 150 includes a decoder 160 that extracts information and parity bits from baseband data 145. Decoder 160 decodes baseband data 145 to obtain information data generated by baseband circuitry 110 of communication system 105.

[0032] In some embodiments, each of baseband circuitry 110 (including encoder 130), transmitter circuitry 120, receiver circuitry 140, and baseband circuitry 150 (including decoder 160) may be implemented as one or more processors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or any combination thereof.

[0033] Figure 2 is a schematic block diagram of a computing system according to an embodiment. The illustrated example computing system 2000 includes one or more processors 2010 that communicate directly or indirectly with memory 2060 via a communication system 2040 (e.g., a bus), at least one network interface controller 2030 having a network interface port for connecting to a network (not shown), and other components, such as input / output ("I / O") components 2050. Typically, the processor(s) 2010 will execute instructions (or computer programs) received from memory. The illustrated processor(s) 2010 incorporate or are connected to cache memory 2020. In some examples, instructions are read from memory 2060 into cache memory 2020 and executed by the processor(s) 2010 from cache memory 2020. The computing system 2000 may not necessarily contain Figure 2 All of these components shown in the , and may contain Figure 2 Other components not shown.

[0034] In more detail, processor(s) 2010 may be any logic circuitry that processes instructions (e.g., instructions retrieved from memory 2060 or cache 2020). In many embodiments, processor(s) 2010 are microprocessor units or special-purpose processors. Computing device 2000 may be based on any processor or group of processors capable of operating as described herein. Processor(s) 2010 may be a single-core or multi-core processor(s). Processor(s) 2010 may be a plurality of different processors.

[0035] The memory 2060 may be any device suitable for storing computer-readable data. The memory 2060 may be a device having fixed storage or a device for reading removable storage media. Examples include all forms of volatile memory (e.g., RAM), nonvolatile memory, media and memory devices, semiconductor memory devices (e.g., EPROM, EEPROM, SDRAM, and flash memory devices), magnetic disks, magneto-optical disks, and optical disks (e.g., CD ROM, DVD-ROM, or The computing system 2000 may have any number of memory devices 2060 .

[0036] Cache memory 2020 is typically a form of computer memory placed near the processor(s) 2010 to achieve fast read times. In some embodiments, cache memory 2020 is part of the processor(s) 2010, or is on the same chip as the processor(s) 2010. In some embodiments, there are multiple levels of cache 2020, such as L2 and L3 cache layers.

[0037] The network interface controller 2030 manages data exchange via a network interface (sometimes referred to as a network interface port). The network interface controller 2030 handles the physical and data link layers of the OSI model for network communications. In some embodiments, some network interface controller tasks are handled by one or more of the processor(s) 2010. In some embodiments, the network interface controller 2030 is part of the processor 2010. In some embodiments, the computing system 2000 has multiple network interfaces controlled by a single controller 2030. In some embodiments, the computing system 2000 has multiple network interface controllers 2030. In some embodiments, each network interface is a connection point for a physical network link (e.g., a Cat-5 Ethernet link). In some embodiments, the network interface controller 2030 supports wireless network connections and the interface port is a wireless (e.g., radio) receiver or transmitter (e.g., for any of the IEEE 802.11 protocols, near field communication "NFC", Bluetooth, ANT, or any other wireless protocols). In some embodiments, the network interface controller 2030 implements one or more network protocols, such as Ethernet. Typically, the computing device 2000 exchanges data with other computing devices via a physical or wireless link through a network interface. The network interface can be linked directly to another device or linked to another device through an intermediate device (e.g., a network device that connects the computing device 2000 to a data network (e.g., the Internet), such as a hub, bridge, switch, or router).

[0038] The computing system 2000 may include, or provide an interface for, one or more input or output ("I / O") devices. Input devices include, but are not limited to, keyboards, microphones, touch screens, foot pedals, sensors, MIDI devices, and pointing devices such as a mouse or trackball. Output devices include, but are not limited to, video displays, speakers, refreshable Braille terminals, lights, MIDI devices, and 2-D or 3-D printers.

[0039] Other components may include I / O interfaces, external serial device ports, and any additional coprocessors. For example, the computing system 2000 may include interfaces (e.g., Universal Serial Bus (USB) interfaces) for connecting input devices, output devices, or additional storage devices (e.g., portable flash drives or external media drives). In some implementations, the computing system 2000 includes additional devices such as coprocessors, such as math coprocessors that can assist the processor 2010 in performing high-precision or complex calculations.

[0040] Component 2090 may be configured to connect to external media, display 2070, input device 2080, or any other component in computing system 2000, or a combination thereof. Display 2070 may be a liquid crystal display (LCD), an organic light emitting diode (OLED) display, a flat panel display, a solid-state display, a cathode ray tube (CRT) display, a projector, a printer, or other display device now known or later developed for outputting determined information. Display 2070 may serve as an interface for a user to view the operation of processor(s) 2010, or, in particular, as an interface with software stored in memory 2060.

[0041] The input device 2080 may be configured to allow a user to interact with any of the components of the computing system 2000. The input device 2080 may be a plurality of keypads, a keyboard, a cursor control device such as a mouse or a joystick. Furthermore, the input device 2080 may be a remote control, a touch screen display (which may be a combination of the display 2070 and the input device 2080), or any other device operable to interact with the computing system 2000, such as any device operable to serve as an interface between the user and the computing system 2000.

[0042] In one aspect, a parity check matrix defines a set of equations that any valid codeword satisfies. Parity check matrices can be used to encode low-density parity check ("LDPC") codes, as described by Richardson and Urbanke in IEEE Transactions on Information Theory, Vol. 47, No. 2 (February 2001). Typically, many wireless and wired communication systems use LDPC as a forward error correction coding scheme.

[0043] On the one hand, constellation shaping is an energy-efficiency enhancement method used in digital signal modulation. Constellation shaping improves traditional modulation techniques such as amplitude and phase shift keying (APSK) and quadrature amplitude modulation (QAM) by modifying the continuous and uniform distribution of data symbols to match the channel characteristics.

[0044] Figure 3A 、 Figure 3B and Figure 3C A diagram depicting an LDPC coded modulation system using a uniformly distributed QAM constellation and the information-theoretic limit of the uniformly distributed QAM constellation. Figure 3A The constellation structure 300 for 1024QAM (with constellation size M=1024) is shown, where there are 4 different partitions (e.g., divisions or subdivisions) 301, 302, 303, 304 depending on the real and imaginary dimensions so that the decoder can exploit this simple partitioning scheme. Figure 3BA block diagram of an LDPC coded modulation system 320 is shown that includes an LDPC encoder 322 and a pulse amplitude modulation (PAM) symbol mapper (or "PAM mapper") 324. The LDPC encoder 322 can receive multiple binary values (e.g., values in the F2 field) from a source and generate a codeword of length N at its output. The PAM mapper 324 can map each log2M value (from an M-ary signal constellation (e.g., 1024QAM)) into an analog waveform for transmission. The LDPC coded modulation system 320 can be an LDPC-BICM system combined with conventional QAM (with a uniformly distributed QAM constellation). BICM refers to a binary interleaved coded modulation system, which is a model of the coded modulation system on which most communication systems are based. The system 320 may leave gaps in the limits of what can be achieved, such as Figure 3C As shown in . Figure 3C The spectral efficiency of various modulation schemes is shown, including binary phase shift keying (BPSK), quadrature phase shift keying (QPSK), 16-QAM, 64-QAM, 256-QAM, 1024-QAM and 4096-QAM, indicated by lines 357, 356, 355, 354, 353, 352 and 351, respectively. Figure 3C Also shown is the limit of the spectral efficiency of the channel (the Shannon limit), indicated by line 351, and a gap 352 of 1.53 dB between the Shannon limit and QAM (eg, 4096-QAM).

[0045] The Shannon limit (or Shannon capacity) refers to the maximum rate at which error-free data can theoretically be transmitted over a channel for a specific noise level, given the presence of random data transmission errors on the link. The Shannon limit is a fundamental limit of the channel, achieved when the code distribution matches the optimal distribution for a given channel. The Shannon limit is achieved when the mutual information is maximized, and this maximization occurs when the input distribution matches the optimal distribution. For example, for a white Gaussian noise (AWGN) channel, the mutual information is maximized when the codebook also has a Gaussian distribution, and that maximum mutual information is the Shannon limit. The Shannon limit may not change with distribution, but is a fixed number for a given channel (while the actual rate may depend on the distribution).

[0046] The maximum achievable transmission rate can be improved by matching the probability to the input distribution, increasing the block length (to have a large block length) and / or using Gaussian random codes. The achievable capacity may also be limited by finite length performance. For example, the Polyanskiy bound can provide a bound on the energy required per bit in a communication system, which is a baseline for finite length performance. The capacity of BICM may depend on the uniform codebook, the large block length and / or the random code. A communication system using a uniformly distributed QAM constellation may incur a loss of up to πe / 6 (≈1.53 dB) close to the Shannon limit. If a communication system uses a codebook constructed with a uniform distribution (and does not induce a distribution to the codebook), then a 1.53 dB gap exists for certain channels. To reduce this gap, the communication system may perform constellation shaping to benefit from moving away from uniform QAM. For example, in a broad sense, there are two constellation shaping methods: geometric constellation shaping (see Figure 4A and Figure 4B ) and probabilistic constellation shaping (see Figure 5A and Figure 5B ).

[0047] Figure 4A and Figure 4B Figures 400 and 450 illustrate geometric constellation shaping according to one or more embodiments. Geometric constellation shaping aims to shape the constellation points into a nearly Gaussian geometry so that the constellation can have a Gaussian distribution with a large M. For example, the points can be unequally spaced (e.g., by varying the distance between the points) but placed with uniform probability. Although tracking when radio frequency (RF) impairments are significant is not straightforward, geometric constellation shaping is employed in some cable systems and / or standards.

[0048] Figure 5A and Figure 5B is a diagram depicting probabilistic constellation shaping in accordance with one or more embodiments. Figure 5A A diagram 500 is shown depicting a grid depicting constellations weighted with different probabilities. Figure 5B A graph 550 depicting a probability distribution on a grid is shown, with curve 551 indicating an ideal mapping (eg, a Gaussian mapping). Figure 5B It is also shown that grids with larger lengths (eg, grids at or near ±60) map to small probabilities.

[0049] In one aspect, a communication system (e.g., an LDPC coded modulation / demodulation system) may include a shaping encoder configured to apply a constellation shaping scheme (e.g., probabilistic constellation shaping) to QAM. For example, if the shaping encoder generates a constellation of length (k s -n s ) produces an input bit block of length n s Amplitude block (where k s >n s ), then the shaping rate (or compression rate) R sIt can be defined as follows:

[0050]

[0051] Because the shaping rate R s Less than 1(R s <1), the communication system's shaping encoder will act as forward error correction (FEC). Consequently, the constellation shaping performed by the shaping encoder will negatively impact the overall code rate. The code rate refers to the code rate of the LDPC code, which is the ratio of the size of the information bit to the size of the coded bit generated by the LDPC encoder using the information bit input. For example, assuming a desired code rate of 5 / 6, if the shaping encoder applies probabilistic QAM to a conventional communication system (e.g., LDPC coded modulation system 320), the overall code rate will be less than 5 / 6. This reduction in overall code rate makes it difficult to determine the optimal parameters for probabilistic shaping.

[0052] Furthermore, in an LDPC coded modulation system using M-ary QAM (or M-QAM or M-QAM modulator), the M-QAM may include a PAM symbol mapper (e.g., PAM mapper 324) configured to calculate the Cartesian product of two sqrt(M)-PAMs such that each sqrt(M)-PAM has m bits. In other words, the QAM after the Cartesian product may have 2m bits. Therefore, the number of bits m in the real dimension of the M-QAM (or equivalently, the number of bits m in the sqrt(M)-PAM) may be defined as follows:

[0053]

[0054] For example, 4096-QAM (M=4096) is the Cartesian product of 64-PAM×64-PAM, so that each PAM has 6 bits (m=6). In other words, QAM can have 6 bits in the real dimension and 6 bits in the imaginary dimension, for a total of 12 bits. This Cartesian product can be implemented using a computationally expensive (matrix) multiplication operation (e.g., using circuitry, firmware, or software to multiply two matrices).

[0055] To address these issues, according to certain aspects, embodiments of the present disclosure relate to a technique for applying constellation shaping to QAM modulation with different rates using a shaping encoder (e.g., a probabilistic shaping encoder) with LDPC, thereby achieving a shaping gain of 1.53 dB. The shaping gain can refer to (1) an increase in the information rate (e.g., average entropy per symbol) achieved by constellation shaping compared to a uniformly distributed constellation; or (2) enhanced energy efficiency of the information rate achieved by constellation shaping compared to a uniformly distributed constellation.

[0056] In some embodiments, an LDPC coded modulation system may perform a LDPC / FEC code rate (e.g., R c ), the number of shaped bits (e.g., KL u ) and the number of unshaped bits (e.g., L u ) is selected to produce the desired code rate (e.g., R target ) multiplexes and encodes the data. In some implementations, the LDPC coded modulation system may determine an appropriate number of punctured (or discarded, removed, deleted) bits (e.g., Δ) to align the boundary between the coded bits and the parity bits.

[0057] In some implementations, an LDPC coded modulation system may use or define a desired shaping codebook. In some implementations, different shaping codebooks corresponding to different MCSs are defined and provided. These codebooks may be lookup tables (LUTs) that may be implemented using a dictionary or tree parser, a Huffman decoder, or prefix-free coding.

[0058] In some implementations, an LDPC coded modulation system may avoid direct multiplication (e.g., matrix multiplication to perform a Cartesian product in a PAM symbol mapper) and instead use bit operations that are mathematically equivalent to expensive multiplication operations (e.g., a symbol mapper may concatenate one or more bit arrays with one or more bits), multiplexing, and / or demultiplexing (e.g., using a multiplexer to combine two input streams, using a demultiplexer to split one binary stream into two binary streams).

[0059] In some implementations, the LDPC coded modulation system may determine optimized parameters using a trade-off analysis. For example, the LDPC coded modulation system may determine the LDPC code rate (e.g., R c ), the LDPC code rate can be used to achieve the target code rate (e.g., R target ) while minimizing the number of punctured / discarded bits. In some implementations, the LDPC coded modulation system may set the parameters to appropriate values (e.g., L u =0) to act as a non-shaping system.

[0060] In some embodiments, an LDPC coded modulation system may include a shaping encoder, an LDPC encoder (or an adjustable encoder), and / or a symbol mapper. In some embodiments, the symbol mapper may be a PAM symbol mapper. In some embodiments, the modulation system may be implemented in baseband circuitry or transmitter circuitry of a communication system.

[0061] In some implementations, the shaping encoder may include an amplitude shaper and an amplitude to bits (Amp2Bits) converter. The amplitude shaper may receive input data (e.g., input binary values) and apply probabilistic constellation shaping to the QAM symbols to generate amplitudes corresponding to the QAM symbols (e.g., n s The amplitude in the dimension is given by For example, the shaping rate R of the amplitude shaper s It can be 0.95, which is less than or equal to the entropy H of the amplitude A, as follows:

[0062] R s =0.95≤H(A)……………(Equation 3)

[0063] In some implementations, an Amp2Bits converter may convert the shaped amplitude into a binary value. In some implementations, an LDPC coded modulation system may determine the number of unshaped bits (L u ), and the shaping encoder (eg, amplitude shaper and / or Amp2Bits converter) outputs (KL u ) The units digit of the number.

[0064] In some embodiments, the adjustable encoder (or LDPC coded modulation system) can identify / determine / obtain the target code rate R of the LDPC coded modulation system. target (For example, a code rate of 5 / 6). The adjustable encoder (or LDPC coded modulation system) can be based on the target code rate R target Determine (e.g., identify, adjust, calculate, compute) one or more parameters, including (1) the code rate R of the LDPC code c (or the code rate of the LDPC encoder) or (2) the number of unshaped bits to be input to the LDPC encoder but not output from the shaping encoder (L u In some implementations, the adjustable encoder (or LDPC coded modulation system) may determine one or more parameters using the following equations:

[0065]

[0066] Where N is the number of input information bits to the LDPC encoder.

[0067] In some implementations, the LDPC coded modulation system may include a multiplexer (MUX) that may be implemented using circuitry, firmware, and / or software. The MUX may be configured to receive (1) the output of the shaping encoder (N·R c -L u =KL u) bits (K is the number of information bits) and (2) L from the input data (e.g., input binary value) u The K information bits are provided as MUX input, and the K information bits are provided as MUX output to the LDPC encoder.

[0068] In some embodiments, the LDPC encoder may use a code rate R c (K=N·R c ) bits are encoded to generate the encoded data. In some embodiments, the LDPC coded modulation system may include a parity puncturer configured to discard or puncture some parity bits from the encoded data. In some embodiments, the code rate of the LDPC encoder (or the code rate of the LDPC code used in the LDPC encoder) may be set / adjusted to be higher than the code rate R target The code rate R c For example, R c is 7 / 8, which is higher than the code rate R of 5 / 6 target In some implementations, the parity of the encoded data may be uniformly distributed.

[0069] In some embodiments, the adjustable encoder may encode data at a total code rate R (e.g., an actual code rate or an actually achieved code rate) as follows:

[0070]

[0071] Where K is the number of input information bits of the LDPC encoder In some implementations, the total ratio R may be a product of a shaping codebook (e.g., one or more shaping codes), one or more shaping factors (e.g., shaping scheme, shaping rate, shaping gain), an FEC code rate (e.g., code rate R of an LDPC encoder), and a c ) or a function of at least one of the puncture length.

[0072] In some implementations, an LDPC coded modulation system may include a demultiplexer (DMUX) that may be implemented using circuitry, firmware, and / or software. The DMUX may be configured to receive N number of coded bits (e.g., codewords) as DMUX inputs and output (1) (KL) from the N number of coded bits. u ) number of coded bits and (2) P (=NK) number of parity bits from the N number of coded bits.

[0073] In some implementations, the parity puncturer may receive P (=NK) number of parity bits output from the DMUX, and discard (or puncture, remove, delete) Δ number of parity bits from the P number of parity bits to generate (P-Δ) number of parity bits (Δ is the number of discarded / punctured / removed parity bits).

[0074] In some embodiments, a symbol mapper (eg, a PAM symbol mapper) may receive (1) the (KL) output from the DMUX. u ) number of coded bits and (2) (P-Δ) number of parity bits output from the parity puncturer, and generate a bit array of size equal to 2m. The symbol mapper can provide the generated bit array to the M-QAM so that the M-QAM can convert the received bit array into an analog waveform for transmission.

[0075] In some embodiments, the LDPC coded modulation system may convert the number of unshaped information bits (L u ) is determined as K(L u =K) and constellation shaping may not be performed. In this case, the symbol mapper may receive (1) K number of coded bits output from the DMUX and (2) (P-Δ) number of parity bits output from the parity puncturer, and convert the received binary data into an analog waveform for transmission.

[0076] In some embodiments, the LDPC coded modulation system may determine the number of discarded / punctured / removed parity bits (Δ) to be zero (Δ=0) and may not perform parity puncturing. In this case, the symbol mapper may receive (1) the (KL) output from the DMUX. u ) number of coded bits and (2) P number of parity bits output from the DMUX, and converts the received binary data into an analog waveform for transmission.

[0077] In some embodiments, in response to receiving (1) (KL) output from DMUX u ) number of coded bits and (2) (P-Δ) number of parity bits output from the parity puncturer, the symbol mapper can generate a symbol map with (m-1) number of rows and (KL u ) / (m-1) number of columns and generate an encoded bit matrix of size (KL u ) of the parity bit array. In some embodiments, the symbol mapper can be configured by transforming (KL u ) number of coded bits into (m-1) blocks such that the (m-1) blocks correspond to the (m-1) number of rows to generate the coded bit matrix. For example, the symbol mapper may convert (KL u ) number of coded bits are divided or split into (m-1) blocks. In this way, the symbol mapper can act as a stream converter or matrix stream reshaper to convert one stream into a two-dimensional stream.

[0078] In some implementations, the symbol mapper may generate the encoded bit matrix such that the number of columns of the matrix is equal to the size of the parity bit array, as follows:

[0079]

[0080] Where 0≤L u ≤K,0≤Δ≤Δ max For example, Δ max It can be 250 (bits).

[0081] In some embodiments, assuming N, R c and m is fixed or determined according to the LDPC encoder and M-QAM, the LDPC coded modulation system can determine L that satisfies Equation 6 u In some implementations, assuming that N and m are fixed or determined, the LDPC coded modulation system may determine a code rate R that satisfies Equations 4 and 6 and minimizes the number of discarded / punctured bits Δ. c In this way, the LDPC coded modulation system can determine the code rate R c , the code rate R c Achievable target bit rate R target , while avoiding significant pruning losses.

[0082] In some embodiments, using a matrix of encoded bits and an array of parity bits that satisfy Equation 6, a symbol mapper can implement post-FEC padding by performing bit operations, as explained in the following sections. The symbol mapper may include a stream parser configured to rearrange or reorder the columns of the matrix of encoded bits. In some embodiments, the stream parser may randomly rearrange or reorder the columns of the matrix of encoded bits so as to spread the encoded bits across the columns of the matrix. In this way, an LDPC coded modulation system combined with a multiple-input multiple-output (MIMO) system can achieve MIMO diversity (e.g., spatial diversity, spatial multiplexing, or interference alignment) to effectively improve reliability and reduce the effects of interference or fading channels. In some embodiments, assuming the number of spatial streams (N ss ) is two (N ss=2), the stream parser may assign one set of streams to one antenna and another set of streams to another antenna. For example, the stream parser may randomly rearrange or reorder the columns of the encoded bit matrix (e.g., the number of columns of the matrix is 100), select two columns from the rearranged columns of the matrix, and assign the two columns to the first and second MIMO antennas, respectively, among the multiple MIMO antennas, so that the stream parser can output 50 columns (e.g., 50 bit arrays) to the first MIMO antenna and another 50 columns (e.g., 50 bit arrays) to the second MIMO antenna. In some implementations, the stream parser may sequentially select two columns from the columns of the matrix in the order of the columns, and assign the two columns to the first and second MIMO antennas, respectively, among the multiple MIMO antennas.

[0083] In some implementations, the stream parser may extract the KL u ) / (m-1) columns, and selects two bits (e.g., a first bit and a second bit) corresponding to the two columns of the matrix from the parity bit array (e.g., the first bit and the second bit, respectively). Next, a symbol mapper may combine the first column, the second column, the first bit, and the second bit to generate a bit array of size 2m and provide the bit array to the M-QAM. In some implementations, the symbol mapper may sequentially concatenate the first column, the second column, the first bit, and the second bit to generate the bit array. In some implementations, the symbol mapper may combine the first column, the second column, the first bit, and the second bit so that the first bit or the second bit may be the most significant bit (MSB) of the bit array or the MSB of a constellation point in the M-QAM.

[0084] In some embodiments, L of the K number of information bits u The number of information bits is not shaped by the shaping encoder. The LDPC encoder (or MUX) can receive L u In some embodiments, the LDPC coded modulation system may select L u The number of information bits makes L u The number of information bits is evenly distributed across the K number of information bits. In some implementations, the shaping encoder may use a size less than (KL u ) is generated by a set of unshaped bits (KL u ) shaped bits. In response to the shaping encoder generating (KL u ) shaped bits, the LDPC coded modulation system (eg, MUX) can combine (KL u ) shaped bits and L uunshaped bits to form exactly K information bits in each block at the LDPC encoder. These K information bits can be processed agnostically by the LDPC encoder (e.g., it is not known which of the K information bits are shaped and which are unshaped). The LDPC encoder can encode the K information bits to produce N coded bits (where ). Next, the LDPC coded modulation system (eg, DMUX) may perform post-LDPC grouping to generate a first coded bit group and a second parity bit group. Next, the symbol mapper may obtain or input (KL u ) digits and only obtain or input (KL) from the second group u ) / (m-1) parity bits. (KL u The input of ) / (m-1) parity bits can be achieved by dropping, removing or puncturing Δ number of bits from the (NK) parity bits in the second group. Parameters (eg, L u , Δ, N, K) can be selected by finding integer solutions (e.g., solutions to Equation 4 and / or Equation 6). The symbol mapper can perform post-LDPC padding by: (1) generating a matrix with (m-1) number of rows and (KL u ) / (m-1) number of columns, and (2) combining one or two columns of the matrix with (KL u ) / (m-1) parity bits corresponding to the one or two columns to form a bit array of size 2m. In some implementations, the symbol mapper may provide the bit array (of size 2m) to the M-QAM to perform QAM mapping such that (KL u ) / (m-1) parity bits can serve as the (several) MSBs of the PAM constellation points. In other words, (KL u ) / (m-1) parity bits can determine the symbol of the PAM constellation.

[0085] In some embodiments, by selecting one or more parameters (e.g., R c or L u or Δ) to achieve the target bit rate (e.g., R target ), the combination of a shaping encoder and an LDPC encoder (or the combination of a shaping encoder and an adjustable encoder) can act as a coded modulation system with different code rates.

[0086] In some embodiments, parameters may be selected to achieve an overall code rate R of 5 / 6, even when using probabilistic QAM. For example, if the target code rate R target is 5 / 6, then the parameters can be selected so that according to M-QAM (e.g., according to Equation 2), m is fixed; R c =7 / 8; Lu = 81 and / or N = 1944. Using these parameters, the LDPC coded modulation system can achieve not only a total code rate R of 5 / 6, but also the same spectral efficiency (10 bits) as MCS13 (Modulation and Coding Scheme (MCS) index 13) and a shaping gain of 1.53 dB.

[0087] In some embodiments, the shaping encoder may use a shaping codebook containing one or more shaping codes. For example, the shaping codebook may contain a shaping code for 4096-QAM with an LDPC code rate of 7 / 8 to achieve a shaping rate (R) of 0.952. s ), an overall code rate (R) of 5 / 6, and the same spectral efficiency as MCS13. The shaping code may include multiple mappings (e.g., 32 mappings) from input binary data (e.g., 4-bit strings, 5-bit strings, 6-bit strings, 7-bit strings, 8-bit strings) to output binary data (e.g., 5-bit strings), each with different probabilities. For example, one or more mappings from a 4-bit string to a 5-bit string may have a probability of 1 / 16; one or more mappings from a 5-bit string to a 5-bit string may have a probability of 1 / 32; one or more mappings from a 6-bit string to a 5-bit string may have a probability of 1 / 64; one or more mappings from a 7-bit string to a 5-bit string may have a probability of 1 / 128; and / or one or more mappings from an 8-bit string to a 5-bit string may have a probability of 1 / 256. In some implementations, using shaping codes, the shaping encoder may shape / map / convert / assign the input string [1111110] to the output string

[00011] with a probability of 1 / 128. In some other embodiments, using another shaping code, the shaping encoder may shape / map / convert / assign the input string [1111110] to the output string

[11100] with a probability of 1 / 128.

[0088] In some embodiments, a reshaping encoder may use a prefix-free code to reshape / map / convert / assign a variable-length input string (e.g., a string of 4, 5, 6, 7, or 8 bits) into a fixed-length output string (e.g., a string of 5 bits). A prefix-free code is a code such that no codeword (generated using the code) is a prefix of another codeword. In some embodiments, the mapping defined by the prefix-free code may be a reversible operation, such that each mapping is a one-to-one mapping. In some embodiments, a reshaping encoder may use a Huffman encoding method using the prefix-free code. For example, a reshaping encoder may use the prefix-free code to reshape / map / convert / assign a variable-length input string into a fixed-length output string based on the frequency of the input string. In some embodiments, a reshaping encoder may use a tree structure for the prefix-free code so that Huffman decoding can be performed using the tree structure. In some embodiments, a reshaping encoder may use other structures (e.g., a lookup table or dictionary) to represent the prefix-free code so that Huffman decoding can be performed using the same structure. In some embodiments, a reshaping encoder may receive uniformly distributed input data and assign non-uniform probabilities to the output data. This probabilistic constellation shaping may have an inherent rate loss such that the shaping encoder acts as FEC.In some embodiments, given an input string or symbol X, a prefix-free code may be used to map / assign / shape / convert N number of different input strings or N different symbols (e.g., N=32).

[0089] In some embodiments, a device may include a transmitter and one or more processors. The one or more processors may be configured to identify a code rate of a low-density parity-check (LDPC) code. The one or more processors may be configured to receive a set of information bits from an LDPC encoder. The one or more processors may be configured to encode the set of information bits using the code rate by the LDPC encoder to generate a set of coded bits and a set of parity bits. The one or more processors may be configured to generate a bit array matrix from the set of coded bits. The one or more processors may be configured to discard one or more parity bits from the set of parity bits to generate a parity bit array having a size equal to the number of columns of the matrix. The one or more processors may be configured to generate a bit array by concatenating (1) one or more bit arrays selected from the bit array matrix and (2) one or more bits corresponding to the one or more bit arrays selected from the parity bit array. The one or more processors may be configured to modulate the bit array by a modulator to generate modulated data for transmission by a transmitter. A modulator refers to an amplitude modulator, a frequency modulator, a digital modulator such as a phase-shift keying (PSK) modulator or a quadrature amplitude modulator (QAM), or any circuit system, firmware, or software that can superimpose an information signal onto a signal for wireless / wireless transmission.

[0090] In some embodiments, the transmitter may transmit modulated data. In some embodiments, the set of information bits includes a first set of bits (e.g., shaped bits) and a second set of bits (e.g., unshaped bits). The one or more processors may recognize a shaping code via a shaping encoder. A shaping encoder refers to any circuitry, firmware, or software that uses a shaping code to modify a signal distribution to improve the efficiency of wireless / optical communication. A shaping code refers to a geometric shaping code, a probabilistic shaping code, or any code or data used to modify a signal distribution to improve the efficiency of wireless / optical communication. The one or more processors may encode the data using the shaping code via the shaping encoder to generate a first set of information bits. The one or more processors may receive the first set of information bits from the output of the shaping encoder via an LDPC encoder.

[0091] In some embodiments, when modulating the bit array, the one or more processors may perform quadrature amplitude modulation using the number of bits per symbol on the bit array to generate modulated data. When generating the bit array matrix, the one or more processors may determine the number of columns of the bit array matrix based at least on the number of bits per symbol and the size of the set of encoded bits. The one or more processors may determine the number of rows of the bit array matrix based at least on the number of bits per symbol. The bit array may have a size equal to the number of bits per symbol.

[0092] In some embodiments, when generating the bit array, one or more processors may select a first column and a second column from a bit array matrix. One or more processors may select a first bit and a second bit corresponding to the first column and the second column of the bit array matrix, respectively, from a parity bit array. One or more processors may concatenate the first column, the second column, the first bit, and the second bit to generate the bit array. The generated bit array may sequentially include the first column, the first bit, the second column, and the second bit. The first column and the second column may be randomly selected from the columns of the bit array matrix. The first column and the second column may be sequentially selected from the columns of the bit array matrix in the order of the columns of the bit array matrix.

[0093] In some embodiments, a device may include a transmitter and one or more processors. The one or more processors may be configured to identify a target code rate for encoding data. The one or more processors may be configured to determine a code rate and a number of unshaped bits of a low-density parity-check (LDPC) code to encode the data at the target code rate. The one or more processors may be configured to receive data comprising shaped bits generated by a shaping encoder and a set of unshaped bits of a size equal to the number by an LDPC encoder, and encode the data using the code rate to generate an encoded bit matrix and a set of parity bits. The one or more processors may be configured to discard one or more parity bits from the set of parity bits based on at least the number to generate a parity bit array. The one or more processors may be configured to generate a bit array by concatenating (1) one or more bit arrays obtained from a column of the matrix and (2) one or more bits corresponding to the one or more bit arrays obtained from the parity bit array. The one or more processors may be configured to modulate the bit array by the modulator to generate modulated data for transmission by the transmitter.

[0094] When determining a code rate, the one or more processors may determine one or more code rates to encode data at a target rate. The one or more processors may determine, for each of the one or more code rates, a number of parity bits to discard before modulation. The one or more processors may select, from the one or more code rates, a code rate corresponding to the minimum number of parity bits to discard before modulation.

[0095] The embodiments of the present disclosure have at least the following advantages and benefits. First, the embodiments of the present disclosure can provide a method for target ) is a useful technique for adjusting the modulation / demodulation process, thereby achieving fine control of the overall code rate (R). For example, choosing an LDPC code rate (e.g., R c =7 / 8) and / or having a 95% shaping (or compression) rate (e.g., R s =0.95) of the unshaped information bits (e.g., L u =81) results in an overall code rate of 5 / 6. In some embodiments, the LDPC coded modulation system may perform a LDPC / FEC code rate (e.g., R c ), the number of shaped bits (e.g., KL u ) and the number of unshaped bits (e.g., L u ) is selected to produce the desired code rate (e.g., R target ) multiplexes and encodes the data. In some implementations, the LDPC coded modulation system may determine optimized parameters using a trade-off analysis. For example, the LDPC coded modulation system may determine the LDPC code rate (e.g., R c ), the LDPC code rate can be used to achieve the target code rate (e.g., Rtarget ) while minimizing the number of punctured / discarded bits. In some implementations, the LDPC coded modulation system may set the parameters to appropriate values (e.g., L u =0) to act as a non-shaping system.

[0096] Second, embodiments of the present disclosure may provide useful techniques for avoiding direct multiplication (e.g., matrix multiplication to perform Cartesian products in a PAM symbol mapper), and instead using bit operations that are mathematically equivalent to expensive multiplication operations (e.g., a symbol mapper may concatenate one or more bit arrays and one or more bits), multiplexing, and / or demultiplexing (e.g., using a multiplexer to combine two input streams, using a demultiplexer to split one binary stream into two binary streams).

[0097] Third, embodiments of the present disclosure may provide useful techniques for using or defining desired shaping codebooks. In some implementations, different shaping codebooks corresponding to different MCSs are defined and provided. These codebooks may be lookup tables (LUTs) that can be implemented using a dictionary or tree parser, a Huffman decoder, or prefix-free encoding.

[0098] Fourth, embodiments in the present disclosure may provide useful techniques for achieving 1.53 dB of shaping gain when using high spectral efficiency QAM modulation, thereby achieving 1.53 dB of shaping gain (or higher in impairment-limited systems).

[0099] Figure 6A 、 Figure 6B and Figure 6C FIG6 is a diagram illustrating an example LDPC coded modulation system 600 according to one or more embodiments. LDPC coded modulation system 600 may include a shaping encoder 630, a multiplexer (MUX) 612, an LDPC encoder (or an adjustable encoder) 613, a demultiplexer (DMUX) 614, a parity puncturer 615, a symbol mapper 660, and / or a modulator 616 (e.g., an M-QAM modulator). Symbol mapper 660 may be a PAM symbol mapper. Modulation system 600 may be implemented in baseband circuitry (e.g., baseband circuitry 110) or transmitter circuitry (e.g., transmitter circuitry 120) of a communication system (e.g., communication system 105).

[0100] refer to Figure 6A and Figure 6B , the shaping encoder 630 may include an amplitude shaper 631 and an amplitude to bit (Amp2Bits) converter 632. The amplitude shaper 631 may receive input data 621 (eg, input binary values) and apply probabilistic constellation shaping to the QAM symbols to generate amplitudes corresponding to the QAM symbols (eg, n s The amplitude in the dimension is given by For example, according to Equation 3, the shaping rate R of the amplitude shaper is s may be 0.95, which is less than or equal to the entropy H of the amplitude A. The Amp2Bits converter 632 may convert the shaped amplitude into a binary value 642 .

[0101] In some embodiments, the LDPC coded modulation system 600 may determine the number of unshaped bits (L u ), and the shaping encoder 630 (eg, the amplitude shaper 631 and / or the Amp2Bits bit converter 632) outputs (KL u ) number of information bits 642, so that the LDPC encoder 613 (or MUX 612) can receive K number of information bits 622 (including L u The number of information bits 611 and (KL u ) number of bits 642 as input. L among K number of information bits 622 u The number of information bits 611 is not shaped by the shaping encoder 630. The LDPC coded modulation system 600 may select L u The number of information bits 611 makes L u The number of information bits 611 is evenly distributed across the K number of information bits 622. The shaping encoder 630 may use a value with a value less than (KL u ) generates (KL u ) shaped bits 642.

[0102] In some embodiments, the LDPC coded modulation system 600 (or the adjustable encoder 613) can identify / determine / obtain the target code rate R of the LDPC coded modulation system 600. target (For example, a code rate of 5 / 6). The LDPC coded modulation system 600 (or the adjustable encoder 613) may be based on the target code rate R target Determine (e.g., identify, adjust, calculate, compute) one or more parameters including (1) the code rate R of the LDPC code c (or the code rate of the LDPC encoder) or (2) the number of unshaped bits to be input to the LDPC encoder but not output from the shaping encoder (L u In some implementations, the adjustable encoder 613 may determine one or more parameters using Equation 4.

[0103] refer to Figure 6A, the LDPC coded modulation system 600 may include a multiplexer (MUX) 612 that may be implemented using circuitry, firmware, and / or software. The MUX 612 may be configured to receive (1) the output of the shaping encoder 630 (N·R c -L u =KL u ) information bits 642 and (2) L from input data (e.g., input binary value) u The K information bits 611 are used as MUX inputs, and the K information bits 622 are provided as MUX outputs to the LDPC encoder 613. The LDPC encoder 613 may use a code rate of R c (K=N·R c ) bits are encoded to generate coded data. The LDPC coded modulation system 600 may include a parity puncturer 615 configured to discard or puncture some parity bits from the coded data (e.g., parity data 624 of size (P=NK)). In some implementations, the LDPC encoder 613 may set or adjust the code rate of the LDPC encoder 613 (or the code rate of the LDPC code used in the LDPC encoder 613) to be higher than the code rate R target The code rate R c For example, R c is 7 / 8, which is higher than the code rate R of 5 / 6 target In some implementations, the parity of the encoded data may be uniformly distributed.

[0104] In some embodiments, the adjustable encoder 613 may encode the data at a total code rate R (e.g., an actual code rate or an actually achieved code rate) according to Equation 5. The total code rate R may be a combination of a shaping codebook (e.g., one or more shaping codes), one or more shaping factors (e.g., a shaping scheme, a shaping rate, a shaping gain), an FEC code rate (e.g., the code rate R of the LDPC encoder), and a coding scheme. c ) or a function of at least one of the puncturing length Δ.

[0105] refer to Figure 6A , the LDPC coded modulation system 600 may include a demultiplexer (DMUX) 614 that may be implemented using circuitry, firmware, and / or software. The DMUX 614 may be configured to receive N number of coded bits 623 (e.g., codewords) as DMUX inputs and output (1) (KL) from the N number of coded bits 623. u) number of coded bits 651 and (2) P (=NK) number of parity bits 624 from the N number of coded bits 623. The parity puncturer 615 may receive the P (=NK) number of parity bits 624 output from the DMUX and discard (or puncture, remove, or delete) Δ number of parity bits from the P number of parity bits 624 to generate (P-Δ) number of parity bits 652 (Δ is the number of discarded / punctured / removed parity bits).

[0106] refer to Figure 6A and Figure 6C , the symbol mapper 660 (eg, a PAM symbol mapper) may receive (1) the (KL u ) number of coded bits 651 and (2) (P-Δ) number of parity bits 652 output from parity puncturer 615, and generates a bit array 670 of size equal to 2m. Symbol mapper 660 may provide generated bit array 670 to M-QAM 616 so that M-QAM 616 may convert received bit array 670 into an analog waveform for transmission.

[0107] In some embodiments, the LDPC coded modulation system 600 may convert the number of unshaped bits 611 (L u ) is determined as K(L u =K) and constellation shaping may not be performed. In this case, the symbol mapper 660 may receive (1) K number of coded bits output from the DMUX and (2) (P-Δ) number of parity bits output from the parity puncturer, and convert the received binary data into an analog waveform for transmission.

[0108] In some embodiments, the LDPC coded modulation system 600 may determine the number of discarded / punctured / removed parity bits (Δ) to be zero (Δ=0) and may not perform parity puncturing. In this case, the symbol mapper 660 may receive (1) the (KL) output from the DMUX. u ) number of coded bits and (2) P number of parity bits output from the DMUX, and converts the received binary data into an analog waveform for transmission.

[0109] refer to Figure 6C , in response to receiving (1) (KL u ) number of coded bits 651 and (2) (P-Δ) number of parity bits 652 output from the parity puncturer, the symbol mapper 660 can generate a symbol map with (m-1) number of rows and (KL u ) / (m-1) number of columns and generates an encoded bit matrix 661 of size (KL u) of the parity bit array 662. The symbol mapper 660 can be configured by converting (KL u ) number of coded bits 651 are converted into (m-1) blocks to generate a coded bit matrix 661, such that the (m-1) blocks correspond to the (m-1) number of rows in the matrix 661. For example, the symbol mapper 660 may convert (KL u ) number of coded bits 651 are divided or split into (m-1) blocks. In this way, the symbol mapper 660 can act as a stream converter or matrix stream shaper to convert one stream (e.g., (KL u ) number of encoded bits 651) into a two-dimensional stream (e.g., an encoded bit matrix 661).

[0110] In some implementations, according to Equation 6, the symbol mapper 660 may generate an encoded bit matrix 661 such that the number of columns of the matrix (KL u ) / (m-1) is equal to the size of the parity bit array (P-Δ). Using Equation 6, assuming N, R c and m are fixed or determined according to the LDPC encoder 613 and the M-QAM 616, then the LDPC coded modulation system 600 can determine the L that satisfies Equation 6. u In some implementations, assuming that N and m are fixed or determined, the LDPC coded modulation system 600 may determine a code rate R that satisfies Equations 4 and 6. c And minimize the number of discarded / punctured bits Δ. In this way, the LDPC coded modulation system 600 can determine the code rate R c , the code rate R c Achievable target bit rate R target , while avoiding significant pruning losses.

[0111] refer to Figure 6C , using the coded bit matrix 661 and the parity bit array 662 that satisfy Equation 6, the symbol mapper 660 can implement post-FEC padding by performing bit operations, as explained in the following sections. The symbol mapper 660 may include a stream parser 663 configured to rearrange or reorder the columns of the coded bit matrix 661. The stream parser 663 may randomly rearrange or reorder the columns of the coded bit matrix 661 so as to spread the coded bits across the columns of the matrix 661. In this way, the LDPC coded modulation system 600 combined with a MIMO system (not shown) can achieve MIMO diversity (e.g., spatial diversity, spatial multiplexing, or interference alignment) to effectively improve reliability and reduce the impact of interference or fading channels. In some implementations, assuming the number of spatial streams (N ss ) is two (N ss=2), the stream parser 663 may assign one set of streams to one antenna and another set of streams to another antenna. For example, the stream parser 663 may randomly rearrange or reorder the columns of the coded bit matrix 661 (e.g., the number of columns of the matrix is 100), select two columns from the rearranged columns of the matrix 661, and assign the two columns to the first and second MIMO antennas, respectively, so that the stream parser can output 50 columns (e.g., 50 bit arrays) to the first MIMO antenna and another 50 columns (e.g., 50 bit arrays) to the second MIMO antenna. In some implementations, the stream parser 663 may sequentially select two columns from the columns in the order of the columns of the matrix and assign the two columns to the first and second MIMO antennas, respectively, among the multiple MIMO antennas.

[0112] In some implementations, the stream parser 663 may extract the encoded bit matrix 661 from (KL u ) / (m-1) columns, and two bits (e.g., first bit 672 and second bit 674) corresponding to the two columns of the matrix are selected from the parity bit array 662 (e.g., the selected first and second bits are in (KL u ) / (m-1) bits and the selected first and second columns in (KL u ) / (m-1) columns). Next, the symbol mapper 660 may combine the first column 671, the second column 673, the first bit 672, and the second bit 674 to generate a bit array 670 of size 2m and provide the bit array 670 to the M-QAM 616. In some implementations, the symbol mapper 660 may sequentially concatenate the first column 671, the second column 673, the first bit 672, and the second bit 674 to generate the bit array 670. In some implementations, the symbol mapper may combine the first column, the second column, the first bit, and the second bit such that the first or second bit may be the most significant bit (MSB) of the bit array or the MSB of a constellation point in the M-QAM. For example, the symbol mapper 660 may sequentially concatenate the second bit 674, the first bit 672, the second column 673, and the first column 671 to generate the bit array 670 such that the second bit 674 may be the MSB of the bit array 670.

[0113] refer to Figure 6A and Figure 6C , in response to the shaping encoder 630 generating (KL u ) shaped bits 642, the LDPC coded modulation system 600 (eg, MUX 612) may combine (KL u ) shaped bits 642 and L uunshaped bits 611 to form exactly K information bits 622 in each block at the LDPC encoder 613. These K information bits 622 can be processed agnostically by the LDPC encoder 613 (e.g., without knowing which of the K information bits are shaped and which are unshaped). The LDPC encoder 613 can encode the K information bits 622 to produce N coded bits 623 (where ). Next, the LDPC coded modulation system 600 (e.g., DMUX 614) may perform post-LDPC grouping to generate a first coded bit group (e.g., a first bit stream) and a second parity bit group 624 (e.g., a second bit stream). Next, the symbol mapper 660 may obtain or input (KL u ) digits 651 and only obtain or input (KL) from the second group u ) / (m-1) parity bits 624. (KL u The input of the (NK) / (m-1) parity bits 662 can be implemented by dropping, removing, or puncturing a number of Δ bits from the (NK) parity bits 624 in the second group. u , Δ, N, K) can be obtained by finding integer solutions (e.g., solutions of Equation 4 and / or Equation 6, where L u , Δ are non-negative integers and N, K are positive integers). The symbol mapper 660 can perform post-LDPC padding by: (1) generating a matrix with (m-1) number of rows and (KL u ) / (m-1) number of columns of the matrix 661, and (2) combining one or two columns of the matrix 661 with (KL u ) / (m-1) parity bits 662 corresponding to the one or two columns to form a bit array 670 of size 2m. In some implementations, the symbol mapper 660 may provide the bit array 670 (of size 2m) to the M-QAM 616 to perform QAM mapping such that (KL u ) / (m-1) parity bits 662 may serve as the MSB(s) of the PAM constellation points. In other words, (KL u ) / (m-1) parity bits 662 can determine the symbol of the PAM constellation.

[0114] In some embodiments, by selecting one or more parameters (e.g., R c or L u or Δ) to achieve the target bit rate (e.g., R target), the combination of the shaping encoder 630 and the LDPC encoder 613 (or the combination of the shaping encoder and the adjustable encoder) can act as a coded modulation system with different rates. Parameters can be selected to achieve an overall code rate R of 5 / 6 even when using probabilistic QAM. For example, if the target code rate R target is 5 / 6, then the parameters can be selected so that according to M-QAM (e.g., according to Equation 2), m is fixed; R c =7 / 8; L u = 81 and / or N = 1944. Using these parameters, the LDPC coded modulation system 600 can not only achieve a total code rate R of 5 / 6, but also achieve the same spectral efficiency (10 bits) as MCS13 and a shaping gain of 1.53 dB.

[0115] Figure 7 is a diagram depicting an example shaping code 700 according to one or more embodiments. A shaping encoder (e.g., shaping encoder 630) may use a shaping codebook containing one or more shaping codes. For example, the shaping codebook may contain the following code for 4096-QAM with an LDPC code rate of 7 / 8: Figure 7 The shaping code 700 shown in FIG. 7 is used to achieve a shaping rate (R s ), an overall code rate (R) of 5 / 6, and the same spectral efficiency as MCS13. Shaping code 700 may include multiple mappings (e.g., 32 mappings indexed 701 from 1 to 32) from input binary data 702 of length 709 (e.g., 4-bit string, 5-bit string, 6-bit string, 7-bit string, 8-bit string) to output binary data 703 (e.g., 5-bit string; equivalent decimal data is shown in column 706), the mappings having different probabilities shown in columns 705 and 707 and / or amplitude values corresponding to the mappings (column 704). For example, one or more mappings from a 4-bit string to a 5-bit string (e.g., mapping 1 to 8) may have a probability of 1 / 16 (=0.0625); one or more mappings from a 5-bit string to a 5-bit string (e.g., mapping 9 to 18) may have a probability of 1 / 32 (=0.03125); one or more mappings from a 6-bit string to a 5-bit string (e.g., mapping 19 to 29) may have a probability of 1 / 64 (=0.015625); one or more mappings from a 7-bit string to a 5-bit string (e.g., mapping 30) may have a probability of 1 / 128 (=0.0078125); and / or one or more mappings from an 8-bit string to a 5-bit string (e.g., mapping 31 to 32) may have a probability of 1 / 256 (=0.00390625). For example, using the shaping code 700, the shaping encoder 630 can shape / map / convert / assign the input string [1111110] to the output string

[00011] with a probability of 1 / 128 (see mapping 30).

[0116] Figure 8A、 Figure 8B 、 Figure 8C and Figure 8D is a diagram depicting an example shaping code according to one or more embodiments. Figure 8A and Figure 8B 800 and 820 illustrate example shaping codes according to one or more embodiments. A shaping encoder (e.g., shaping encoder 630) may use a shaping codebook containing one or more shaping codes. For example, the shaping codebook may contain the following code for 4096-QAM with an LDPC code rate of 7 / 8: Figure 8A The shaping code 800 shown in FIG is used to achieve a shaping rate (R s ), an overall code rate (R) of 5 / 6, and the same spectral efficiency as MCS13. Shaping code 800 may include multiple mappings (e.g., 32 mappings indexed 801 from 1 to 32) from input binary data 802 of length 804 (e.g., 4-bit strings, 5-bit strings, 6-bit strings, 7-bit strings, 8-bit strings) to output binary data 803 (e.g., 5-bit strings), each with different probabilities 805. For example, one or more mappings from a 4-bit string to a 5-bit string (e.g., mapping 1 to 8) may have a probability of 1 / 16 (=0.0625); one or more mappings from a 5-bit string to a 5-bit string (e.g., mapping 9 to 18) may have a probability of 1 / 32 (=0.03125); one or more mappings from a 6-bit string to a 5-bit string (e.g., mapping 19 to 29) may have a probability of 1 / 64 (=0.015625); one or more mappings from a 7-bit string to a 5-bit string (e.g., mapping 30) may have a probability of 1 / 128 (=0.0078125); and / or one or more mappings from an 8-bit string to a 5-bit string (e.g., mapping 31 to 32) may have a probability of 1 / 256 (=0.00390625). For example, using the shaping code 800, the shaping encoder 630 can shape / map / convert / assign the input string [1111110] to the output string

[11100] with a probability of 1 / 128 (see mapping 30). Figure 8B A histogram 820 depicting the probability distribution over mapping indices 821 , codewords 822 , and input data 823 is shown.

[0117] Figure 8C Graphs 840 and 845 are shown depicting example simulation results using payload sizes of 800 and 8100 bytes of integer codes. Graph 840 shows the probability distribution of QAM mappings (e.g., amplitude values). Graph 845 shows the amplitude values of constellation points in an XY coordinate system (e.g., Z axis), where the X axis corresponds to the real (I) axis and the Y axis corresponds to the imaginary (Q) axis. Similarly, Figure 8DGraphs 860 and 865 are shown depicting example simulation results using integer code 800 and a payload size of 40100 bytes. Graph 860 shows the probability distribution of QAM mappings (e.g., amplitude values). Graph 865 shows the amplitude values of constellation points in an XY coordinate system (e.g., Z-axis), where the X-axis corresponds to the real (I) axis and the Y-axis corresponds to the imaginary (Q) axis.

[0118] Figure 9A 、 Figure 9B and Figure 9C is a graph depicting example simulation results using an LDPC coded modulation system according to one or more embodiments. In some implementations, assume that N, R c and m are fixed or determined according to the LDPC encoder and M-QAM, then the LDPC coded modulation system can determine L that satisfies Equation 6 u and / or integer values of Δ. Figure 9A Shows that when R c =7 / 8, N = 1944 and m = 6, satisfying the L of Equation 6 u and integer values of Δ, and shows that when R c =11 / 12, N=1944 and m=6, satisfying the L of Equation 6 u and a graph 902 of integer values of Δ.

[0119] Figure 9B Is displayed in the integer bit rate R s =0.9 and the target bit rate R target = 0.75 = 3 / 4 (shown as line 924) when using a code with a different code rate (e.g., for R c =11 / 12 of a set of points 921; for R c =7 / 8 of a set of points 922; for R c =5 / 6 of a set of points 923) of LDPC code in the parity check redundancy percentage (%) of the effective ratio R (see equation 5). In the simulation, Figure 9A The L shown in u and Δ values are used for R c =7 / 8 of a group of points 922 and a group of points 921 (R c =11 / 12). Figure 9B Also show the L corresponding to each point u For example, point 925 indicates the use of L u =207 and R c =11 / 12, which indicates that an effective ratio of 0.85 is achieved with about 33% parity puncturing (e.g., the number of punctured bits in the original parity bits). Figure 9B As shown in u =0 and Rc =5 / 6 (corresponding to point 926) can achieve the target code rate R target =0.75.

[0120] Figure 9C Is displayed in the integer bit rate R s =0.9518 and the target bit rate R target =0.83 ... =5 / 6 (shown as line 954) when using LDPC codes with different code rates (e.g., for R c =11 / 12 of a set of points 951; for R c =7 / 8 of a set of points 952; for R c =5 / 6 of a set of points 953) in the parity check redundancy percentage (%) of the effective ratio R (see equation 5). In the simulation, Figure 9A The L shown in u and Δ values are used for R c =7 / 8 of a group of points 952 and a group of points 951 (R c =11 / 12). Figure 9C Also show the L corresponding to each point u For example, point 955 indicates the use of L u =207 and R c =11 / 12, which indicates that an effective ratio of 0.92 is achieved with about 33% parity puncturing (e.g., the number of punctured bits in the original parity bits). Figure 9C As shown in u =81 and R c =7 / 8 (corresponding to point 956) and the simulation results of L u =75 and R c =5 / 6 (corresponding to point 957) can achieve the target code rate R target =0.83. In some embodiments, the LDPC coded modulation system may determine whether to meet the target code rate R target Multiple code rates R c (For example, R c =5 / 6 and R c =7 / 8), and then select the code rate that minimizes the parity puncturing percentage or the number of discarded parity bits (Δ). Figure 9C As shown in the figure, the modulation system can select the code rate R c =7 / 8, this is because R c = 7 / 8 (eg, point 956) shows that the simulation results show that the ratio R c =5 / 6 (eg, point 957) and a smaller parity puncturing percentage (eg, 0%) for the simulation result.

[0121] In some implementations, an apparatus (e.g., modulation system 600, communication system 105) may include a transmitter (e.g., transmitter circuitry 120) and one or more processors (e.g., processor 2010). The one or more processors may be configured to identify a target code rate for encoding data (e.g., Figure 9C R in target = 0.83). The one or more processors may be configured to determine a code rate and a number of unshaped bits (e.g., corresponding to a low-density parity check (LDPC) code) for the LDPC code. Figure 9C Point 956 and L u =81), and encode the data at the target code rate. The one or more processors may be configured to receive from an LDPC encoder (eg, LDPC encoder 613) a data frame including shaped bits generated by the shaping encoder and a size equal to the number (eg, L u =81) of a set of unshaped bits (eg, unshaped bits 611), and using a code rate (eg, ) encodes the data to generate a matrix of encoded bits (e.g., matrix 661) and a set of parity bits (e.g., (PK) number of parity bits 624). One or more processors may be configured to generate a matrix of encoded bits (e.g., matrix 661) and a set of parity bits (e.g., (PK) number of parity bits 624). u =81 and Equation 6) discard one or more parity bits (e.g., Δ number of parity bits) from the set of parity bits to generate a parity bit array (e.g., parity bit array 662). The one or more processors may be configured to generate a bit array (e.g., bit array 670) by concatenating (1) one or more bit arrays (e.g., first column 671 and second column 673) obtained from the columns of matrix 661 and (2) one or more bits (e.g., first bit 672 and second bit 674) corresponding to the one or more bit arrays obtained from parity bit array 662. The one or more processors may be configured to modulate bit array 670 by a modulator (e.g., M-QAM 616) to generate modulated data for transmission by a transmitter (e.g., transmitter circuitry 120).

[0122] In determining the code rate, the one or more processors may identify one or more code rates (e.g., Figure 9C R in c =5 / 6 and R c =7 / 8) to match the target ratio (e.g. Figure 9C R in target =0.83) to encode the data. The one or more processors may determine, for each of the one or more code rates, the number of parity bits to discard before modulation (e.g., Figure 9C For R c=5 / 6, the parity puncturing percentage is 28%, and for R c =7 / 8, parity puncturing percentage is 0%). The one or more processors may select a code rate (e.g., R ) corresponding to the minimum number of parity bits discarded before modulation (e.g., parity puncturing percentage of 0%) from among the one or more code rates. c =7 / 8).

[0123] Figure 10 1 is a diagram illustrating an example LDPC coded demodulation system 1000 according to one or more embodiments. The LDPC coded demodulation system 1000 may include a demodulator (e.g., an M-QAM -1 ) 1010, a stream demultiplexer 1020, a parity check puncture unit 1030, a multiplexer (MUX) 1040, an LDPC decoder 1050, a demultiplexer (DMUX) 1060, and a shaping decoder 1070. The demodulation system 1000 may be implemented in a baseband circuit system (e.g., baseband circuit system 150) or a receiver circuit system (e.g., receiver circuit system 140) of a communication system (e.g., communication system 108).

[0124] In some embodiments, a demodulator (e.g., M-QAM -1 ) 1010 may perform the inverse operation of the corresponding modulator (e.g., M-QAM 616) in the LDPC coded modulation system 600. In some embodiments, the stream deparser 1020 may perform the inverse operation of the corresponding stream parser 663 in the LDPC coded modulation system 600. In some embodiments, the parity check complement puncturer 1030 may perform the inverse operation of the corresponding parity check puncturer 615 in the LDPC coded modulation system 600. In some embodiments, the LDPC decoder 1050 may perform the inverse operation of the corresponding LDPC encoder 613 in the LDPC coded modulation system 600. In some embodiments, the reshaping decoder 1070 may perform the inverse operation of the corresponding reshaping encoder 630 in the LDPC coded modulation system 600.

[0125] refer to Figure 10 , demodulator (e.g., M-QAM -1 , where M=2m) may output an LLR value array 1011 of size 2m. For example, the LLR value array 1011 may include a first set of LLR values 1001, a second set of LLR values 1003, a first LLR value 1002, and a second LLR value 1004. In some implementations, assuming the number of spatial streams (N ss ) is two (N ss=2), the first set of LLR values 1001 of the LLR value array 1011 corresponds to one antenna (e.g., the first MIMO antenna), and the second set of LLR values 1003 of the bit array 1011 corresponds to another antenna (e.g., the second MIMO antenna). The stream inverse parser can receive multiple LLR value arrays 1011 (e.g., multiple streams of arrays 1011) and extract the first set of LLR values 1001 and the second set of LLR values 1003 to generate a matrix with (m-1) rows and (KL u ) / (m-1) columns of the matrix 1021. The demodulation system 1000 can generate (KL u ) LLR value array 1022 (eg, by serializing the matrix 1021). The demodulation system 1000 can extract the first LLR value 1002 and the second LLR value 1004 from the plurality of LLR value arrays 1011 to generate a LLR value of size (KL u ) / (m-1)=P-Δ LLR value array 1012. The parity check pruner 1030 may add (or pad) Δ values to the (P-Δ) LLR value array 1012 and generate a bit array 1031 of P (=NK) LLR values.

[0126] MUX 1040 can receive (KL u ) LLR values array 1022 and P LLR value bit array 1031, and generates N LLR values (e.g., codeword) 1041. The LDPC decoder can receive the N LLR values 1041 and generate the codeword according to the code rate R of the LDPC code used in the corresponding LDPC encoder 613 of the LDPC coded modulation system 600. c The N LLR values 1041 are decoded to generate K decoded bits 1051. The DMUX 1060 may receive the K decoded bits 1051 and generate (KL u ) Units digit 1061 and L u The units digit 1062. The shaping decoder 1070 can use the shaping code (eg, shaping code 700) to (KL u ) bits 1061 are decoded to generate decoded data 1071 (corresponding to Figure 6A The original input data 621 in).

[0127] Figure 11108. FIG1 is a flow chart showing a process 1100 for encoding and / or decoding data using a shaping code and an LDPC code according to an embodiment. In some embodiments, the process 1100 is performed by one or more processors of the first device (e.g., encoder 130 or processor 2010 of communication system 105, processor 2010 of communication system 108, modulation system 600). In other embodiments, the process 1100 is performed by other entities (e.g., computing systems other than communication systems 105 or 108). In some embodiments, the process 1100 includes a Figure 11 There may be more, fewer, or different steps than those shown in .

[0128] At step 1102, one or more processors may identify a code rate (e.g., R c =7 / 8). At step 1104, one or more processors may receive a set of information bits (e.g., K information bits 622) via an LDPC encoder (e.g., LDPC encoder 613). In some implementations, the set of information bits may include a first set of bits (e.g., shaped information bits 642) and a second set of bits (e.g., unshaped information bits 611). A shaping encoder (e.g., shaping encoder 630) may identify a shaping code (e.g., shaping code 700). The shaping encoder may encode the data using the shaping code to generate a first set of information bits (e.g., shaped information bits 642). The LDPC encoder may receive the first set of information bits from an output of the shaping encoder.

[0129] At step 1106, one or more processors may use a code rate (e.g., R c =7 / 8) encodes the set of information bits (eg, K information bits 622) to generate a set of coded bits (eg, (KL u ) coded bits 651) and a set of parity bits (e.g., P number of parity bits 624).

[0130] At step 1108, one or more processors may select from the set of encoded bits (eg, (KL u ) coded bits 651) to generate a bit array matrix (e.g., matrix 661). At step 1110, the one or more processors may discard one or more parity bits (e.g., Δ number of parity bits) from the set of parity bits (e.g., P number of parity bits 624) to generate a matrix of a size equal to the number of columns of the matrix (e.g., (KL u ) / (m-1)) of a parity bit array (eg, parity bit array 662).

[0131] At step 1112, one or more processors may generate a bit array (e.g., bit array 670) by concatenating (1) one or more bit arrays (e.g., first column 671 and second column 673) selected from a bit array matrix (e.g., matrix 661) and (2) one or more bits (e.g., first bit 672 and second bit 674) corresponding to the one or more bit arrays selected from a parity bit array (e.g., parity bit array 662).

[0132] In some implementations, when generating a bit array, a first column (e.g., first column 671) and a second column (e.g., second column 673) may be selected from a bit array matrix (e.g., matrix 661). A first bit (e.g., first bit 672) and a second bit (e.g., second bit 674) corresponding to the first column and the second column of the bit array matrix, respectively, may be selected from a parity bit array (e.g., parity bit array 662). The first column, the second column, the first bit, and the second bit may be concatenated to generate the bit array. The generated bit array may include, in sequence, the first column, the first bit, the second column, and the second bit. For example, as Figure 6C , bit array 670 includes, in sequence, a first column 671, a first bit 672, a second column 673, and a second bit 674. The first column and the second column may be randomly selected from the columns of the bit array matrix (e.g., by stream parser 663). The first column and the second column may be sequentially selected from the columns of the bit array matrix in the order of the columns of the bit array matrix.

[0133] At step 1114, the one or more processors may modulate the bit array (e.g., bit array 670) with a modulator (e.g., M-QAM 616) to generate modulated data for transmission by a transmitter (e.g., transmitter circuitry 120). In some implementations, the transmitter may transmit the modulated data.

[0134] In some implementations, when modulating the bit array, the modulator (e.g., M-QAM 616) may perform quadrature amplitude modulation using the number of bits per symbol (e.g., 2m) on the bit array (e.g., bit array 670) to generate modulated data. When generating the bit array matrix (e.g., matrix 661), the bit array matrix may be based on at least the number of bits per symbol (e.g., 2m) and the size of the set of coded bits (e.g., (KL)). u )) determines the number of columns of the bit array matrix (e.g., (KL u ) / (m-1) columns). The number of rows of the bit array matrix (e.g., m-1) may be determined based at least on the number of bits per symbol (e.g., 2m). The bit array (e.g., bit array 670) may have a size equal to the number of bits per symbol (e.g., 2m).

[0135] Figure 12A and Figure 12B1200 , 1220 are diagrams depicting example shaping codes (which may be included in a shaping codebook) according to one or more embodiments. Figure 12A Demonstrates the ability to achieve a shaping rate (R) of 0.8346 s ) and a shaping code 1200 for 4096-QAM with an LDPC code rate of 5 / 6, with the same spectral efficiency as MCS11. Shaping code 1200 may include multiple mappings (e.g., 32 mappings indexed 1207 from 0 to 31) from input binary data 1202 of length 1204 to output binary data 1203, each with different probabilities 1205. For example, using shaping code 1200, shaping encoder 630 may shape / map / convert / assign the input string [1110100] to the output string

[11001] with a probability of 1 / 128 (see Mapping 14). Figure 12B A histogram 1220 is shown depicting the probability distribution over mapping indices 1221 , codewords 1222 , and input data 1223 .

[0136] Figure 13A and Figure 13B 1300 , 1320 are diagrams depicting example shaping codes (which may be included in a shaping codebook) according to one or more embodiments. Figure 13A Demonstrated to achieve a shaping rate of 0.891 (R s ) and a shaping code 1300 for 4096-QAM with an LDPC code rate of 3 / 4 with the same spectral efficiency as MCS12. The shaping code 1300 may include multiple mappings (e.g., 32 mappings indexed 1307 from 0 to 31) from input binary data 1302 of length 1304 to output binary data 1303, each with different probabilities 1305. For example, using the shaping code 1300, the shaping encoder 630 may shape / map / convert / assign the input string [1111000] to the output string

[01110] with a probability of 1 / 128 (see mapping 20). Figure 13B A histogram 1320 depicting the probability distribution over mapping indices 1321 , codewords 1322 , and input data 1323 is shown.

[0137] Figure 14A and Figure 14B 1400 , 1420 are diagrams depicting example shaping codes (which may be included in a shaping codebook) according to one or more embodiments. Figure 14A Demonstrated to achieve a shaping rate of 0.91 (R s) and a shaping code 1400 for 4096-QAM with an LDPC code rate of 3 / 4 with the same spectral efficiency as MCS12. The shaping code 1400 may include multiple mappings (e.g., 32 mappings indexed 1407 from 0 to 31) from input binary data 1402 of length 1404 to output binary data 1403, each with different probabilities 1405. For example, using the shaping code 1400, the shaping encoder 630 may shape / map / convert / assign the input string [1111000] to the output string

[01110] with a probability of 1 / 128 (see mapping 20). Figure 14B A histogram 1420 depicting the probability distribution over mapping indices 1421 , codewords 1422 , and input data 1423 is shown.

[0138] Figure 15A and Figure 15B 1500 , 1520 are diagrams depicting example shaping codes (which may be included in a shaping codebook) according to one or more embodiments. Figure 15A Demonstrated to achieve a shaping rate of 0.686 (R s ) and a shaping code 1500 for 4096-QAM with an LDPC code rate of 5 / 6, with the same spectral efficiency as MCS9. The shaping code 1500 may include multiple mappings (e.g., 32 mappings indexed 1507 from 0 to 31) from input binary data 1502 of length 1504 to output binary data 1503, each with different probabilities 1505. For example, using the shaping code 1500, the shaping encoder 630 may shape / map / convert / assign the input string [1111000] to the output string

[11101] with a probability of 1 / 128 (see Mapping 9). Figure 15B A histogram 1520 depicting the probability distribution over mapping indices 1521 , codewords 1522 , and input data 1523 is shown.

[0139] Figure 16A and Figure 16B 1600 , 1620 are diagrams depicting example shaping codes (which may be included in a shaping codebook) according to one or more embodiments. Figure 16A Demonstrated to achieve a shaping rate of 0.83 (R s) and the same spectral efficiency as MCS9 for 1024-QAM with an LDPC code rate of 5 / 6. The shaping code 1600 may include multiple mappings (e.g., 16 mappings indexed 1607 from 0 to 15) from input binary data 1602 of length 1604 to output binary data 1603, each with different probabilities 1605. For example, using the shaping code 1600, the shaping encoder 630 may shape / map / convert / assign the input string [1111110] to the output string

[0011] with a probability of 1 / 128 (see Mapping 13). Figure 16B A histogram 1620 depicting the probability distribution over mapping indices 1621 , codewords 1622 , and input data 1623 is shown.

[0140] References to "or" may be interpreted as inclusive, such that any term described using "or" may mean any of a single, more than one, or all of the described items. References to at least one term in a term combination list may be interpreted as inclusive, or to indicate any of a single, more than one, and all of the described items. For example, reference to "at least one of 'A' and 'B'" may include only 'A', only 'B', and both 'A' and 'B'. Such references used in conjunction with "including" or other open-ended terms may include additional items.

[0141] It should be noted that certain paragraphs of this disclosure may refer to terms related to transmit spatial streams, sounding frames, responses, and subsets of devices (e.g., "first" and "second") to identify or distinguish one from another or one from others. These terms are not intended to relate entities (e.g., first and second devices) solely in time or order, although in some cases, these entities may include such a relationship. These terms also do not limit the number of possible entities (e.g., STAs, APs, beamformers, and / or beamformees) that may operate within a system or environment. It should be understood that the systems described above may provide multiple of any or each of these components, and these components may be provided on a standalone machine or, in some embodiments, on multiple machines in a distributed system. Furthermore, bit field positions may vary and multi-bit words may be used. In addition, the systems and methods described above can be provided as one or more computer-readable programs or executable instructions embodied on or in one or more articles of manufacture, such as a floppy disk, hard disk, CD-ROM, flash memory card, PROM, RAM, ROM, or magnetic tape. The programs can be implemented in any programming language (e.g., LISP, PERL, C, C++, C#) or in any bytecode language (e.g., JAVA). The software programs or executable instructions can be stored as object code on or in one or more articles of manufacture.

[0142] Although the foregoing written description of the methods and systems enables one of ordinary skill to make and use embodiments thereof, one of ordinary skill will understand and appreciate that there are variations, combinations, and equivalents of the specific embodiments, methods, and examples. Therefore, the methods and systems should not be limited to the above-described embodiments, methods, and examples, but rather to all embodiments and methods within the scope and spirit of the present disclosure.

Claims

1. A device comprising: A transmitter and one or more processors, wherein The one or more processors are configured to: Identify the code rate of low-density parity check LDPC codes; An LDPC encoder receives a set of information bits; encoding, by the LDPC encoder, the set of information bits using the code rate to generate a set of coded bits and a set of parity bits; generating a bit array matrix from the set of encoded bits; discarding one or more parity bits from the set of parity bits to generate a parity bit array having a size equal to the number of columns of the matrix; generating a bit array by concatenating (1) one or more bit arrays selected from the bit array matrix and (2) one or more bits corresponding to the one or more bit arrays selected from the parity bit array; and The bit array is modulated by a modulator to generate modulated data for transmission by the transmitter.

2. The apparatus of claim 1, wherein the transmitter is configured to transmit the modulated data.

3. The apparatus according to claim 1, wherein The group of information bits includes a first group of bits and a second group of bits; The one or more processors are configured to: The integer code is recognized by the integer encoder; encoding data using the shaping code by the shaping encoder to generate the first set of information bits; and The first set of information bits is received by the LDPC encoder from an output of the shaping encoder.

4. The apparatus according to claim 1, wherein In modulating the bit array, the one or more processors are configured to perform quadrature amplitude modulation using a number of bits per symbol on the bit array to generate the modulated data; and In generating the bit array matrix, the one or more processors are configured to: determining the number of columns of the bit array matrix based at least on the number of bits per symbol and a size of the set of encoded bits; and The number of rows of the bit array matrix is determined based on at least the number of bits per symbol.

5. The apparatus of claim 4, wherein the bit array has a size equal to the number of bits per symbol.

6. The apparatus of claim 1 , wherein in generating the bit array, the one or more processors are configured to: selecting a first column and a second column from the bit array matrix; and selecting a first bit and a second bit corresponding to the first column and the second column of the bit array matrix, respectively, from the parity bit array; and The first column, the second column, the first bit, and the second bit are concatenated to generate the bit array.

7. The apparatus of claim 6, wherein the generated bit array comprises, in sequence, the first column, the first bit, the second column, and the second bit.

8. The apparatus of claim 6, wherein the first column and the second column are randomly selected from columns of the bit array matrix.

9. The apparatus of claim 6, wherein the first column and the second column are selected sequentially from the columns of the bit array matrix in the order of the columns of the bit array matrix.

10. A method comprising: identifying, by the one or more processors, a code rate of a low-density parity check (LDPC) code; An LDPC encoder receives a set of information bits; encoding, by the LDPC encoder, the set of information bits using the code rate to generate a set of coded bits and a set of parity bits; generating a bit array matrix from the set of encoded bits; discarding, by the one or more processors, one or more parity bits from the set of parity bits to generate an array of parity bits having a size equal to the number of columns of the matrix; generating, by the one or more processors, a bit array by concatenating (1) one or more bit arrays selected from the bit array matrix and (2) one or more bits corresponding to the one or more bit arrays selected from the parity bit array; and The bit array is modulated by a modulator to generate modulated data for transmission by the transmitter.

11. The method according to claim 10, further comprising: The modulated data is transmitted by a transmitter.

12. The method according to claim 10, wherein The group of information bits includes a first group of bits and a second group of bits; The method comprises: The integer code is recognized by the integer encoder; encoding data using the shaping code by the shaping encoder to generate the first set of information bits; and The first set of information bits is received by the LDPC encoder from an output of the shaping encoder.

13. The method according to claim 10, wherein Modulating the bit array includes performing, by the modulator, quadrature amplitude modulation using a number of bits per symbol on the bit array to generate the modulated data; Generating the bit array matrix includes: determining the number of columns of the bit array matrix based at least on the number of bits per symbol and a size of the set of encoded bits; and The number of rows of the bit array matrix is determined based on at least the number of bits per symbol. The method of claim 13 , wherein the bit array has a size equal to the number of bits per symbol.

15. The method of claim 10, wherein generating the bit array comprises: selecting a first column and a second column from the bit array matrix; and selecting a first bit and a second bit corresponding to the first column and the second column of the bit array matrix, respectively, from the parity bit array; and The first column, the second column, the first bit, and the second bit are concatenated to generate the bit array.

16. The method of claim 15, wherein the generated bit array comprises, in sequence, the first column, the first bit, the second column, and the second bit.

17. The method of claim 15, wherein the first column and the second column are randomly selected from columns of the bit array matrix.

18. The method of claim 15, wherein the first column and the second column are sequentially selected from the columns of the bit array matrix in the order of the columns of the bit array matrix.

19. An apparatus comprising: transmitter; and One or more processors configured to: identifying a target bit rate for encoding the data; determining a code rate of a low-density parity check (LDPC) code and a number of unshaped bits to encode the data at the target code rate; receiving, by an LDPC encoder, the data comprising shaped bits generated by a shaping encoder and a set of unshaped bits of size equal to the number, and encoding the data using the code rate to generate a matrix of coded bits and a set of parity bits; discarding one or more parity bits from the set of parity bits based at least on the number to generate an array of parity bits; generating a bit array by concatenating (1) one or more bit arrays obtained from a column of the matrix and (2) one or more bits corresponding to the one or more bit arrays obtained from the parity bit array; and The bit array is modulated by the modulator to generate modulated data for transmission by a transmitter.

20. The apparatus of claim 19, wherein in determining the code rate, the one or more processors are configured to: identifying one or more code rates for encoding the data at the target rate; For each of the one or more code rates, determining a number of parity bits discarded prior to the modulation; and A code rate is selected from among the one or more code rates corresponding to a minimum number of parity bits discarded prior to the modulation.

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