Tunneling oxide passivation contact cells, photovoltaic modules and methods of making same

Abstract

The invention relates to the field of solar cells, particularly provides a tunneling oxide layer passivation contact cell, a photovoltaic module and a manufacturing method thereof, and aims to solve the problem that the open-circuit voltage of the cell is reduced due to the fact that excessive hydrogen is gathered on the interface of polycrystalline silicon and silicon oxide to form a new recombination center. In order to achieve the purpose, the tunneling oxide layer passivation contact cell comprises a silicon substrate, a tunneling oxide layer, a first doped polycrystalline silicon layer, a dielectric layer, a second doped polycrystalline silicon layer and a passivation layer are sequentially arranged on the back face of the silicon substrate, and the interface of the dielectric layer has a defect state; the defect state can capture hydrogen atoms released by the first doped polycrystalline silicon layer, the second doped polycrystalline silicon layer and the passivation layer. The defect state on the dielectric layer can capture a part of hydrogen released in the sintering process, the number of hydrogen atoms gathered on a polycrystalline silicon and / or silicon oxide interface is reduced, formation of a new recombination center is inhibited, and the influence of excessive gathering of hydrogen atoms on open-circuit voltage is weakened.

Description

Technical Field

[0001] The present invention relates to the field of solar cells, and in particular provides a tunneling oxide layer passivation contact cell, a photovoltaic module and a manufacturing method thereof. Background Art

[0002] Existing tunnel oxide passivated contact cells consist of crystalline silicon, silicon oxide (tunnel oxide), and polysilicon, arranged in that order. The silicon oxide layer passivates dangling bonds at the interface between the crystalline silicon and silicon oxide, while also preventing dopant atoms from the polysilicon from diffusing into the crystalline silicon. In industrial production, an AlOx / SiNx passivation layer is typically deposited on top of the polysilicon. Both the polysilicon layer and the AlOx / SiNx passivation layer decompose during the high-temperature sintering step of the subsequent screen-printed metallization process, releasing a large amount of hydrogen atoms. This hydrogen is intended to diffuse into the polysilicon and crystalline silicon to repair dangling bonds and reduce recombination. However, in phosphorus-doped N-type polysilicon, hydrogen tends to exist in a positively charged form. Because phosphorus doping introduces free electrons, positively charged hydrogen is attracted to these electrons. This causes excess hydrogen to accumulate at the polysilicon and / or silicon oxide interfaces, forming new recombination centers and lowering the cell's open-circuit voltage (iVoc).

[0003] In existing technology, by increasing the annealing temperature during the preparation of phosphorus-doped polysilicon and increasing the depth of dopant atom diffusion, the field passivation effect determined by the dopant atoms becomes dominant in the phosphorus-doped polysilicon structure, thereby reducing the proportion of chemical passivation determined by hydrogen atoms in the passivation effect of the phosphorus-doped polysilicon structure and preventing a decrease in open-circuit voltage. Furthermore, by lowering the sintering temperature or extending the light injection / dark annealing time, excess hydrogen can escape over a long period (tens of minutes) at temperatures of approximately 200-300°C, reducing the hydrogen content at the poly Si / SiOx interface and improving passivation quality.

[0004] The above method weakens the influence of chemical passivation by improving the field passivation effect, but increasing the annealing temperature will lead to the deterioration of the quality of the tunneling oxide layer between the polysilicon and the silicon substrate, and excessive internal expansion depth will also aggravate the deterioration of the passivation quality, resulting in a decrease in open-circuit voltage; in addition, lowering the sintering temperature or extending the light injection / dark annealing time is difficult to match with the wire mesh segment metal and is time-consuming, making it difficult to achieve in actual production.

[0005] Accordingly, this field requires a new technical problem to solve the above problems. Summary of the Invention

[0006] The present invention aims to solve the above-mentioned technical problem, namely, to address the problem of reduced open-circuit voltage of a battery due to excess hydrogen accumulation at the interface between polysilicon and silicon oxide, forming new recombination centers. To this end, the present invention provides a tunneling oxide layer passivated contact battery, comprising: a silicon substrate, a tunneling oxide layer, a first doped polysilicon layer, a second doped polysilicon layer, and a passivation layer disposed in sequence on the back side of the silicon substrate; and a dielectric layer disposed between the first doped polysilicon layer and the second doped polysilicon layer, wherein the dielectric layer has defect states at its interface, wherein the defect states are capable of capturing hydrogen atoms released by the first doped polysilicon layer, the second doped polysilicon layer, and the passivation layer.

[0007] In the above embodiment of the cell with tunneling oxide layer passivation contact, the thickness of the dielectric layer is 1-3 nm.

[0008] In the above embodiment of the cell with tunneling oxide passivation contact, the density of defect states on the dielectric layer interface is: .

[0009] In the above embodiment of the cell with tunneling oxide layer passivation contact, the defect state density on the dielectric layer interface is: .

[0010] In the above embodiment of the cell with tunneling oxide layer passivation contact, the dielectric layer is made of any one of silicon oxide, silicon nitride, silicon carbide or titanium dioxide.

[0011] In the above-mentioned specific embodiment of the tunneling oxide layer passivated contact cell, the material of the dielectric layer is phosphorus-doped silicon oxide, and the phosphorus-doped silicon oxide is deposited using silane, phosphine and oxygen source gas, and the oxygen source gas includes one or more of oxygen, nitrous oxide and ozone.

[0012] In the above embodiment of the cell with tunnel oxide passivation contact, the second doped polysilicon layer is a phosphorus-doped polysilicon layer, wherein the phosphorus doping concentration range is: .

[0013] In the above embodiment of the cell with tunnel oxide passivation contact, the doping concentration of phosphorus in the second doped polysilicon layer is in the range of: .

[0014] The present invention further provides a photovoltaic module, comprising any one of the tunneling oxide layer passivation contact cells described above.

[0015] The present invention also provides a method for manufacturing a tunneling oxide layer passivation contact cell, the manufacturing method comprising the following steps: depositing a tunneling oxide layer and a first doped amorphous silicon layer in sequence on a silicon substrate; depositing a dielectric layer on the first doped amorphous silicon layer; depositing a second doped amorphous silicon layer on the dielectric layer; Annealing is performed to crystallize the first doped amorphous silicon layer and the second doped amorphous silicon layer into a first doped polysilicon layer and a second doped polysilicon layer.

[0016] In the case of adopting the above-mentioned technical solution, the present invention provides a dielectric layer between the first doped polysilicon layer and the second doped polysilicon layer. Excess hydrogen atoms released during the sintering process of the first doped polysilicon layer, the second doped polysilicon layer, and the passivation layer are partially captured by defect states in the dielectric layer, preferentially saturating the defect states at the interface between the dielectric layer and the first doped polysilicon layer and the second doped polysilicon layer. This reduces the number of hydrogen atoms accumulated at the polysilicon and / or silicon oxide interface, inhibits the formation of new recombination centers, and thus reduces the impact of excessive hydrogen atom accumulation on the open circuit voltage. Compared with the prior art methods of increasing the annealing temperature, lowering the sintering temperature, or extending the light injection / dark annealing time when preparing phosphorus-doped polysilicon, the cell structure with a dielectric layer in this embodiment does not require increasing the polysilicon annealing temperature, can avoid tunneling damage to the oxide layer, and does not require long light injection / dark annealing, additional equipment, or changes to the existing screen printing process, greatly improving the feasibility of application in actual production. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The preferred embodiments of the present invention are described below with reference to the accompanying drawings, in which: Figure 1 It is a schematic diagram of the structure of the tunnel oxide passivation contact cell in the invention; Figure 2 This is a flow chart of the method for manufacturing a tunnel oxide layer passivation contact cell in the invention.

[0018] In the figure: 1. Silicon substrate, 2. Front polysilicon layer, 3. Front passivation anti-reflection layer, 4. Tunneling oxide layer, 5. First doped polysilicon layer, 6. Dielectric layer, 7. Second doped polysilicon layer, 8. Passivation layer, 9. Front gate line, 10. Back gate line. DETAILED DESCRIPTION

[0019] Preferred embodiments of the present invention are described below with reference to the accompanying drawings. Those skilled in the art should understand that these embodiments are intended only to illustrate the technical principles of the present invention and are not intended to limit the scope of protection of the present invention. Those skilled in the art may adjust these embodiments as needed to suit specific applications.

[0020] It should be noted that, in the description of the present invention, terms such as "upper," "lower," "left," "right," "inner," and "outer" indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings. These are used solely for ease of description and are not intended to indicate or imply that the relevant devices or components must have, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention. Furthermore, ordinal numbers such as "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0021] Furthermore, it should be noted that, in the description of the present invention, unless otherwise expressly specified or limited, the terms "mounted" and "connected" should be understood in a broad sense. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; and direct or indirect connections through an intermediary. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0022] Furthermore, in order to more clearly demonstrate the core technical solution of the present invention, the description of the well-known structures of solar cells is omitted in the following description. However, this omission is only for the convenience of description and does not mean that solar cells can be without these structures.

[0023] like Figure 1 As shown, the present invention proposes a tunneling oxide passivation contact cell, comprising: a silicon substrate 1, on one side of which are sequentially provided a tunneling oxide layer 4, a first doped polysilicon layer 5, a second doped polysilicon layer 7, and a passivation layer 8. The first doped polysilicon layer 5 and the second doped polysilicon layer 7 may both be phosphorus-doped polysilicon layers, wherein the doping concentration of the first doped polysilicon layer 5 is lower than the doping concentration of the second doped polysilicon layer 7. The silicon substrate 1 also comprises: a dielectric layer 6, disposed between the first doped polysilicon layer 5 and the second doped polysilicon layer 7. The dielectric layer 6 has defect states at its interface, which can capture hydrogen atoms released from the first doped polysilicon layer 5, the second doped polysilicon layer 7, and the passivation layer 8. The passivation layer 8 may be made of silicon nitride (SiNx), which primarily serves as a passivation layer and may also provide a certain anti-reflection effect.

[0024] In this embodiment, in order to solve the problem of a decrease in the open-circuit voltage of the battery due to excessive accumulation of hydrogen released from the passivation layer 8 at the interface of polysilicon and / or silicon oxide (tunneling through the oxide layer 4) to form new recombination centers, a dielectric layer 6 is provided between the first doped polysilicon layer 5 and the second doped polysilicon layer 7. Excess hydrogen atoms released by the first doped polysilicon layer 5, the second doped polysilicon layer 7, and the passivation layer 8 during the sintering process will be partially captured by defect states on the dielectric layer 6, preferentially saturating the defect states at the interface between the dielectric layer 6 and the first doped polysilicon layer 5 and the second doped polysilicon layer 7, thereby reducing the number of hydrogen atoms accumulated at the interface of polysilicon and / or silicon oxide, inhibiting the formation of new recombination centers, and thus weakening the effect of excessive accumulation of hydrogen atoms on the open-circuit voltage.

[0025] A certain amount of defect states (such as oxygen vacancies, dangling bonds, etc.) are introduced into the structure of the dielectric layer 6. The defect sites have a chemical affinity for hydrogen atoms (such as forming Si-H bonds, OH bonds, etc.) and thereby stabilize and bind the hydrogen atoms to prevent them from diffusing and escaping again.

[0026] In this embodiment, a portion of hydrogen is captured by defect states on the interface of the dielectric layer 6, thereby solving the problem of reduced open-circuit voltage of the battery due to excessive hydrogen accumulation at the polysilicon and / or silicon oxide interface to form new recombination centers. Compared with the prior art method of increasing the annealing temperature, lowering the sintering temperature, or extending the light injection / dark annealing time when preparing phosphorus-doped polysilicon, the battery structure with the dielectric layer 6 in this embodiment does not need to increase the polysilicon annealing temperature, can avoid damage to the tunneling oxide layer 4, and does not require long-term light injection / dark annealing, additional equipment, or changes to the existing screen printing process, thereby greatly improving the feasibility of application in actual production.

[0027] like Figure 1 As shown, the tunneling oxide passivation contact cell also includes: a front polysilicon layer 2 and a front passivation anti-reflection layer 3 sequentially arranged on the silicon substrate 1 in a direction away from the silicon substrate 1, the front polysilicon layer 2 can be a boron-doped polysilicon layer, that is, a front emitter, and the front passivation anti-reflection layer 3 is composed of a front passivation layer and a front anti-reflection layer sequentially arranged in a direction away from the silicon substrate 1, the front passivation layer can be aluminum oxide, and the front anti-reflection layer can be a silicon nitride layer; it also includes a front gate line 9 and a back gate line 10, the bottom of the front gate line 9 is arranged on the front polysilicon layer 2, and the top of the front gate line 9 extends in a direction away from the silicon substrate 1 to penetrate the front passivation anti-reflection layer 3, and the front gate line 9 can be a silver-aluminum gate line; the bottom of the back gate line 10 is arranged on the first doped polysilicon layer 5, and the top of the back gate line 10 extends in a direction away from the silicon substrate 1 to penetrate the passivation layer 8 arranged on the back of the silicon substrate 1, and the back gate line 10 can be a silver gate line.

[0028] Taking phosphorus-doped silicon oxide as the dielectric layer 6 as an example, a set of control experiments was set up to illustrate the effect of the dielectric layer 6. Among them, the cell layer structure of the tunnel oxide passivation contact cell in the experimental group is: silicon substrate 1, the front side of the silicon substrate 1 is sequentially provided with a front polysilicon layer 2, a front passivation anti-reflection layer 3 and a front gate line 9, and the back side of the silicon substrate 1 is sequentially provided with a tunnel oxide layer 4, a first doped polysilicon layer 5, a dielectric layer 6, a second doped polysilicon layer 7, a passivation layer 8 and a back gate line 10. The thickness of the dielectric layer 6 is 1.8 nm, and the carrier lifetime (τ) test is obtained. , according to the formula The interface defect state density of the dielectric layer 6 can be calculated as (For n-type silicon ).

[0029] The cell layer structure of the tunnel oxide passivated contact cell in the control group is as follows: a silicon substrate 1, with a front polysilicon layer 2, a front passivation anti-reflection layer 3, and a front gate line 9 disposed on the front side of the silicon substrate 1 in this order; and a tunnel oxide layer 4, a first doped polysilicon layer 5, a second doped polysilicon layer 7, a passivation layer 8, and a back gate line 10 disposed on the back side of the silicon substrate 1 in this order. To control for variables, the only difference between the control and experimental groups in the cell layer structure is the presence of a dielectric layer 6 in the experimental group, while the control group lacks one. Otherwise, the cell manufacturing methods, formation conditions of the various layer structures, and thicknesses were identical in the experimental and control groups.

[0030] Under the same environment, the open circuit voltage iVoc of the cells in the experimental group and the control group were tested before and after sintering. The open circuit voltage iVoc of the cells in the experimental group did not decline before and after sintering, while the open circuit voltage iVoc of the cells in the control group declined to a certain extent. In addition, the secondary ion mass spectra of the two cells after sintering were tested, and the area near the silicon oxide was integrated to describe the hydrogen concentration. The hydrogen concentration at the polysilicon and silicon oxide in the control group was In the experimental group, due to the presence of dielectric layer 6, the hydrogen concentration dropped to This set of control experiments fully demonstrates that the dielectric layer 6 in this embodiment can reduce the excessive accumulation of hydrogen at the interface between polysilicon and silicon oxide, thereby solving the problem of open circuit voltage reduction caused by hydrogen accumulation.

[0031] It should be noted that although the layered structure of the tunneling oxide passivation contact cell in this embodiment is: a silicon substrate 1, the front side of the silicon substrate 1 is sequentially provided with a front polysilicon layer 2, a front passivation anti-reflection layer 3 and a front gate line 9, and the back side of the silicon substrate 1 is sequentially provided with a tunneling oxide layer 4, a first doped polysilicon layer 5, a dielectric layer 6, a second doped polysilicon layer 7, a passivation layer 8 and a back gate line 10, but this is not a limitation of the present invention. The change in the layered structure of the cell is not the focus of the present invention. Without departing from the basic principles of the present invention, those skilled in the art can adopt cells with other layered structures, as long as the dielectric layer 6 is provided between the first doped polysilicon layer 5 and the second doped polysilicon layer 7. For example, removing or adding a certain layered structure does not deviate from the principles of the present invention and therefore will fall within the scope of protection of the present invention.

[0032] Furthermore, the thickness of dielectric layer 6 is 1-3 nm. In this embodiment, dielectric layer 6 is introduced to allow defect states at its interface to capture hydrogen atoms, so the thickness of dielectric layer 6 does not need to be excessively thick. The thickness of dielectric layer 6 is preferably 1-1.8 nm. It should be noted that those skilled in the art can adjust the thickness of dielectric layer 6 according to actual conditions, as long as it does not affect the capture of hydrogen atoms by defect states at the interface of dielectric layer 6.

[0033] Furthermore, the density of defect states on the interface of dielectric layer 6 is: , that is, on the interface of the dielectric layer 6, the unit area And the number of interface defect states within a unit energy range eV is .

[0034] In this embodiment, dielectric layer 6 is designed to introduce defect states to capture hydrogen atoms. If the density of defect states at the interface of dielectric layer 6 is too low, the number of captured hydrogen atoms will decrease, and the effect of reducing hydrogen atom aggregation at the polysilicon and silicon oxide interface will be ineffective. If the density of defect states at the interface of dielectric layer 6 is too high, an excessive number of captured hydrogen atoms will result, resulting in a decrease in the number of hydrogen atoms diffusing into polysilicon and crystalline silicon. Consequently, the purpose of allowing hydrogen atoms to repair dangling bonds in silicon and reduce recombination cannot be achieved. To control the number of hydrogen atoms captured by dielectric layer 6 and avoid other impacts of dielectric layer 6 on the battery, the density of defect states in dielectric layer 6 is limited to the above range.

[0035] Furthermore, the density of defect states on the interface of the dielectric layer 6 is preferably: , that is, on the interface of the dielectric layer 6, the unit area ( ) and the number of interface defect states within a unit energy range (eV) is It should be noted that those skilled in the art can adjust the defect state density on the interface of the dielectric layer 6 according to actual conditions.

[0036] Furthermore, the material of dielectric layer 6 can be selected from any of silicon oxide, silicon nitride, silicon carbide, or titanium dioxide. The silicon oxide can be phosphorus-doped silicon oxide or boron-doped silicon oxide. These materials can effectively introduce a certain amount of defect states for trapping hydrogen atoms. It should be noted that those skilled in the art can choose other materials as long as they can form defect states at the interface of dielectric layer 6 for trapping hydrogen atoms.

[0037] Dielectric layer 6 is preferably made of phosphorus-doped silicon oxide, which is deposited using silane, phosphine, and an oxygen source gas. The oxygen source gas may include one or more of oxygen, nitrous oxide, and ozone. Phosphine-doped silicon oxide can be deposited at 2000-3000 sccm of silane (SiH4), 10,000-13,000 sccm of nitrous oxide (N2O), and 1-1000 sccm of phosphine (PH3).

[0038] Furthermore, in this embodiment, the second doped polysilicon layer 7 is a high-concentration phosphorus-doped polysilicon layer. In order to further reduce the aggregation of hydrogen atoms at the interface between polysilicon and silicon oxide, the phosphorus doping concentration of the second doped polysilicon layer 7 is increased, wherein the phosphorus doping concentration range is: .

[0039] For the second doped polysilicon layer 7, the higher the doping concentration is, the higher the crystallinity of the polysilicon film is. The hydrogen atoms therein are mainly SiH2 and The existence of hydrogen in the form of bonds indicates that the proportion of bonded hydrogen in the polysilicon layer increases, thereby reducing the number of hydrogen atoms released from the polysilicon layer during the annealing process; on the other hand, the polysilicon film with a high doping concentration is porous, and the higher the porosity of the film, the more hydrogen is captured.

[0040] Generally, it's difficult to increase the phosphorus doping concentration in polysilicon because such an increase can degrade the passivation performance of the tunneling oxide layer 4. In this embodiment, due to the presence of the dielectric layer 6, the phosphorus doping concentration of the second doped polysilicon layer 7 can be further increased to further reduce the total amount of released hydrogen. In this embodiment, the dielectric layer 6 and the second doped polysilicon layer 7 with an increased phosphorus doping concentration jointly suppress the drop in open-circuit voltage caused by excessive hydrogen accumulation at the polysilicon-silicon oxide interface, forming new recombination centers.

[0041] Furthermore, in the second doped polysilicon layer 7, the doping concentration range of phosphorus is preferably: It should be noted that those skilled in the art can adjust the doping concentration range of phosphorus in the second doped polysilicon layer 7 according to actual conditions.

[0042] A photovoltaic module comprises any one of the above tunnel oxide layer passivation contact cells.

[0043] A method for manufacturing a tunneling oxide passivation contact cell comprises the following steps: depositing a tunneling oxide layer 4 and a first doped amorphous silicon layer on a silicon substrate 1 in sequence; depositing a dielectric layer 6 on the first doped amorphous silicon layer; depositing a second doped amorphous silicon layer on the dielectric layer 6; and annealing to crystallize the first doped amorphous silicon layer and the second doped amorphous silicon layer into a first doped polysilicon layer 5 and a second doped polysilicon layer 7.

[0044] Prior to the step of depositing a tunneling oxide layer 4 on the silicon substrate 1, the manufacturing method further includes: performing double-sided alkaline texturing on the n-type single-crystal silicon substrate 1. After texturing, both the front and back surfaces of the silicon substrate 1 exhibit a pyramidal morphology of 0.5 to 5 μm. A front polysilicon layer 2 is formed on the front surface of the silicon substrate 1. Specifically, BBr3 or BCl3 is used as a boron source to form a boron-doped layer at 900 to 1100°C for 15 to 30 minutes, followed by oxidation for 45 to 70 minutes to form borosilicate glass (BSG). The BSG plated on the back and side surfaces and the polysilicon remaining from the back boron diffusion are cleaned to prepare for the back deposition of the tunneling oxide layer 4 and other layered structures. Specifically, HF is used to remove the BSG plated on the back and side surfaces of the silicon wafer obtained in the previous step, and alkaline polishing is performed to remove the polysilicon plated on the back and side surfaces.

[0045] After the post-annealing step, the manufacturing method further comprises the following steps: Remove the silicon oxide mask and polysilicon from the front and side surfaces (during PECVD deposition of the first / second doped amorphous silicon layers, amorphous silicon may form on the front surface due to wraparound deposition, and subsequent annealing will crystallize the polysilicon on the front surface) to avoid affecting the subsequent preparation of the front passivation anti-reflection layer 3. Specifically, use HF and RCA cleaning to remove the silicon oxide mask and polysilicon from the front and side surfaces of the silicon wafer obtained in the previous step.

[0046] A front-side passivation anti-reflection layer 3 is deposited on the front polysilicon layer 2, and a passivation layer 8 is deposited on the back side. Specifically, 2-10 nm of aluminum oxide is deposited on the front side using ALD (Atomic Layer Deposition), and the front-side passivation anti-reflection layer 3 and passivation layer 8 are deposited on the front and back sides, respectively, using PECVD. The front-side passivation anti-reflection layer 3 comprises three layers of SiNx and two layers of SiNOx, with a total thickness of 70-85 nm and a refractive index of 1.9-2.2. The passivation layer 8 is SiNx with a total thickness of 80-95 nm and a refractive index of 1.9-2.2. Passivation layer 8 primarily serves as a passivation layer and may also provide a certain degree of anti-reflection.

[0047] Silver paste is printed and sintered to form front-side gate lines 9 and back-side gate lines 10. Specifically, silver paste is printed on both the front and back sides of the silicon wafer obtained in the previous step and sintered at a temperature of 800-900°C. Front-side gate lines 9 penetrate the front-side passivation anti-reflection layer 3 and contact the front-side polysilicon layer 2. Back-side gate lines 10 penetrate the passivation layer 8, the second doped polysilicon layer 7, and the dielectric layer 6 and contact the first doped polysilicon layer 5.

[0048] Furthermore, “sequentially depositing a tunneling oxide layer 4 and a first doped amorphous silicon layer on the silicon substrate 1” specifically includes: first forming a tunneling oxide layer 4 on the back side of the silicon substrate 1 by plasma enhanced chemical vapor deposition (PECVD), wherein the tunneling oxide layer 4 is deposited at a temperature of 415°C to 435°C, a nitrous oxide (N2O) flow rate of 11,000 to 15,000 sccm (i.e., 11,000 to 15,000 standard cubic centimeters of nitrous oxide is introduced into the reaction chamber per minute), and a vacuum pressure in the reaction chamber of 1,700 to 2,000 mTorr; the thickness of the tunneling oxide layer 4 can be controlled to be 1 to 1.8 nm. A temperature of 415°C to 435°C can promote the formation of silicon oxide while avoiding thermal damage to the silicon substrate 1. Nitrous oxide, as an oxygen source, decomposes into active oxygen species under the action of plasma, and reacts with the silicon substrate 1 to form a tunneling oxide layer 4. At the same time, the thickness of the generated tunneling oxide layer 4 is precisely controlled by controlling the deposition time (usually several seconds to tens of seconds) and the gas flow rate, so that the thickness of the tunneling oxide layer 4 is within the range of 1 to 1.8 nm.

[0049] Next, a first doped amorphous silicon layer is deposited on the tunneling oxide layer 4. The first doped amorphous silicon layer is deposited under the following conditions: a phosphine (PH3) flow rate of 125 to 350 sccm (i.e., 125 to 350 standard cubic centimeters of phosphine is introduced into the reaction chamber per minute), a silane (SiH4) flow rate of 8,000 to 10,000 sccm (i.e., 8,000 to 10,000 standard cubic centimeters of silane is introduced into the reaction chamber per minute), and a vacuum pressure in the reaction chamber of 2,700 to 3,100 mTorr. The thickness of the first doped amorphous silicon layer can be controlled to be 30 to 50 nm.

[0050] Furthermore, when the material of the dielectric layer 6 is phosphorus-doped silicon oxide, “depositing the dielectric layer 6 on the first doped amorphous silicon layer” specifically includes: depositing the dielectric layer 6 (phosphorus-doped silicon oxide layer) under the conditions of a silane (SiH4) flow rate of 2000 to 3000 sccm (i.e., 2000 to 3000 standard cubic centimeters of silane are introduced into the reaction chamber per minute), a nitrous oxide (N2O) flow rate of 10,000 to 13,000 sccm (i.e., 10,000 to 13,000 standard cubic centimeters of nitrous oxide are introduced into the reaction chamber per minute), and a phosphine (PH3) flow rate of 1 to 1000 sccm (i.e., 1 to 1000 standard cubic centimeters of phosphine are introduced into the reaction chamber per minute); the thickness of the dielectric layer 6 is controlled to be 1 to 1.8 nm.

[0051] Furthermore, “depositing a second doped amorphous silicon layer on the dielectric layer 6” specifically includes: depositing the second doped amorphous silicon layer under the following conditions: a phosphine (PH3) flow rate of 350 to 700 sccm (i.e., 350 to 700 standard cubic centimeters of phosphine are introduced into the reaction chamber per minute), a silane (SiH4) flow rate of 8000 to 10000 sccm (i.e., 8000 to 10000 standard cubic centimeters of silane are introduced into the reaction chamber per minute), and a vacuum pressure in the reaction chamber of 2700 to 3100 mTorr; the second doped amorphous silicon layer has a thickness of 50 to 80 nm.

[0052] The manufacturing method also includes the following steps: prior to annealing, depositing a silicon oxide mask on the second doped amorphous silicon layer; depositing the silicon oxide mask at a silane (SiH4) flow rate of 2,000 to 3,000 sccm and a nitrous oxide (N2O) flow rate of 10,000 to 13,000 sccm; the silicon oxide mask has a thickness of 20 to 40 nm. The silicon oxide mask serves to temporarily protect the backside layer from damage during subsequent processing and must be removed after use.

[0053] Furthermore, “annealing to crystallize the first doped amorphous silicon layer and the second doped amorphous silicon layer into the first doped polysilicon layer 5 and the second doped polysilicon layer 7” specifically includes: annealing at 880-920° C. to crystallize the first doped amorphous silicon layer and the second doped amorphous silicon layer into the first doped polysilicon layer 5 and the second doped polysilicon layer 7, thereby activating phosphorus atoms and advancing the junction depth.

[0054] like Figure 2 As shown, in a possible embodiment, the manufacturing method is specifically the following steps: S1: performing double-sided texturing on the silicon substrate 1 .

[0055] S2: forming a front polysilicon layer 2 on the front surface of the silicon substrate 1; S3: Clean the BSG on the back and side and the poly silicon remaining from the boron diffusion on the back; S4: depositing a tunneling oxide layer 4, a first doped amorphous silicon layer, a dielectric layer 6, a second doped amorphous silicon layer and a silicon oxide mask in sequence on the silicon substrate 1.

[0056] S5 : Annealing to crystallize the first doped amorphous silicon layer and the second doped amorphous silicon layer into a first doped polysilicon layer 5 and a second doped polysilicon layer 7 .

[0057] S6: Remove the silicon oxide mask on the front and side surfaces and the poly silicon formed after PECVD coating on the front.

[0058] S7: depositing a front passivation anti-reflection layer 3 on the front polysilicon layer 2 and a passivation layer 8 on the back surface.

[0059] S8: Printing silver paste and sintering to form front grid lines 9 and back grid lines 10.

[0060] Those skilled in the art will appreciate that although some embodiments described herein include certain features included in other embodiments but not other features, combinations of features from different embodiments are intended to be within the scope of this application and to form different embodiments. For example, in the claims of this application, any of the claimed embodiments may be used in any combination.

[0061] Thus far, the technical solutions of the present invention have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it will be readily understood by those skilled in the art that the scope of protection of the present invention is obviously not limited to these specific embodiments. Without departing from the principles of the present invention, those skilled in the art may make equivalent changes or substitutions to the relevant technical features, and the technical solutions after such changes or substitutions will fall within the scope of protection of the present invention.

Claims

1. A tunneling oxide layer passivation contact cell, comprising: A silicon substrate (1), wherein a tunneling oxide layer (4), a first doped polysilicon layer (5), a second doped polysilicon layer (7) and a passivation layer (8) are sequentially provided on the back side of the silicon substrate (1), and the silicon substrate (1) is characterized in that it further comprises: a dielectric layer (6), wherein the dielectric layer (6) is provided between the first doped polysilicon layer (5) and the second doped polysilicon layer (7), and the dielectric layer (6) has a defect state at its interface, wherein the defect state can capture hydrogen atoms released by the first doped polysilicon layer (5), the second doped polysilicon layer (7) and the passivation layer (8).

2. The tunneling oxide passivation contact cell according to claim 1, characterized in that: The thickness of the dielectric layer (6) is 1-3 nm.

3. The tunneling oxide passivation contact cell according to claim 1, characterized in that: The density of defect states on the interface of the dielectric layer (6) is: 。 4. The tunneling oxide passivation contact cell according to claim 3, characterized in that: The defect state density on the interface of the dielectric layer (6) is: 。 5. The tunneling oxide passivation contact cell according to claim 1, characterized in that: The material of the dielectric layer (6) is any one of silicon oxide, silicon nitride, silicon carbide or titanium dioxide.

6. The tunneling oxide passivation contact cell according to claim 5, characterized in that: The material of the dielectric layer (6) is phosphorus-doped silicon oxide, and the phosphorus-doped silicon oxide is deposited using silane, phosphine and an oxygen source gas, wherein the oxygen source gas includes one or more of oxygen, nitrous oxide and ozone.

7. The tunnel oxide passivation contact cell according to any one of claims 1 to 6, characterized in that: The second doped polysilicon layer (7) is a phosphorus-doped polysilicon layer, wherein the phosphorus doping concentration range is: 。 8. The tunneling oxide passivation contact cell according to claim 7, characterized in that: In the second doped polysilicon layer (7), the phosphorus doping concentration range is: 。 9. A photovoltaic module, characterized in that: The photovoltaic module comprises a tunnel oxide passivation contact cell according to any one of claims 1 to 7.

10. A method for manufacturing a tunnel oxide passivation contact cell, characterized in that: The manufacturing method comprises the following steps: Depositing a tunneling oxide layer (4) and a first doped amorphous silicon layer in sequence on a silicon substrate (1); Depositing a dielectric layer (6) on the first doped amorphous silicon layer; Depositing a second doped amorphous silicon layer on the dielectric layer (6); Annealing is performed to crystallize the first doped amorphous silicon layer and the second doped amorphous silicon layer into a first doped polysilicon layer (5) and a second doped polysilicon layer (7).

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