Starting circuit applied to ultra-low power consumption BGR circuit

Abstract

The invention discloses a starting circuit applied to an ultra-low power consumption BGR circuit, and belongs to the technical field of starting circuit design, and the starting circuit applied to the ultra-low power consumption BGR circuit comprises PMOS (P-channel Metal Oxide Semiconductor) tubes P1-P11, NMOS (N-channel Metal Oxide Semiconductor) tubes N1-N8, resistors R1-R4, voltage stabilizing capacitors C1 and C2 and bipolar junction pnp triodes Q1-Q3. The starting circuit applied to the ultra-low power consumption BGR circuit is closed when the BGR normally works, only consumes extremely low power consumption, and does not work at an electrification stage, so that the risk is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of startup circuit design, and in particular relates to a startup circuit applied to an ultra-low power consumption BGR circuit. Background Art

[0002] The voltage-mode bandgap reference (BGR) circuit has two solutions (operating points) that satisfy the KCL / KVL circuit equations. Only one of them is the target operating point. Therefore, a startup circuit needs to be added to make the other degenerate operating point become a non-solution (that is, it no longer satisfies the KVL / KCL circuit equation with the startup circuit). In other words, the startup circuit is used to pull the BGR circuit out of the "dead zone". Common ultra-low power BGR startup circuits include Figure 1 As shown, if the circuit operates in the "dead zone," the gate voltages of P1, P2, and P3 are high, the current flowing out of current sources P1, P2, and P3 is low, and voltage VFB is low, turning N1 off. Current flows through P4, P5, and P6 to charge the gate of N2, gradually increasing the voltage, turning on N2. This lowers the gate voltages of P1, P2, and P3, increasing their current flow and pulling the BGR circuit out of the "dead zone." When the BGR circuit operates normally, VFB is high, turning on N1, reducing the gate voltage of N2, turning off N2, and disabling the startup circuit. However, the N1 path remains open during normal BGR operation and consumes current. Because ultra-low-power BGRs are normally-on circuits, they desire to minimize power consumption while meeting performance requirements. Reducing current consumption requires increasing the length of the load transistors P4, P5, and P6, thereby increasing their impedance, or adding large resistors. This occupies a large area and yields very little benefit in ultra-low-power circuits. In addition, the PMOS tubes P4, P5, and P6 of this structure can be equivalent to resistors, and N1 can be equivalent to a switch. The current flowing through this path increases with the increase of the power supply voltage. The current can be reduced by connecting more PMOS tubes in series, but this will increase the risk of the startup circuit not working under low voltage conditions. Therefore, it is only suitable for circuits with a relatively small power supply voltage variation range, such as around 1.8V or 3.3V with a deviation of plus or minus 10%. For a wide power supply voltage such as 1.62-3.63V, it is difficult for this startup circuit to ensure low power consumption while working normally under various process angles.

[0003] Figure 2 It is a current type starting circuit, and Figure 1The difference is that capacitor C2 replaces load tubes P4, P5, and P6, so that when the BGR is working normally, no current flows through this path and no power is consumed. However, it can only be started once during the power-on process. If the power-on process fails to successfully pull the BGR out of the "dead zone", or the BGR accidentally enters the "dead zone" during operation, the startup circuit will not work and the power can only be turned off again to discharge completely and then power on again. In addition, the timing of the startup circuit is related to the power-on speed of the power supply and the capacitance of capacitors C2 and C3. In some cases, the BGR may be shut down before being pulled out of the dead zone, so you need to be very careful when designing.

[0004] Therefore, it is desirable to design a startup circuit that is shut down when the BGR is operating normally, consumes very little power, and operates not only during the power-up phase. Summary of the Invention

[0005] The object of the present invention is to provide a BGR startup circuit structure that consumes extremely low power and operates more than once during the power-up phase, so as to solve the problems raised in the above-mentioned background technology.

[0006] To achieve the above objectives, the present invention provides the following technical solutions: a startup circuit for an ultra-low power consumption BGR circuit, the startup circuit comprising PMOS transistors P1-P11, NMOS transistors N1-N8, resistors R1-R4, voltage stabilizing capacitors C1 and C2, and bipolar junction pnp transistors Q1-Q3;

[0007] In the startup circuit, the gate of the PMOS transistor P1 is connected to the gates of the PMOS transistors P2, P3, P4, and P5, the drain of the PMOS transistor P9, the drain of the NMOS transistor N6, and the negative electrode of the voltage-stabilizing capacitor C1; the source of the PMOS transistor P1 is connected to the power supply voltage AVDD, and the drain is connected to the emitter of the bipolar junction pnp transistor Q1 and the gate of the PMOS transistor P10; the positive electrode of the voltage-stabilizing capacitor C1 is connected to the power supply voltage AVDD; the source of the PMOS transistor P2 is connected to the power supply voltage AVDD, and the drain is connected to the positive electrode of the resistor R1 and the gate of the PMOS transistor P11; The negative electrode of resistor R1 is connected to the emitter of bipolar junction pnp transistor Q2; the source of PMOS transistor P3 is connected to the power supply voltage AVDD, and the drain is connected to the positive electrode of resistor R2 and the positive electrode of voltage stabilizing capacitor C2; the negative electrode of voltage stabilizing capacitor C2 is connected to ground GND; the negative electrode of resistor R2 is connected to the positive electrode of resistor R3; the negative electrode of resistor R3 is connected to the emitter of bipolar junction pnp transistor Q3; the source of PMOS transistor P4 is connected to the power supply voltage AVDD, and the drain is connected to the gate of PMOS transistor P6, the gate of PMOS transistor P7, and the drain of NMOS transistor N1; NMOS The source of transistor N1 is connected to the drain of NMOS transistor N2; the source of NMOS transistor N2 is connected to the drain of NMOS transistor N3; the source of NMOS transistor N3 is connected to the drain of NMOS transistor N4; the source of NMOS transistor N4 is connected to the positive electrode of resistor R4; the negative electrode of resistor R4 is connected to ground GND; the source of PMOS transistor P6 is connected to the power supply voltage AVDD, and the drain is connected to the source of PMOS transistor P7; the drain of PMOS transistor P7 is connected to the gate and drain of NMOS transistor N8, the gate of NMOS transistor N6, and the drain of PMOS transistor P11; PMOS transistor P8 The source of the PMOS transistor P8 is connected to the power supply voltage AVDD, the gate and drain of the PMOS transistor P8 are connected to the gate of the PMOS transistor P9 and the drain of the NMOS transistor N5; the source of the PMOS transistor P9 is connected to the power supply voltage AVDD; the source of the PMOS transistor P5 is connected to the power supply voltage AVDD, and the drain is connected to the source and substrate of the PMOS transistor P10 and the source and substrate of the PMOS transistor P11; the drain of the PMOS transistor P10 is connected to the drain and gate of the NMOS transistor N7 and the gate of the NMOS transistor N5; the sources of the NMOS transistors N5, N6, N7 and N8 are connected to the ground GND.

[0008] Preferably, the PMOS tubes P1-P5 form a current mirror, the PMOS tubes P1, P2, P3 and P4 have the same size, and the width-to-length ratio of the PMOS tube P5 is half of those of the PMOS tubes P1, P2, P3 and P4; the NMOS tubes N1, N2, N3 and N4 are intrinsic tubes for providing high resistance, and the threshold voltages of the NMOS tubes N1, N2, N3 and N4 are small under all process corners; the gates of the NMOS tubes N1, N2, N3 and N4 are grounded GND and can all be turned on normally to provide high resistance; at the same time, the NMOS tubes N1, N2, N3 and N4 are connected in series to increase the total gate length to increase the resistance.

[0009] Preferably, the collectors and bases of the bipolar junction pnp transistors Q1 , Q2 and Q3 are all connected to the ground GND.

[0010] Preferably, the drain of the PMOS transistor P4 is connected to the gate of the PMOS transistor P6, the gate of the PMOS transistor P7, and the drain of the NMOS transistor N1. When the power supply AVDD is powered on, the gate voltage of the NMOS transistor N6 is quickly increased while the voltage at the node VBAIS is lowered, thereby quickly starting the BGR to reduce the risk of oscillation.

[0011] Compared with the prior art, the present invention has the following beneficial effects:

[0012] The present invention provides a startup circuit applied to an ultra-low power consumption BGR circuit, which is closed when the BGR is working normally, consumes only very small power consumption, and works not only in the power-up stage, thereby reducing risks. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 Design a circuit diagram for a common ultra-low power BGR startup circuit.

[0014] Figure 2 Design a circuit diagram for a current-type starting circuit.

[0015] Figure 3 This is a circuit diagram of the startup circuit design applied to the ultra-low power consumption BGR circuit of the present invention. DETAILED DESCRIPTION

[0016] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0017] Because ultra-low-power BGRs are normally-on circuits, they require minimal power consumption while meeting performance requirements. Currently, the startup circuitry of common BGR circuits cannot be completely shut down during normal BGR operation, which consumes a certain amount of power. Minimizing this power consumption requires a MOSFET load with a very long gate length or a large resistor, both of which consume a large area. Using a diode connected to a PMOS to reduce current consumption cannot guarantee proper operation across all power domains, i.e., the 1.62-3.63V range. Capacitor-based startup circuits only operate once during the power-up phase, which carries significant risks and requires a large capacitor area. To address or alleviate these issues, a startup circuit has been designed that is shut down during normal BGR operation, consumes minimal power, and operates beyond the power-up phase.

[0018] Figure 1 It is a common ultra-low power BGR startup circuit. The gates of P4, P5, and P6 are connected to the ground GND, the source of P4 is connected to the power supply voltage AVDD, and the drain is connected to the source of P5; the drain of P5 is connected to the source of P6; the drain of P6 is connected to the drain of N1 and the gate of N2; the gate of N1 is connected to the negative electrode of R2 and the positive electrode of R3, and the source is connected to the ground GND; the drain of N2 is connected to the gates of P1, P2, and P3, and the output stage of the op amp, and the source is connected to the ground GND; the source of P1 is connected to the power supply voltage AVDD, and the drain is connected to the negative input stage of the op amp and the emitter of the bipolar junction pnp transistor Q1. The source of P2 is connected to the power supply voltage AVDD, and the drain is connected to the positive input stage of the op amp and the positive electrode of R1; the negative electrode of R1 is connected to the emitter of the bipolar junction pnp transistor Q2; the source of P3 is connected to the power supply voltage AVDD, and the drain is connected to the positive electrode of R2 and the positive electrode of C1; the negative electrode of C1 is connected to the ground GND; the negative electrode of R3 is connected to the emitter of the bipolar junction pnp transistor Q3; the collector and base of Q1, the collector and base of Q2, and the collector and base of Q3 are all connected to the ground GND; the substrates of all NMOS devices are grounded, and the substrates of all PMOS devices are connected to the power supply voltage.

[0019] Figure 1If the circuit operates in the "dead zone," the gate voltages of P1, P2, and P3 are high, resulting in low current from current sources P1, P2, and P3. VFB is low, N1 is off, and current flows through P4, P5, and P6 to charge the gate of N2. The voltage gradually increases, turning on N2, which in turn lowers the gate voltages of P1, P2, and P3, increasing their current flow and pulling the BGR circuit out of the "dead zone." When the BGR circuit operates normally, VFB is high, turning on N1, reducing the gate voltage of N2 and turning off N2. This deactivates the startup circuit, but the N1 path remains open during normal BGR operation and consumes current. Because ultra-low-power BGRs are normally-on circuits, they desire to minimize power consumption while meeting performance requirements. To reduce current consumption, the length of the load transistors P4, P5, and P6 must be increased, thereby increasing impedance, or adding large resistors. This occupies a large area and yields very little benefit in ultra-low-power circuits. In addition, the PMOS tubes P4-P6 of this structure can be equivalent to resistors, and N1 can be equivalent to a switch. The current flowing through this path increases with the increase of the power supply voltage. The current can be reduced by connecting more PMOS tubes in series, but this will increase the risk of the startup circuit not working under low voltage conditions. Therefore, it is only suitable for circuits with a relatively small power supply voltage variation range, such as around 1.8V or 3.3V with a deviation of plus or minus 10%. For a wide power supply voltage such as 1.62-3.63V, it is difficult for this startup circuit to ensure low power consumption while working normally under various process angles.

[0020] Figure 2 It is a capacitor-type startup circuit. The positive electrode of C2 is connected to the power supply voltage AVDD, and the negative electrode is connected to the drain of N1 and the gate of N2; the gate of N1 is connected to the positive electrode of C3, the negative electrode of R2, and the positive electrode of R3, and the source is connected to the ground GND; the negative electrode of C3 is connected to the ground GND; the drain of N2 is connected to the gates of P1, P2, and P3, and the output stage of the op amp, and the source is connected to the ground GND; the source of P1 is connected to the power supply voltage AVDD, and the drain is connected to the negative input stage of the op amp and the emitter of the bipolar junction pnp transistor Q1; the source of P2 is connected to the power supply voltage AVDD The drain is connected to the positive input stage of the op amp and the positive electrode of R1; the negative electrode of R1 is connected to the emitter of the bipolar junction pnp transistor Q2; the source of P3 is connected to the power supply voltage AVDD, and the drain is connected to the positive electrode of R2 and the positive electrode of C1; the negative electrode of C1 is connected to the ground GND; the negative electrode of R3 is connected to the emitter of the bipolar junction pnp transistor Q3; the collector and base of Q1, the collector and base of Q2, and the collector and base of Q3 are all connected to the ground GND; except that the substrates of all NMOS devices are grounded, the substrates of all PMOS devices are connected to the power supply voltage. Figure 1The difference is that capacitor C2 replaces load tubes P4, P5, and P6, so that when the BGR is working normally, no current flows through this path and no power is consumed. However, it can only be started once during the power-on process. If the power-on process fails to successfully pull the BGR out of the "dead zone", or the BGR accidentally enters the dead zone during operation, the startup circuit will not work. The power supply can only be turned off again to discharge completely and then power on again. The timing of the startup circuit is related to the power-on speed of the power supply and the capacitance of capacitors C2 and C3. In some cases, the BGR may be shut down before being pulled out of the dead zone, so you need to be very careful when designing.

[0021] like Figure 3 As shown, an embodiment of the present invention provides a startup circuit for an ultra-low-power BGR circuit. This circuit is disabled during normal BGR operation, consumes very little power, and can operate beyond the power-up phase. In this circuit, P1-P11 are PMOS transistors, N1-N8 are NMOS transistors, R1-R4 are resistors, and C1 and C2 are voltage-stabilizing capacitors. N1-N4 are intrinsic transistors that provide high resistance and have a very low threshold voltage (VTH).

[0022] The gate of P1 is connected to the gates of P2, P3, P4, and P5, the drain of P9, the drain of N6, and the negative electrode of C1. The source is connected to the power supply voltage AVDD, and the drain is connected to the emitter of the bipolar junction pnp transistor Q1 and the gate of P10. The positive electrode of C1 is connected to the power supply voltage AVDD. The source of P2 is connected to the power supply voltage AVDD, and the drain is connected to the positive electrode of R1 and the gate of P11. The negative electrode of R1 is connected to the bipolar junction pnp transistor Q1 and the positive electrode of P11. The emitter of transistor Q2 is connected; the source of P3 is connected to the power supply voltage AVDD, and the drain is connected to the positive electrode of R2 and the positive electrode of C2; the negative electrode of C2 is connected to ground GND; the negative electrode of R2 is connected to the positive electrode of R3; the negative electrode of R3 is connected to the emitter of bipolar junction pnp transistor Q3; the source of P4 is connected to the power supply voltage AVDD, and the drain is connected to the gate of P6, the gate of P7, and the drain of N1; the gates of N1, N2, N3, and N4 are connected to The source of N1 is connected to the drain of N2; the source of N2 is connected to the drain of N3; the source of N3 is connected to the drain of N4; the source of N4 is connected to the positive electrode of R4; the negative electrode of R4 is connected to the ground GND; the source of P6 is connected to the power supply voltage AVDD, and the drain is connected to the source of P7; the drain of P7 is connected to the gate and drain of N8, the gate of N6, and the drain of P11; the source of P8 is connected to the power supply voltage AVDD, The gate and drain of P8 are connected to the gate of P9 and the drain of N5; the source of P9 is connected to the power supply voltage AVDD; the source of P5 is connected to the power supply voltage AVDD, and the drain is connected to the source and substrate of P10, and the source and substrate of P11; the drain of P10 is connected to the drain and gate of N7 and the gate of N5; the drain of P11 is connected to the drain and gate of N8 and the gate of N6; the sources of N5, N6, N7, and N8 are connected to ground GND. The collector and base of Q1, the collector and base of Q2, and the collector and base of Q3 are all connected to ground GND;

[0023] The substrates of all NMOS devices except the self-well device are grounded, and the substrates of all PMOS devices are connected to the power supply voltage.

[0024] PMOS transistors P1-P5 form a current mirror. P1, P2, P3, and P4 are the same size, with P5's aspect ratio half that of P1-P4. NMOS transistors N1, N2, N3, and N4 are intrinsic transistors, providing high resistance. Their threshold voltages are low across all process corners, and their gates remain grounded to GND, allowing them to operate normally and provide high resistance. The series connection of NMOS transistors N1-N4 increases their total gate length, thereby increasing their resistance. By adjusting their dimensions, node VB is at a low level when the current flowing through P4 is less than 200pA across all process corners. This prevents leakage in the P4 circuit, which could cause the startup circuit to fail due to a high VB level. The current margin in this circuit can be adjusted based on the process. As the current continues to increase, VFB rapidly rises to VDD, placing P4 in a deep linear region, disabling the startup circuit and consuming only a small amount of current. This design operates normally across voltages from 1.62V to 3.63V. When the BGR is not operating, VB is low, P6 and P7 are turned on, raising the voltage at node VCT. This increases the current through N6, lowering the voltage at node VBAIS, and increasing the current through P1-P5, pulling the BGR out of its dead zone. The reason for not directly lowering the voltage at VBAIS is that, in the ultra-low-power BGR circuit, the current flowing through P5 is low during stability. Directly lowering the voltage at VBAIS would, in some cases, rapidly increase the current through P1-P5, causing node voltage VINN to exceed VINP. Current would flow through P10, leaving only a small current through P11. This would require a longer time for VCT to charge to a stable level, and consequently, for the BGR to stabilize. Therefore, the VCT node is pulled up. Even after the BGR is powered on, if the circuit enters its dead zone again under certain circumstances, node VB will return to a low level, restarting the startup circuit.

[0025] The startup circuit applied to the ultra-low power consumption BGR circuit of the present invention is closed when the BGR is working normally, consumes only very small power consumption, and works not only in the power-up stage, thereby reducing risks.

[0026] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0027] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A startup circuit for an ultra-low power consumption BGR circuit, characterized in that: The startup circuit includes PMOS transistors P1-P11, NMOS transistors N1-N8, resistors R1-R4, voltage stabilizing capacitors C1 and C2, and bipolar junction pnp transistors Q1-Q3; In the startup circuit, the gate of the PMOS transistor P1 is connected to the gates of the PMOS transistors P2, P3, P4, and P5, the drain of the PMOS transistor P9, the drain of the NMOS transistor N6, and the negative electrode of the voltage-stabilizing capacitor C1; the source of the PMOS transistor P1 is connected to the power supply voltage AVDD, and the drain is connected to the emitter of the bipolar junction pnp transistor Q1 and the gate of the PMOS transistor P10; the positive electrode of the voltage-stabilizing capacitor C1 is connected to the power supply voltage AVDD; the source of the PMOS transistor P2 is connected to the power supply voltage AVDD, and the drain is connected to the positive electrode of the resistor R1 and the gate of the PMOS transistor P11; The negative electrode of resistor R1 is connected to the emitter of bipolar junction pnp transistor Q2; the source of PMOS transistor P3 is connected to the power supply voltage AVDD, and the drain is connected to the positive electrode of resistor R2 and the positive electrode of voltage stabilizing capacitor C2; the negative electrode of voltage stabilizing capacitor C2 is connected to ground GND; the negative electrode of resistor R2 is connected to the positive electrode of resistor R3; the negative electrode of resistor R3 is connected to the emitter of bipolar junction pnp transistor Q3; the source of PMOS transistor P4 is connected to the power supply voltage AVDD, and the drain is connected to the gate of PMOS transistor P6, the gate of PMOS transistor P7, and the drain of NMOS transistor N1; NMOS The source of transistor N1 is connected to the drain of NMOS transistor N2; the source of NMOS transistor N2 is connected to the drain of NMOS transistor N3; the source of NMOS transistor N3 is connected to the drain of NMOS transistor N4; the source of NMOS transistor N4 is connected to the positive electrode of resistor R4; the negative electrode of resistor R4 is connected to ground GND; the source of PMOS transistor P6 is connected to the power supply voltage AVDD, and the drain is connected to the source of PMOS transistor P7; the drain of PMOS transistor P7 is connected to the gate and drain of NMOS transistor N8, the gate of NMOS transistor N6, and the drain of PMOS transistor P11; PMOS transistor P8 The source of the PMOS transistor P8 is connected to the power supply voltage AVDD, the gate and drain of the PMOS transistor P8 are connected to the gate of the PMOS transistor P9 and the drain of the NMOS transistor N5; the source of the PMOS transistor P9 is connected to the power supply voltage AVDD; the source of the PMOS transistor P5 is connected to the power supply voltage AVDD, and the drain is connected to the source and substrate of the PMOS transistor P10 and the source and substrate of the PMOS transistor P11; the drain of the PMOS transistor P10 is connected to the drain and gate of the NMOS transistor N7 and the gate of the NMOS transistor N5; the sources of the NMOS transistors N5, N6, N7 and N8 are connected to the ground GND.

2. The startup circuit for an ultra-low power consumption BGR circuit according to claim 1, characterized in that: The PMOS transistors P1-P5 form a current mirror. The PMOS transistors P1, P2, P3 and P4 have the same size, and the width-to-length ratio of the PMOS transistor P5 is half that of the PMOS transistors P1, P2, P3 and P4. The NMOS transistors N1, N2, N3 and N4 are intrinsic transistors for providing high resistance, and the threshold voltages of the NMOS transistors N1, N2, N3 and N4 are small under all process corners.

3. The startup circuit for an ultra-low power consumption BGR circuit according to claim 2, wherein: The gates of the NMOS transistors N1, N2, N3 and N4 are grounded GND and can all be turned on normally to provide high resistance. At the same time, the NMOS transistors N1, N2, N3 and N4 are connected in series to increase the total gate length to increase the resistance.

4. The startup circuit for an ultra-low power consumption BGR circuit according to claim 1, wherein: The collectors and bases of the bipolar junction pnp transistors Q1 , Q2 and Q3 are all connected to the ground GND.

5. The startup circuit for an ultra-low power consumption BGR circuit according to claim 1, wherein: The drain of the PMOS transistor P4 is connected to the gate of the PMOS transistor P6, the gate of the PMOS transistor P7, and the drain of the NMOS transistor N1. When the power supply AVDD is powered on, the gate voltage of the NMOS transistor N6 is quickly increased and the voltage at the node VBAIS is simultaneously lowered, thereby quickly starting the BGR to reduce the risk of oscillation.

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