Package with field emission device and x-ray apparatus having same

Abstract

The present invention relates to a package having a field emission device and an X-ray apparatus having the same, the package having the field emission device comprising: a processing layer; a buried layer laminated on the processing layer; the device layer is stacked on the buried layer; an insulating layer laminated on an upper region of the device layer; a gate electrode laminated on an upper region of the insulating layer; and at least one light emitting device disposed in a lower region of the device layer and configured to emit light through the device layer. The insulating layer is composed of a plurality of insulating regions separated by first separation regions, and the gate electrode is composed of a plurality of metal regions separated by second separation regions. The device layer has a protruding portion formed to protrude between the first separation region between the insulating regions and the second separation region between the metal regions.

Description

Technical Field

[0001] The present invention relates to a package having a field emission device, and more particularly to a package having a field emission device and an X-ray device having the package. Background Art

[0002] In probe-type field emission devices, the field emission current density is highly sensitive to the probe's shape (height, probe radius, etc.). In particular, the probe radius is on the order of nanometers, and the current density of a particular probe can increase dramatically with even the slightest difference in radius. Consequently, probe deformation or micro-arc plasma can cause an electrical short to the gate electrode, leading to serious reliability issues.

[0003] Currently, various methods are being tried to ensure reliability while maintaining high current density. However, completely solving the reliability problem caused by arcing is a very difficult task.

[0004] As for silicon probes, since the probes are made by etching a silicon wafer, it is difficult to form an additional impedance layer under the probes. To address this problem, there are currently no reports on current-limiting impedance layers.

[0005] In the case of n-type silicon, where electrons are the majority carrier, a high current density can be achieved. However, it is difficult to avoid arcing caused by localized plasma generation, making reliability a problem.

[0006] To ensure reliability, one can consider using a p-type wafer, where the majority of carriers are holes, or a silicon emitter with a pn junction. While this approach offers higher reliability, the current density is limited due to a lack of electrons available for emission, preventing high currents.

[0007] As a method to overcome the limitations of reliability and current density, transistors such as MOSFETs (metal oxide semiconductor field effect transistors) and JFETs (junction field effect transistors) can be fabricated and the current can be adjusted by adjusting the gate voltage of the transistors. However, there are problems such as the complexity of the fabrication process and the need for additional area to form the transistors, which reduces the density of probes. Summary of the Invention

[0008] The purpose of this specification is to provide a package having a field emission device and an X-ray device having the package.

[0009] The present specification also aims to increase current density and ensure reliability in packaging and X-ray devices.

[0010] Another object of this specification is to provide a structure and a manufacturing method of a device integrating a probe formed of a p-type wafer and an LED (or LD).

[0011] Another object of the present invention is to ensure reliability by preventing excessive current from flowing in a single probe and to adjust the current density of emitted electrons by adjusting the intensity of LED light.

[0012] The package having a field emission device of the present specification includes: a handle layer; a buried layer stacked on the handle layer; a device layer stacked on the buried layer; an insulating layer stacked on an upper region of the device layer; a gate electrode stacked on an upper region of the insulating layer; and at least one light-emitting device disposed in a lower region of the device layer and configured to emit light through the device layer. The insulating layer is composed of a plurality of insulating regions separated by first separation regions, and the gate electrode is composed of a plurality of metal regions separated by second separation regions. The device layer has a protrusion formed so as to protrude between the first separation regions between the insulating regions and the second separation regions between the metal regions.

[0013] According to an embodiment, the device layer may be formed with a p-type silicon substrate, and the protrusion of the device layer may be formed with n-type silicon.

[0014] According to an embodiment, the upper region of the protrusion may be formed of n-type silicon. The lower region of the protrusion and the main portion of the device layer may be formed of a p-type silicon substrate. The main portion of the device layer may be formed flat so that the insulating layer is disposed on the upper end of the main portion.

[0015] According to an embodiment, the protrusion and the upper region of the main body of the device layer integrally formed with the protrusion may be formed of n-type silicon. The lower region of the main body may be formed of a p-type silicon substrate. The buried layer may be stacked at the lower end of the lower region of the main body.

[0016] According to an embodiment, an SOI wafer may be further included, wherein a recessed region is formed in the center of the SOI wafer by an etching process. Protruding regions that protrude more than the recessed region may be formed in one side region and another side region of the center of the wafer. A first thickness from the lower end of the wafer to the upper end of the protruding region may be thicker than a second thickness from the lower end of the wafer to the upper end of the recessed region.

[0017] According to an embodiment, the package may further include: a first oxide layer disposed on the recessed region at the upper end of the wafer and on the raised regions on one side and the other side of the recessed region; and a second oxide layer disposed on the lower end of the wafer. The package may further include: a first metal electrode disposed on the raised region; and a second metal electrode disposed on the recessed region. The light-emitting device may be disposed on top of the second metal electrode.

[0018] According to an embodiment, the first metal electrode can form the LED cathode, the second metal electrode can form the LED anode, the lower end of the light-emitting device can be arranged in the recessed area formed with the second metal electrode, and the upper end of the light-emitting device can be arranged in the open area of ​​the handling layer.

[0019] According to an embodiment, the light emitting device may be provided as a plurality of LEDs spaced apart along a vertical axis in the region where the second metal electrode is formed. One side and the other side of each of the plurality of LEDs may be connected to the first metal electrode on one side and the first metal electrode on the other side of the protruding region by wire bonding.

[0020] According to an embodiment, the package may further include: a thin film stacked on the lower end of one side area and the lower end of the other side area of ​​the processing layer, the central portion of the processing layer is removed by an etching process, and the processing layer is arranged on the one side area and the other side area to form an opening area in the central portion; and a transparent electrode formed on the lower end of the thin film, the inner side surface of the one side area, the inner side surface of the other side area and the lower end of the device layer.

[0021] According to an embodiment, the encapsulation may include a second thin film formed on the lower end of the transparent electrode, the inner side surface of one side region of the transparent electrode, and the inner side surface of another side region of the transparent electrode. The second thin film may be formed in the opening region formed in the center portion of the transparent electrode stacked on the device layer. The opening region may be formed with a first opening length at the upper end of the handling layer and a second opening length at the lower end of the handling layer.

[0022] According to an embodiment, the second opening length may be formed to be longer than the first opening length.A length of the light emitting device on a horizontal axis may be formed to be shorter than the first opening length.

[0023] According to an embodiment, a gate voltage may be applied to at least one of the gate electrode and the first metal electrode, and a driving voltage may be applied to at least one of the second metal electrode and the first metal electrode.

[0024] According to an embodiment, an anode layer may be formed on a surface of a detector configured to detect an electron beam from the field emission device, and an anode voltage may be applied to at least one of the anode layer and the first metal electrode.

[0025] According to an embodiment, the gate voltage may be variable. A fixed voltage may be applied as the anode voltage. If the driving voltage is not applied, the emission current of the electron beam emitted by the light emitting device may increase as the gate voltage increases.

[0026] According to an embodiment, when the light-emitting device emits light when the driving voltage is applied, the emission current may increase at a first slope within a range of the gate voltage from 50 V to a first driving voltage. When the light-emitting device emits light, the emission current may increase at a second slope lower than the first slope within a range of the gate voltage from the first driving voltage to 100 V. Under the first driving voltage condition, the emission current is greater than 100 μA.

[0027] Another aspect of the present disclosure relates to an X-ray device having a field emission device, including: a main body having a front surface, a rear surface, and a plurality of side surfaces, forming the exterior appearance of the X-ray device; an electron emission device disposed within the main body through one side surface; and an X-ray emission device disposed within the main body through another side surface, such that electron beams emitted from the electron emission device are reflected and emitted from the main body through the front surface. The electron emission device includes: a handle layer; a buried layer stacked on the handle layer; a device layer stacked on the buried layer; an insulating layer stacked on an upper region of the device layer; a gate electrode stacked on an upper region of the insulating layer; and at least one light-emitting device disposed in a lower region of the device layer, configured to emit light through the device layer. The insulating layer is composed of a plurality of insulating regions separated by first separation regions, and the gate electrode is composed of a plurality of metal regions separated by second separation regions. The device layer has a protrusion formed so as to protrude between the first separation regions between the insulating regions and the second separation regions between the metal regions.

[0028] According to an embodiment, the electron emission device further includes an SOI wafer, a recessed area is formed in the center of the SOI wafer by an etching process, and protruding areas that protrude more than the recessed area are formed in one side area and the other side area of ​​the center of the wafer, and a first thickness from the lower end of the wafer to the upper end of the protruding area is thicker than a second thickness from the lower end of the wafer to the upper end of the recessed area.

[0029] According to an embodiment, it also includes: a first oxide layer, which is configured in the recessed area at the upper end of the chip, and the convex areas on one side and the other side of the recessed area; a second oxide layer, which is configured in the lower end of the chip; a first metal electrode, which is configured in the convex area; and a second metal electrode, which is configured in the recessed area; the light-emitting device is configured in the upper part of the second metal electrode, the first metal electrode forms a cathode, the second metal electrode forms an anode, the lower end of the light-emitting device is configured in the recessed area where the second metal electrode is formed, the upper end of the light-emitting device is configured in the opening area of ​​the processing layer, and the light-emitting device is configured as a plurality of LEDs separated along the vertical axis direction in the area where the second metal electrode is formed.

[0030] According to an embodiment, the electron emission device includes: a thin film stacked on the lower end of one side area and the lower end of the other side area of ​​the processing layer, the central portion of the processing layer is removed by an etching process, and the processing layer is arranged in the one side area and the other side area to form an opening area in the central portion; a transparent electrode formed on the lower end of the thin film, the inner side surface of the one side area, the inner side surface of the other side area and the lower end of the device layer; and a second thin film formed on the lower end of the transparent electrode, the inner side surface of one side area and the inner side surface of the other side area of ​​the transparent electrode; the second thin film is formed in the opening area formed in the central portion of the transparent electrode stacked on the device layer, and the opening area is formed with a first opening length at the upper end of the processing layer and with a second opening length at the lower end of the processing layer.

[0031] According to an embodiment, the device layer is formed with a p-type silicon substrate, the protrusion of the device layer is formed with n-type silicon, a gate voltage is applied to at least one of the gate electrode and the first metal electrode, a driving voltage is applied to at least one of the second metal electrode and the first metal electrode, an anode layer is formed on the surface of the X-ray emission device configured to reflect the electron beam from the field emission device, the anode layer is formed to be inclined at a specified angle to the Z axis, and an anode voltage is applied to at least one of the anode layer and the first metal electrode.

[0032] According to the present specification, a package including a field emission device and an X-ray apparatus including the package can be provided.

[0033] According to the present specification, in order to improve current density and ensure reliability in a package and an X-ray device, the current of a single probe can be effectively adjusted.

[0034] According to this specification, the principle that p-type or pn junction generates carriers when receiving light energy can be used to provide a structure and manufacturing method of a device integrating a probe formed of a p-type wafer and an LED (or LD).

[0035] According to this specification, current is adjusted by light from a light emitting device, thereby ensuring reliability by preventing excessive current from flowing in a single probe, and current density of emitted electrons can be adjusted by adjusting the intensity of LED light. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 A cross-sectional view and current-voltage characteristics of an n-type field emission device according to a conventional invention are shown.

[0037] Figure 2 A cross-sectional view and current-voltage characteristics of a p-type field emission device according to a conventional invention are shown.

[0038] Figure 3 A cross-sectional view and current-voltage characteristics of a pn junction field emission device according to a prior art invention are shown.

[0039] Figure 4 and Figure 5 This is a process diagram showing the production of a field emission device.

[0040] Figure 6 and Figure 7 This is a process diagram showing the lower structure of a package having a field emission device.

[0041] Figure 8 It means that a light-emitting device is provided. Figure 6 A top view of the lower structure.

[0042] Figure 9 and Figure 10 The figures are cross-sectional views taken in different axial directions showing a package of a field emission device having a light-emitting device disposed on a lower structure.

[0043] Figure 11 and Figure 12 FIG. 1 is a cross-sectional view showing an LED integrated device having a PN junction according to an embodiment.

[0044] Figure 13 This shows a configuration in which a bias voltage is applied to a package having a field emission device.

[0045] Figure 14 It represents the emission current emitted by the light emitting device according to the change of the gate voltage.

[0046] Figure 15 The following shows the configuration of an X-ray apparatus having a field emission device according to this specification. DETAILED DESCRIPTION

[0047] The technology disclosed in this specification is applied to a package having a field emission device and an X-ray device having the package. However, the technology disclosed in this specification is not limited thereto and can be applied to any package having a field emission device and an X-ray device having the package to which the technical concept of the technology can be applied.

[0048] It should be noted that the technical terms used in this specification are only used to illustrate specific embodiments and are not intended to limit the present invention. In addition, unless otherwise defined in this specification, the technical terms used in this specification should be interpreted as the meanings commonly understood by those of ordinary skill in the art, and should not be interpreted as excessive generalizations or excessive reductions. In addition, when the technical terms used in this specification are erroneous technical terms that cannot accurately express the technical ideas disclosed in this specification, they should be replaced and understood with technical terms that can be correctly understood by those skilled in the art. In addition, the common terms used in this specification should be interpreted according to dictionary definitions or according to preceding and following articles, and should not be interpreted with excessive reductions.

[0049] In addition, unless the context clearly indicates a different meaning, expressions in the singular include expressions in the plural. In this specification, terms such as "comprising" or "including" should not be interpreted as necessarily including all of the various components or steps described in the specification, but should be interpreted as not including some of the components or steps, or including additional components or steps.

[0050] In addition, the suffixes "module" and "section" used in this specification for the constituent elements are only given or used interchangeably in consideration of the convenience of writing the specification, and they themselves do not have mutually distinguishing meanings or functions.

[0051] In addition, terms such as "first" and "second" used in this specification may be used to describe various components, but the components are not limited to these terms. These terms are only used to distinguish one component from other components. For example, without departing from the scope of the claims of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component.

[0052] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same or similar components are denoted by the same reference numerals regardless of the drawing numbers, and repeated description thereof will be omitted.

[0053] In addition, in the process of describing the present invention, when it is determined that the detailed description of the relevant known technology makes the gist of the present invention unclear, the detailed description thereof will be omitted. In addition, it should be noted that the drawings are provided only to facilitate the understanding of the concept of the present invention and should not be interpreted as limiting the concept of the present invention to the drawings.

[0054] Regarding this, Figure 1 A cross-sectional view and current-voltage characteristics of an n-type field emission device according to a conventional invention are shown. Figure 2 A cross-sectional view and current-voltage characteristics of a p-type field emission device according to a conventional invention are shown. Figure 3 A cross-sectional view and current-voltage characteristics of a pn junction field emission device according to a prior art invention are shown.

[0055] Figure 1 (a) is a cross-sectional view of an n-type field emission device. Figure 1 (b) indicates Figure 1 (a) Current-voltage characteristics of an n-type field emission device. Figure 1 In (a), protrusions PR1 and PR2, which become probes, can be formed by etching a silicon wafer 1010a. Wafer 1010a can be formed from an n-type silicon substrate. An insulating layer 510 can be formed between protrusions PR1 and PR2. A gate electrode 520 can be formed in an upper region of insulating layer 510.

[0056] A first electrode 210, serving as a cathode, can be formed in the lower region of wafer 1010a. When a voltage is applied between first electrode 210 and gate electrode 520, an electric field concentrates on protrusions PR1 and PR2, whose ends are formed as sharp probes. This thins the tunnel barrier in a vacuum. Consequently, electrons from the probe-shaped protrusions PR1 and PR2 are emitted into the vacuum due to tunneling. The tunnel current (J) can be expressed as the following equation 1.

[0057] Mathematical formula 1

[0058]

[0059] Here, V is the voltage applied to the field emission device, is the work function of the material, and β is the field enhancement factor (β). The tunneling current (J) is very sensitive to the field enhancement factor (β). The field enhancement factor represents the increase in the electric field at the probe surface due to the probe's shape. It is proportional to the probe's height and inversely proportional to the probe's radius.

[0060] Reference Figure 1(b) shows the voltage-current characteristics of the field emission device according to the tunneling current (J) in Mathematical Formula 1. It can be confirmed that the current is very sensitive to the voltage and the field enhancement factor, and changes similarly to an exponential function, for example.

[0061] Although the voltage can be adjusted to be constant, it is very difficult to keep the field enhancement coefficient constant. The field enhancement coefficient changes according to the radius of the probe, but it is almost impossible to uniformly maintain the radius of the probe at the level of several nm. In addition, the field enhancement coefficient also changes very sensitively to surface contamination, etc. Therefore, even if the same voltage is applied to a single probe, a large current difference will be generated. Thus, when a specific probe does not emit electrons (electron emission), other probe parts may also produce arcs due to excessive current. Therefore, an electrical short circuit with the gate electrode may be caused, or a fatal problem may be caused to reliability.

[0062] On the other hand, the field emission device of this specification needs to prevent arcing. Therefore, diode devices and transistor-type devices are conceivable as field emission devices. Figure 2 (a) is a cross-sectional view of a field emission device using a p-type wafer. Figure 2 (b) and Figure 2 (c) shows the energy band diagram and FN (Fowler-Nordheim) curve for a field emission device using a p-type wafer.

[0063] Reference Figure 2 (a) A silicon wafer 1010 may be etched to form protrusions PR1 and PR2, forming the probe portion. Wafer 1010 may be formed of a p-type silicon substrate. An insulating layer 510 may be formed between protrusions PR1 and PR2. A gate electrode 520 may be formed in an upper region of insulating layer 510. A first electrode 210 serving as a cathode may be formed in a lower region of wafer 1010.

[0064] In the p-type wafer 1010, electrons are minority carriers and the supply of electrons is limited. Based on this, it is possible to limit the excessive current flowing through the probe. Figure 2 In the energy band diagram (b), a depletion layer is formed in the boundary region. Electron-hole pairs generated by thermal generation in the depletion layer become the main source of electrons. Therefore, if the resistance is high, the size of the depletion layer increases, thereby increasing the current. Figure 2The FN plot in (c) shows FN emission characteristics under low voltage conditions. Under high voltage conditions, the current is limited due to the limited electron supply of the p-type wafer.

[0065] The above method can prevent arcing by suppressing a large current from flowing through the protrusions PR1 and PR2 as probes. However, due to the limited supply of electrons, there are limitations in obtaining the high current required for a field emission device.

[0066] On the other hand, there is a field emission device formed with a pn junction structure as a conventional invention. Figure 3 (a) is a cross-sectional view of a field emission device formed with a pn junction structure. Figure 3 (b) and Figure 3 (c) shows the energy band diagram and FN curve of a field emission device formed with a pn junction structure.

[0067] Reference Figure 3 (a) A wafer 1010 made of silicon may be etched to form protrusions PR1 and PR2 as probes. Wafer 1010 may be formed as a pn-type silicon substrate. The upper regions PR1a and PR2a of the protrusions PR1 and PR2 may be formed as n-type silicon probes. The lower regions PR1b and PR2b of the protrusions PR1 and PR2 and wafer 1010 may be formed of p-type silicon. An insulating layer 510 may be formed between the protrusions PR1 and PR2. A gate electrode 520 may be formed in the upper region of the insulating layer 510. A first electrode 210 serving as a cathode may be formed in the lower region of the wafer 1010.

[0068] Reference Figure 3 In the energy band diagram (b), the electron-hole pairs formed in the depletion layer of the pn junction are the main source of electrons. Therefore, the supply of electrons is affected by the size of the depletion layer of the pn junction. That is, if the size of the depletion layer increases, the current increases. Figure 3 The FN plot in (c) shows emission characteristics similar to those of a p-type emitter, but current limitation is evident under high voltage conditions. This is similar to the characteristic of a pn junction diode under reverse bias, where the current does not increase with voltage but remains nearly constant.

[0069] As a method to overcome the reliability and current density limitations, transistors such as MOSFETs and JFETs can be fabricated and the current can be adjusted by adjusting the gate voltage of the transistors. However, due to the complexity of the fabrication process and the additional area required to form the transistors, the number of probes per unit area must be significantly reduced.

[0070] As a method of increasing electron-hole pairs in a device using a P-type or pn junction, although emission current can be increased by irradiating light, no specific method for device formation has been proposed.

[0071] In the present invention, a field emission device is described that can limit the current sensitivity to the radius of the probe and increase the emission current. The driving principle of the field emission device is to apply 10 7 ~10 8 When a high electric field of 100 V / cm is applied, the potential barrier on the semiconductor surface is reduced. This phenomenon is called Fowler-Nordheim Tunneling, where electrons are emitted from a vacuum state due to the quantum mechanical tunneling effect where electrons pass through the reduced potential barrier on the semiconductor surface.

[0072] The most effective way to reduce the electric field contributing to the FN tunneling effect is to form sharp probes measuring several to tens of nanometers. This type of probe concentrates the electric field, which is proportional to the height of the probe's emitter and inversely proportional to the radius of the probe's tip, at the probe's tip, thereby reducing the drive voltage to tens of volts. However, n-type silicon wafers are susceptible to device damage due to high currents flowing through specific probes caused by current unevenness within the probes.

[0073] On the other hand, there is a problem in using a p-type device in that a high emission current required for a medical field emission device cannot be obtained due to insufficient current supply.

[0074] The field emission device of the present specification can increase the emission current while limiting the current sensitivity to the radius, etc. With reference to the accompanying drawings, the package with the field emission device and the X-ray device with the field emission device of the present specification are described in detail. Figure 4 and Figure 5 This is a process diagram showing the production of a field emission device. Figure 6 and Figure 7 A process diagram showing the lower structure of a package with a field emission device.

[0075] Reference Figure 4(a) The field emission device of the present invention is made of SOI (Silicon on Insulator) with a buried layer 20 stacked in the lower region of the device layer 100. The device layer is formed of a p-type silicon substrate to limit current sensitivity, and the buried layer 20 is made of a silicon oxide film (SiO 2) The handle layer 10 is a silicon wafer, which can be either p-type or n-type.

[0076] Reference Figure 4 (b) The upper end of the first region of the device layer 100 can be removed, and protrusions PR1, PR2, and PR3 that function as probes can be formed in the second region whose upper end is not removed. Insulating regions IR1, IR2, IR3, and IR4 can be formed in the upper region of the first region from which the upper end is removed. The plurality of insulating regions IR1, IR2, IR3, and IR4 can form an insulating layer 510. Metal regions MR1, MR2, MR3, and MR4 can be formed in the upper region of the insulating layer 510. The plurality of metal regions MR1, MR2, MR3, and MR4 can form a gate electrode 520. In addition, a thin film 210 can be disposed in the lower region of the device layer 100.

[0077] Although the front side of a field emission device has the same structure as a conventional silicon field emission device, the back side requires additional silicon etching and electrode formation. The reason for the back side silicon etching is to ensure that the light emitted from the light-emitting device, such as an LED, can better reach the device surface with a depletion layer.

[0078] In this regard, if the silicon handle layer 10 is not etched, most of the light is absorbed by the silicon handle layer 10 and cannot reach the device layer 100 and the protrusions PR1 , PR2 , and PR3 functioning as probes.

[0079] Reference Figure 4 (c) The center portion of the silicon processing layer 10 can be removed by etching. The processing layer 10 can be divided into a first processing layer region 10a and a second processing layer region 10b based on the center portion removed by etching. A hole region (hole region) can be formed in the center portion of the processing layer 10. The processing layer 10 can be divided into the first processing layer region 10a and the second processing layer region 10b based on the center of the hole region in the center portion removed by etching. The first processing layer region 10a and the second processing layer region 10b are formed as a whole and form the processing layer 10.

[0080] The first region 10a of the process layer can be arranged on one side of the lower portion of the device layer 100. The second region 10b of the process layer can be arranged on the other side of the lower portion of the device layer 100. The upper end length L1a of the first region 10a of the process layer can be greater than the lower end length L1b. The upper end length L2a of the second region 10b of the process layer can be greater than the lower end length L2b. The thin film 210 formed in the lower region of the device layer 100 can also be removed from the center portion and arranged on both sides. The lengths of the thin films 210 arranged on both sides can be the same as the lower end lengths L1b and L2b of the first and second regions 10a, 10b of the process layer. The thin film 210 can be formed as a Si3N4 thin film layer deposited on the process layer 10.

[0081] The upper length L1a of the first region 10a of the handle layer can be the same as the upper length L2a of the second region 10b of the handle layer. The lower length L1b of the first region 10a of the handle layer can be the same as the lower length L2b of the second region 10b of the handle layer. By forming the first and second regions 10a, 10b of the handle layer symmetrically about the centerline of the field emission device, structural stability can be ensured even when the opening region 220R is formed through etching. In particular, by making the upper lengths L1a and L2a of the first and second regions 10a, 10b of the handle layer greater than the lower lengths L1b and L2b, multiple light-emitting devices can be arranged in the lower region. Therefore, etching the silicon handle layer 10 also helps ensure space for integrating LEDs as light-emitting devices. Furthermore, by making the upper region of the opening region 220R narrower than the lower region, the light collection area for the light-emitting devices can be concentrated, thereby increasing the emission current per unit area.

[0082] On the other hand, it is very difficult to adjust the etching rate so that silicon is left at a predetermined, thin thickness through silicon etching. In particular, even if the buried layer 20 is formed thinner than the handle layer 10, the central portion must be removed through etching. Therefore, in this specification, an SOI wafer is used, and a silicon structure of a predetermined thickness is left on both sides through etching.

[0083] The following briefly describes the manufacturing process. A silicon emitter is formed using the device layer 100 of an SOI wafer. The processes for forming the protrusions PR1, PR2, and PR3 that serve as the probe portion by etching, forming the insulating layer 510, and forming the gate electrode 520 can be the same or similar to the process for forming a silicon emitter. Currently, various methods for forming silicon emitters have been developed, and the manufacturing processes of such silicon emitters can also be applied to the silicon etching process, etc. of this specification. In this case, the device layer 100 uses a boron-doped p-type wafer, and the thickness can be approximately in the range of 2 to 50 μm.

[0084] The following additional process is performed after the silicon emitter manufacturing process. First, the silicon can be etched from the back. Silicon etching can adopt an anisotropic etching method using solutions such as KOH, TMAH (tetramethylammonium hydroxide), and the etching mask can use a Si3N4 film deposited by the LPCVD (low pressure chemical vapor deposition) method. In addition, although dry etching methods such as deep RIE (deep reactive ion etching) can be used to etch silicon, there is a problem of difficulty in side deposition when forming electrodes. During silicon etching, if the etching solution encounters the BOX layer (buried oxide layer (SiO2)), the etching almost stops, and the BOX layer can be additionally etched to retain only the device layer 100.

[0085] The device layer that plays the role of cathode needs to be electrically connected, but since it is not only necessary to electrically connect but also to transmit light, a transparent electrode 300 is deposited. Figure 5 (a), a transparent electrode 300 can be formed between the lower end of the thin film 210 arranged on both sides, the inner side of the processing layer 10 and the buried layer 20. Since the thin film 210 has no special function after silicon etching, it can be removed and ITO can be deposited directly on the lower part of the processing layer. ITO (Indium Tin Oxide) can be used as a transparent electrode, but is not limited to this. Various transparent electrodes can be used depending on the application. After depositing the transparent electrode 300, a metal layer such as gold (Au) can be deposited to bond with the substrate integrated with the LED. Ti, Cr, etc. can be used as an adhesion layer when depositing Au.

[0086] The transparent electrode 300 may be composed of a plurality of parts. The transparent electrode 300 may include a first part 310, a second part 320, a third part 330, a fourth part 340, and a fifth part 350. The first part 310 of the transparent electrode 300 may be disposed below the thin film layer 210 formed below the first region 10a of the processing layer. The second part 320 of the transparent electrode 300 may be connected to the first part 310 and the third part 330 of the transparent electrode 300. The second part 320 of the transparent electrode 300 may be disposed inward of the first region 10a of the processing layer formed in an inclined structure.

[0087] The third portion 330 of the transparent electrode 300 may be connected to the second portion 320 and the fourth portion 340 of the transparent electrode 300. The third portion 330 of the transparent electrode 300 may be disposed between the buried layer 20 formed above the first and second regions 10a and 10b of the handling layer. The third portion 330 of the transparent electrode 300 may be disposed at the lower end of the device layer 100.

[0088] The fourth portion 340 of the transparent electrode 300 can be connected to the third portion 330 and the fifth portion 350 of the transparent electrode 300. The fourth portion 340 of the transparent electrode 300 can be disposed in an area inside the second region 10b of the handle layer formed in an inclined structure. The fourth portion 340 of the transparent electrode 300 can be formed to be symmetrical with the second portion 320 relative to the center line. The fifth portion 350 of the transparent electrode 300 can be connected to the fourth portion 340 of the transparent electrode 300. The fifth portion 350 of the transparent electrode 300 can be disposed below the thin film 210 formed below the second region 10b of the handle layer. The fifth portion 350 of the transparent electrode 300 can be formed to be symmetrical with the first portion 310 relative to the center line.

[0089] Reference Figure 5 (b), a second thin film 220 may be formed on the inner region of the lower portion and the side surface of the transparent electrode 300. The second thin film 220 may include a first portion 221, a second portion 222, a third portion 223, and a fourth portion 224.

[0090] Reference Figure 5 (a) and Figure 5 In (b), the first portion 221 of the second film 220 may be formed at the lower end of the first portion 310 of the transparent electrode 300. One end of the second portion 222 of the second film 220 may be connected to the first portion 221 of the second film 220. The second portion 222 of the second film 220 may be formed inside the second portion 320 of the transparent electrode 300. The other end of the second portion 222 of the second film 220 may extend a predetermined length along the lower end of the third portion 330 of the transparent electrode 300. An opening region 220R may be formed between the second portion 222 and the third portion 223 of the second film 220 with a first opening length AL1.

[0091] The third portion 223 of the second film 220 may be formed inside the fourth portion 340 of the transparent electrode 300. The fourth portion 224 of the second film 220 may be connected to one end portion of the third portion 223 of the second film 220. One end portion of the third portion 223 of the second film 220 may extend a predetermined length along the other side of the lower end of the third portion 330 of the transparent electrode 300. An opening region 220R may be formed between the second portion 222 and the third portion 223 of the second film 220, with a first opening length AL1.

[0092] The fourth portion 224 of the second thin film 220 can be formed at the lower end of the fifth portion 350 of the transparent electrode 300. An opening region 220R can be formed between the first portion 221 and the fourth portion 224 of the second thin film 220, with a second opening length AL2. The second opening length AL2 of the opening region 220R can be greater than the first opening length AL1. Therefore, the emission current can be increased by concentrating the light-collecting region formed by the light-emitting devices to be arranged in the lower region of the opening region 220R in the region having the first opening length AL1. Furthermore, the arrangement space for the light-emitting devices arranged in the lower region of the opening region 220R can be expanded to a space equivalent to the second opening length AL2.

[0093] Reference Figure 6 and Figure 7 The lower structure 1000b of the package having the field emission device of this specification will be described. The lower structure 1000b of the package may be provided with a substrate in the form of a wafer to which an LED is bonded.

[0094] When bonding a field emission device to a wafer-like substrate with LEDs attached to it, it is crucial to minimize residual stress caused by differences in thermal expansion coefficients. Manufacturing an X-ray tube using the finished device requires temperatures of at least 350°C. If the thermal expansion coefficients of the field emission device and the LED-bonded substrate differ, significant residual stress can occur, potentially damaging the device.

[0095] LED substrates can be made of aluminum oxide (Al2O3) or printed circuit boards (PCBs). However, these substrates have a poor thermal expansion coefficient. To address this issue, the present invention aims to create an LED bonding substrate using a silicon wafer, the same material as the field emission device.

[0096] Figure 6 (a) to Figure 6 (c) shows the process of manufacturing a substrate to which a light emitting device such as an LED is to be bonded. Figure 6 (a), an SOI wafer 1010 made of silicon can be prepared.

[0097] Reference Figure 6In step (b), the portion of silicon SOI wafer 1010 that will form the LED anode can be etched. As silicon SOI wafer 1010 is etched, recessed region 1010a is formed, creating a structure that can easily prevent electrical shorting between the cathode and the LED anode when bonding the LED integrated substrate to the field emission device. Recessed region 1010a can be formed in the center of silicon wafer 1010, while protruding regions 1010b and 1010c can be formed on either side.

[0098] Reference Figure 6 In (c), to insulate the substrate, a first oxide layer 1110 and a second oxide layer 1120 may be deposited as insulating films on the SOI wafer 1010. The first oxide layer 1110 may be referred to as a first insulating film, and the second oxide layer 1120 may be referred to as a second insulating film. As insulating films, the first oxide layer 1110 and the second oxide layer 1120 may be deposited as silicon dioxide (SiO2) oxide layers by thermal oxidation.

[0099] Figure 7 (a) and Figure 7 (b) shows a process of forming electrodes on the insulating film of the SOI wafer 1010 and configuring a light emitting device such as an LED to realize connection wiring. Figure 7 (a) Electrodes to be used as cathodes for light-emitting devices and field emission devices can be formed. First metal electrodes 1210 and 1220 connected to the upper structure of the package containing the field emission device can be formed in the raised areas 1010b and 1010c of the SOI wafer 1010. A second metal electrode 1230 can be formed in the recessed area 1010a of the SOI wafer 1010, where the light-emitting device is located. Au can be used as the electrode material, and an adhesion layer such as Cr or Ti can be first deposited between the SiO2 and Au.

[0100] Next, Au-Sn and other materials can be formed at the joint for field emission devices and eutectic bonding. As eutectic bonding materials, various materials such as Au-Sn and Ag-Sn can be used. Figure 7(b) The light emitting device 400 can be placed on the second metal electrode 1230 corresponding to the anode and die bonded. At least one of the first metal electrodes 1210 and 1220 can be electrically connected to the light emitting device 400. At least one of the first metal electrodes 1210 and 1220 and the light emitting device 400 can be connected by wire bonding. On the other hand, the lower area 1000b of the package can be connected to the second metal electrode 1230 by using the welding area 230. Figure 5 The width of the welding region 230 may be narrower than the width of the first metal electrodes 1210 and 1220.

[0101] By performing die bonding and wire bonding on the light emitting device 400, electrodes for connecting the cathode and anode of the light emitting device 400 are formed. As the light emitting device 400, an LD (laser diode) can be used instead of an LED, thereby improving efficiency by increasing the rectilinearity of light.

[0102] Furthermore, light emitting devices 400 can use LEDs and LDs of various wavelengths. The absorption rate of silicon decreases as the wavelength decreases. Therefore, to ensure optimal light transmission to the devices on the silicon surface, it is necessary to select LEDs and LDs with wavelengths appropriate to the thickness of the device layer. Furthermore, in addition to blue and red LEDs, infrared LEDs with suitable wavelengths can also be used as light emitting devices 400.

[0103] on the other hand, Figure 8 Indicates that a light-emitting device is configured Figure 6 A top view of the lower structure. Figure 9 and Figure 10 Cross-sectional views in different axial directions of a package having a field emission device, in which a light-emitting device is arranged in a lower structure.

[0104] Reference Figure 7 (b) and Figure 8 The lower structure 1000b of the package with the field emission device may include first metal electrodes 1210, 1220 and a second metal electrode 1230. The first metal electrodes 1210, 1220 corresponding to the cathode may be configured in the protruding areas 1010b, 1010c of the SOI wafer. The second metal electrode 1230 may be configured in the recessed area 1010a of the SOI wafer.

[0105] The second metal electrode 1230 formed in the recessed region 1010a of the wafer may be provided with light emitting devices 410, 420, and 430. One side and the other side of each of the light emitting devices 410, 420, and 430 may be connected to the first metal electrodes 1210 and 1220 by wire bonding.

[0106] Figure 9 yes Figure 8 A cross-sectional view taken along line AA′ in a horizontal axis direction of a package having a field emission device equipped with a light-emitting device. Figure 9 A cross-sectional view in the horizontal axis direction of a cathode bonding portion where the light emitting device 400 is arranged is shown. Figure 10 yes Figure 8 A cross-sectional view of a package having a field emission device equipped with a light-emitting device taken along a vertical axis line is shown. Figure 10 A cross-sectional view in the vertical axis direction is shown of a portion where anodes of light-emitting devices 410, 420, and 430 are arranged.

[0107] Reference Figures 7 to 9 The cathode of light-emitting device 400 can be bonded to the cathode of the field emission device and grounded together. The step formed by the initial etching of the substrate can ensure space so that the anode of light-emitting device 400 and the cathode of light-emitting device 400 do not bond. The power of light-emitting device 400 can be adjusted by applying a voltage to the anode of light-emitting device 400.

[0108] The upper region 1000a and the lower region 1000b of the package can be bonded using a eutectic bonding method, which is achieved by melting a solder under vacuum conditions at a temperature of 300 to 450°C. The upper region 1000a and the lower region 1000b of the package can be joined by bonding at a welding region 230. The width of the welding region 230 can be narrower than the width of the first metal electrodes 1210 and 1220.

[0109] Reference Figures 4 to 10 , the package 1000 with a field emission device of this specification is described.

[0110] The package 1000 having the field emission device may include a device layer 100 , a thin film 210 , a transparent electrode 300 , and a light emitting device 400 . The package 1000 may further include a handle layer 10 , a buried layer 20 , and a second thin film 220 .

[0111] The buried layer 20 may be formed to be stacked on the handle layer 10. The device layer 100 may be formed to be stacked on the buried layer 20. The thin film 210 may be formed to be stacked on the lower end of one side region and the lower end of the other side region of the handle layer 10. The central portion of the handle layer 10 may be removed by an etching process. The handle layer 10 may be disposed at the lower end of one side region and the other side region, and may have an opening region 220R formed in the central portion.

[0112] The transparent electrode 300 may be formed on the lower end, the inner side surface of one side region, and the inner side surface of the other side region of the thin film 210. The transparent electrode 300 may be formed on the lower end of the device layer 100. At least one light-emitting device 400 may be disposed in the lower region of the transparent electrode 300. The light-emitting device 400 may be configured to emit light through the transparent electrode 300 and the device layer 100.

[0113] Package 1000 with a field emission device can be combined with a lower region structure. The lower region structure of package 1000 can include an SOI wafer 1010. The lower region structure of package 1000 can also include a first oxide layer 1110 and a second oxide layer 1120. The lower region structure of package 1000 can also include first metal electrodes 1210 and 1220 and a second metal electrode 1230.

[0114] Wafer 1010 may be, but is not limited to, a silicon wafer and may vary depending on the application. A recessed region 1010a may be formed in the center of wafer 1010 by etching. Protruding regions 1010b and 1010c that protrude from recessed region 1010a may be formed on one side and the other side of the center of wafer 1010.

[0115] A first thickness t1 from the lower end of the SOI wafer 1010 to the upper end of the protruding regions 1010 b , 1010 c may be thicker than a second thickness t2 from the lower end of the wafer 1010 to the upper end of the recessed region 1010 a .

[0116] The first oxide layer 1110 can be disposed in the recessed region 1010a at the top of the wafer 1010, and in the protruding regions 1010b and 1010c on one side and the other side of the recessed region 1010a. A second oxide layer 1120 can be disposed at the bottom of the wafer 1010. The first oxide layer 1110 and the second oxide layer 1120 formed at the top and bottom of the wafer 1010, respectively, form insulating films. Therefore, the first oxide layer 1110 can be referred to as a first insulating layer, and the second oxide layer 1120 can be referred to as a second insulating layer.

[0117] First metal electrodes 1210 and 1220 may be disposed on the protruding regions 1010b and 1010c of the wafer 1010. A second metal electrode 1230 may be disposed on the recessed region 1010a of the wafer 1010. A light emitting device 400 may be disposed on top of the second metal electrode 1230.

[0118] The first metal electrodes 1210 and 1220 can form the LED cathode. The second metal electrode 1230 can form the LED anode. The lower end of the light-emitting device 400 can be disposed in the recessed area 1010a where the second metal electrode 1230 is formed. The upper end of the light-emitting device 400 can be disposed in the opening area of ​​the handle layer 10 of the upper structure of the package 1000.

[0119] The light-emitting device 400 includes a plurality of LEDs 410, 420, and 430. The plurality of LEDs 410, 420, and 430 can be spaced apart and arranged along the vertical axis in the region where the second metal electrode 1230 is formed. The light-emitting device 400 is not limited to LEDs and can be implemented as any light-emitting device. One side and the other side of each of the plurality of LEDs 410, 420, and 430 can be connected to the first metal electrodes 1210 and 1220 of the protruding regions 1010b and 1010c of the wafer 1010 by wire bonding. One side and the other side of each of the plurality of LEDs 410, 420, and 430 can also be connected to the first metal electrodes 1210 and 1220 by other bonding structures besides wire bonding. For example, one side and the other side of each of the plurality of LEDs 410, 420, and 430 can also be connected to the first metal electrodes 1210 and 1220 by using a bonding structure in the internal region of the wafer 1010.

[0120] The upper and lower structures of package 1000 can be combined using one side region and another side region. The second film 220 at the lower end of the upper structure of package 1000 can be connected to the first metal electrodes 1210 and 1220 forming the LED cathode at the upper end of the lower structure of package 1000.

[0121] The upper structure of the package 1000 may further include an insulating layer 510 and a gate electrode 520. The insulating layer 510 may be formed to be stacked on an upper region of the device layer 100. The gate electrode 520 may be formed to be stacked on an upper region of the insulating layer 510.

[0122] The insulating layer 510 may be composed of a plurality of insulating regions IR1, IR2, IR3, and IR4 separated by a first separation region. The gate electrode 520 may be composed of a plurality of metal regions MR1, MR2, MR3, and MR4 separated by a second separation region. Each of the plurality of metal regions MR1, MR2, MR3, and MR4 of the gate electrode 520 may be stacked on top of each of the plurality of insulating regions IR1, IR2, IR3, and IR4 of the insulating layer 510.

[0123] Device layer 100 may have protrusions PR1, PR2, and PR3. The protrusions PR1, PR2, and PR3 of device layer 100 may be formed to protrude between insulating regions IR1, IR2, IR3, and IR4 and metal regions MR1, MR2, MR3, and MR4. On the Z-axis, the upper ends of the protrusions PR1, PR2, and PR3 may be positioned higher than the upper ends of the insulating regions IR1, IR2, IR3, and IR4. On the Z-axis, the upper ends of the protrusions PR1, PR2, and PR3 may be positioned higher than the upper ends of the metal regions MR1, MR2, MR3, and MR4.

[0124] The second film 220 of the upper structure of the package 1000 may be formed to correspond to the shape of the transparent electrode 300. The second film 220 of the upper structure of the package 1000 may be formed on the lower end of the transparent electrode 300, the inner side surface of one side region of the transparent electrode 300, and the inner side surface of the other side region.

[0125] The second film 220 can form an opening region 220R corresponding to the center portion of the transparent electrode 300 stacked on the device layer 100. The opening region 220R of the second film 220 can be formed at the upper end of the handle layer 10 with a first opening length AL1. The opening region 220R of the second film 220 can be formed at the lower end of the handle layer 10 with a second opening length AL2. The second opening length AL2 of the opening region 220R of the second film 220 can be longer than the first opening length AL1. The horizontal axial length of the light-emitting device 400 can be shorter than the first opening length AL1. This allows direct light emitted from the light-emitting device 400 with a predetermined wide angle to be transmitted through the transparent electrode 300 to the upper structure of the package 1000. Furthermore, interference signals caused by external light signals or diffusely reflected light signals from the light-emitting device 400 can be blocked by the metallic second film 220.

[0126] The device layer 100 can be formed with a p-type silicon substrate. The protrusions PR1, PR2, and PR3 of the device layer 100 can be formed with n-type silicon. By forming a depletion layer with a vacuum using a p-type silicon substrate, electron-hole pairs generated by light can be formed, thereby increasing the photocurrent. However, the efficiency can be further improved by using a PN junction structure. In this regard, Figure 11 and Figure 12 FIG. 5 is a cross-sectional view showing an LED integrated device having a PN junction according to an embodiment.

[0127] Reference Figures 4 to 11 The upper regions of the protrusions PR1, PR2, and PR3 can be formed of n-type silicon. The lower regions of the protrusions PR1, PR2, and PR3 and the main body of the device layer 100 can be formed of a p-type silicon substrate. The main body of the device layer 100 can be formed flat so that the insulating layer 510 can be disposed on its upper end.

[0128] like Figure 11 , can also be formed by doping n-type dopants in the upper region of the protrusions PR1, PR2, PR3. Figure 12 , can also be formed by doping the protrusions PR1, PR2, PR3 and a portion of the substrate with n-type dopants. Figure 10 By confining the N-type dopant to the upper regions of the protrusions PR1, PR2, and PR3, photocurrent is generated for each probe. This prevents cross-talk between the photocurrents of the protrusions PR1, PR2, and PR3, reducing the possibility of arcing. However, due to the small area where photocurrent is generated, there are limitations on achieving sufficient photocurrent growth.

[0129] Reference Figures 4 to 10 、 Figure 12 The protrusions PR1, PR2, and PR3 and the upper region 100a of the main body of the device layer 100, which is integrally formed with the protrusions, can be formed of n-type silicon. The lower region 100b of the main body of the device layer 100 can be formed as a p-type silicon substrate. The upper region 100a of the main body of the device layer 100 and the lower region 100b of the main body of the device layer 100 form the device layer 100. The buried layer 20 can be stacked on the lower region 100b of the main body of the device layer 100.

[0130] like Figure 12 When n-type dopants are doped into the protrusions PR1, PR2, PR3 and a portion of the substrate, a higher photocurrent can be obtained. However, the photocurrent is not limited to the individual protrusions PR1, PR2, PR3 as a single probe part, so they may interfere with each other, causing reliability problems such as arcing. Therefore, it is necessary to appropriately select the desired emission current, reliability, etc. Figure 10 structure or Figure 12 structure.

[0131] On the other hand, the package 1000 with the field emission device of the present specification can be configured to emit photocurrent by applying a bias voltage. Figure 13Indicates a configuration in which a bias voltage is applied to a package having a field emission device. Figure 14 Indicates the emission current emitted by a light-emitting device according to the change in gate voltage.

[0132] Reference Figure 13 , the upper region 1000a and the lower region 1000b of the package 1000 having the field emission device can be bonded. The package 1000 having the field emission device can be bonded by Figure 13 The same structure is used to realize the X-ray emitter.

[0133] The cathode of the light-emitting device 400 and the cathode of the field emission device are connected to ground. The gate voltage Vg of the field emission device is connected to the gate electrode 520 of the field emission device, and the driving voltage Vled of the light-emitting device 400 is connected to the anode of the light-emitting device 400. Furthermore, to emit X-rays, an accelerating voltage is applied to the metal plate of the anode layer 1510. While tungsten can be used as the metal plate of the anode layer 1510, the metal plate is not limited thereto and may vary depending on the application. The accelerating voltage applied to the metal plate of the anode layer 1510 may be in the range of 20 to 150 kV.

[0134] The emission current of the light emitting device 400 can be adjusted by maintaining a constant gate voltage Vg of the field emission device while adjusting the current of the light emitting device 400. The gate voltage Vg of the field emission device can vary within a range of about 50 to 150V depending on the device.

[0135] Reference Figure 14 , represents the emission current that changes according to the gate voltage of the field emission device. Figure 13 The number of protrusions PR1, PR2, and PR3 is 52,500, and the area is 18.9 cm 2 It was confirmed that when the driving voltage Vled was applied through the light emitting device 400, the current increased to approximately 200 μA.

[0136] Reference Figures 4 to 14 , the bias voltage applied to the metal electrodes of the package 100 having a field emission device and the corresponding operation will be described. The gate voltage Vg may be applied to at least one of the gate electrode 520 and the first metal electrodes 1210 and 1220. The driving voltage Vled may be applied to at least one of the second metal electrode 1230 and the first metal electrodes 1210 and 1220.

[0137] On the other hand, an anode layer 1510 may be formed on the surface of the detector 1500 configured to detect an electron beam from a field emission device. An anode voltage Va may be applied to the anode layer 1510. The gate voltage Vg may vary. For example, the gate voltage Vg may vary within a range of 50V to 150V.

[0138] A fixed voltage may be applied as the anode voltage Va. For example, a fixed voltage in the range of 20 kV to 150 kV may be applied as the anode voltage Va. If the driving voltage Vled is not applied, the emission current of the electron beam emitted by the light-emitting device 400 may increase as the gate voltage Vg increases. For example, when the gate voltage Vg is in the range of 50 V to 100 V, the emission current of the electron beam emitted by the light-emitting device 400 may increase from 0 μA to 100 μA.

[0139] When the light-emitting device 400 emits light by applying the driving voltage Vled, the emission current may increase at a first slope within a range of the gate voltage Vg from 50 V to the first driving voltage. When the light-emitting device 400 emits light, the emission current may increase at a second slope smaller than the first slope within a range of the gate voltage Vg from the first driving voltage to 100 V. Characteristically, under the first driving voltage condition, the emission current is greater than 100 μA.

[0140] The above describes the package 1000 with a field emission device according to one aspect of the present specification. The following describes the X-ray device with a field emission device according to another aspect of the present specification. Figure 15 The present invention relates to an X-ray device having a field emission device, which generates electron-hole pairs by applying light to a p-type pn junction device, thereby increasing emission current.

[0141] Reference Figure 15 An X-ray device 2000 with a field emission device may include a main body 2010, an electron emission device 1000, and an X-ray emission device 1500. In an X-ray tube-based X-ray device 2000, an LED or other device may be attached to direct light to the electron emission device 1000 to increase the emission current. However, this increases the size of the X-ray tube, making it difficult to form a lens for focusing electrons. Furthermore, it is difficult to effectively focus light on the X-ray emission device 1500.

[0142] Therefore, in order to solve this problem, an electron emission device 1000 that emits electron beams related to X-rays may be arranged on one side of the X-ray device 2000. The electron emission device 1000 may be connected to Figures 4 to 14The upper structure 1000a and the lower structure 1000b of the package 1000 having a field emission device are shown.

[0143] On the other hand, the main body 2010 may have a front surface S1, a back surface S2, and a plurality of side surfaces. The main body 2010 may form the exterior of the X-ray device 2000. The electron emission device 1000 may be disposed inside the main body 2010 through a side surface S3. Figures 4 to 14 The package 1000 with the field emission device corresponds to. Figures 4 to 14 All the configurations and features of the package 1000 having a field emission device can be applied to the following X-ray apparatus 2000 having a field emission device.

[0144] The X-ray emitting device 1500 can be disposed inside the main body 2010 through the other side surface S4. The X-ray emitting device 1500 is composed of a metal target and emits X-rays when the emitted electron beam collides with the target with high energy. After reflection, the X-rays are emitted to the outside of the main body 2010 through the front surface S1 of the main body 2010.

[0145] An anode layer 1510 may be formed on the front surface Sb1 of the X-ray emitting device 1500 to collide with electrons emitted from the electron emitting device 1000. The front surface Sb1 of the X-ray emitting device 1500 may be formed in an inclined structure, tilted at a predetermined angle relative to the Z-axis. Therefore, the anode layer 1510 disposed on the front surface Sb1 of the X-ray emitting device 1500 may also be formed in an inclined structure, tilted at a predetermined angle relative to the Z-axis.

[0146] Reference Figures 4 to 15 , an X-ray device 2000 having a field emission device is described. The electron emission device 1000 of the X-ray device 2000 may include a device layer 100, a thin film 210, a transparent electrode 300, and a light-emitting device 400. The electron emission device 1000 may also include a handle layer 10, a buried layer 20, and a second thin film 220.

[0147] The buried layer 20 may be formed to be stacked on the handle layer 10. The device layer 100 may be formed to be stacked on the buried layer 20. The thin film 210 may be formed to be stacked on the lower end of one side region and the lower end of the other side region of the handle layer 10. The center portion of the handle layer 10 may be removed by an etching process. The handle layer 10 may be disposed at the lower end of one side region and the other side region, and an opening region 220R may be formed in the center portion.

[0148] The transparent electrode 300 may be formed on the lower end, the inner side surface of one side region, and the inner side surface of the other side region of the thin film 210. The transparent electrode 300 may be formed on the lower end of the device layer 100. At least one light-emitting device 400 may be disposed in the lower region of the transparent electrode 300. The light-emitting device 400 may be configured to emit light through the transparent electrode 300 and the device layer 100.

[0149] The electron emission device 1000 of the X-ray device 2000 having a field emission device can be combined with a lower region structure. The lower region structure of the electron emission device 1000 can include a wafer 1010. The lower region structure of the electron emission device 1000 can also include a first oxide layer 1110 and a second oxide layer 1120. The lower region structure of the electron emission device 1000 can also include first metal electrodes 1210 and 1220, and a second metal electrode 1230.

[0150] Wafer 1010 may be, but is not limited to, a silicon wafer and may vary depending on the application. A recessed region 1010a may be formed in the center of SOI wafer 1010 by etching. Protruding regions 1010b and 1010c that protrude from recessed region 1010a may be formed on one side and the other side of the center of SOI wafer 1010.

[0151] A first thickness t1 from the lower end of the SOI wafer 1010 to the upper end of the protruding regions 1010 b , 1010 c may be greater than a second thickness t2 from the lower end of the wafer 1010 to the upper end of the recessed region 1010 a .

[0152] A first oxide layer 1110 may be disposed in the recessed region 1010a at the top of the SOI wafer 1010 and in the raised regions 1010b and 1010c on one side and the other side of the recessed region 1010a. A second oxide layer 1120 may be disposed at the bottom of the SOI wafer 1010. The first oxide layer 1110 and the second oxide layer 1120 formed at the top and bottom of the SOI wafer 1010 form insulating films. Therefore, the first oxide layer 1110 may be referred to as a first insulating layer, and the second oxide layer 1120 may be referred to as a second insulating layer.

[0153] First metal electrodes 1210 and 1220 may be disposed on the protruding regions 1010b and 1010c of the SOI wafer 1010. A second metal electrode 1230 may be disposed on the recessed region 1010a of the SOI wafer 1010. A light emitting device 400 may be disposed on top of the second metal electrode 1230.

[0154] The first metal electrodes 1210 and 1220 can form the LED cathode. The second metal electrode 1230 can form the LED anode. The lower end of the light-emitting device 400 can be disposed in the recessed area 1010a formed with the second metal electrode 1230. The upper end of the light-emitting device 400 can be disposed in the opening area of ​​the handle layer 10 of the upper structure of the package 1000.

[0155] The light-emitting device 400 may include a plurality of LEDs 410, 420, and 430, each of which is spaced apart along a vertical axis in a region where the second metal electrode 1230 is formed. The light-emitting device 400 may be implemented as any light-emitting device, not limited to an LED. One side and the other side of each of the plurality of LEDs 410, 420, and 430 may be connected to the first metal electrode 1210 on one side and the first metal electrode 1220 on the other side of the protruding regions 1010b and 1010c of the wafer 1010 by wire bonding. The one side and the other side of each of the plurality of LEDs 410, 420, and 430 may also be connected to the first metal electrodes 1210 and 1220 by other bonding structures other than wire bonding. For example, the one side and the other side of each of the plurality of LEDs 410, 420, and 430 may also be connected to the first metal electrodes 1210 and 1220 by a bonding structure within the wafer 1010.

[0156] The upper and lower structures of package 1000 can be combined through one side region and another side region. The second film 220 at the lower end of the upper structure of package 1000 can be connected to the first metal electrodes 1210 and 1220 forming the LED cathode at the upper end of the lower structure of package 1000.

[0157] The upper structure of the package 1000 may further include an insulating layer 510 and a gate electrode 520. The insulating layer 510 may be formed to be stacked on an upper region of the device layer 100. The gate electrode 520 may be formed to be stacked on an upper region of the insulating layer 510.

[0158] The insulating layer 510 may be composed of a plurality of insulating regions IR1, IR2, IR3, and IR4 separated by a first separation region. The gate electrode 520 may be composed of a plurality of metal regions MR1, MR2, MR3, and MR4 separated by a second separation region. Each of the plurality of metal regions MR1, MR2, MR3, and MR4 forming the gate electrode 520 may be stacked on top of each of the plurality of insulating regions IR1, IR2, IR3, and IR4 of the insulating layer 510.

[0159] Device layer 100 may have protrusions PR1, PR2, and PR3. The protrusions PR1, PR2, and PR3 of device layer 100 may be formed to protrude between insulating regions IR1, IR2, IR3, and IR4 and metal regions MR1, MR2, MR3, and MR4. On the Z-axis, the upper ends of the protrusions PR1, PR2, and PR3 may be positioned higher than the upper ends of the insulating regions IR1, IR2, IR3, and IR4. On the Z-axis, the upper ends of the protrusions PR1, PR2, and PR3 may be positioned higher than the upper ends of the metal regions MR1, MR2, MR3, and MR4.

[0160] The second film 220 of the upper structure of the package 1000 may be formed corresponding to the shape of the transparent electrode 300. The second film 220 of the upper structure of the package 1000 may be formed on the lower end of the transparent electrode 300, the inner side surface of one side region of the transparent electrode 300, and the inner side surface of the other side region.

[0161] The second film 220 can form an opening region 220R corresponding to the center portion of the transparent electrode 300 stacked on the device layer 100. The opening region 220R of the second film 220 can be formed at the upper end of the handle layer 10 with a first opening length AL1. The opening region 220R of the second film 220 can be formed at the lower end of the handle layer 10 with a second opening length AL2. The second opening length AL2 of the opening region 220R of the second film 220 can be longer than the first opening length AL1. The horizontal axial length of the light-emitting device 400 can be shorter than the first opening length AL1. Thus, direct light emitted from the light-emitting device 400 with a predetermined wide angle can be transmitted through the transparent electrode 300 to the upper structure of the package 1000. Furthermore, interference signals caused by external light signals or light signals diffusely reflected from the light-emitting device 400 can be blocked by the metallic second film 220.

[0162] The device layer 100 can be formed using a p-type silicon substrate. The protrusions PR1, PR2, and PR3 formed on the upper portion of the device layer 100 can be formed using n-type silicon. The following describes the bias voltages applied to the metal electrodes of the electron emission device 1000 of the X-ray device 2000 having a field emission device and the corresponding operation. A gate voltage Vg can be applied to at least one of the gate electrode 520 and the first metal electrodes 1210 and 1220. A driving voltage Vled can be applied to at least one of the second metal electrode 1230 and the first metal electrode 1210.

[0163] On the other hand, an anode layer 1510 can be formed on the surface of a detector 1500 configured to detect an electron beam from a field emission device. Anode layer 1510 can be tilted at a predetermined angle along the Z axis. An anode voltage Va can be applied to at least one of anode layer 1510 and first metal electrodes 1210 and 1220. The gate voltage Vg can vary within a range of 50 V to 150 V.

[0164] A fixed voltage ranging from 20 kV to 150 kV may be applied as the anode voltage Va. If the driving voltage Vled is not applied, the emission current of the electron beam emitted by the light emitting device 400 may increase from 0 μA to 100 μA when the gate voltage Vg is within the range of 50 V to 100 V.

[0165] When the light-emitting device 400 emits light by applying the driving voltage Vled, the emission current may increase at a first slope within a range of the gate voltage Vg from 50V to the first driving voltage. When the light-emitting device 400 emits light, the emission current may increase at a second slope smaller than the first slope within a range of the gate voltage Vg from the first driving voltage to 100V. The emission current is greater than 100u under the first driving voltage condition.

[0166] The package having a field emission device and the X-ray device having the package have been described above. Next, the technical effects of the package having a field emission device and the X-ray device having the package will be described.

[0167] According to the present specification, a package including a field emission device and an X-ray apparatus including the package can be provided.

[0168] According to the present specification, in order to improve current density and ensure reliability in a package and an X-ray device, the current of a single probe can be effectively adjusted.

[0169] According to this specification, the principle that a p-type or pn junction generates carriers when receiving light energy can be used to provide a structure and a manufacturing method for a device integrating a probe formed on a p-type wafer and an LED (or LD).

[0170] According to this specification, current is adjusted by light from a light emitting device, thereby ensuring reliability by preventing excessive current from flowing in a single probe, and current density of emitted electrons can be adjusted by adjusting the intensity of LED light.

[0171] The above detailed description will further clarify the scope of the additional application of this specification. However, since those skilled in the art can clearly understand the various changes and modifications within the concept and scope of this specification, it should be understood that the specific embodiments described in the detailed description and the preferred embodiments of this specification are only examples.

Claims

1. A package having a field emission device, wherein: include: Processing layer; a buried layer stacked on the processing layer; a device layer stacked on the buried layer; an insulating layer stacked on an upper region of the device layer; a gate electrode stacked on an upper region of the insulating layer; as well as at least one light-emitting device, disposed in a lower region of the device layer and configured to emit light through the device layer; The insulating layer is composed of a plurality of insulating regions separated by first separation regions, and the gate electrode is composed of a plurality of metal regions separated by second separation regions. The device layer has a protrusion formed to protrude between the first separation region between the insulating regions and the second separation region between the metal regions.

2. The package having a field emission device according to claim 1, wherein The device layer is formed with a p-type silicon substrate, The protruding portion of the device layer is formed of n-type silicon.

3. The package having a field emission device according to claim 2, wherein: The upper region of the protrusion is formed of n-type silicon, The lower region of the protrusion and the main body of the device layer are formed of a p-type silicon substrate. The main body portion of the device layer is formed flatly so that the insulating layer is disposed on an upper end of the main body portion.

4. The package having a field emission device according to claim 2, wherein: The protrusion and the upper region of the main body of the device layer formed integrally with the protrusion are formed of n-type silicon. The lower region of the main body is formed with a p-type silicon substrate. The buried layer is stacked on the lower end of the lower region of the main body.

5. The package having a field emission device according to claim 1, wherein Also included is an SOI wafer, wherein a recessed area is formed in the center of the SOI wafer by an etching process, A convex region that is more convex than the concave region is formed in one side region and the other side region of the central portion of the wafer. A first thickness from a lower end of the wafer to an upper end of the protruding region is thicker than a second thickness from a lower end of the wafer to an upper end of the recessed region.

6. The package having a field emission device according to claim 5, wherein: Also includes: a first oxide layer disposed on the recessed area at the upper end of the wafer, and on one side and the other side of the recessed area; a second oxide layer disposed on the lower end of the wafer; A first metal electrode is disposed on the protruding area; and a second metal electrode disposed in the recessed area; The light emitting device is disposed on the upper portion of the second metal electrode.

7. The package having a field emission device according to claim 6, wherein: The first metal electrode forms the LED cathode, and the second metal electrode forms the LED anode. The lower end of the light emitting device is disposed in the recessed area where the second metal electrode is formed, and the upper end of the light emitting device is disposed in the open area of ​​the handling layer.

8. The package having a field emission device according to claim 7, wherein: The light emitting device is configured as a plurality of LEDs spaced apart along a vertical axis in a region where the second metal electrode is formed. One side and the other side of each of the plurality of LEDs are connected to the first metal electrode on one side and the first metal electrode on the other side of the protruding region by wire bonding.

9. The package having a field emission device according to claim 1, in, include: a thin film stacked on the lower end of one side region and the lower end of the other side region of the processing layer, wherein the central portion of the processing layer is removed by an etching process, and the processing layer is arranged in the one side region and the other side region to form an opening region in the central portion; as well as A transparent electrode is formed on the lower end of the film, the inner side surface of the one side region, the inner side surface of the other side region, and the lower end of the device layer.

10. An X-ray device having a field emission device, wherein: include: a main body having a front surface, a back surface, and a plurality of side surfaces, forming the appearance of the X-ray device; an electron emission device, disposed inside the X-ray device through a side surface of the main body; as well as An X-ray emitting device is disposed inside the X-ray device through the other side surface of the main body, so that the electron beam emitted from the electron emitting device is reflected and emitted to the outside of the main body through the front surface. The electron emission device comprises: Processing layer; a buried layer stacked on the processing layer; a device layer stacked on the buried layer; an insulating layer stacked on an upper region of the device layer; a gate electrode stacked on an upper region of the insulating layer; and at least one light-emitting device, disposed in a lower region of the device layer and configured to emit light through the device layer; The insulating layer is composed of a plurality of insulating regions separated by first separation regions, and the gate electrode is composed of a plurality of metal regions separated by second separation regions. The device layer has a protrusion formed to protrude between the first separation region between the insulating regions and the second separation region between the metal regions.

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