Phase modulation system and method

Abstract

The subject matter of the present disclosure is a phase modulation system and method. In a phase modulation method, an enable signal may be sequentially generated based on a clock signal to generate an enable signal sequence, and a signal is delayed based on the enable signal sequence and a digital bit value by a delay value generated from a delay unit. The phase modulator may include a first delay circuit configured to: delay a clock signal based on a first delay value to generate a first delayed clock signal; and delaying a carrier signal based on the first delayed clock signal to generate a first delayed carrier signal; and a second delay circuit configured to: delay the first delayed clock signal based on a second delay value to generate a second delayed clock signal; and delaying the first delayed carrier signal based on the second delayed clock signal to generate a second delayed carrier signal.

Description

[0001] This application is a divisional application of the invention patent application with international application number PCT / US2019 / 026977, international application date April 11, 2019, application number 201980044689.9, and invention name “Phase Modulation System and Method”, which entered the Chinese national phase on December 31, 2020. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate aspects of the disclosure and, together with the description, further serve to explain the principles of the aspects and to enable one skilled in the relevant art to make and use the aspects.

[0003] Figure 1 A communication device according to an exemplary aspect of the present disclosure is shown.

[0004] Figure 2 A polar transmitter according to an exemplary aspect of the present disclosure is shown.

[0005] Figure 3 A phase modulator according to an exemplary aspect of the present disclosure is shown.

[0006] Figure 4 A phase modulator according to an exemplary aspect of the present disclosure is shown.

[0007] Figures 5A to 5B Settling time results based on process and temperature variations according to exemplary aspects of the present disclosure are shown.

[0008] Figures 6A to 6B Signal reconstruction and spectrum analysis according to exemplary aspects of the present disclosure are shown.

[0009] 7A to 7C A phase modulator according to an exemplary aspect of the present disclosure is shown.

[0010] Figure 8 A delay unit according to an exemplary aspect of the present disclosure is shown.

[0011] Figure 9 A delay unit according to an exemplary aspect of the present disclosure is shown.

[0012] Figure 10 Phase-based insertion loss analysis and input matching analysis according to exemplary aspects of the present disclosure are shown.

[0013] Figures 11A to 11B Settling time results according to exemplary aspects of the present disclosure are shown.

[0014] Figure 12 Phase transition performance according to exemplary aspects of the present disclosure is shown.

[0015] 13A to 13B Signal reconstruction and spectrum analysis according to exemplary aspects of the present disclosure are shown.

[0016] Figure 14 A flow chart illustrating a phase modulation method according to an exemplary aspect of the present disclosure is shown.

[0017] Figure 15 A flow chart illustrating a phase modulation method according to an exemplary aspect of the present disclosure is shown.

[0018] Exemplary aspects of the present disclosure will be described with reference to the accompanying drawings.The drawing in which an element first appears is generally indicated by the leftmost digit(s) in the corresponding reference number. DETAILED DESCRIPTION

[0019] Numerous specific details are shown in the following description in order to provide a thorough understanding of various aspects of the present disclosure. However, it will be apparent to those skilled in the art that aspects including structures, systems, and methods can be practiced without these specific details. The descriptions and representations herein are general means for those skilled in the art to most effectively convey the essence of their work to others skilled in the art. In other cases, well-known methods, processes, components, and circuits have not been described in detail to avoid unnecessarily obscuring various aspects of the present disclosure.

[0020] Aspects described herein generally relate to phase modulation systems and methods, including polar phase modulation systems and methods, such as polar phase modulators. Aspects may also include wireless networks, wireless communications, and corresponding wireless communication devices that implement one or more polar modulation systems (e.g., polar phase modulators).

[0021] Various aspects of the present disclosure will be described with reference to a wireless system configured for use in the millimeter wave (mmWave) spectrum (e.g., 24 GHz-300 GHz), but is not limited thereto. In one or more aspects, the system is configured to operate at a carrier frequency of 71 GHz to 76 GHz and a carrier signal bandwidth of 2 GHz, but is not limited thereto. Various aspects of the present disclosure may be applied to fifth generation (5G) wireless technologies and related spectrum, or other wireless technologies and spectrum, as will be understood by one of ordinary skill in the relevant art.

[0022] Wireless communications are expanding to include communications with increasing data rates (e.g., from Institute of Electrical and Electronics Engineers (IEEE) 802.11a / g to IEEE 802.11n to IEEE 802.11ac, etc.). Currently, 5G cellular communications and the Wireless Gigabit Alliance (WiGig) standard are being introduced for wireless cellular devices and / or wireless local area networks (WLANs).

[0023] Some aspects of the present disclosure relate to wireless local area networks (WLANs) and Wi-Fi networks, including networks operating according to the Institute of Electrical and Electronics Engineers (IEEE) 802.11 family of standards, such as IEEE 802.11ac, IEEE 802.11ad, and IEEE 802.11ay, the IEEE 802.11ax Study Group (SG) (known as DensiFi), and the Wireless Gigabit Alliance (WiGig). Other aspects of the present disclosure relate to mobile wireless communication devices such as 4G and 5G cellular communication standards. The technical field more particularly relates to radar systems and radar systems that can be implemented in communication systems.

[0024] Figure 1 A communication device 100 is shown according to an exemplary aspect of the present disclosure. The communication device 100 is configured to transmit and / or receive wireless communications via one or more wireless technologies. For example, the communication device 100 can be configured for wireless communications that conform to, for example, one or more fifth generation (5G) cellular communication protocols, such as a 5G protocol using a 28 GHz spectrum, and / or a communication protocol conforming to the Wireless Gigabit Alliance (WiGig) standard, such as IEEE 802.11ad and / or IEEE 802.11ay using a 60 GHz spectrum. The communication device 100 is not limited to these communication protocols and can be configured for one or more additional or alternative communication protocols, such as one or more 3rd Generation Partnership Project (3GPP) protocols (e.g., Long Term Evolution (LTE)), one or more wireless local area network (WLAN) communication protocols, and / or one or more other communication protocols, as will be understood by one of ordinary skill in the relevant art. For example, the communication device 100 can be configured to transmit and / or receive wireless communications using one or more communication protocols that utilize the millimeter wave (mmWave) spectrum (e.g., 24 GHz-300 GHz), such as WiGig (IEEE 802.11ad and / or IEEE 802.11ay) operating at 60 GHz and / or one or more 5G protocols using, for example, the 28 GHz spectrum.

[0025] The communication device 100 may be configured to communicate with one or more other communication devices, including, for example, one or more base stations, one or more access points, one or more other communication devices, and / or one or more other devices, as will be understood by one of ordinary skill in the relevant art.

[0026] In an exemplary aspect, the communication device 100 includes a controller 140 communicatively coupled to one or more transceivers 105 .

[0027] The transceiver 105 is configured to transmit and / or receive wireless communications via one or more wireless technologies. In an exemplary aspect, the transceiver 105 includes a processor circuit configured to transmit and / or receive wireless communications conforming to one or more wireless protocols.

[0028] In an exemplary aspect, the transceiver 105 includes a transmitter 110 and a receiver 120 configured to transmit and receive wireless communications, respectively, via one or more antennas 130. In aspects having two or more transceivers 105, the two or more transceivers 105 may have their own antennas 130, or may share a communication antenna via a duplexer. In an exemplary aspect, the transceiver 105 (including the transmitter 110 and / or the receiver 120) is configured to perform one or more baseband processing functions (e.g., media access control (MAC), encoding / decoding, modulation / demodulation, data symbol mapping; error correction, etc.).

[0029] In an exemplary aspect, transmitter 110 is a polar transmitter 110 configured to perform one or more polar modulation operations, and receiver 120 is a Cartesian receiver 120 configured to perform one or more Cartesian demodulation operations (e.g., demodulating the in-phase component and the quadrature-phase component of the received signal). In these aspects, transmitter 110 is a polar transmitter and receiver 120 is a Cartesian receiver, but the present disclosure is not limited in this regard. In other aspects, receiver 120 is also a polar receiver configured to perform one or more polar demodulation operations.

[0030] Antenna 130 may include one or more antenna elements forming an integer array of antenna elements. In an exemplary aspect, antenna 130 is a phased array antenna that includes a plurality of radiating elements (antenna elements), each radiating element having a corresponding phase shifter. Antenna 130 configured as a phased array antenna may be configured to perform one or more beamforming operations, including generating a beam formed by shifting the phase of a signal transmitted from each radiating element to provide constructive / destructive interference in order to steer the beam in a desired direction.

[0031] In an exemplary aspect, controller 140 includes processor circuitry 150 configured to control overall operation of communication device 100, such as operation of transceiver 105. Processor circuitry 150 may be configured to control transmission and / or reception of wireless communications via transceiver 105.

[0032] In an exemplary aspect, the processor circuit 150 is configured to perform one or more baseband processing functions (e.g., media access control (MAC), encoding / decoding, modulation / demodulation, data symbol mapping; error correction, etc.) in cooperation with the transceiver 105 or in lieu of performing such operations / functions by the transceiver 105. The processor circuit 150 is configured to run one or more applications and / or operating systems; power management (e.g., battery control and monitoring); display settings; volume control; and / or user interaction via one or more user interfaces (e.g., keyboard, touch screen display, microphone, speaker, etc.) in one or more aspects.

[0033] In an exemplary aspect, controller 140 also includes a memory 160 that stores data and / or instructions that, when executed by processor circuit 150 , control processor circuit 150 to perform the functions described herein.

[0034] Memory 160 can be any known volatile and / or nonvolatile memory, including, for example, read-only memory (ROM), random access memory (RAM), flash memory, magnetic storage media, optical disks, erasable programmable read-only memory (EPROM), and programmable read-only memory (PROM). Memory 160 can be non-removable or removable, or a combination of both.

[0035] Examples of communication device 100 include (but are not limited to) mobile computing devices (mobile devices) such as laptop computers, tablet computers, mobile phones or smartphones, "phablets," personal digital assistants (PDAs), and mobile media players; wearable computing devices such as computerized wristwatches or "smart" watches and computerized glasses; and / or Internet of Things (IoT) devices. In some aspects of the present disclosure, communication device 100 may be a fixed communication device, including, for example, a fixed computing device such as a personal computer (PC), a desktop computer, a television, a smart home device, a security device (e.g., an electronic / smart lock), an ATM, a computerized self-service terminal, and / or an automotive / aviation / marine dashboard computer terminal.

[0036] In one or more aspects, the communication device 100 or one or more components of the communication device 100 are additionally or alternatively configured to perform digital signal processing (e.g., using a digital signal processor (DSP)), modulation and / or demodulation (using a modulator / demodulator), digital-to-analog conversion (DAC) and / or analog-to-digital conversion (ADC) (using corresponding DA and AD converters), encoding / decoding (e.g., using a coder / decoder with convolution, tail-biting, turbo, Viterbi and / or low-density parity check (LDPC) functions), frequency conversion (e.g., using a mixer, a local oscillator and a filter), fast Fourier transform (FFT), precoding and / or constellation mapping / demapping to transmit and / or receive wireless communications in accordance with one or more wireless protocols, and / or facilitate beamforming scanning operations and / or beamforming communication operations.

[0037] Figure 2 1. Shown is a transmitter 200 according to an exemplary aspect of the present disclosure. In one aspect, transmitter 200 is an implementation of transmitter 110.

[0038] In an exemplary aspect, transmitter 200 includes a rectangular to polar converter 205, a phase modulator 210, a decoder 215, and a digital power amplifier 220. In an exemplary aspect, digital power amplifier 220 includes one or more amplifiers 225.1 through 225.N and a summer 230. In an exemplary aspect, amplifier 225 is a power amplifier subunit.

[0039] In an exemplary aspect, the rectangular to polar converter 205 is configured to receive an input signal having an in-phase component 202 and a quadrature component 203 and convert the rectangular in-phase component (I) 202 and the quadrature component (Q) 203 into a signal having an amplitude (α) and a phase (α). In an exemplary aspect, the rectangular to polar converter 205 includes a processor circuit configured to convert the rectangular in-phase component (I) 202 and the quadrature component (Q) 203 into a polar output signal having an amplitude (α) component and a phase (α) component. In an exemplary aspect, the rectangular to polar converter 205 includes a digital circuit configured to convert the rectangular in-phase component (I) 202 and the quadrature component (Q) 203 into a polar output signal having an amplitude (α) component and a phase (α) component. Polar coordinate output signal of the components.

[0040] In an exemplary aspect, the amplitude (α) component and the phase The weight is determined based on the following equation:

[0041]

[0042] In an exemplary aspect, the phase modulator 210 is configured to receive the phase Components, and modulate the phase to generate one or more phase modulated (e.g., phase shifted) signals. The phase modulated signal may be provided to the digital power amplifier 220, such as to a corresponding amplifier 225 of the digital power amplifier 220. In an exemplary aspect, the phase modulator 210 is a polar coordinate phase modulator. In an exemplary aspect, the phase modulator 210 includes a processor circuit (e.g., a digital circuit) configured to modulate the phase to generate one or more phase modulated (e.g., phase shifted) signals. Figure 3 and Figure 4 Additional aspects of the phase modulator 210 are described.

[0043] In an exemplary aspect, decoder 215 is configured to receive the amplitude (α) from rectangular to polar converter 205 and decode the amplitude (α) to generate one or more decoded signals. In an exemplary aspect, the decoded signal is an envelope control signal. The decoded signal may be provided to digital power amplifier 220, such as to a corresponding amplifier 225 of digital power amplifier 220. In an exemplary aspect, the decoded signal provided to amplifier 225 operates as a control signal (e.g., an envelope control signal) to turn digital power amplifier 220 on or off, thereby adjusting the output power of digital power amplifier 220 or modulating the envelope of the RF output signal. In an exemplary aspect, the decoded signal provided to amplifier 225 operates as a control signal to obtain the gain of the corresponding amplifier 225. In an exemplary aspect, decoder 215 includes a processor circuit (e.g., a digital circuit) configured to decode the amplitude (α) to generate one or more decoded signals (e.g., a control signal for modulating the envelope of digital power amplifier 220).

[0044] In an exemplary aspect, the digital power amplifier 220 is configured to receive a phase modulated (e.g., phase shifted) signal from the phase modulator 210 and a decoded signal from the decoder 215, and to generate a radio frequency (RF) output signal 235 based on the received phase modulated (e.g., phase shifted) signal and the decoded signal.

[0045] In an exemplary aspect, amplifier 225 is turned on or off depending on a control signal (eg, envelope control signal) from decoder 215. The outputs from amplifier 225 are then summed / added by adder 230 to produce envelope modulated RF output signal 235.

[0046] In an exemplary aspect, the amplified signals 227 are provided to an adder (or summer) 230. The adder 230 is configured to combine the amplified signals 227 to generate an RF output signal 235 (e.g., an envelope modulated RF output signal). In an exemplary aspect, the adder 230 is configured to add the amplified signals 227 together to generate the RF output signal 235. The RF output signal 235 can then be provided to an antenna (e.g., antenna 130) for transmission.

[0047] Figure 3 A phase modulator 300 is shown according to an exemplary aspect of the present disclosure. In an exemplary aspect, the phase modulator 300 is an implementation of the phase modulator 210.

[0048] In an exemplary aspect, the phase modulator 300 includes an artificial transmission line (ATL) having an input 305 that receives an input signal V from, for example, an unmodulated frequency generator (e.g., at mmWave frequencies). RF In an exemplary aspect, the unmodulated frequency generator is a mmWave phase-locked loop (PLL). In this example, the digital control bits b1 to b k Corresponding to the phase from the rectangular to polar converter 205 In an exemplary aspect, the phase modulator 300 includes one or more delay units 310.1 to 310.K configured to delay a received signal (e.g., an input signal or an output from a previous delay unit 310) to generate a corresponding delayed signal. In an exemplary aspect, the delay units 310.1 to 310.K are configured to delay a received signal (e.g., an input signal or an output from a previous delay unit 310) based on the corresponding digital bits b1 to b2. k In an exemplary aspect, the delay units 310.1 to 310.K are arranged consecutively (eg, in cascade) to form a transmission line. In an exemplary aspect, the delay t of the delay unit 310 is d The following equation is satisfied:

[0049] t d =t0+b x Δt

[0050] Where t0 is the input to the delay cell, b is a digital bit, where x corresponds to the number within the delay cell sequence, and Δt is the delay constant. In an exemplary aspect, all digital bits b1 to b k The update is performed at time τ (ie, all bits are updated at the same time / simultaneously).

[0051] In an exemplary aspect, the phase modulator 300 is configured to linearly phase shift an input signal. In an exemplary aspect, due to the passive structure of the phase modulator implemented using a transmission line (e.g., ATL), the phase modulator 300 advantageously reduces process, voltage, temperature (PVT) variations (e.g., compared to active phase modulation systems), supports a large bandwidth due to the dispersion-free propagation and small impedance / insertion loss variations across the phase-shifted code. Figure 3 As shown, in the phase shifter of the phase modulator 300, the phase shift code (i.e., digital bit b) at each delay cell 310 changes simultaneously at a time point τ0. In this example, an instantaneous phase shift is generated at each delay cell 310. By this instantaneous phase shift, the phase shift at a particular delay cell 310 is achieved at the output (e.g., at RL) only after passing through all subsequent delay cells 310 in the continuous arrangement. For example, the phase shift at delay cell 310.1 is achieved at the output only after propagating through all subsequent delay cells 310.2 to 310.K. In operation, any change in delay that occurs at an earlier stage (e.g., delay cell 310.1) takes longer to appear at the output of the phase modulator 300 than at a later stage (e.g., delay cell 310.3) in the continuous arrangement. In one aspect, the worst-case settling time of the phase shifter of the phase modulator 300 is limited by the propagation delay starting from the first delay cell 310.1 in the transmission line. As Figure 3 As shown in the lower part, with the digital bits b1 to b k Updated simultaneously, the delay applied to the unmodulated carrier waveform (V RF ) on the differences.

[0052] Figure 4 A phase modulator 400 is shown according to an exemplary aspect of the present disclosure. In an exemplary aspect, the phase modulator 400 is an implementation of the phase modulator 210.

[0053] In an exemplary aspect, phase modulator 400 includes a first artificial transmission line (ATL) 401 and a second artificial transmission line 403. In one aspect, ATL 401 is similar to the ATL of phase modulator 300.

[0054] In an exemplary aspect, the phase modulator 400 includes one or more delay circuits 430.1 through 430.K. In one aspect, the delay circuits 430.1 through 430.K are arranged consecutively along the ATLs 401 and 403. In this arrangement, the delay circuit 430.1 is arranged closer to the inputs 405 and 407 of the ATLs 401 and 403, respectively, while the delay circuit 430.K is positioned closer to the respective outputs (e.g., R L and R L,CK ).

[0055] In an exemplary aspect, one or more (or each) of the delay circuits 430 includes a first delay unit 410, a second delay unit 415, and a memory 420. In an exemplary aspect, the memory 420 is a retiming circuit 420. In an exemplary aspect, the memory 420 (retiming circuit 420) is a flip-flop or a latch, but is not limited thereto. In an exemplary aspect, the memory 420 is a D flip-flop (i.e., a data flip-flop or a delay flip-flop) and includes an enable input, a data input for receiving a data bit, and a data output configured to output the bit value at the data input based on the signal value at the enable input. For example, if the data input has a bit value of "1," the data output will output a bit value of "1" at the next rising edge of the clock signal provided to the enable input. In this example, the flip-flop 420 is a clocked (synchronous or edge-triggered) flip-flop.

[0056] In an exemplary aspect, ATL 401 is a transmission line based phase shifter that carries a carrier signal V RF (e.g., an unmodulated mmWave sinusoidal carrier signal), and ATL 403 carries the sampling clock V CK In an exemplary aspect, the delay unit 410 of the delay circuit 430 is configured to delay a received signal (eg, an input carrier signal V RF or the output from the previous delay unit 410) to generate a corresponding delayed signal. For example, the delay unit 410 receives an input carrier signal V RF (e.g., phase from rectangular to polar converter 205 component) and generates an input carrier signal V corresponding to the input carrier signal delayed by the delay value RF The delayed output V O,1 In an exemplary aspect, the delayed output of delay unit 410 satisfies the following equation:

[0057] V O =t0+b x Δt

[0058] where t0 is the input to the delay cell, b is the digital bit, where x corresponds to the number within the delay cell sequence, and Δt is the delay constant.

[0059] In an exemplary aspect, each of the flip-flops 420.1 through 420 is configured to receive a respective digital bit b1 through b2 at its corresponding data input. k The flip-flop 420 is configured to receive a sampling clock V from the ATL 403 based on the sampling clock V CK In an exemplary aspect, the second delay unit 415 of the corresponding delay circuit 430 is configured to delay the received signal (eg, the received clock signal VCK or output from a previous delay unit 415) to generate a corresponding delayed clock signal. In an exemplary aspect, delay units 415.1 through 415.K have the same fixed delay (e.g., a fixed delay equal to t0). The present disclosure is not limited to a common fixed delay, and in other aspects, the delays of delay units 415 are variable and / or different.

[0060] In an exemplary aspect, delay cells 415.1 through 415.K carry clock signal V CK The ATL 403 of the delay unit 415 is arranged in series (eg, cascaded). In an exemplary aspect, the delay t CK The following equation is satisfied:

[0061] t CK =t IN +t0

[0062] where t IN is the input to the delay unit 415 , and t 0 is the delay of the delay unit 415 (eg, a fixed delay).

[0063] In an exemplary embodiment, the delay t0 of each delay unit 415 is additive based on a sequential arrangement. For example, the outputs of delay units 415.1 through 415.K are delayed by t0, 2t0, ..., kt0, respectively. In operation, the corresponding flip-flops 420 are sequentially enabled along ATL 403 based on the increasing delay of the clock signal. For example, flip-flops 420.1 through 420.K are enabled at times t0, 2t0, ..., kt0, respectively. Therefore, at times t0, 2t0, ..., kt0, respectively, the corresponding bits b1 through b2 are enabled. k This sequential enabling differs from the simultaneous updating of digital bits b1 to b2 in that the delay units 410.1 to 410.K are enabled. k Operation of the phase modulator 300.

[0064] In an exemplary aspect, the delays of both ATLs 401, 403 are matched to the first stage by layout so that the rising edge of the sampling clock arrives at the delay unit 415 after a similar (or identical) delay as the RF signal passing through the main phase shifter 410. In this example, the sampling clock is retimed to the phase shift code by a flip-flop 420.

[0065] In an exemplary operation, the carrier and phase shift code in the phase modulator 400 are applied at the i-th delay circuit 430 with the same delay i×t0. o,i The resulting delay change at is applied to the same point on the carrier waveform as the sum of the delays from all previous stages, as Figure 4As shown in the lower part of . In this example, instead of the ATL of the phase modulator 300 in which all codes are updated simultaneously, the codes in the phase modulator 400 are applied after delay compensation, and the delay changes (i.e., Δt) in each delay circuit are coherently added at the output. This advantageously provides a faster settling time compared to the phase modulator 300. As another advantage, the phase modulator 400 is robust against PVT variations and achieves linear phase shift across codes. Moreover, the phase modulator 400 can be configured such that the phase modulator 400 is calibration-free at mmWave frequencies.

[0066] exist Figures 5A to 6B The performance of the phase modulator 400 is shown in FIG. Figure 5A , it is shown that the phase modulator 400 exhibits a settling time of less than 20 picoseconds over process variations (e.g., over typical slow corners and fast corners). Similarly, the phase modulator 400 exhibits a settling time of less than 20 picoseconds over temperature variations (for a 180 degree phase shift at the phase shifter output at a 72 GHz carrier frequency, at temperatures of -40°C, 27°C, and 110°C), as shown in FIG. Figure 5B In these figures, the phase change occurs within less than 1 cycle of the waveform (i.e., <20 ps) at a 72 GHz carrier frequency. Figure 6A shows the constellation diagram of a 16QAM signal reconstructed at a 2GS / s symbol rate, and Figure 6B The spectral mask for WiGig (IEEE 802.11ad) is shown. In this example, the phase modulator performs better than -31 dB and 2.8% EVM without any PVT calibration when meeting the spectral mask.

[0067] 7A to 7C A phase modulator 700 is shown according to an exemplary aspect of the present disclosure. In these figures, exemplary operating states 701, 702, and 703 of the phase modulator are shown. In an exemplary aspect, the phase modulator 700 is an implementation of the phase modulator 210.

[0068] In an exemplary aspect, the phase modulator 700 includes one or more delay cells 710 forming an artificial transmission line (ATL). In an exemplary aspect, the phase modulator 700 includes five delay cells 710.1 through 710.5, but is not limited thereto. The delay cells 710 are arranged in series, with the output of one delay cell 710 being provided as an input to the next delay cell 710 in the arrangement. In an exemplary aspect, the delay cells 710 are configured to selectively operate in a high-delay operating state and a low-delay operating state. By selecting the delay state, the boundary 705 between the high-delay state and the low-delay state shifts along the arrangement of the delay cells 710.

[0069] like 7A to 7C As shown, in an exemplary aspect, the delay units 710.1 and 710.5 on the input and output are configured to be in a high delay state and a low delay state, respectively, but are not limited thereto.

[0070] In an exemplary aspect, the total delay of the phase modulator 700 is the sum of the corresponding delays of each of the delay cells 710 forming the ATL structure. In an exemplary aspect, the phase modulator 700 is configured with a variable delay by adjusting the delay state (between a high delay state and a low delay state) of one or more of the delay cells 710 arranged along the ATL. The adjustment of the delay state moves the boundary 705 between the two edge delay cells 710.1 and 710.5 toward the input side (delay cell 710.1) to reduce the delay ( Figure 7B ), or move towards the output side (delay unit 710.5) to increase the delay of the ATL structure ( Figure 7C ).

[0071] In an exemplary embodiment, phase modulator 700 is a differential ATL-based phase modulator. In this example, phase modulator 700 receives a differential signal at the input side (i.e., the input to delay unit 710.1). The two signals of the differential signal (positive "+" and negative "-") are each split into two signals, so that delay unit 710 includes four signal lines (two positive signal lines and two negative signal lines).

[0072] In an exemplary aspect, the delay state of each of the delay cells 710 is digitally controlled. As explained in more detail below, the phase modulator 700 provides a coarse phase shifter that advantageously reduces active area and switching glitches. In an exemplary aspect, the phase modulator 700, configured as a coarse phase shifter, is arranged in a cascade arrangement with fine phase shifters based on single-ended ATL to cover a wide phase shift range with fine phase resolution. In addition, the settling time of the phase modulator 700 advantageously supports high data rates with high phase accuracy over PVT. Furthermore, due to the differential arrangement of the ATL, the phase modulator 700 generates negligible glitches during phase transitions and is not affected by external noise.

[0073] Figure 8An exemplary aspect of a delay cell 710 is shown. In this aspect, the differential delay cell 710 includes two identical differential lines that are magnetically and electrically coupled to each other. The coupling strength can be digitally programmed by rerouting the differential signal path using one or more switches (e.g., CMOS switches). This configuration advantageously results in simultaneous variation of both the inductance and capacitance per unit length of the ATL to vary the delay of the delay cell 710 while maintaining a constant (or substantially constant) characteristic impedance and a constant (or substantially constant) insertion loss in all phase settings. Furthermore, unwanted short-term pulse interference generated by charge injection from the switches appears as common mode at the differential output and is therefore advantageously rejected (see Figure 12 In an exemplary aspect, both the coarse phase shifter arrangement and the fine phase shifter arrangement are coupled with an auxiliary transmission line (e.g., Figure 4 The auxiliary transmission line is used to retime the digital phase-shift code to achieve a settling time of less than 20 ps.

[0074] refer to Figure 8 and Figure 9 In an exemplary aspect, the delay unit 710 includes four signal lines (lines 1-4) 810, 815, 820, 825, switches S1-S8, and capacitors that couple the positive lines to corresponding negative lines (e.g., line 1 to line 3 and line 2 to line 4) in one operating state (e.g., high) and couple the positive lines to the positive lines and the negative lines to the negative lines in another operating state (e.g., low).

[0075] Go to Figure 8 In an exemplary aspect, the differential input of the delay unit 710 enters from the left and is connected to one or more of the switches S1-S8. In operation, the switches S1-S8 are configured to adjust the position of the positive line relative to the negative line to move the boundary 705 toward the left or right (in 7A to 7C ), thereby changing the delay of the phase modulator 700. In an exemplary aspect, when switches S1-S4 are on (i.e., closed) and switches S5-S8 are off (open), the differential signal is connected (or otherwise coupled) directly through the delay unit 710 in the same configuration. Alternatively, when switches S5-S8 are on (i.e., closed) and switches S1-S4 are off (open), the wire configuration changes to another delay state, which adjusts the boundary 705 between the delay states.

[0076] like Figure 9As shown, in the high-latency state, lines 1 and 2 (810, 815) have positive polarity and lines 3 and 4 (820, 825) have negative polarity. In this arrangement, the inductance increases due to the positive mutual coupling between the lines. Alternatively, in the low-latency state, lines 1 and 3 (810, 820) have positive polarity, while lines 2 and 4 have negative polarity. In this configuration, when the return current with negative polarity is closer to the corresponding positive polarity signal line, less magnetic flux and inductance are generated.

[0077] In exemplary aspects, continue to refer to Figure 9 , capacitors C are connected differentially across the lines in a high-latency operating state (the capacitors couple the positive lines to the corresponding negative lines), and are connected in common mode in a low-latency operating state (the capacitors couple the positive lines together and the negative lines together). For example, in the high-latency operating state, positive line 1 (810) is coupled to negative line 3 (820) via one or more capacitors, and positive line 2 (815) is coupled to negative line 4 (825) via one or more capacitors. In the low-latency operating state, positive line 1 (810) is coupled to positive line 3 (820) via one or more capacitors, and negative line 2 (815) is coupled to negative line 4 (825) via one or more capacitors. These configurations advantageously provide that the capacitance of the line may be automatically changed in a lossless manner without the need to use series switches present in single-ended transmission lines to maintain a constant characteristic impedance between these delay states. In addition, a constant characteristic impedance of the line across phase-shift codes is achieved.

[0078] In an exemplary embodiment, switches S1-S8 are configured to be digitally programmable between a high operating state and a low operating state. Advantageously, the parasitic capacitance of the switches is always present on the line, and the capacitors do not experience parasitic resonant behavior. Consequently, delay cell 710 achieves a higher phase change in a given area compared to a single-ended transmission line.

[0079] In an exemplary aspect, insertion loss is a function of the number of switches in series (e.g., the number of delay cells in the cascade). Thus, in an exemplary aspect, to minimize insertion loss, the phase modulator 700 can be used to achieve coarse phase shifting, while fine phase resolution can be achieved by cascading the phase modulator 700 with a phase shifter based on a single-ended transmission line. Additionally, the number of switches turned on is constant between the high-delay state and the low-delay state (e.g., 4 switches), resulting in constant insertion loss across the entire phase shift range. This is desirable for reducing distortion from phase modulation to amplitude modulation of the modulated signal.

[0080] like Figure 12As shown, the short-term pulse interference generated during the phase transition appears common to the differential lines and appears to be common mode, and therefore the short-term pulse interference is rejected. Another advantage is that the phase modulator 700 is insensitive to external noise from nearby signal lines and circuits, while being robust to PVT variations. In addition, the fast settling time is achieved by configuring an auxiliary transmission line with a delayed digital code to update the delay state in each delay cell, as shown in Figure 4 In the aspects shown.

[0081] exist Figures 10 to 13B Additional advantages and performance characteristics are shown in FIG. Figure 10 Figure 7 shows the analog input match (S11), insertion loss (S21), and phase shift across phase shift codes. In this example, a constant insertion loss of 9 dB is achieved, and a constant characteristic impedance is maintained across the entire phase shift range. Furthermore, compared to a single-ended phase shifter, the phase modulator 700 occupies one-third the area while providing a 180-degree phase shift range.

[0082] Figures 11A to 11B The transient behavior of the phase modulator 700 for a phase shift of 0 to 180 degrees is shown. As shown, the phase change occurs within less than 1 cycle of the waveform at a 72 GHz carrier frequency (i.e., <20 ps). In these graphs, the 180-degree reference carrier is shown by line 1105, the 0-degree reference carrier is shown by line 1110, and the modulated carrier is shown by line 1115.

[0083] Likewise, due to the differential nature of the phase modulator 700, the short pulse interference generated by the switch appears in common mode and can be ignored, as shown in FIG. Figure 12 shown.

[0084] exist 13A to 13B The performance of the phase modulator 700 is shown in FIG. Figure 13A shows the constellation diagram of a 16QAM signal reconstructed at a 2GS / s symbol rate (and 6x oversampling rate), while Figure 13B The spectral mask of WiGig (IEEE 802.11ad) is shown. In this example, the phase modulator performs better than -31 dB and 2.7% EVM while meeting the spectral mask of WiGig (IEEE 802.11ad) without any PVT calibration.

[0085] Figure 14 A flow chart 1400 is shown of a phase modulation method according to an exemplary aspect of the present disclosure. Figures 1 to 13B1400. The operations of these methods are not limited to the order described below, and various operations may be performed in a different order. In addition, two or more operations of these methods may be performed simultaneously with each other. In an exemplary aspect, mobile device 400 is configured to perform the method of flowchart 1400.

[0086] The method of flowchart 1400 begins at operation 1405 where a clock signal is delayed based on a first delay value to generate a first delayed clock signal. For example, delay unit 415.1 delays the clock signal to generate an enable signal for enabling flip-flop 420.1.

[0087] After operation 1405, flowchart 1400 proceeds to operation 1410, where the carrier signal is delayed based on the first delayed clock signal to generate a first delayed carrier signal. For example, delay unit 410.1 delays the carrier signal based on the digital bit value (b1) passed by flip-flop 420.1 in response to the enable signal.

[0088] After operation 1410, flowchart 1400 proceeds to operation 1415, where the first delayed clock signal is delayed based on a second delay value to generate a second delayed clock signal. For example, delay unit 415.2 delays the delayed clock signal delayed by delay unit 415.1 to generate an enable signal for enabling flip-flop 420.2.

[0089] After operation 1415, flowchart 1400 proceeds to operation 1420, where the first delayed carrier signal is delayed based on the second delayed clock signal to generate a second delayed carrier signal. For example, delay unit 410.2 delays the delayed carrier signal delayed by delay unit 410.1 based on the digital bit value (b2) passed by flip-flop 420.2 in response to the enable signal generated by delay unit 415.2. In this example, the generation of the enable signal by delay unit 415.2 delays the cumulative delay (e.g., the delay caused by delay unit 415.1 + the delay caused by delay unit 415.2).

[0090] Figure 15 Flowchart 1500 shows a phase modulation method according to an exemplary aspect of the present disclosure. Figures 1 to 13B 1500. The operations of these methods are not limited to the order described below, and various operations may be performed in a different order. In addition, two or more operations of these methods may be performed simultaneously with each other. In an exemplary aspect, mobile device 400 is configured to perform the method of flowchart 1500.

[0091] The method of flowchart 1500 begins at operation 1505, where a delay value is incrementally adjusted (e.g., increased) based on a corresponding delay cell in a sequence of delay cells. For example, delay cells 415.1 through 415.K delay a clock signal. Because delay cells 415.1 through 415.K are connected in series, the delay of the clock signal is incrementally increased by each subsequent delay cell 415. For example, the clock signal is delayed by an increasing delay, which increases by t0 at each delay cell 415.

[0092] After operation 1505, flowchart 1500 proceeds to operation 1510, where corresponding enable signals are sequentially generated based on the incrementally adjusted delay values. For example, the incrementally increased delayed clock signal generates corresponding enable signals for the corresponding flip-flops 420.1 through 420.K. In this example, enable signals for delay circuits 430.1, 430.2, ..., 430.K are generated at times t0, 2t0, ..., Kt0.

[0093] After operation 1510, the flowchart 1500 proceeds to operation 1515, where the carrier signal is sequentially delayed by a corresponding delay value at the delay unit based on the corresponding enable signal. For example, the corresponding enable signal controls the corresponding flip-flops 420.1 to 420.K to pass their corresponding bits b1, b2, ..., b K Then the bit adjustment delay units 410.1 to 410.K are used to delay the signal carrier. Because the flip-flops 420.1 to 420.K sequentially pass their corresponding bits b1, b2, ..., b3 based on the sequentially generated enable signals. K Therefore, the carrier signal is delayed by the corresponding delay units 410.1, 410.2, ..., 410.K at time t0, 2t0, ..., Kt0. That is, the carrier signal is not delayed simultaneously by the corresponding delay circuits 430, but is delayed sequentially.

[0094] Example

[0095] Embodiment 1 is a phase modulation method including: sequentially generating enable signals based on a clock signal to generate an enable signal sequence; and delaying a signal by a delay value generated from a delay unit based on the enable signal sequence and a digital bit value.

[0096] Embodiment 2 is the subject matter of embodiment 1, wherein the enable signal and the digital bit value of the enable signal sequence correspond to the delay unit, respectively.

[0097] Embodiment 3 is the subject matter of any one of embodiments 1 to 2, wherein the sequentially generating the enable signal comprises delaying the clock signal at the delay unit based on an incrementally adjusted delay value.

[0098] Embodiment 4 is the subject matter of embodiment 3, wherein the incrementally adjusted delay value increases incrementally at each of the delay cells.

[0099] Embodiment 5 is the subject matter of embodiment 4, wherein the delay cells are arranged sequentially to form a delay cell sequence.

[0100] Embodiment 6 is the subject matter of embodiment 5, wherein the sequence of enable signals respectively corresponds to the sequence of delay units.

[0101] Embodiment 7 is the subject matter of any one of embodiments 1 to 6, wherein the delay cells are sequentially arranged to form a sequence of delay cells that respectively generate the delay value, wherein the delay value increases incrementally at each delay cell in the sequence of delay cells.

[0102] Embodiment 8 is the subject matter of embodiment 7, wherein the sequence of delay elements forms an artificial transmission line.

[0103] Embodiment 9 is a phase modulator comprising: a first delay circuit configured to: delay a clock signal based on a first delay value to generate a first delayed clock signal; and delay a carrier signal based on the first delayed clock signal to generate a first delayed carrier signal; and a second delay circuit configured to: delay the first delayed clock signal based on a second delay value to generate a second delayed clock signal; and delay the first delayed carrier signal based on the second delayed clock signal to generate a second delayed carrier signal.

[0104] Embodiment 10 is the subject matter of embodiment 9, wherein the second delayed carrier signal is delayed by a sum of the first delay value and the second delay value.

[0105] Embodiment 11 is the subject matter of any one of embodiments 9-10, wherein the first delay value and the second delay value are equal.

[0106] Embodiment 12 is the subject matter of any one of embodiments 9 to 11, wherein the first delay circuit comprises: a first delay unit configured to delay the clock signal to generate the first delayed clock signal; a first memory configured to provide a first bit value based on the first delayed clock signal; and a second delay unit configured to delay the carrier signal based on the first bit value.

[0107] Embodiment 13 is the subject matter of embodiment 12, wherein the first memory is a flip-flop configured to transfer the first bit value based on the first delayed clock signal.

[0108] Embodiment 14 is the subject matter of any one of embodiments 9 to 13, wherein the second delay circuit comprises: a third delay unit configured to delay the first delayed clock signal to generate the second delayed clock signal; a second memory configured to provide a second bit value based on the second delayed clock signal; and a fourth delay unit configured to delay the first delayed carrier signal based on the second bit value.

[0109] Embodiment 15 is the subject matter of embodiment 14, wherein the second memory is a flip-flop configured to transfer the second bit value based on the second delayed clock signal.

[0110] Embodiment 16 is the subject matter of any one of embodiments 9 to 15, wherein the first delay circuit and the second delay circuit form an artificial transmission line.

[0111] Embodiment 17 is a wireless communication device comprising the phase modulator according to embodiments 9 to 16.

[0112] Embodiment 18 is a delay circuit comprising: a first delay unit configured to delay a clock signal to generate a delayed clock signal; a memory configured to provide a bit value based on the delayed clock signal; and a second delay unit configured to delay a signal based on the delayed signal.

[0113] Embodiment 19 is the subject matter of embodiment 18, wherein the memory is a flip-flop configured to transfer the bit value based on the delayed clock signal, wherein the delayed clock signal is configured as an enable signal for the flip-flop.

[0114] Embodiment 20 is a phase modulator comprising the delay circuit according to any one of Embodiments 18 to 19.

[0115] Embodiment 21 is a phase modulator comprising two or more delay circuits according to any one of Embodiments 18 to 19.

[0116] Embodiment 22 is a phase modulator according to embodiment 21, wherein the two or more delay circuits are configured to delay the signal cooperatively and sequentially.

[0117] Embodiment 23 is the subject matter of any one of embodiments 21 to 22, wherein the two or more delay circuits are configured as artificial transmission lines.

[0118] Embodiment 24 is the subject matter of any one of embodiments 18 to 20, wherein the delay circuit is configured as an artificial transmission line.

[0119] Embodiment 25 is a phase modulator comprising: a first delay device, the first delay device being used to: delay a clock signal based on a first delay value to generate a first delayed clock signal; and delay a carrier signal based on the first delayed clock signal to generate a first delayed carrier signal; and a second delay device, the second delay device being used to: delay the first delayed clock signal based on a second delay value to generate a second delayed clock signal; and delay the first delayed carrier signal based on the second delayed clock signal to generate a second delayed carrier signal.

[0120] Embodiment 26 is the subject matter of embodiment 25, wherein the second delayed carrier signal is delayed by a sum of the first delay value and the second delay value.

[0121] Embodiment 27 is the subject matter of any one of embodiments 25 to 26, wherein the first delay value and the second delay value are equal.

[0122] Embodiment 28 is the subject matter of any one of embodiments 25 to 27, wherein the first delay device includes: a first delay unit, which is configured to delay the clock signal to generate the first delayed clock signal; a first memory, which is configured to provide a first bit value based on the first delayed clock signal; and a second delay unit, which is configured to delay the carrier signal based on the first bit value.

[0123] Embodiment 29 is the subject matter of embodiment 28, wherein the first memory is a flip-flop configured to transfer the first bit value based on the first delayed clock signal.

[0124] Embodiment 30 is the subject matter of any one of embodiments 25 to 29, wherein the second delay device includes: a third delay unit, the third delay unit being configured to delay the first delayed clock signal to generate the second delayed clock signal; a second memory, the second memory being configured to provide a second bit value based on the second delayed clock signal; and a fourth delay unit, the fourth delay unit being configured to delay the first delayed carrier signal based on the second bit value.

[0125] Embodiment 31 is the subject matter of embodiment 30, wherein the second memory is a flip-flop configured to transfer the second bit value based on the second delayed clock signal.

[0126] Embodiment 32 is the subject matter of any one of embodiments 25 to 31, wherein the first delay device and the second delay device form an artificial transmission line.

[0127] Embodiment 33 is a wireless communication device comprising the phase modulator according to embodiments 25 to 32.

[0128] Embodiment 34 is a delay circuit comprising: a first delay device for delaying a clock signal to generate a delayed clock signal; a storage device for providing a bit value based on the delayed clock signal; and a second delay device for delaying a signal based on the delayed signal.

[0129] Embodiment 35 is the subject matter of embodiment 34, wherein the memory device is a flip-flop configured to transfer the bit value based on the delayed clock signal, wherein the delayed clock signal is configured as an enable signal for the flip-flop.

[0130] Embodiment 36 is a phase modulator comprising the delay circuit according to any one of Embodiments 34 to 35.

[0131] Embodiment 37 is a phase modulator comprising two or more delay circuits according to any one of Embodiments 34 to 35.

[0132] Embodiment 38 is a phase modulator according to embodiment 37, wherein the two or more delay circuits are configured to delay the signal cooperatively and sequentially.

[0133] Embodiment 39 is the subject matter of any one of embodiments 37 to 38, wherein the two or more delay circuits are configured as artificial transmission lines.

[0134] Embodiment 40 is the subject matter of any one of embodiments 34 to 36, wherein the delay circuit is configured as an artificial transmission line.

[0135] Embodiment 41 is a computer-readable medium comprising program instructions, which, when executed, cause a processor to perform the method according to any one of embodiments 1 to 8.

[0136] Example 42 is a device substantially as shown and described.

[0137] Example 43 is a method substantially as shown and described.

[0138] in conclusion

[0139] The foregoing description of specific aspects will fully demonstrate the general nature of the present disclosure, so that others can easily modify and / or adjust various applications of such specific aspects by applying knowledge within the technical scope of the art without undue experimentation and without departing from the general concept of the present disclosure. Therefore, based on the teachings and guidance presented herein, such adjustments and modifications are intended to be within the meaning and scope of equivalents of the aspects disclosed herein. It should be understood that the wording or terminology herein is for illustrative purposes only and not for limiting purposes, so the terms or wording of this specification will be interpreted by the skilled person in accordance with the teachings and guidance.

[0140] References in the specification to "one aspect," "aspect," "exemplary aspects," and the like indicate that the described aspect may include a particular feature, structure, or characteristic, but not necessarily every aspect includes that particular feature, structure, or characteristic. Furthermore, such expressions do not necessarily refer to the same aspect. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with one aspect, it is considered within the knowledge of those skilled in the art to implement such feature, structure, or characteristic in conjunction with other aspects, whether explicitly described or not.

[0141] The exemplary aspects described herein are provided for illustrative purposes and are not limiting. Other exemplary aspects are possible, and the exemplary aspects may be modified. Therefore, this description is not intended to limit the present disclosure. Instead, the scope of the present disclosure is defined only in accordance with the following claims and their equivalents.

[0142] Aspects may be implemented in hardware (e.g., circuits), firmware, software, or any combination thereof. Aspects may also be implemented as instructions stored on a machine-readable medium that can be read and executed by one or more processors. A machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computing device). For example, a machine-readable medium may include read-only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustic, or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.), and others. In addition, firmware, software, routines, instructions may be described herein as performing certain actions. However, it should be understood that such descriptions are for convenience only, and that such actions are actually caused by a computing device, processor, controller, or other device that executes the firmware, software, routines, instructions, etc. In addition, any of the specific implementation variations may be executed by a general-purpose computer.

[0143] For the purposes of this discussion, the term "processor circuit" should be understood as a circuit, a processor, a logic unit, or a combination thereof. For example, a circuit includes an analog circuit, a digital circuit, a state machine logic unit, other structural electronic hardware, or a combination thereof. A processor includes a microprocessor, a digital signal processor (DSP), a central processing unit (CPU), an application specific instruction set processor (ASIP), a graphics and / or image processor, a multi-core processor, or other hardware processor. According to the aspects described herein, instructions can be "hard-coded" to the processor to perform corresponding functions. Alternatively, the processor can access internal memory and / or external memory to retrieve instructions stored in the memory, which, when executed by the processor, perform corresponding functions associated with the processor and / or one or more functions and / or operations related to the operation of the component in which the processor is included.

[0144] In one or more exemplary aspects described herein, the processor circuitry may include a memory for storing data and / or instructions. The memory may be any known volatile and / or non-volatile memory, including, for example, read-only memory (ROM), random access memory (RAM), flash memory, magnetic storage media, optical disks, erasable programmable read-only memory (EPROM), and programmable read-only memory (PROM). The memory may be non-removable, removable, or a combination of both.

[0145] Based on the teachings herein, it will be apparent to one of ordinary skill in the art that the exemplary aspects are not limited to communication protocols utilizing millimeter wave (mmWave) spectrum (e.g., 24 GHz-300 GHz), such as WiGig (IEEE 802.11ad and / or IEEE 802.11ay) operating at 60 GHz and / or one or more 5G protocols using, for example, 28 GHz spectrum. The exemplary aspects can be applied to other wireless communication protocols / standards (e.g., LTE or other cellular protocols, other IEEE 802.11 protocols, etc.), as will be understood by one of ordinary skill in the relevant art.

Claims

1. A phase modulation method, comprising: sequentially generating enable signals based on the clock signal to generate an enable signal sequence; as well as delaying the signal by a delay value generated from the delay unit based on the enable signal sequence and the digital bit value, The delay value t d Satisfies the following equation: t d =t0+b x Δt Where t0 is the input of the delay unit, b x is the digital bit value, and Δt is the delay constant.

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