Laminated capacitor plate preparation process

Abstract

The invention discloses a laminated capacitor plate preparation process which comprises the following steps: S1, deposition: a capacitor plate is deposited on a substrate, and the capacitor plate is a laminated layer formed by TaN / A < l > / TaN; s2, photoetching: coating the surface of the capacitor plate with photoresist, manufacturing a patterned photoresist layer through exposure and development processes, and providing an accurate patterned mask for subsequent etching; s3, etching: placing the capacitor plate in a metal etching cavity of etching equipment; s4, photoresist removal: transferring the capacitor plate into a photoresist removal cavity of etching equipment, and removing the photoresist on the surface of the capacitor plate; and S5, cleaning: moving the capacitor plate into a cleaning cavity, and cleaning the surface of the capacitor plate. According to the method, the problem of TaN residue is effectively solved by regulating and controlling the gas components, the process condition parameters and the post-treatment process in stages, the etching uniformity of the TaN / Al / TaN lamination is improved, the dimensional precision and the surface flatness of the capacitor polar plate are improved, and the electrical property stability of the capacitor polar plate is guaranteed.

Description

Technical Field

[0001] The invention belongs to the technical field of stacked capacitor plate preparation, and in particular relates to a stacked capacitor plate preparation process. Background Art

[0002] As semiconductor technology continues to advance toward higher performance and greater integration, MIM capacitors (Metal-Insulator-Metal)—key energy storage components in integrated circuits—are increasingly becoming increasingly important in fields like radio frequency circuits and power management chips. MIM capacitors are typically manufactured using a stacked metal layer, dielectric layer, and metal layer structure, where the choice of metal layer material plays a crucial role in capacitor performance and reliability.

[0003] At present, aluminum metal is often used in industry as the conductive layer of MIM capacitors, and Ti or TiN is used as the barrier layer. Aluminum has become the preferred material for the conductive layer due to its good conductivity and low cost, while Ti or TiN can prevent the diffusion of aluminum atoms to a certain extent, ensuring the stability of the capacitor structure. However, as device size continues to shrink, the requirements for capacitor performance are becoming increasingly stringent, and the limitations of Ti and TiN in terms of barrier performance, corrosion resistance, and contact resistance are gradually emerging. In contrast, TaN shows significant advantages as a barrier layer. It has higher thermal stability, better barrier performance, and can more effectively inhibit the diffusion of aluminum atoms. At the same time, the contact resistance formed by TaN and semiconductor materials is lower, and it has stronger corrosion resistance, which can greatly improve the reliability and electrical performance of MIM capacitors.

[0004] However, in practical applications, the difficult etching characteristics of TaN have become a technical bottleneck. The presence of aluminum in the MIM capacitor plate requires the use of Cl-based gases for etching, and although traditional fluorine-based gases (such as CF4, CHF3, SF6) can be used to etch TaN, they are not suitable for etching aluminum-containing structures. This situation brings two major technical difficulties: First, the Cl-based gas will produce low-volatility residual by-products during the etching of TaN. These residual substances are difficult to remove and will have an adverse effect on the insulation performance and electrical parameters of the capacitor; second, the uniformity of the stacking etching of TaN and Al is difficult to ensure, which in turn affects the capacitance accuracy of the capacitor. Summary of the Invention

[0005] The present invention overcomes the deficiencies of the prior art and provides a process for preparing a stacked capacitor plate to solve the problems existing in the prior art.

[0006] To achieve the above object, the technical solution adopted by the present invention is: a process for preparing a stacked capacitor plate, comprising the following steps:

[0007] S1. Deposition: depositing a capacitor plate on a substrate, wherein the capacitor plate is a stack of TaN / Al / TaN;

[0008] S2, photolithography: Coating photoresist on the surface of the capacitor plate, and making a patterned photoresist layer through exposure and development processes to provide a precise patterned mask for subsequent etching;

[0009] S3, etching: placing the capacitor plate in a metal etching chamber of an etching device, specifically comprising the following steps:

[0010] S31, surface pretreatment: Under the conditions of pressure 40-60mTorr, power 800W, and electrostatic chuck temperature 40-50°C, 60-70sccm of BCl2 gas, 15-25sccm of Cl2 gas, and 10sccm of Ar gas are simultaneously introduced into the metal etching chamber for 5-7s;

[0011] S32, upper TaN layer etching: under the conditions of pressure 30-40 mTorr, power 800 W, and electrostatic chuck temperature 40-50°C, 60-70 sccm of BCl3 gas, 60-70 sccm of Cl2 gas, and 15-25 sccm of N2 gas are simultaneously introduced into the metal etching chamber for 8-12 seconds;

[0012] S33, Al layer etching: Under the conditions of pressure 200-250mTorr, power 800W, and electrostatic chuck temperature 40-50°C, 20-30sccm of BCl3 gas, 90-100sccm of Cl2 gas, and 30-40sccm of N2 gas are simultaneously introduced into the metal etching chamber for 20-25s;

[0013] S34, lower TaN layer etching: under the conditions of pressure 30-40 mTorr, power 800 W, and electrostatic chuck temperature 40-50°C, 60-70 sccm of BCl3 gas, 60-70 sccm of Cl2 gas, and 15-25 sccm of N2 gas are simultaneously introduced into the metal etching chamber for 15-20 seconds;

[0014] S4, photoresist removal: the capacitor plate is transferred to the photoresist removal chamber of the etching equipment to remove the photoresist on the surface of the capacitor plate;

[0015] S5. Cleaning: Move the capacitor plate into the cleaning chamber and clean the surface of the capacitor plate.

[0016] In a preferred embodiment of the present invention, the capacitor plate includes an upper TaN layer, an Al layer, and a lower TaN layer sequentially arranged from top to bottom.

[0017] In a preferred embodiment of the present invention, the thickness of the upper TaN layer is 80 nm, the thickness of the Al layer is 150 nm, and the thickness of the lower TaN layer is 50 nm.

[0018] In a preferred embodiment of the present invention, in step S2, a positive photoresist is spin-coated on the surface of the upper TaN layer at a rotation speed of 2500-3000 rpm, a thickness of the photoresist layer of 1.5 μm, a pre-baking condition of 110°C / 100s, a UV lithography machine with a wavelength of 365nm, and an exposure energy of 50mJ / cm 2 The top electrode of the capacitor plate is exposed, developed with 2.5% potassium hydroxide solution for 60-80 seconds, and baked at 120°C for 70 seconds to form a patterned photoresist mask.

[0019] In a preferred embodiment of the present invention, in step S4, oxygen plasma dry method is used to remove the photoresist on the surface of the capacitor plate to prevent residual Cl ions from reacting with water molecules in the atmosphere to corrode the Al layer.

[0020] In a preferred embodiment of the present invention, in step S5, the etched capacitor plate is cleaned with an EKC solution to remove residual polymers and byproducts on the surface thereof.

[0021] The present invention solves the defects existing in the background technology and has the following beneficial effects:

[0022] The stacked capacitor plate preparation process of the present invention effectively solves the problem of TaN residue by regulating gas composition, process condition parameters and post-processing process in stages, improves the etching uniformity of TaN / Al / TaN stack, enhances the dimensional accuracy and surface flatness of the capacitor plate, and ensures the electrical performance stability of the capacitor plate. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The present invention will be further described below with reference to the accompanying drawings and examples;

[0024] Figure 1 is an overall flow chart of a preferred embodiment of the present invention;

[0025] Figure 2 This is an etching result diagram of a preferred embodiment of the present invention; DETAILED DESCRIPTION

[0026] The present invention will be further described below with reference to the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and implement it. However, the embodiments are not intended to limit the present invention.

[0027] Combine Figure 1 and Figure 2 As shown, this embodiment provides the following preparation process:

[0028] 1. Substrate Preparation

[0029] An 8-inch wafer substrate is selected and the contaminants on the wafer substrate are removed through a standard RCA cleaning process, and then the subsequent process is carried out after drying.

[0030] 2. Deposition

[0031] Capacitor plates are deposited on the surface of the wafer substrate. The specific operation is to deposit a lower TaN layer, an Al layer and an upper TaN layer in sequence. The thickness of the upper TaN layer is 80nm, the thickness of the Al layer is 150nm, and the thickness of the lower TaN layer is 50nm.

[0032] 3. Photolithography

[0033] Glue coating: Spin-coat the upper TaN layer with positive photoresist (model: AZ5214) at a speed of 3000 rpm, a thickness of 1.5 μm, and pre-bake at 100°C for 120 seconds.

[0034] Exposure: UV lithography with a wavelength of 365nm and an exposure energy of 50mJ / cm 2 ;

[0035] Development: Use 2.5% potassium hydroxide (KOH) solution for 70 seconds, and then bake at 110° C. for 60 seconds to form a patterned photoresist mask.

[0036] 4. Reactive Ion Etching

[0037] Using etching equipment, the metal etching chamber and the debonding chamber are connected through a vacuum transmission system, and the capacitor plates are kept in a vacuum environment throughout the process to avoid atmospheric pollution.

[0038] Step 1: Surface Pretreatment

[0039] Gas: 70 sccm (standard cubic centimeters per minute) of BCl2 gas, 20 sccm of Cl2 gas, and 10 sccm of Ar gas;

[0040] Process parameters: chamber pressure 60mTorr, RF power 800W, electrostatic chuck temperature 40°C, etching time 6s;

[0041] Ar ion physical bombardment combined with BCl3 / Cl2 chemical reaction is used to remove the TaN surface oxide layer (about 5nm), laying the foundation for subsequent etching.

[0042] Step 2: Etching the upper TaN layer

[0043] Gas: 70 sccm of BCl3 gas, 65 sccm of Cl2 gas, and 20 sccm of N2 gas;

[0044] Process parameters: pressure 35mTorr, power 800W, electrostatic chuck temperature 40°C, etching time 8s;

[0045] Increasing the proportion of Cl2 gas accelerates TaN etching, BCl3 gas and N2 gas work together to protect the side walls of the capacitor plates, and low gas pressure promotes the volatilization of by-products such as TaCl5, achieving efficient etching of the upper TaN layer.

[0046] Step 3: Al layer etching

[0047] Gas: 20 sccm of BCl3 gas, 95 sccm of Cl2 gas, and 35 sccm of N2 gas;

[0048] Process parameters: pressure 200mTorr, power 800W, electrostatic chuck temperature 40°C, etching time 22s;

[0049] The etching uniformity is ensured in a high-pressure environment, the high Cl2 gas flow maintains the etching rate, and the remaining thickness of TaN is precisely controlled to complete the etching of the Al layer.

[0050] Step 4: Etching the lower TaN layer

[0051] Gas: 70 sccm of BCl3 gas, 70 sccm of Cl2 gas, and 20 sccm of N2 gas;

[0052] Process parameters: pressure 35mTorr, power 800W, electrostatic chuck temperature 40°C, etching time 15s;

[0053] The gas formula and pressure used for etching the upper TaN layer are used, and the etching time is extended to ensure that the lower TaN layer and metal layer are completely removed to avoid residue.

[0054] 5. Glue removal

[0055] After etching, oxygen plasma dry method is used to remove the photoresist on the surface of the capacitor plate to prevent residual Cl ions from reacting with water molecules in the atmosphere to corrode the Al layer. The capacitor plate is transferred to the degumming chamber through vacuum, and H2O / O2 / N2 are introduced at 300 / 2500 / 200sccm respectively, with a power of 1400W and a pressure of 2mTorr. The plasma degumming time is 5min.

[0056] 6. Cleaning

[0057] The etched capacitor plates were cleaned using EKC solution (cleaning solution after etching and ashing) at 70° C. for 10 min to remove residual polymers and byproducts on their surfaces.

[0058] Effect verification

[0059] like Figure 2As shown, the etching uniformity of the capacitor plate is verified: a step profiler is used to measure the etching depth at nine positions of the wafer: top, middle, bottom, left, right, upper left, lower left, upper right, and lower right. The uniformity is within ±3%.

[0060] Etching morphology: FIB slices of the edge of the pattern area after etching are as follows Figure 2 As shown, the etching angle is maintained at 78°.

[0061] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of the present invention.

Claims

1. A process for preparing a stacked capacitor plate, characterized in that: The following steps are involved: S1. Deposition: depositing a capacitor plate on a substrate, wherein the capacitor plate is a stack of TaN / Al / TaN; S2, photolithography: Coating photoresist on the surface of the capacitor plate, and making a patterned photoresist layer through exposure and development processes to provide a precise patterned mask for subsequent etching; S3, etching: placing the capacitor plate in a metal etching chamber of an etching device, specifically comprising the following steps: S31, surface pretreatment: Under the conditions of pressure 40-60mTorr, power 800W, and electrostatic chuck temperature 40-50°C, 60-70sccm of BCl2 gas, 15-25sccm of Cl2 gas, and 10sccm of Ar gas are simultaneously introduced into the metal etching chamber for 5-7s; S32, upper TaN layer etching: under the conditions of pressure 30-40 mTorr, power 800 W, and electrostatic chuck temperature 40-50°C, 60-70 sccm of BCl3 gas, 60-70 sccm of Cl2 gas, and 15-25 sccm of N2 gas are simultaneously introduced into the metal etching chamber for 8-12 seconds; S33, Al layer etching: Under the conditions of pressure 200-250mTorr, power 800W, and electrostatic chuck temperature 40-50°C, 20-30sccm of BCl3 gas, 90-100sccm of Cl2 gas, and 30-40sccm of N2 gas are simultaneously introduced into the metal etching chamber for 20-25s; S34, lower TaN layer etching: under the conditions of pressure 30-40 mTorr, power 800 W, and electrostatic chuck temperature 40-50°C, 60-70 sccm of BCl3 gas, 60-70 sccm of Cl2 gas, and 15-25 sccm of N2 gas are simultaneously introduced into the metal etching chamber for 15-20 seconds; S4, photoresist removal: the capacitor plate is transferred to the photoresist removal chamber of the etching equipment to remove the photoresist on the surface of the capacitor plate; S5. Cleaning: Move the capacitor plate into the cleaning chamber and clean the surface of the capacitor plate.

2. A process for preparing a stacked capacitor plate according to claim 1, characterized in that: The capacitor plate includes an upper TaN layer, an Al layer and a lower TaN layer arranged in sequence from top to bottom.

3. A process for preparing a stacked capacitor plate according to claim 2, characterized in that: The thickness of the upper TaN layer is 80 nm, the thickness of the Al layer is 150 nm, and the thickness of the lower TaN layer is 50 nm.

4. The process for preparing a stacked capacitor plate according to claim 1, wherein: In step S2, positive photoresist is spin-coated on the surface of the upper TaN layer at a rotation speed of 2500-3000 rpm, a thickness of 1.5 μm, a pre-baking condition of 110°C / 100s, a UV lithography machine with a wavelength of 365 nm, and an exposure energy of 50 mJ / cm 2 The top electrode of the capacitor plate is exposed, developed with 2.5% potassium hydroxide solution for 60-80 seconds, and baked at 120°C for 70 seconds to form a patterned photoresist mask.

5. The process for preparing a stacked capacitor plate according to claim 1, wherein: In step S4, the photoresist on the surface of the capacitor plate is removed by an oxygen plasma dry method to prevent residual Cl ions from reacting with water molecules in the atmosphere to corrode the Al layer.

6. The process for preparing a stacked capacitor plate according to claim 1, wherein: In step S5, the etched capacitor plates are cleaned with an EKC solution to remove residual polymers and byproducts on the surface thereof.

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