Asymmetric semiconductor discharge tube chip and manufacturing method thereof

Abstract

The present invention discloses an asymmetric semiconductor discharge tube chip, comprising a substrate, a first doped region, a second doped region, a third doped region, a fourth doped region, multiple fifth doped regions, multiple sixth doped regions, a first electrode, and a second electrode. The present invention also discloses a method for manufacturing the asymmetric semiconductor discharge tube chip. The asymmetric semiconductor discharge tube chip of the present invention forms multiple fifth doped regions within the first doped region, with depths decreasing from the sides to the center, and multiple sixth doped regions within the second doped region, with widths increasing from the sides to the center. This chip forms an NPN-PNP dual triode, capable of both low-voltage rapid conduction from the positive electrode to the negative electrode and high-voltage rapid discharge from the negative electrode to the positive electrode, thereby achieving bidirectional protection with different protection thresholds for positive and negative overvoltages. The present invention also features a simple structure, an environmentally friendly manufacturing process, and stable and reliable protection performance.

Description

Technical Field

[0001] The present invention relates to a semiconductor discharge tube chip, and in particular to an asymmetric semiconductor discharge tube chip and a manufacturing method thereof. Background Art

[0002] A semiconductor discharge tube (TSS) is a fast-switching, high-voltage, high-current semiconductor device with advantages such as fast response, low noise, and low power consumption. It is widely used in power electronics, communications, optoelectronics, and other fields. In the power electronics field, a TSS is often used as an overvoltage protection device, protecting circuits through short-circuit discharge.

[0003] The existing semiconductor discharge tube chip structure is as follows Figure 1 As shown, this chip has a vertically symmetrical structure. Like a bidirectional discharge tube, it can protect circuits from transient overvoltages in both directions (positive and negative polarity). However, in practical applications, the positive and negative overvoltage requirements of a circuit are often set to different values, and existing semiconductor discharge tube chips cannot meet this requirement. Therefore, finding a semiconductor discharge tube chip that can simultaneously meet the different positive and negative overvoltage requirements of a circuit has become an urgent problem. Summary of the Invention

[0004] The present invention provides an asymmetric semiconductor discharge tube chip, which is used to solve the problem that the existing semiconductor discharge tube cannot simultaneously meet the different positive and negative overvoltage requirements of the circuit.

[0005] The present invention also provides a method for manufacturing an asymmetric semiconductor discharge tube chip.

[0006] To achieve the purpose of the present invention, the present invention provides an asymmetric semiconductor discharge tube chip, the chip comprising:

[0007] a substrate comprising opposing upper and lower surfaces;

[0008] a first doped region, which is a groove structure extending downward from the upper surface of the substrate, wherein a first PN junction is connected between the first doped region and the substrate;

[0009] a second doped region, which is a groove structure extending upward from the lower surface of the substrate, and a second PN junction is connected between the second doped region and the substrate;

[0010] a third doped region, disposed at an end position of the first PN junction, and being an annular groove-shaped structure with an outer side extending downward from the upper surface of the substrate and an inner side extending downward from the upper surface of the first doped region; a third PN junction is connected between the third doped region and the first doped region, and a reverse avalanche voltage of the third PN junction is lower than a reverse avalanche voltage of the first PN junction;

[0011] a fourth doped region, disposed at an end portion of the second PN junction, and being an annular groove-shaped structure having an outer side extending upward from the lower surface of the substrate and an inner side extending upward from the lower surface of the second doped region; a fourth PN junction being connected between the fourth doped region and the second doped region, and a reverse avalanche voltage of the fourth PN junction being lower than a reverse avalanche voltage of the second PN junction;

[0012] a plurality of fifth doping regions, spaced apart and disposed inside the third doping region, wherein the depth of the fifth doping regions decreases from both sides to the middle, and a fifth PN junction is connected between each of the fifth doping regions and the first doping region;

[0013] a plurality of sixth doping regions, spaced apart and arranged inside the fourth doping region, wherein the width of each sixth doping region increases sequentially from both sides to the middle, and each sixth doping region is connected to the second doping region via a sixth PN junction;

[0014] a first electrode connected to the first doping region and the fifth doping region respectively;

[0015] The second electrode is connected to the second doping region and the sixth doping region respectively.

[0016] Furthermore, the substrate is N-type doped, the first doping region and the second doping region are P-type doped, the third doping region, the fourth doping region, the fifth doping region and the sixth doping region are N-type doped, and the doping concentration of the third doping region and the fourth doping region is higher than the doping concentration of the substrate.

[0017] In some embodiments, the chip also includes a first passivation layer, which is a plate-like structure, the lower surface of which covers part of the upper surface of the substrate, the upper surface of the third doped region, the end of the third PN junction and part of the upper surface of the first doped region, and the upper surface of which is a stepped structure with the thickness increasing from the middle to the edge.

[0018] In some embodiments, the chip also includes a second passivation layer, which is a plate-like structure, the upper surface of which covers part of the lower surface of the substrate, the lower surface of the fourth doped region, the end of the fourth PN junction and part of the lower surface of the second doped region, and the lower surface of which is a stepped structure with the thickness increasing from the middle to the edge.

[0019] In some embodiments, the chip further includes a first metal passivation layer, which covers a portion of the upper surface of the first passivation layer, a side of the first electrode, and a portion of the upper surface of the first electrode.

[0020] In some embodiments, the chip further includes a second metal passivation layer, which covers a portion of the lower surface of the second passivation layer, a side portion of the second electrode, and a portion of the lower surface of the second electrode.

[0021] Furthermore, the first electrode is a metal electrode made of aluminum-silicon-copper or titanium-nickel-silver; the second electrode is a metal electrode made of aluminum-silicon-copper or titanium-nickel-silver.

[0022] Furthermore, the first passivation layer includes SiO2, semi-insulating oxygen-doped polysilicon, phosphosilicate glass, borophosphosilicate glass and low-pressure deposited silicon nitride passivation film; the second passivation layer includes SiO2, semi-insulating oxygen-doped polysilicon, phosphosilicate glass, borophosphosilicate glass and low-pressure deposited silicon nitride passivation film.

[0023] Furthermore, the first metal passivation layer is a SiN, NSG, phosphosilicate glass or polyamide metal passivation layer; the second metal passivation layer is a SiN, NSG, phosphosilicate glass or polyamide metal passivation layer.

[0024] The present invention also provides an asymmetric semiconductor discharge tube chip, the method comprising:

[0025] providing a substrate;

[0026] Doping is performed on the upper surface of the substrate to form a first doping region, wherein a first PN junction is formed at a connection position between the first doping region and the substrate;

[0027] Doping is performed on the lower surface of the substrate to form a second doping region, wherein a second PN junction is formed at a connection position between the second doping region and the substrate;

[0028] Doping is performed at an end portion of the first PN junction to form a third doping region, wherein a connection position between the third doping region and the first doping region forms a third PN junction;

[0029] Doping is performed at an end portion of the second PN junction to form a fourth doping region, wherein a connection position between the fourth doping region and the second doping region forms a fourth PN junction;

[0030] Doping is performed in the first doping region to form a plurality of fifth doping regions, wherein the plurality of fifth doping regions are spaced apart inside the third doping region, and the depth of each fifth doping region decreases from both sides to the middle, and each fifth doping region forms a fifth PN junction at a connection position with the first doping region;

[0031] Doping is performed in the second doping region to form a plurality of sixth doping regions, wherein the plurality of sixth doping regions are spaced apart inside the fourth doping region, and the width of each sixth doping region increases sequentially from both sides to the middle, and each sixth doping region forms a sixth PN junction at a connection position with the second doping region;

[0032] forming a first passivation layer at an end of the third PN junction;

[0033] forming a second passivation layer at an end of the fourth PN junction;

[0034] Disposing a first electrode on the upper surface of the first doped region;

[0035] Disposing a second electrode on the lower surface of the second doped region;

[0036] forming a first metal passivation layer on the first electrode;

[0037] A second metal passivation layer is formed on the second electrode.

[0038] The beneficial effects of the present invention are:

[0039] 1) By forming a first doping region and a second doping region on the upper and lower surfaces of the substrate, respectively, forming multiple fifth doping regions with depths decreasing from both sides to the middle in the first doping region, and forming multiple sixth doping regions with widths increasing from both sides to the middle in the second doping region, the chip forms an NPN-PNP dual triode, thereby achieving bidirectional overvoltage protection.

[0040] 2) Because the depths of the multiple fifth doping regions decrease from the sides to the middle, while the widths of the multiple sixth doping regions increase from the sides to the middle, when the positive electrode is overvoltage, the outermost fifth doping regions are turned on first, and then the middle fifth doping regions are turned on in sequence, thereby achieving a faster turn-on speed, reducing the reaction time of the device in actual application, and making the protection more sensitive; when the negative electrode is overvoltage, the width of the outermost sixth doping regions is the smallest, while the width of the middle sixth doping region is the largest, which is conducive to achieving uniform current flow, thereby enabling large current discharge to quickly reduce voltage and withstand higher breakdown voltage. Therefore, the present invention can achieve a bidirectional protection function with different protection thresholds for positive and negative overvoltages.

[0041] 3) By providing a first passivation layer and a second passivation layer, composite, highly reliable passivation protection can be provided for the third PN junction J3 and the fourth PN junction J4, respectively. Furthermore, by configuring the first and second passivation layers as a stepped structure, the charge of the first and second electrodes is extended to the first and second metal passivation layers at the device edge, extending the space charge region to the edge. This allows the blocking voltage to reach the internal breakdown voltage, reducing the probability of soft breakdown and improving product reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 It is a structural diagram of an existing semiconductor discharge tube chip.

[0043] Figure 2 It is a structural schematic diagram of the present invention.

[0044] Figure 3It is a current-voltage curve diagram of the overvoltage performance test of the present invention.

[0045] Figure 4 It is a flow chart of the method of the present invention.

[0046] In the figure, 101 is a substrate, 102 is a first doped region, 103 is a second doped region, 104 is a third doped region, 105 is a fourth doped region, 106 is a fifth doped region, 107 is a sixth doped region, 108 is a first electrode, 109 is a second electrode, 110 is a first passivation layer, 111 is a second passivation layer, 112 is a first metal passivation layer, 113 is a second metal passivation layer, J1 is a first PN junction, J2 is a second PN junction, J3 is a third PN junction, J4 is a fourth PN junction, J5 is a fifth PN junction, and J6 is a sixth PN junction. DETAILED DESCRIPTION

[0047] The technical solutions of the present invention will be described clearly and completely below with reference to the accompanying drawings and specific embodiments. It is obvious that the embodiments described are only some embodiments of the present invention, not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative work shall fall within the scope of protection of the present invention.

[0048] Example 1

[0049] See also Figure 2 The present invention provides an asymmetric semiconductor discharge tube chip, comprising a substrate 101, a first doped region 102, a second doped region 103, a third doped region 104, a fourth doped region 105, multiple fifth doped regions 106, multiple sixth doped regions 107, a first electrode 108, and a second electrode 109. The asymmetric semiconductor discharge tube chip of this embodiment not only provides low-voltage rapid conduction from the positive electrode to the negative electrode, but also provides high-voltage rapid discharge from the negative electrode to the positive electrode, thereby achieving bidirectional protection with different protection thresholds for positive and negative overvoltages.

[0050] like Figure 2As shown, the substrate 101 is a plate-shaped body, which includes an upper surface and a lower surface relative to each other. <111> A single crystal silicon substrate has a high resistivity. A first doped region 102 is provided on the upper surface of substrate 101. This first doped region 102 is a P-type doped recessed structure extending downward from the upper surface of substrate 101. In this embodiment, an oxide layer is grown on the upper surface of substrate 101 by hydrogen-oxygen synthesis, followed by photolithography to form a P-type well region. Boron pre-diffusion and main-diffusion are performed in the P-type well region to form the first doped region 102. A first PN junction J1 is connected between the first doped region 102 and substrate 101. A second doped region 103 is provided on the lower surface of substrate 101. This second doped region 103 is a P-type doped recessed structure extending upward from the lower surface of substrate 101. In this embodiment, an oxide layer is grown on the lower surface of substrate 101 by hydrogen-oxygen synthesis, followed by photolithography to form a P-type well region. Boron pre-diffusion and main-diffusion are performed in the P-type well region to form the second doped region 103. A second PN junction J2 is connected between the second doped region 103 and substrate 101. The substrate 101 of this embodiment is an N-type substrate with a relatively high resistivity. <111> A single crystal silicon substrate is formed, and then phosphorus diffusion is used to form a first doped region 102 and a second doped region 103, thereby achieving ultra-low capacitance and a lower breakdown voltage. The temperature and time of phosphorus diffusion can be controlled to effectively control the breakdown value and ensure the low junction capacitance of the device, thereby reducing the electromagnetic interference of the device parasitic capacitance on the overall circuit, and can be suitable for circuit protection of communications and high-frequency devices.

[0051] like Figure 2 As shown, a third doped region 104 is provided at the junction between the substrate 101 and the first doped region 102. This third doped region 104 is an annular groove structure extending downward from the upper surface of the substrate 101 on the outside and downward from the upper surface of the first doped region 102 on the inside. Its groove depth is less than that of the first doped region 102. One side of the third doped region 104 is connected to the substrate 101, and the other side is connected to the first doped region 102. Its bottom is connected to a portion of the substrate 101, a portion of the first PN junction J1, and a portion of the first doped region 102. The third doped region 104 is N-type doped, and its doping concentration is greater than that of the substrate 101. A third PN junction J3 is connected between the third doped region 104 and the first doped region 102. Because the doping concentration of the third doped region 104 is greater than that of the substrate 101, the reverse avalanche voltage of the third PN junction J3 is less than that of the first PN junction J1. The volume of the third PN junction J3 is smaller than that of the first PN junction J1 , so its doping concentration can be better controlled, and thus the magnitude of the reverse avalanche voltage of the third PN junction J3 can be better controlled.

[0052] A fourth doped region 105 is provided at the junction of the lower surface of the substrate 101 and the second doped region 103. This fourth doped region 105 is an annular groove structure extending upward from the lower surface of the substrate 101 on the outside and upward from the lower surface of the second doped region 103 on the inside. Its groove depth is less than that of the second doped region 103. One side of the fourth doped region 105 is connected to the substrate 101, and the other side is connected to the second doped region 103. Its top is connected to a portion of the substrate 101, a portion of the second PN junction J2, and a portion of the second doped region 103. The fourth doped region 105 is N-type doped, and its doping concentration is greater than that of the substrate 101. A fourth PN junction J4 is connected between the fourth doped region 105 and the second doped region 103. Because the doping concentration of the fourth doped region 105 is greater than that of the substrate 101, the reverse avalanche voltage of the fourth PN junction J4 is less than that of the second PN junction J2. The volume of the fourth PN junction J4 is smaller than that of the second PN junction J2 , so its doping concentration can be better controlled, and thus the magnitude of the reverse avalanche voltage of the fourth PN junction J4 can be better controlled.

[0053] like Figure 2 As shown, a plurality of fifth doping regions 106 are provided in the first doping region 102, and are spaced apart on the inner side of the third doping region 104. The fifth doping regions 106 on both sides are annular groove structures extending downward from the upper surface of the first doping region 102, and the fifth doping region 106 in the middle is a groove structure extending downward from the upper surface of the first doping region 102. The plurality of fifth doping regions 106 are N-type doped, and each fifth doping region 106 is connected to the first doping region 102 with a fifth PN junction J5. The plurality of fifth doping regions 106 have the same width, and their depths decrease from the outside to the middle, that is, the fifth doping region 106 located on the outermost side has the largest depth, and the fifth doping region 106 located in the middle has the smallest depth. As shown Figure 2In the illustrated embodiment, three fifth doping regions 106 are provided (in this embodiment, the depths of the three fifth doping regions 106 are 15 microns, 10 microns, and 5 microns, respectively, from the outside to the inside, and the width of each fifth doping region 106 is 30 mils). The three fifth doping regions 106 are spaced apart and arranged inside the third doping region 104. The two fifth doping regions 106 on either side have an annular groove structure, while the fifth doping region 106 in the middle has a recessed structure. When a positive overvoltage occurs, it is typically a low-voltage, low-current overvoltage protection. In this case, precise control of the turn-on voltage is required, which requires an increase in the turn-on speed. Since a greater diffusion depth of the doping region corresponds to a lower diffusion concentration, the sheet resistance increases. Therefore, in this embodiment, when an overvoltage occurs in the first doping region 102, the voltage rises rapidly, the fifth doping region 106 located on the outermost side is turned on first, and then the other fifth doping regions 106 are turned on in sequence, and finally the fifth doping region 106 located in the middle is turned on, thereby achieving rapid conduction, reducing the reaction time during actual overvoltage protection, and improving the sensitivity of overvoltage protection.

[0054] like Figure 2 As shown, a plurality of sixth doping regions 107 are provided in the second doping region 103, and are spaced apart on the inner side of the fourth doping region 105. The sixth doping regions 107 on both sides are annular groove structures extending upward from the lower surface of the second doping region 103, and the sixth doping region 107 in the middle is a groove structure extending upward from the lower surface of the second doping region 103. The plurality of sixth doping regions 107 are N-type doped, and each sixth doping region 107 is connected to the second doping region 103 with a sixth PN junction J6. The depths of the plurality of sixth doping regions 107 are the same (the depths of the plurality of sixth doping regions 107 in this embodiment are all 5 microns), and their widths increase from the outside to the middle, that is, the width of the sixth doping region 107 on the outermost side is the smallest, and the width of the sixth doping region 107 in the middle is the largest. As shown Figure 2 In the embodiment shown, four sixth doping regions 107 are provided (in this embodiment, the widths of the four sixth doping regions 107 are 15 mils, 20 mils, 25 mils, and 30 mils, respectively, from the outside to the inside), and the four sixth doping regions 107 are spaced apart on the inner side of the fourth doping region 105. The three sixth doping regions 107 on both sides are annular groove structures, and the sixth doping region 107 in the middle is a groove structure. When a reverse overvoltage occurs, it is usually an overvoltage protection for high voltage and high current, and at this time, a large current needs to pass uniformly. Since the width of the sixth doping region 107 located on the outermost side is the smallest, and the width of the sixth doping region 107 located in the middle is the largest, this is not only conducive to rapid high-voltage discharge, but also achieves uniform current flow, thereby reducing the heat generation of the silicon material, and ultimately achieving the flow capacity during application to meet the reverse overvoltage protection.

[0055] like Figure 2 As shown, a first electrode 108 is provided on the upper surface of the substrate 101, and the first electrode 108 is connected to the first doping region 102 and the fifth doping region 106 respectively. The first electrode 108 of this embodiment is a metal electrode, which is formed by depositing a layer of metal such as aluminum silicon copper or titanium nickel silver by PVD or chemical plating. Specifically, the first electrode 108 covers a portion of the upper surface of the first doping region 102 and the upper surface of the fifth doping region 106. A second electrode 109 is provided on the lower surface of the substrate 101, and the second electrode 109 is connected to the second doping region 103 and the sixth doping region 107 respectively. The second electrode 109 of this embodiment is a metal electrode, which is formed by depositing a layer of metal such as aluminum silicon copper or titanium nickel silver by PVD or chemical plating. Specifically, the second electrode 109 covers a portion of the lower surface of the second doping region 103 and the lower surface of the sixth doping region 107.

[0056] like Figure 2 As shown, a first passivation layer 110 is provided on the upper surface of the substrate 101 to protect the third PN junction J3. This passivation layer is a passivation film deposited by thermal growth or CVD. The first passivation layer 110 includes SiO2, semi-insulating oxygen-doped polysilicon (Sipos), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-pressure deposited silicon nitride (LPSiN), and the like. In this embodiment, the first passivation layer 110 has a plate-like structure. Its lower surface covers a portion of the upper surface of the substrate 101, the upper surface of the third doped region 104, the end of the third PN junction J3, and a portion of the upper surface of the first doped region 102. Its upper surface has a plate-like stepped structure with increasing thickness from the center to the edge. This embodiment provides composite, high-reliability passivation protection for the third PN junction J3 by disposing a first passivation layer 110 at the edge of the third PN junction J3. The semi-insulating oxygen-doped polysilicon not only reduces high-temperature leakage current at the third PN junction J3 but also reduces the stress exerted by the first metal passivation layer 112 on the silicon substrate, further reducing the risk of chip cracking. The thermally oxidized SiO2 layer effectively isolates the device from the surrounding environment. The negative ion centers within the thermally oxidized SiO2 layer effectively capture metal ions, preventing contamination of the third PN junction J3 by metal ions, thereby reducing leakage current and enhancing the product's high-temperature performance. The low-temperature SiO2 film effectively prevents the effects of thermal expansion and contraction of the solder during melting and solidification on the glass during soldering. Furthermore, this embodiment employs a stepped structure in the first passivation layer 110, allowing the charge of the first electrode 108 to spread to the first metal passivation layer 112 at the device edge. This extends the space charge region at the edge, thereby increasing the blocking voltage to the internal breakdown voltage, reducing the probability of soft breakdown and improving product reliability.

[0057] like Figure 2As shown, a second passivation layer 111 is provided on the lower surface of the substrate 101 to protect the fourth PN junction J4. The second passivation layer 111 is a passivation film deposited by thermal growth or CVD. The second passivation layer 111 includes SiO2, semi-insulating oxygen-doped polysilicon (Sipos), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-pressure deposited silicon nitride (LPSiN), etc. In this embodiment, the second passivation layer 111 has a plate-like structure. Its upper surface covers a portion of the lower surface of the substrate 101, the lower surface of the fourth doped region 105, the end of the fourth PN junction J4, and a portion of the lower surface of the second doped region 103. The lower surface has a plate-like stepped structure with increasing thickness from the middle to the edge. This embodiment provides composite, high-reliability passivation protection for the fourth PN junction J4 by disposing a second passivation layer 111 at the edge of the fourth PN junction J4. The semi-insulating oxygen-doped polysilicon not only reduces high-temperature leakage current at the fourth PN junction J4 but also reduces the stress exerted by the second metal passivation layer 113 on the silicon substrate, further reducing the risk of chip cracking. The thermally oxidized SiO2 layer effectively isolates the device from the surrounding environment. The negative ion centers within the thermally oxidized SiO2 layer effectively capture metal ions, preventing contamination of the fourth PN junction J4 by metal ions, thereby reducing leakage current and enhancing the product's high-temperature performance. The low-temperature SiO2 film effectively prevents the effects of thermal expansion and contraction of the solder during melting and solidification on the glass during soldering. Furthermore, this embodiment employs a stepped structure in the second passivation layer 111, allowing the charge of the second electrode 109 to extend above the second metal passivation layer 113 at the device edge. This extends the space charge region at the edge, thereby increasing the blocking voltage to the internal breakdown voltage, reducing the probability of soft breakdown and improving product reliability.

[0058] like Figure 2As shown, a first metal passivation layer 112 is provided on the first electrode 108 to protect the first electrode 108. The first metal passivation layer 112 includes a metal passivation layer such as SiN, NSG, phosphosilicate glass (PSG), and polymide. The first metal passivation layer 112 covers a portion of the upper surface of the first passivation layer 110, the side surfaces of the first electrode 108, and a portion of the upper surface of the first electrode 108. A second metal passivation layer 113 is provided on the second electrode 109 to protect the second electrode 109. The second metal passivation layer 113 includes a metal passivation layer such as SiN, NSG, phosphosilicate glass (PSG), and polymide. The second metal passivation layer 113 covers a portion of the lower surface of the second passivation layer 111, the side surfaces of the second electrode 109, and a portion of the lower surface of the second electrode 109. In this embodiment, the first metal passivation layer 112 and the second metal passivation layer 113 only contain silicon, SiO2 and Polymide, and there is no glass on the scribing path, so the blade is in direct contact with the silicon during subsequent scribing. The full-cut process is used during scribing to avoid the generation of scribing cracks, effectively increase the scribing speed, reduce the generation of wastewater in production, and improve the environmental friendliness of the production process.

[0059] like Figure 2 and Figure 3 As shown, the working principle of this embodiment is: when the first electrode 108 is at a negative voltage and the second electrode 109 is at a positive voltage, the second PN junction J2, the fourth PN junction J4 and the fifth PN junction J5 are forward biased, and the first PN junction J1, the third PN junction J3 and the sixth PN junction J6 are reverse biased. Since the reverse avalanche voltage of the third PN junction J3 is lower than the reverse avalanche voltage of the first PN junction J1, the reverse breakdown voltage is mainly determined by the third PN junction J3. When the voltage difference between the second electrode 109 and the first electrode 108 exceeds the reverse avalanche breakdown voltage of the third PN junction J3, the current increases sharply, and when the product of the current and the resistance of the first doped region 102 reaches the forward voltage drop of the fifth PN junction J5 of 0.7V, the fifth PN junction J5 is forward-conducted, and the current is injected into the fifth doped region 106, eventually forming an NPN structure composed of the fifth doped region 106, the first doped region 102, and the substrate 101, and a PNP structure composed of the first doped region 102, the substrate 101, and the second doped region 103, thereby forming a mutual amplification effect of positive feedback of the NPN-PNP dual triode. Figure 3 The forward blocking mode shown is the current-voltage curve of the forward overvoltage performance test. Figure 3 It can be seen from the forward blocking mode curve that when there is a forward overvoltage, the current and voltage are small. When the third PN junction J3 is turned on, the waveform quickly retraces, thereby realizing the circuit protection of forward overvoltage short-circuit discharge.

[0060] In addition, when the fifth PN junction J5 is forward-conducted, since the depths of the multiple fifth doped regions 106 decrease from the outside to the middle, the square resistance of the fifth doped region 106 located on the outermost side is the largest, and its voltage rises faster, so that the outermost fifth doped region 106 is turned on first, and then the middle doped regions are turned on in turn, thereby achieving a faster conduction speed, reducing the response time of the device in actual application, and making the protection more sensitive.

[0061] like Figure 2 As shown, when the first electrode 108 is at a positive voltage and the second electrode 109 is at a negative voltage, the second PN junction J2, the fourth PN junction J4 and the fifth PN junction J5 are reverse biased, and the first PN junction J1, the third PN junction J3 and the sixth PN junction J6 are forward biased. Since the reverse avalanche voltage of the fourth PN junction J4 is less than the reverse avalanche voltage of the second PN junction J2, the reverse breakdown voltage is mainly determined by the fourth PN junction J4. When the voltage difference between the first electrode 108 and the second electrode 109 exceeds the reverse avalanche breakdown voltage of the fourth PN junction J4, the current increases sharply, and when the product of the current and the resistance of the second doped region 103 reaches the forward voltage drop of the sixth PN junction J6 of 0.7V, the sixth PN junction J6 is forward-conducted, and the current is injected into the sixth doped region 107, eventually forming an NPN structure composed of the sixth doped region 107, the second doped region 103, and the substrate 101, and a PNP structure composed of the second doped region 103, the substrate 101, and the first doped region 102, thereby forming a mutual amplification effect of positive feedback of the NPN-PNP dual triode. Figure 3 The reverse blocking mode shown is a current-voltage curve for reverse overvoltage performance testing, wherein the ratio of current to voltage in the reverse blocking mode is different from that in the forward blocking mode. Figure 3 It can be seen from the reverse blocking mode curve that when the reverse overvoltage occurs, the current is large, and the waveform appears to fly back after the fourth PN junction J4 is turned on, thereby realizing the circuit protection of reverse overvoltage short-circuit discharge.

[0062] In addition, when the sixth PN junction J6 is forward-conducted, since the widths of the multiple sixth doped regions 107 increase from the outside to the middle, the width of the sixth doped region 107 located in the middle is the largest, and a large current can pass through evenly, thereby realizing large current discharge for rapid voltage reduction, and reducing the heat generation of the silicon material, thereby being able to withstand a higher breakdown voltage.

[0063] Example 2

[0064] See Figure 4 The method for manufacturing the asymmetric semiconductor discharge tube chip of this embodiment includes the following steps:

[0065] S10, providing a substrate 101.

[0066] In this step, the substrate 101 includes an upper surface and a lower surface opposite to each other, which are N-type. <111> The crystalline substrate single crystal has a thickness of 100-6000 μm and a resistivity of 0.002-1000 Ω·cm. The interior of the substrate 101 can be doped with phosphorus, that is, P-type doping.

[0067] S20 , performing doping on the upper surface of the substrate 101 to form a first doping region 102 .

[0068] In this step, an oxide layer is formed on the upper surface of the substrate 101 by hydrogen-oxygen synthesis, and then a first doped region 102 is formed by photolithography. Boron pre-diffusion and boron main diffusion are performed in the first doped region 102 to form a P-type doped first doped region 102. A first PN junction J1 is formed at the connection between the first doped region 102 and the substrate 101.

[0069] S30 , performing doping on the lower surface of the substrate 101 to form a second doping region 103 .

[0070] In this step, an oxide layer is formed on the lower surface of the substrate 101 by hydrogen-oxygen synthesis, and then a second doped region 103 is formed by photolithography. Boron pre-diffusion and boron main diffusion are performed in the second doped region 103 to form a P-type doped second doped region 103. A second PN junction J2 is formed at the connection between the second doped region 103 and the substrate 101.

[0071] S40 , performing doping on the upper surface of the first doping region 102 to form a third doping region 104 and a plurality of fifth doping regions 106 .

[0072] In this step, an oxide layer is formed on the upper surface of the first doping region 102 through hydrogen-oxygen synthesis, and then a plurality of fifth doping regions 106 and a third doping region 104 are sequentially formed by photolithography. Phosphorus pre-diffusion and phosphorus main diffusion are performed in each of the plurality of fifth doping regions 106 and the third doping region 104, respectively, to form N-type doped fifth doping regions 106 and third doping regions 104. The depth of the plurality of fifth doping regions 106 decreases from the outer edge to the middle, and the depth of the third doping region 104 is the same as the depth of the fifth doping region 106 located in the middle. A third PN junction J3 is formed at the junction of the third doping region 104 and the first doping region 102, and a fifth PN junction J5 is formed at the junction of the fifth doping region 106 and the first doping region 102.

[0073] S50 , performing doping on the lower surface of the second doping region 103 to form a fourth doping region 105 and a plurality of sixth doping regions 107 .

[0074] In this step, an oxide layer is formed on the lower surface of the second doping region 103 through hydrogen-oxygen synthesis, and then a fourth doping region 105 and multiple sixth doping regions 107 are sequentially formed by photolithography. Phosphorus pre-diffusion and phosphorus main diffusion are performed in the fourth doping region 105 and the multiple sixth doping regions 107, respectively, to form N-type doped fourth doping regions 105 and sixth doping regions 107. The multiple sixth doping regions 107 have the same depth, and their widths increase from the outside to the center. The width of the fourth doping region 105 is the same as that of the third doping region 104. A fourth PN junction J4 is formed at the junction of the fourth doping region 105 and the second doping region 103, and a sixth PN junction J6 is formed at the junction of the sixth doping region 107 and the second doping region 103.

[0075] S60 , forming a first passivation layer 110 at an end portion of the third PN junction J3 , and forming a second passivation layer 111 at an end portion of the fourth PN junction J4 .

[0076] In this step, a first passivation layer 110 is formed at the end of the third PN junction J3. The first passivation layer 110 is a passivation film formed by thermal growth or CVD deposition, and the passivation film structure is SiO2, Sipos, PSG, BPSG, LPSiN, etc. A second passivation layer 111 is formed at the end of the fourth PN junction J4. The second passivation layer 111 is a passivation film formed by thermal growth or CVD deposition, and the passivation film structure is SiO2, Sipos, PSG, BPSG, LPSiN, etc.

[0077] S70 , forming a first electrode 108 on the upper surface of the first doping region 102 , and forming a second electrode 109 on the lower surface of the second doping region 103 .

[0078] In this step, the electrode region is exposed on the first passivation layer 110 by photolithographic etching. The electrode region is located on the upper surface of the first doping region 102, and the end of its lower surface is located between the third doping region 104 and the outermost fifth doping region 106. A layer of metal such as aluminum-silicon-copper or titanium-nickel-silver is deposited on the electrode region. The metal is formed by PVD or chemical plating. Then, photolithographic etching is performed on the metal to form the first electrode 108, so that the first electrode 108 is connected to the first doping region 102 and the fifth doping region 106 respectively. The electrode region is exposed on the second passivation layer 111 by photolithographic etching. The electrode region is located on the lower surface of the second doping region 103, and the end of its upper surface is located between the fourth doping region 105 and the outermost sixth doping region 107. A layer of metal such as aluminum-silicon-copper or titanium-nickel-silver is deposited on the electrode region. The metal is formed by PVD or chemical plating. Then, photolithography and etching are performed on the metal to form the second electrode 109 , so that the second electrode 109 is connected to the second doping region 103 and the sixth doping region 107 respectively.

[0079] S80 , forming a first metal passivation layer 112 on the first electrode 108 , and forming a second metal passivation layer 113 on the second electrode 109 .

[0080] In this step, a first metal passivation layer 112 is formed on the first electrode 108 using a photoresist to protect the first electrode 108. The first metal passivation layer 112 can be made of a metal passivation layer such as SiN, NSG, PSG, or Polymide. A second metal passivation layer 113 is formed on the second electrode 109 using a photoresist to protect the second electrode 109. The second metal passivation layer 113 can be made of a metal passivation layer such as SiN, NSG, PSG, or Polymide.

[0081] In summary, the asymmetric semiconductor discharge tube chip of the present invention forms an NPN-PNP dual triode by disposing a highly doped third doping region 104 at the end of the first PN junction J1, a highly doped fourth doping region 105 at the end of the second PN junction J2, multiple fifth doping regions 106 with decreasing depth from the outside to the center within the first doping region 102, and multiple sixth doping regions 107 with increasing width from the outside to the center within the second doping region 103. Furthermore, the chip implements bidirectional overvoltage protection by providing bidirectional overvoltage protection. Furthermore, due to the asymmetric arrangement of the multiple fifth doping regions 106 within the first doping region 102 and the multiple sixth doping regions 107 within the second doping region 103, the second electrode 109 serves as the positive electrode and the first electrode 108 serves as the negative electrode. When the positive electrode is overvoltaged, a lower breakdown voltage is provided, enabling rapid conduction and more sensitive protection. When the negative electrode is overvoltage, a high current discharge can be achieved to quickly reduce the voltage, thereby being able to withstand a higher breakdown voltage. This allows for bidirectional protection with different protection thresholds for positive and negative overvoltages. Furthermore, by providing a first passivation layer 110 and a second passivation layer 111, composite, highly reliable passivation protection can be provided for the third PN junction J3 and the fourth PN junction J4, respectively. The first passivation layer 110 and the second passivation layer 111 are configured as a stepped structure, allowing the charge of the first electrode 108 and the second electrode 109 to extend to the first metal passivation layer 112 and the second metal passivation layer 113 at the edge of the device, thereby extending the space charge region to the edge. This allows the blocking voltage to reach the internal breakdown voltage, reducing the probability of soft breakdown and improving product reliability.

[0082] Although the present invention is disclosed through the above embodiments, the protection scope of the present invention is not limited thereto. Without departing from the concept of the present invention, any deformation or replacement of the above components shall fall within the scope of the claims of the present invention.

Claims

1. An asymmetric semiconductor discharge tube chip, characterized in that: The chip includes: a substrate comprising opposing upper and lower surfaces; a first doped region, which is a groove structure extending downward from the upper surface of the substrate, wherein a first PN junction is connected between the first doped region and the substrate; a second doped region, which is a groove structure extending upward from the lower surface of the substrate, and a second PN junction is connected between the second doped region and the substrate; a third doped region, disposed at an end position of the first PN junction, and being an annular groove-shaped structure with an outer side extending downward from the upper surface of the substrate and an inner side extending downward from the upper surface of the first doped region; a third PN junction is connected between the third doped region and the first doped region, and a reverse avalanche voltage of the third PN junction is lower than a reverse avalanche voltage of the first PN junction; a fourth doped region, disposed at an end portion of the second PN junction, and being an annular groove-shaped structure having an outer side extending upward from the lower surface of the substrate and an inner side extending upward from the lower surface of the second doped region; a fourth PN junction being connected between the fourth doped region and the second doped region, and a reverse avalanche voltage of the fourth PN junction being lower than a reverse avalanche voltage of the second PN junction; a plurality of fifth doping regions, spaced apart and disposed inside the third doping region, wherein the depth of the fifth doping regions decreases from both sides to the middle, and a fifth PN junction is connected between each of the fifth doping regions and the first doping region; a plurality of sixth doping regions, spaced apart and arranged inside the fourth doping region, wherein the width of each sixth doping region increases sequentially from both sides to the middle, and each sixth doping region is connected to the second doping region via a sixth PN junction; a first electrode connected to the first doping region and the fifth doping region respectively; The second electrode is connected to the second doping region and the sixth doping region respectively.

2. The asymmetric semiconductor discharge tube chip according to claim 1, wherein: The substrate is N-type doped, the first doping region and the second doping region are P-type doped, the third doping region, the fourth doping region, the fifth doping region and the sixth doping region are N-type doped, and the doping concentration of the third doping region and the fourth doping region is higher than the doping concentration of the substrate.

3. The asymmetric semiconductor discharge tube chip according to claim 1, wherein: The chip also includes a first passivation layer, which is a plate-like structure. The lower surface of the first passivation layer covers part of the upper surface of the substrate, the upper surface of the third doped region, the end of the third PN junction and part of the upper surface of the first doped region. The upper surface of the first passivation layer is a stepped structure with the thickness increasing from the middle to the edge.

4. The asymmetric semiconductor discharge tube chip according to claim 1, wherein: The chip also includes a second passivation layer, which is a plate-like structure. Its upper surface covers part of the lower surface of the substrate, the lower surface of the fourth doped region, the end of the fourth PN junction and part of the lower surface of the second doped region. Its lower surface is a stepped structure with the thickness increasing from the middle to the edge.

5. The asymmetric semiconductor discharge tube chip according to claim 3, wherein: The chip further includes a first metal passivation layer, which covers a portion of the upper surface of the first passivation layer, a side portion of the first electrode, and a portion of the upper surface of the first electrode.

6. The asymmetric semiconductor discharge tube chip according to claim 4, wherein: The chip further includes a second metal passivation layer, which covers a portion of the lower surface of the second passivation layer, a side portion of the second electrode, and a portion of the lower surface of the second electrode.

7. The asymmetric semiconductor discharge tube chip according to claim 1, wherein: The first electrode is a metal electrode made of aluminum-silicon-copper or titanium-nickel-silver; the second electrode is a metal electrode made of aluminum-silicon-copper or titanium-nickel-silver.

8. The asymmetric semiconductor discharge tube chip according to claim 5, wherein: The first passivation layer includes SiO2, semi-insulating oxygen-doped polysilicon, phosphosilicate glass, borophosphosilicate glass and low-pressure deposited silicon nitride passivation film; the first metal passivation layer is SiN, NSG, phosphosilicate glass or polyamide metal passivation layer.

9. The asymmetric semiconductor discharge tube chip according to claim 6, wherein: The second passivation layer includes SiO2, semi-insulating oxygen-doped polysilicon, phosphosilicate glass, borophosphosilicate glass and low-pressure deposited silicon nitride passivation film; the second metal passivation layer is SiN, NSG, phosphosilicate glass or polyamide metal passivation layer.

10. A method for manufacturing an asymmetric semiconductor discharge tube chip according to any one of claims 1 to 9, characterized in that: The method includes: providing a substrate; Doping is performed on the upper surface of the substrate to form a first doping region, wherein a first PN junction is formed at a connection position between the first doping region and the substrate; Doping is performed on the lower surface of the substrate to form a second doping region, wherein a second PN junction is formed at a connection position between the second doping region and the substrate; Doping is performed at an end portion of the first PN junction to form a third doping region, wherein a connection position between the third doping region and the first doping region forms a third PN junction; Doping is performed at an end portion of the second PN junction to form a fourth doping region, wherein a connection position between the fourth doping region and the second doping region forms a fourth PN junction; Doping is performed in the first doping region to form a plurality of fifth doping regions, wherein the plurality of fifth doping regions are spaced apart inside the third doping region, and the depth of each fifth doping region decreases from both sides to the middle, and each fifth doping region forms a fifth PN junction at a connection position with the first doping region; Doping is performed in the second doping region to form a plurality of sixth doping regions, wherein the plurality of sixth doping regions are spaced apart inside the fourth doping region, and the width of each sixth doping region increases sequentially from both sides to the middle, and each sixth doping region forms a sixth PN junction at a connection position with the second doping region; forming a first passivation layer at an end of the third PN junction; forming a second passivation layer at an end of the fourth PN junction; Disposing a first electrode on the upper surface of the first doped region; Disposing a second electrode on the lower surface of the second doped region; forming a first metal passivation layer on the first electrode; A second metal passivation layer is formed on the second electrode.

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