Chip temperature control method and device, electronic equipment, storage medium and program product

Abstract

The invention relates to a chip temperature control method and device, electronic equipment, a storage medium and a program product. The method comprises the steps that target power consumption of all calculation core sets in a target chip is determined, any calculation core set comprises at least one calculation core, any calculation core comprises at least one processor set, and any processor set comprises at least one processor; for any calculation core group, adjusting the working voltage and the working frequency of the calculation core group according to the target power consumption of the calculation core group; and for any calculation core group, adjusting the utilization rate of each processor group in the calculation core group. According to the method, the chip is subjected to temperature control from the chip level, the calculation core group level and the processor group level, and effective control and uniform distribution of the internal temperature of the chip can be realized, so that the heat dissipation performance and the working reliability of the chip are improved, and the increasing high-performance calculation requirement is met.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a chip temperature control method, a chip temperature control device, an electronic device, a computer-readable storage medium, and a computer program product. Background Art

[0002] As electronic device performance continues to improve, the heat generated by chips during operation is also increasing. This is especially true when chips are performing complex processing tasks, where power consumption and heat generation are particularly significant. For example, GPUs (Graphics Processing Units) experience significant increases in power consumption and heat generation when performing complex graphics processing tasks. To ensure proper chip operation and extend their lifespan, effective chip temperature control is crucial. Summary of the Invention

[0003] The present disclosure provides a technical solution for chip temperature control.

[0004] According to one aspect of the present disclosure, a chip temperature control method is provided, comprising:

[0005] Determining target power consumption for each computing core group in the target chip, wherein any computing core group includes at least one computing core, any computing core includes at least one processor group, and any processor group includes at least one processor;

[0006] For any computing core group, adjusting the operating voltage and operating frequency of the computing core group according to the target power consumption of the computing core group;

[0007] For any computing core group, the utilization rate of each processor group in the computing core group is adjusted.

[0008] In a possible implementation, adjusting the utilization of each processor group in the computing core group includes:

[0009] Collecting the current temperature of each processor group in the computing core group;

[0010] The utilization rate of each processor group is adjusted according to the current temperature of each processor group.

[0011] In a possible implementation, adjusting the utilization of each processor group according to the current temperature of each processor group includes:

[0012] determining a temperature average of the computing core group based on the current temperature of each processor group;

[0013] For any processor group in the computing core group, determining a first target utilization rate of the processor group according to a difference between a current temperature of the processor group and an average temperature of the computing core group;

[0014] The utilization of each processor group is adjusted according to the first target utilization of each processor group.

[0015] In a possible implementation, adjusting the utilization of each processor group according to the first target utilization of each processor group includes:

[0016] determining a sum of first target utilizations of the respective processor groups;

[0017] In response to the sum of the first target utilizations being less than the lower utilization limit of the computing core group, determining a first difference between the lower utilization limit of the computing core group and the sum of the first target utilizations;

[0018] For any processor group in the computing core group, increasing the first target utilization of the processor group according to the first difference to obtain a second target utilization of the processor group;

[0019] The utilization of the processor group is adjusted according to the second target utilization of the processor group.

[0020] In a possible implementation, increasing the first target utilization of the processor group according to the first difference to obtain the second target utilization of the processor group includes:

[0021] determining a ratio of the first difference to the number of processor groups in the computing core group;

[0022] For any processor group in the computing core group, the sum of the first target utilization of the processor group and the ratio is determined as the second target utilization of the processor group.

[0023] In a possible implementation, adjusting the utilization of each processor group according to the current temperature of each processor group includes:

[0024] determining a leading processor group in the computing core group according to current temperatures of the respective processor groups;

[0025] For any non-dominant processor group in the computing core group, the utilization rate of the non-dominant processor group is adjusted according to the difference between the current temperature of the non-dominant processor group and the current temperature of the dominant processor group.

[0026] In a possible implementation, determining the leading processor group in the computing core group according to the current temperature of each processor group in the computing core group includes:

[0027] A processor group with the Nth lowest current temperature among the processor groups is determined as a leading processor group in the computing core group, where N is an integer greater than or equal to 1.

[0028] In a possible implementation, adjusting the utilization of each processor group in the computing core group according to the current temperature of each processor group further includes:

[0029] The utilization rate of the leading processor group is adjusted to a preset maximum utilization rate.

[0030] In a possible implementation, adjusting the utilization of each processor group in the computing core group includes:

[0031] Obtaining current application scenario information of the target chip;

[0032] Obtaining a preset utilization rate corresponding to the current application scenario information;

[0033] According to the preset utilization rate, the utilization rate of each processor group in the computing core group is adjusted.

[0034] In one possible implementation,

[0035] The method further includes: determining the length of a first adjustment period of the operating voltage and operating frequency of the computing core group based on the stabilization time of the temperature of each processor group in the computing core group; determining the length of a second adjustment period of the target power consumption of the computing core group based on the stabilization time of the operating voltage and operating frequency of the computing core group;

[0036] The determining the target power consumption of each computing core group in the target chip includes: in response to entering a new second adjustment cycle, determining the target power consumption of each computing core group in the target chip;

[0037] Adjusting the operating voltage and operating frequency of the computing core group according to the target power consumption of the computing core group includes: in response to entering a new first adjustment cycle, adjusting the operating voltage and operating frequency of the computing core group according to the target power consumption of the computing core group.

[0038] In a possible implementation, determining the target power consumption of each computing core group in the target chip includes:

[0039] Determining a total target power consumption of the target chip;

[0040] Determining the required power consumption of each computing core group in the target chip;

[0041] The target power consumption of each computing core group is determined according to the total target power consumption and the required power consumption of each computing core group.

[0042] In a possible implementation, determining the target power consumption of each computing core group according to the total target power consumption and the required power consumption of each computing core group includes:

[0043] In response to the total target power consumption of the target chip being less than or equal to the total required power consumption of each computing core group, the total target power consumption of the target chip is evenly distributed to each computing core group to obtain the target power consumption of each computing core group;

[0044] or,

[0045] In response to the total target power consumption of the target chip being greater than the total required power consumption of the respective computing core groups, corresponding power consumption is allocated to the respective computing core groups according to the required power consumption of the respective computing core groups; and the remaining power consumption of the target chip is allocated to the M computing core groups with the largest required power consumption among the respective computing core groups, where M is an integer greater than or equal to 1.

[0046] In a possible implementation, adjusting the operating voltage and operating frequency of the computing core group according to the target power consumption of the computing core group includes:

[0047] Inputting the target power consumption of the computing core group and the current power consumption of the computing core group into a first proportional-integral-derivative controller, and outputting the target operating frequency of the computing core group via the first proportional-integral-derivative controller;

[0048] Determining a target operating voltage of the computing core group according to the target operating frequency of the computing core group and a correspondence between the operating voltage and the operating frequency;

[0049] The operating voltage and the operating frequency of the computing core group are adjusted according to the target operating voltage and the target operating frequency of the computing core group.

[0050] In a possible implementation, the target chip includes any one of the following:

[0051] Graphics processor, central processing unit, field programmable gate array, digital signal processor.

[0052] According to one aspect of the present disclosure, a temperature control device for a chip is provided, comprising:

[0053] A first determining module is configured to determine target power consumption of each computing core group in the target chip, wherein any computing core group includes at least one computing core, any computing core includes at least one processor group, and any processor group includes at least one processor;

[0054] A first adjustment module is configured to adjust, for any computing core group, an operating voltage and an operating frequency of the computing core group according to a target power consumption of the computing core group;

[0055] The second adjustment module is used to adjust the utilization rate of each processor group in any computing core group.

[0056] In a possible implementation, the second adjustment module is configured to:

[0057] Collecting the current temperature of each processor group in the computing core group;

[0058] The utilization rate of each processor group is adjusted according to the current temperature of each processor group.

[0059] In a possible implementation, the second adjustment module is configured to:

[0060] determining a temperature average of the computing core group based on the current temperature of each processor group;

[0061] For any processor group in the computing core group, determining a first target utilization rate of the processor group according to a difference between a current temperature of the processor group and an average temperature of the computing core group;

[0062] The utilization of each processor group is adjusted according to the first target utilization of each processor group.

[0063] In a possible implementation, the second adjustment module is configured to:

[0064] determining a sum of first target utilizations of the respective processor groups;

[0065] In response to the sum of the first target utilizations being less than the lower utilization limit of the computing core group, determining a first difference between the lower utilization limit of the computing core group and the sum of the first target utilizations;

[0066] For any processor group in the computing core group, increasing the first target utilization of the processor group according to the first difference to obtain a second target utilization of the processor group;

[0067] The utilization of the processor group is adjusted according to the second target utilization of the processor group.

[0068] In a possible implementation, the second adjustment module is configured to:

[0069] determining a ratio of the first difference to the number of processor groups in the computing core group;

[0070] For any processor group in the computing core group, the sum of the first target utilization of the processor group and the ratio is determined as the second target utilization of the processor group.

[0071] In a possible implementation, the second adjustment module is configured to:

[0072] determining a leading processor group in the computing core group according to current temperatures of the respective processor groups;

[0073] For any non-dominant processor group in the computing core group, the utilization rate of the non-dominant processor group is adjusted according to the difference between the current temperature of the non-dominant processor group and the current temperature of the dominant processor group.

[0074] In a possible implementation, the second adjustment module is configured to:

[0075] A processor group with the Nth lowest current temperature among the processor groups is determined as a leading processor group in the computing core group, where N is an integer greater than or equal to 1.

[0076] In a possible implementation, the second adjustment module is configured to:

[0077] The utilization rate of the leading processor group is adjusted to a preset maximum utilization rate.

[0078] In a possible implementation, the second adjustment module is configured to:

[0079] Obtaining current application scenario information of the target chip;

[0080] Obtaining a preset utilization rate corresponding to the current application scenario information;

[0081] According to the preset utilization rate, the utilization rate of each processor group in the computing core group is adjusted.

[0082] In one possible implementation,

[0083] The apparatus further includes: a second determining module configured to determine the length of a first adjustment period of the operating voltage and operating frequency of the computing core group based on the stabilization time of the temperature of each processor group in the computing core group; and determine the length of a second adjustment period of the target power consumption of the computing core group based on the stabilization time of the operating voltage and operating frequency of the computing core group;

[0084] The first determining module is configured to: determine target power consumption of each computing core group in the target chip in response to entering a new second adjustment cycle;

[0085] The first adjustment module is configured to adjust the operating voltage and operating frequency of the computing core group according to the target power consumption of the computing core group in response to entering a new first adjustment cycle.

[0086] In a possible implementation, the first determining module is configured to:

[0087] Determining a total target power consumption of the target chip;

[0088] Determining the required power consumption of each computing core group in the target chip;

[0089] The target power consumption of each computing core group is determined according to the total target power consumption and the required power consumption of each computing core group.

[0090] In a possible implementation, the first determining module is configured to:

[0091] In response to the total target power consumption of the target chip being less than or equal to the total required power consumption of each computing core group, the total target power consumption of the target chip is evenly distributed to each computing core group to obtain the target power consumption of each computing core group;

[0092] or,

[0093] In response to the total target power consumption of the target chip being greater than the total required power consumption of the respective computing core groups, corresponding power consumption is allocated to the respective computing core groups according to the required power consumption of the respective computing core groups; and the remaining power consumption of the target chip is allocated to the M computing core groups with the largest required power consumption among the respective computing core groups, where M is an integer greater than or equal to 1.

[0094] In a possible implementation, the first adjustment module is configured to:

[0095] Inputting the target power consumption of the computing core group and the current power consumption of the computing core group into a first proportional-integral-derivative controller, and outputting the target operating frequency of the computing core group via the first proportional-integral-derivative controller;

[0096] Determining a target operating voltage of the computing core group according to the target operating frequency of the computing core group and a correspondence between the operating voltage and the operating frequency;

[0097] The operating voltage and the operating frequency of the computing core group are adjusted according to the target operating voltage and the target operating frequency of the computing core group.

[0098] In a possible implementation, the target chip includes any one of the following:

[0099] Graphics processor, central processing unit, field programmable gate array, digital signal processor.

[0100] According to one aspect of the present disclosure, an electronic device is provided, comprising: one or more processors; a memory for storing executable instructions; wherein the one or more processors are configured to call the executable instructions stored in the memory to execute the above method.

[0101] According to one aspect of the present disclosure, a computer-readable storage medium is provided, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the above method is implemented.

[0102] According to one aspect of the present disclosure, a computer program product is provided, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in an electronic device, a processor in the electronic device executes the above method.

[0103] In an embodiment of the present disclosure, by determining the target power consumption of each computing core group in the target chip, wherein any computing core group includes at least one computing core, any computing core includes at least one processor group, and any processor group includes at least one processor, for any computing core group, according to the target power consumption of the computing core group, the operating voltage and operating frequency of the computing core group are adjusted, and for any computing core group, the utilization rate of each processor group in the computing core group is adjusted, thereby proposing a new local hot spot temperature control scheme inside the chip, which controls the chip temperature from the chip level, the computing core group level and the processor group level, and can achieve effective control and uniform distribution of the internal temperature of the chip, thereby improving the heat dissipation performance and working reliability of the chip, and meeting the growing demand for high-performance computing.

[0104] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

[0105] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0106] The accompanying drawings herein are incorporated into and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and, together with the specification, are used to explain the technical solutions of the present disclosure.

[0107] Figure 1A flow chart of a chip temperature control method provided by an embodiment of the present disclosure is shown.

[0108] Figure 2 A block diagram of a chip temperature control device provided by an embodiment of the present disclosure is shown.

[0109] Figure 3 A block diagram of an electronic device 1900 provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0110] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0111] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0112] The term "and / or" herein simply describes an association relationship between associated objects, indicating that three relationships can exist. For example, "A and / or B" can represent the existence of three situations: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" herein refers to any combination of at least two of any one or more of a plurality of items. For example, "at least one of A, B, and C" can represent any one or more elements selected from the set consisting of A, B, and C.

[0113] In addition, numerous specific details are provided in the following detailed description to better illustrate the present disclosure. Those skilled in the art will appreciate that the present disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art are not described in detail in order to highlight the main points of the present disclosure.

[0114] In the related art, temperature control is usually achieved by collecting the power consumption and temperature of the chip and adjusting the operating voltage and operating frequency of the chip. However, in the related art, the problem of uneven temperature distribution within the chip is more prominent. Due to the differences in the working conditions of different functional modules inside the chip, such as some functions working alone while other modules not working, or abnormalities in the heat dissipation medium, and uneven distribution of heat sources, the temperature distribution inside the chip is uneven. This uneven temperature distribution will not only lose the heat dissipation performance and reduce the heat dissipation efficiency of the chip, but may also cause uneven distribution of thermal stress inside the chip, increasing the risk of deformation and damage to the chip. In addition, when the temperature of the chip is too high, it may also affect its working performance, making it unable to operate in the optimal state, and even cause the chip to fail.

[0115] Therefore, effectively addressing the uneven temperature distribution within the chip, improving heat dissipation, and ensuring that the chip's temperature does not exceed the limit during operation have become pressing technical challenges. Ideally, evenly distributing the temperature across the chip would help achieve a more uniform stress distribution, while also maximizing the use of the heat dissipation structure, thereby improving the chip's overall performance and reliability.

[0116] In order to solve technical problems similar to those described above, an embodiment of the present disclosure provides a temperature control method for a chip, by determining the target power consumption of each computing core group in a target chip, wherein any computing core group includes at least one computing core, any computing core includes at least one processor group, and any processor group includes at least one processor. For any computing core group, the operating voltage and operating frequency of the computing core group are adjusted according to the target power consumption of the computing core group, and for any computing core group, the utilization rate of each processor group in the computing core group is adjusted. Thus, a new local hotspot temperature control scheme inside the chip is proposed, which controls the temperature of the chip from the chip level, computing core group level and processor group level, and can achieve effective control and uniform distribution of the internal temperature of the chip, thereby improving the heat dissipation performance and working reliability of the chip, and meeting the growing demand for high-performance computing.

[0117] The temperature control method of a chip provided by an embodiment of the present disclosure is described in detail below with reference to the accompanying drawings.

[0118] Figure 1 A flow chart of a temperature control method for a chip provided by an embodiment of the present disclosure is shown. In one possible implementation, the execution subject of the temperature control method for the chip may be a temperature control device for the chip. For example, the temperature control method for the chip may be executed by a terminal device or a server or other electronic device. The terminal device may be a user equipment (UE), a mobile device, a user terminal, a terminal, a cellular phone, a cordless phone, a personal digital assistant (PDA), a handheld device, a computing device, a vehicle-mounted device or a wearable device, etc. In some possible implementations, the temperature control method for the chip may be implemented by a processor calling computer-readable instructions stored in a memory. As Figure 1 As shown, the chip temperature control method includes steps S11 to S13.

[0119] In step S11 , target power consumption of each computing core group in the target chip is determined, wherein any computing core group includes at least one computing core, any computing core includes at least one processor group, and any processor group includes at least one processor.

[0120] In step S12 , for any computing core group, the operating voltage and operating frequency of the computing core group are adjusted according to the target power consumption of the computing core group.

[0121] In step S13 , for any computing core group, the utilization rate of each processor group in the computing core group is adjusted.

[0122] In the embodiment of the present disclosure, the target chip can be any chip that meets the following architecture: the target chip contains multiple computing core groups, each computing core group contains at least one computing core, each computing core contains at least one processor group, and each processor group contains at least one processor.

[0123] In a possible implementation, the target chip includes any one of the following: a graphics processing unit (GPU), a central processing unit (CPU), a field-programmable gate array (FPGA), and a digital signal processor (DSP).

[0124] In an embodiment of the present disclosure, the temperature of the target chip is controlled based on three levels. Among them, the first level can be called the chip level, the second level can be called the computing core group level, and the third level can be called the processor group level. The chip level can adjust the target power consumption of each computing core group in the target chip so that the temperature of each computing core group is evenly distributed in the target chip; the computing core group level can adjust the operating voltage and operating frequency of each computing core group based on the target power consumption of each computing core group so that each computing core group operates at its target power consumption; the processor group level can adjust the utilization of each processor group in each computing core group so that the temperature of each processor group is evenly distributed in the computing core group.

[0125] In the embodiments of the present disclosure, any computing core group includes at least one computing core, any computing core includes at least one processor group, and any processor group includes at least one processor. Among them, the computing core group can be the smallest unit for adjusting the operating voltage and operating frequency, and the processor group can be the smallest unit for adjusting the utilization. In some application scenarios, the computing core can also be called a core, a core, an operation core, etc., the computing core group can also be called a core group, a voltage regulating core (voltage regulating core), etc., and the processor group can also be called a multiprocessor, etc., which is not limited here.

[0126] In the disclosed embodiment, the target chip can be cooled by air cooling or water cooling to ensure that the heat generated during operation is effectively dissipated, thereby maintaining the normal operating temperature of the target chip and preventing performance degradation or damage due to overheating. Air cooling mainly relies on fans to blow air to take away the heat from the surface of the chip. It is suitable for chips with relatively low power consumption and small heat dissipation requirements; while water cooling absorbs the heat generated by the chip through circulating coolant and transfers it to the radiator for release. It is suitable for chips with high power consumption and large heat dissipation requirements, and can provide more efficient heat dissipation effects. These two heat dissipation methods can be flexibly selected and applied according to the specific power consumption and heat dissipation requirements of the target chip to meet the heat dissipation requirements in different scenarios and ensure the stable operation and performance of the chip.

[0127] In an embodiment of the present disclosure, at the chip level, the target power consumption of each computing core group in the target chip can be adjusted.

[0128] In one possible implementation, determining the target power consumption of each computing core group in the target chip includes: determining the total target power consumption of the target chip; determining the required power consumption of each computing core group in the target chip; and determining the target power consumption of each computing core group based on the total target power consumption and the required power consumption of each computing core group.

[0129] The target chip's total target power consumption represents the power consumption level the target chip should maintain during operation under specific operating conditions. This can be determined based on factors such as the target chip's performance requirements, heat dissipation capabilities, and system design constraints. This ensures the target chip operates safely and stably while meeting its performance requirements and energy efficiency goals.

[0130] As an example of this implementation, determining the total target power consumption of the target chip includes: obtaining a current temperature of the target chip; and determining the total target power consumption of the target chip based on a difference between a preset temperature and the current temperature of the target chip. The preset temperature may be a pre-set upper limit of a safe operating temperature. For example, in a GPU, the preset temperature may be its maximum allowable temperature under high load.

[0131] In this example, if the current temperature of the target chip is lower than the preset temperature by a large margin, this indicates that the target chip has ample room for heat dissipation. The total target power consumption can be appropriately increased to allow the target chip to operate at a higher performance level while ensuring that the temperature does not exceed the preset temperature. If the current temperature of the target chip is close to or exceeds the preset temperature by a small or negative margin, this indicates that the target chip is under significant heat dissipation pressure and requires a reduction in the total target power consumption to reduce heat generated by the target chip and prevent performance degradation or damage due to excessive temperature.

[0132] In this implementation, the required power consumption of any computing core group refers to the power consumption required by that computing core group to perform its specific computing task. Different computing core groups have different functions and workloads, so their required power consumption may also vary. For example, in a GPU, the computing core group responsible for graphics rendering may require higher power consumption, while the computing core group responsible for video encoding and decoding may require lower power consumption.

[0133] In this implementation, the required power consumption of each computing core group can be estimated by simulating its working state and analyzing the complexity and data volume of its processing tasks. For example, for a graphics rendering core group, its required power consumption can be calculated based on factors such as the number of vertices and pixels processed, and the complexity of textures.

[0134] After determining the total target power consumption of the target chip and the required power consumption of each computing core group, the target power consumption of each computing core group can be determined according to a preset allocation method. For example, the target power consumption of each computing core group can be determined according to an average allocation, an on-demand allocation, or a priority allocation method.

[0135] By adopting this implementation, power consumption can be rationally allocated to each compute core group based on the target chip's total target power consumption and the actual power consumption required by each compute core group. This implementation ensures that each compute core group receives appropriate power consumption support based on its workload and performance requirements, without exceeding the chip's total target power consumption. This not only helps improve the chip's overall performance, as the compute core groups can perform tasks more efficiently, but also optimizes the chip's energy efficiency and avoids wasted power. Furthermore, precise power allocation effectively controls the chip's temperature to prevent overheating, thereby improving the chip's stability and reliability and extending its service life.

[0136] As an example of this implementation method, the target power consumption of each computing core group is determined based on the total target power consumption and the required power consumption of each computing core group, including: in response to the total target power consumption of the target chip being less than or equal to the total required power consumption of each computing core group, the total target power consumption of the target chip is evenly distributed to the each computing core group to obtain the target power consumption of each computing core group; or, in response to the total target power consumption of the target chip being greater than the total required power consumption of each computing core group, the corresponding power consumption is allocated to each computing core group according to the required power consumption of each computing core group; and the remaining power consumption of the target chip is allocated to the M computing core groups with the largest required power consumption among the each computing core group, where M is an integer greater than or equal to 1.

[0137] Case 1: The total target power consumption of the target chip is less than or equal to the total required power consumption of each computing core group. In this case, the total required power consumption of the computing core group is greater than or equal to the total target power consumption of the target chip. This means that if the power consumption is allocated according to the actual needs of the computing core group, the target chip may be overloaded, resulting in performance degradation or damage. In order to ensure that the target chip operates within a safe power consumption range, the total target power consumption of the target chip can be evenly distributed among the computing core groups. Specifically, the target power consumption of each computing core group can be equal to the total target power consumption of the target chip divided by the number of computing core groups. By evenly distributing power consumption, it can be ensured that each computing core group can operate without exceeding the total target power consumption of the target chip, thereby avoiding the risk of overload and ensuring the stability and reliability of the target chip.

[0138] Case 2: The target chip's total target power consumption is greater than the total required power consumption of each compute core group. In this case, the target chip's total target power consumption exceeds the total required power consumption of the compute core groups. Allocating power solely based on the basic requirements of the compute core groups may result in underutilization of the target chip's available power consumption, impacting overall system performance. In this case, power consumption can first be allocated based on the actual power consumption requirements of each compute core group to meet their basic operational needs. The remaining power consumption can then be allocated to the M compute core groups with the highest power consumption requirements. This can be done by distributing the power evenly across these compute core groups or by making a more detailed allocation based on their specific needs. This approach can optimize the performance of the target chip because allocating additional power to compute core groups with heavier workloads and higher power requirements allows these compute core groups to operate at a higher performance level, thereby improving overall system performance. This approach also avoids wasted power consumption and improves the energy efficiency of the target chip.

[0139] For example, the target chip has four computing core groups, A, B, C, and D. The required power consumption of each computing core group is: A: 30W; B: 25W; C: 20W; D: 25W. The total required power consumption is 100W.

[0140] Example 1: If the total target power consumption of the target chip is 90W (less than or equal to the total required power consumption of each computing core group, 100W), 90W can be evenly distributed among the four computing core groups. The target power consumption of each computing core group is: A: 22.5W; B: 22.5W; C: 22.5W; D: 22.5W. This ensures that each computing core group operates within the total target power consumption of the target chip, avoiding the risk of overload.

[0141] Example 2: If the total target power consumption of the target chip is 120W (greater than the total required power consumption of 100W for each computing core group), the power consumption can be first allocated based on the actual power consumption requirements of each computing core group: A: 30W; B: 25W; C: 20W; D: 25W. The remaining power consumption is 120W - 100W = 20W. Assuming that the M computing core groups with the highest power consumption requirements are A and B, the remaining 20W can be evenly distributed between A and B, with each computing core group increasing by 10W. The final target power consumption is: A: 40W; B: 35W; C: 20W; D: 25W. In this way, the two computing core groups with the highest power consumption requirements, A and B, can achieve greater computing power while supporting higher power consumption, thereby improving the performance of the entire system.

[0142] As another example of this implementation method, determining the target power consumption of each computing core group based on the total target power consumption and the required power consumption of each computing core group includes: determining the target power consumption of each computing core group based on the total target power consumption, the required power consumption of each computing core group, and the temperature difference between the each computing core group.

[0143] In this example, the temperature differences between the various computing core groups reflect their differences in heat dissipation. In this example, a preliminary power allocation can be made based on the total target power consumption and the required power consumption of each computing core group. Based on this preliminary allocation, the temperature differences between the various computing core groups can be further considered. For example, for computing core groups with higher temperatures, their target power consumption can be appropriately reduced to prevent overheating and performance degradation. For computing core groups with lower temperatures, their target power consumption can be appropriately increased, if heat dissipation conditions permit, to enable more efficient operation.

[0144] In this example, the target power consumption of each computing core group is optimized and balanced by comprehensively considering the total target power consumption of the target chip, the required power consumption of each computing core group, and the temperature difference between each computing core group. This ensures that the temperature of each computing core group is within a safe range while ensuring the overall performance and energy efficiency of the chip, thereby avoiding performance bottlenecks or damage caused by local overheating.

[0145] In the disclosed embodiments, at the computing core group level, the operating voltage and operating frequency of each computing core group can be adjusted based on the target power consumption of each computing core group to ensure that each computing core group operates within its target power consumption. For any computing core group, the operating voltage and operating frequency of the computing core group are key parameters that affect its power consumption and performance. By adjusting the operating voltage and operating frequency of the computing core group, the power consumption output of the computing core group can be controlled to achieve the target power consumption.

[0146] In one possible implementation, adjusting the operating voltage and operating frequency of the computing core group according to the target power consumption of the computing core group includes: inputting the target power consumption of the computing core group and the current power consumption of the computing core group into a first proportional-integral-differential controller, and outputting the target operating frequency of the computing core group via the first proportional-integral-differential controller; determining the target operating voltage of the computing core group according to the target operating frequency of the computing core group and the correspondence between the operating voltage and the operating frequency; and adjusting the operating voltage and operating frequency of the computing core group according to the target operating voltage and target operating frequency of the computing core group.

[0147] In this implementation, the target power consumption and current power consumption of the computing core group can be input as input signals to the first proportional-integral-derivative controller, wherein the target power consumption of the computing core group is the expected power consumption level, and the current power consumption of the computing core group is the power consumption value monitored in real time.

[0148] The first PID controller can calculate the operating frequency that needs to be adjusted based on the deviation between the target power consumption and the current power consumption of the computing core group. The target operating voltage of the computing core group can be determined based on the target operating frequency of the computing core group and the corresponding relationship between the operating voltage and the operating frequency. There is a certain correlation between the operating voltage and the operating frequency. For example, in some cases, increasing the operating frequency may require a corresponding increase in the operating voltage to ensure stable operation of the computing core group.

[0149] Based on the calculated target operating voltage and frequency, the computing core group's operating voltage and frequency can be adjusted. By precisely controlling these two parameters, the computing core group can operate stably within its target power consumption, achieving the expected performance and energy efficiency.

[0150] In this implementation, the power consumption of the computing core group can be precisely controlled through the first proportional integral differential controller and precise voltage and frequency regulation, so that it can run stably at the target power consumption and avoid problems caused by excessive or low power consumption.

[0151] In an embodiment of the present disclosure, at the processor group level, the utilization of each processor group in each computing core group can be adjusted so that the temperature of each processor group is evenly distributed in the computing core group. The utilization of any processor group can represent the proportion of time that the processor group is activated within a certain time period, that is, the proportion of time that the processor group is in a working state within a certain time period. In some application scenarios, the utilization of a processor group can also be referred to as activation rate, operation rate, usage rate, etc., which is not limited here.

[0152] In one possible implementation, for any processor group, the utilization of the processor group can be adjusted by setting a stall pattern parameter of the processor group. In one example, the stall pattern parameter value can be set to 0 to 31. For example:

[0153] A stagnation mode parameter value of 31 means that the processor group has no stagnation time, that is, it is always active during the working cycle, achieving maximum utilization. In this case, the processor group will continuously execute tasks and process data, providing the highest computing performance, but also generating more heat.

[0154] A stall mode parameter value of 30 means that the processor group is active for the vast majority of its working cycle, with only brief periods of stall time. For example, it stalls for one instruction cycle after executing 30 instructions. This setting ensures high processor group utilization, enabling efficient task execution while limiting power consumption and heat generation through short stall times.

[0155] A stall mode parameter value of 15 indicates a balanced distribution of active and idle time for the processor group. For example, after executing 15 instructions, the processor group stalls for 15 instruction cycles. This setting ensures that the processor group is active half the time and idle the other half, thus achieving a certain balance between performance and cooling requirements.

[0156] A stall mode parameter value of 1 means that the processor group spends most of its working cycle in a stalled state, with only a very short period of active time. For example, it will stall for 30 instruction cycles after executing each instruction. This setting results in very low processor group utilization.

[0157] A stagnation mode parameter value of 0 indicates that the processor group is completely stagnant, meaning that no tasks or instructions are executed during the work cycle, minimizing power consumption and heat generation. This setting is suitable for scenarios where the processor group needs to be completely shut down to reduce temperature, save energy, or perform system maintenance. However, the processor group cannot provide any computing performance during this period.

[0158] In a possible implementation, adjusting the utilization of each processor group in the computing core group includes: collecting current temperatures of each processor group in the computing core group; and adjusting the utilization of each processor group according to the current temperatures of each processor group.

[0159] In this implementation, the current temperature of each processor group in the computing core group can be monitored in real time. By analyzing the collected current temperatures of each processor group, it is possible to identify processor groups with excessively high or low temperatures and determine whether the temperature distribution is uniform.

[0160] If a processor group's temperature is too high, exceeding a preset safety threshold or exceeding the temperature of other processor groups, it may be overheating and its utilization needs to be reduced. For example, you can increase its stall mode parameters (such as increasing stall time or stall frequency) to reduce its workload and heat generation, thereby reducing its temperature.

[0161] If the temperature of a processor group is low and heat dissipation conditions permit, its utilization can be appropriately increased. For example, by reducing its stall mode parameters (such as reducing stall time or stall frequency), it can execute more tasks within a certain period of time, increase its heat generation, and balance the temperature distribution.

[0162] For processor groups with moderate and stable temperatures, their current utilization can be kept unchanged to ensure that they operate in optimal working conditions and provide stable computing performance.

[0163] In this implementation, the entire regulation process is dynamic, with the control system continuously adjusting the utilization of each processor group based on real-time temperature changes. This dynamic adjustment rapidly responds to temperature changes, continuously optimizing temperature distribution and performance, and ensuring safe and stable chip operation.

[0164] In another possible implementation, adjusting the utilization of each processor group in the computing core group includes: obtaining current application scenario information of the target chip; obtaining a preset utilization corresponding to the current application scenario information; and adjusting the utilization of each processor group in the computing core group according to the preset utilization.

[0165] In this implementation, the current application scenario of the target chip can be identified first. The application scenario can be the specific tasks or functions of the target chip in different working states. For example, in a GPU, the application scenario can include graphics rendering, video encoding and decoding, computing tasks, etc.; in a CPU, the application scenario can include multitasking, high-load computing, low-power standby, etc.

[0166] As an example of this implementation, information related to the current application scenario can be obtained through a monitoring module within the chip or through communication with an external system. For example, the current application scenario information may include the type of application being run, the size of the task load, and data processing requirements.

[0167] In this implementation, during the chip design and commissioning phase, engineers can pre-configure a set of appropriate processor group utilization settings, known as preset utilization, based on different application scenarios. These preset utilization settings can be optimized by manually debugging different PVT (Process-Voltage-Temperature) material scenarios. The goal is to minimize the temperature variance of the processor group when the target chip is operating, thereby achieving the optimal performance and heat dissipation balance.

[0168] Preset utilization rates can be stored in the firmware or system software of the target chip, corresponding to different application scenarios. Once the current application scenario is identified, the corresponding preset utilization rate settings can be retrieved from the storage. The retrieved preset utilization rates can be applied to each processor group in the computing core group. For example, the stall mode parameters of each processor group can be adjusted based on the preset utilization rate settings to achieve a predetermined utilization level.

[0169] During the operation of the target chip, if the application scenario changes, the new application scenario can be monitored and identified in real time, and then the utilization of the processor group can be dynamically adjusted according to the preset utilization corresponding to the new application scenario to adapt to different working requirements and heat dissipation conditions.

[0170] In this way, the chip can automatically switch to the optimal processor group utilization setting in different application scenarios, ensuring that while meeting performance requirements, minimum temperature variance and good heat dissipation are achieved, thereby improving the overall performance and reliability of the chip.

[0171] In one possible implementation, adjusting the utilization of each processor group based on the current temperature of each processor group includes: determining the average temperature of the computing core group based on the current temperature of each processor group; for any processor group in the computing core group, determining the first target utilization of the processor group based on the difference between the current temperature of the processor group and the average temperature of the computing core group; and adjusting the utilization of each processor group based on the first target utilization of each processor group.

[0172] In this implementation, the current temperature of each processor group in the computing core group can be collected in real time and averaged to obtain a mean temperature for the computing core group. The mean temperature for the computing core group represents the average of the current temperatures of each processor group in the computing core group. The mean temperature reflects the overall temperature level of the computing core group and serves as a reference for subsequent utilization adjustments.

[0173] For any processor group in the computing core group, the difference between its current temperature and the average temperature of the computing core group is calculated. The temperature difference can indicate the degree of deviation of the processor group relative to the overall temperature level. The first target utilization of the processor group can be determined based on the temperature difference. Generally, the larger the temperature difference, the more the temperature of the processor group deviates from the average, which may be overheating or undercooling, and its utilization needs to be adjusted accordingly. For example, the specific adjustment strategy can be:

[0174] If the current temperature of the processor group is higher than the average temperature, it may be overheating and the utilization rate needs to be reduced to reduce heat generation. For example, the first target utilization rate can be set to a value lower than the current utilization rate. The specific value can be determined based on the size of the temperature difference and the heat dissipation requirements.

[0175] If the current temperature of a processor group is lower than the average temperature, it indicates that its temperature is relatively low. If heat dissipation conditions permit, the utilization rate can be appropriately increased to increase heat generation and balance the temperature distribution. For example, the first target utilization rate can be set to a value higher than the current utilization rate. The specific value can also be determined based on the temperature difference and heat dissipation capacity.

[0176] If the current temperature of the processor group is not much different from the average temperature, it means that its temperature is relatively balanced. The current utilization can be maintained or fine-tuned to maintain a stable temperature state.

[0177] In one example, the difference delta_mp between the current temperature of the processor group and the temperature mean can be calculated. The calculated temperature difference delta_mp is normalized to obtain a normalized temperature difference mpt. Normalization can convert the difference into a dimensionless value, for example, between 0 and 1, to facilitate subsequent control and comparison. The normalized temperature difference mpt can be subjected to a PID (Proportional-Integral-Derivative) control operation with the target temperature difference 0 to obtain a utilization adjustment delta_c. The utilization adjustment delta_c can be added to the current utilization of the processor group to obtain a first target utilization.

[0178] In this implementation, the utilization of each processor group can be actually adjusted according to the calculated first target utilization of each processor group.

[0179] In this implementation, the entire adjustment process is dynamic. Based on real-time temperature changes, the control system continuously calculates the average and differential temperatures, updates the primary target utilization for each processor group, and adjusts utilization accordingly. This dynamic adjustment rapidly responds to temperature changes, continuously optimizing temperature distribution and performance, and ensuring safe and stable chip operation.

[0180] As an example of this implementation method, adjusting the utilization of each processor group according to the first target utilization of each processor group includes: determining the sum of the first target utilizations of the each processor group; in response to the sum of the first target utilizations being less than the lower limit of the utilization of the computing core group, determining a first difference between the lower limit of the utilization of the computing core group and the sum of the first target utilizations; for any processor group in the computing core group, increasing the first target utilization of the processor group according to the first difference to obtain the second target utilization of the processor group; and adjusting the utilization of the processor group according to the second target utilization of the processor group.

[0181] In this example, the first target utilization rates of the processor groups in the computing core group may be added together to obtain their total, which reflects the expected utilization level of the entire computing core group.

[0182] In this example, the lower utilization limit for the compute core group is a preset threshold that represents the minimum utilization required for normal operation of the compute core group. The lower utilization limit for the compute core group can be determined based on factors such as chip design requirements, performance targets, and heat dissipation capabilities.

[0183] If the calculated sum of the first target utilizations is less than the lower utilization limit, the current utilization settings may not meet the basic work needs or performance requirements of the compute core group and require further adjustment. The difference between the lower utilization limit and the sum of the first target utilizations is calculated as the first difference. This difference represents the total utilization increase required to reach the lower utilization limit.

[0184] The first difference can be allocated to each processor group in the computing core group according to certain rules to increase their first target utilization. The allocation rule can be average allocation, on-demand allocation, or priority allocation, depending on actual needs and the characteristics of the processor group. By adding the allocated difference to the original first target utilization, a second target utilization for each processor group can be obtained. This second target utilization is an adjusted new target utilization designed to ensure that the overall utilization of the computing core group reaches or exceeds the lower utilization limit.

[0185] In this example, the utilization of each processor group can be adjusted based on the calculated second target utilization. This adjustment ensures that the overall utilization of the computing core group does not fall below the preset lower limit, thereby meeting the basic operating needs and performance requirements of the chip and helping to maintain stable chip operation and performance.

[0186] In one example, the method of increasing the first target utilization of the processor group based on the first difference to obtain the second target utilization of the processor group includes: determining the ratio of the first difference to the number of processor groups in the computing core group; for any processor group in the computing core group, determining the sum of the first target utilization of the processor group and the ratio as the second target utilization of the processor group.

[0187] In this example, the total number of processor groups included in the core group can be determined. For example, if a computing core group consists of four processor groups, the number of processor groups is four. The first difference can be divided by the number of processor groups to obtain a ratio. This ratio represents the average increase in utilization of each processor group required to bring the overall utilization to the lower utilization limit.

[0188] The ratio calculated above can be added to the first target utilization for each processor group. This means that the utilization of each processor group will be increased accordingly to share the additional utilization required by the first difference. After adding the ratio, the new target utilization for each processor group becomes the second target utilization. This second target utilization is the final target utilization adjusted to ensure that the overall utilization of the computing core group meets or exceeds the lower utilization limit.

[0189] For example, a computing core group consists of three processor groups with a utilization lower limit of 90%. The first target utilizations of the three processor groups are 30%, 30%, and 30%, respectively, totaling 90%, which exactly meets the lower limit. In this case, the first difference is 0, and no adjustment is required.

[0190] However, if the sum of the first target utilizations is 84%, which is below the lower limit of 90%, the first difference is 6%. Divide this difference by the number of processor groups, 3, to obtain a ratio of 2%. This 2% is then added to the first target utilization of each processor group to obtain the new second target utilizations of 32%, 32%, and 32%, totaling 96%, which exceeds the lower limit and meets the utilization requirement of the compute core group.

[0191] This example ensures fairness by evenly distributing the first difference to all processor groups, ensuring that each processor group bears the same additional utilization during the adjustment process. It can also quickly respond to and adjust to situations where overall utilization is insufficient, promptly improving the utilization of the computing core group and ensuring its normal operation and performance.

[0192] In another possible implementation, adjusting the utilization of each processor group according to the current temperature of each processor group includes: determining the dominant processor group in the computing core group according to the current temperature of each processor group; and for any non-dominant processor group in the computing core group, adjusting the utilization of the non-dominant processor group according to the difference between the current temperature of the non-dominant processor group and the current temperature of the dominant processor group.

[0193] In this implementation, one processor group can be selected as the dominant processor group based on the current temperature of each processor group. This implementation does not limit the selection criteria for the dominant processor group. For example, the processor group with the lowest current temperature can be selected as the dominant processor group. When heat dissipation conditions are limited or power consumption is high, the processor group with a lower temperature tends to run more stably. As the dominant processor group, it can ensure the stability of the entire computing core group. For another example, the processor group with a temperature closest to the preset operating temperature can be selected as the dominant processor group. The preset operating temperature can refer to the temperature corresponding to the target chip in the optimal working state. Selecting the processor group with a temperature closest to the preset operating temperature as the dominant one can better balance the relationship between performance and heat dissipation, so that other processor groups can follow suit and achieve overall performance optimization.

[0194] In this implementation, for any non-dominant processor group in the computing core group, the difference between its current temperature and the current temperature of the dominant processor group is calculated. This difference reflects the degree of temperature deviation of the non-dominant processor group relative to the dominant processor group. If the current temperature of the non-dominant processor group is higher than that of the dominant processor group, it means that it may be overheated and needs to reduce its utilization rate to reduce heat generation. For example, the utilization rate of the non-dominant processor group can be lowered by a certain proportion, and the specific proportion can be determined based on the size of the temperature difference and the heat dissipation requirements. If the current temperature of the non-dominant processor group is lower than that of the dominant processor group, if the heat dissipation conditions permit, the utilization rate can be appropriately increased to increase heat generation and narrow the temperature gap with the dominant processor group. For example, the utilization rate of the non-dominant processor group can be increased by a certain proportion, and the specific proportion is also determined based on the temperature difference and the heat dissipation capacity.

[0195] In this implementation, the temperature difference between the non-dominant and dominant processor groups is continuously calculated based on real-time temperature data, and the utilization of the non-dominant processor group is dynamically adjusted. This dynamic adjustment rapidly responds to temperature changes, continuously optimizing temperature distribution and performance, and ensuring safe and stable chip operation.

[0196] In this implementation, by adjusting the utilization of non-dominant processor groups to bring their temperatures closer to those of the dominant processor group, a balanced temperature distribution is achieved within the computing core group, preventing local overheating or overcooling and improving heat dissipation efficiency. Furthermore, while ensuring temperature safety, this implementation rationally adjusts the utilization of processor groups to ensure optimal operation, thereby meeting performance requirements while improving energy efficiency and achieving an optimal balance between performance and energy efficiency.

[0197] As an example of this implementation method, determining the dominant processor group in the computing core group based on the current temperatures of the respective processor groups in the computing core group includes: determining the processor group with the Nth lowest current temperature among the respective processor groups as the dominant processor group in the computing core group, where N is an integer greater than or equal to 1.

[0198] In this example, the collected current temperatures of each processor group can be sorted from low to high. In the sorted temperature list, the processor group with the Nth lowest current temperature can be selected as the dominant processor group. Here, N is an integer greater than or equal to 1, and the specific value can be set based on actual needs and policies.

[0199] If N is 1, the dominant processor group is the one with the lowest temperature. In this case, selecting the processor group with the best heat dissipation and the lowest temperature as the dominant processor group provides a conservative baseline for other processor groups, helping to avoid overheating risks.

[0200] If N is greater than 1, for example, N=2 or N=3, the dominant processor group is the second-lowest or third-lowest processor group. In this case, while the selected dominant processor group may not be the lowest temperature, it is still within the lower temperature range, balancing heat dissipation and performance. For example, in some application scenarios, it may be necessary to consider the overall performance of the processor groups or other factors and select a processor group with moderate temperature and good performance as the dominant one.

[0201] In this example, the process of selecting the dominant processor group is made more flexible by introducing the parameter N. The value of N can be adjusted according to different working conditions and requirements to select the dominant processor group that best suits the current scenario.

[0202] As an example of this implementation, adjusting the utilization of each processor group in the computing core group according to the current temperature of each processor group further includes: adjusting the utilization of the leading processor group to a preset maximum utilization.

[0203] In this example, the leading processor group is operating optimally. Maintaining high utilization of the leading processor group ensures that it maximizes its computing power within the compute core group. At the same time, the utilization of other processor groups is adjusted based on the temperature and utilization of the leading processor group, achieving temperature balance and optimized performance across the entire compute core group.

[0204] In one possible implementation, the method further includes: determining the length of a first adjustment cycle of the operating voltage and operating frequency of the computing core group based on the stabilization time of the temperature of each processor group in the computing core group; determining the length of a second adjustment cycle of the target power consumption of the computing core group based on the stabilization time of the operating voltage and operating frequency of the computing core group; determining the target power consumption of each computing core group in the target chip includes: determining the target power consumption of each computing core group in the target chip in response to entering a new second adjustment cycle; adjusting the operating voltage and operating frequency of the computing core group based on the target power consumption of the computing core group includes: adjusting the operating voltage and operating frequency of the computing core group based on the target power consumption of the computing core group in response to entering a new first adjustment cycle.

[0205] In this implementation, the temperature changes of each processor group in the computing core group can be monitored to determine the time required for its temperature to reach a stable state. The temperature stabilization time can refer to the time period during which the temperature fluctuation range of the processor group is small and tends to be constant under certain operating conditions. Based on the stabilization time of the processor group temperature, the length of the first adjustment cycle of the operating voltage and operating frequency of the computing core group can be set. The first adjustment cycle can represent the adjustment cycle of the operating voltage and operating frequency of the computing core group. That is, within the first adjustment cycle, the operating voltage and operating frequency of the computing core group are adjusted once. The length of the first adjustment cycle can be slightly longer than the stabilization time of the processor group temperature to improve the stability of the system.

[0206] In this implementation, the changes in the operating voltage and operating frequency of the computing core group can be monitored to determine the stabilization time of the operating voltage and operating frequency of the computing core group. The stabilization time of the operating voltage and operating frequency can refer to the time period in which the adjusted operating voltage and operating frequency remain stable within a certain period of time and no longer change significantly. According to the stabilization time of the operating voltage and operating frequency of the computing core group, the length of the second adjustment period of the target power consumption of the computing core group can be set. The second adjustment period can represent the adjustment period of the target power consumption of the computing core group. That is, within the second adjustment period, the target power consumption of the computing core group is adjusted once. The length of the second adjustment period can be slightly longer than the stabilization time of the operating voltage and operating frequency of the computing core group to improve the stability of the system.

[0207] In this implementation, when entering a new second adjustment cycle, the target power consumption of each computing core group can be re-determined based on the current operating state (e.g., temperature) and performance requirements. When entering a new first adjustment cycle, the operating voltage and operating frequency of the computing core group are adjusted based on the current target power consumption of the computing core group.

[0208] By adopting this implementation, the stability of each layer can be improved, and the complexity and uncertainty caused by adjusting parameters of multiple layers at the same time can be avoided.

[0209] The chip temperature control method provided by the embodiments of the present disclosure can be applied to technical fields such as sensors, temperature control, and heat dissipation, and is not limited here.

[0210] The following describes a specific application scenario to illustrate the chip temperature control method provided by the embodiment of the present disclosure. In this application scenario, the temperature of the target chip can be controlled at the chip level, the computing core group level, and the processor group level.

[0211] First, the chip level.

[0212] The current temperature of the target chip may be collected, and the total target power consumption of the target chip may be determined based on the difference between the preset temperature and the current temperature of the target chip.

[0213] In response to the total target power consumption of the target chip being less than or equal to the total required power consumption of each computing core group, the total target power consumption of the target chip can be evenly distributed to each computing core group to obtain the target power consumption of each computing core group. Alternatively, in response to the total target power consumption of the target chip being greater than the total required power consumption of each computing core group, corresponding power consumption can be allocated to each computing core group based on the required power consumption of each computing core group; the remaining power consumption of the target chip can be distributed to M computing core groups with the largest required power consumption among the computing core groups, where M is an integer greater than or equal to 1.

[0214] Second, calculate the core group level.

[0215] For any computing core group, the target power consumption of the computing core group and the current power consumption of the computing core group can be input into a first proportional-integral-derivative controller, and the target operating frequency of the computing core group can be output via the first proportional-integral-derivative controller. The target operating voltage of the computing core group can be determined based on the target operating frequency of the computing core group and the corresponding relationship between the operating voltage and the operating frequency. The operating voltage and operating frequency of the computing core group can be adjusted based on the target operating voltage and target operating frequency of the computing core group.

[0216] Third, processor group level.

[0217] For any computing core group, the average temperature of the computing core group may be determined according to the current temperature of each processor group in the computing core group.

[0218] For any processor group in the computing core group, a first target utilization of the processor group can be determined based on the difference between the current temperature of the processor group and the average temperature of the computing core group. The sum of the first target utilizations of the respective processor groups can be determined. In response to the sum of the first target utilizations being less than the lower limit of utilization of the computing core group, a first difference between the lower limit of utilization of the computing core group and the sum of the first target utilizations can be determined. The ratio of the first difference to the number of processor groups in the computing core group can be determined. For any processor group in the computing core group, the sum of the first target utilization of the processor group and the ratio can be determined as the second target utilization of the processor group, and the utilization of the processor group can be adjusted based on the second target utilization of the processor group.

[0219] It is understood that the above-mentioned various method embodiments mentioned in this disclosure can be combined with each other to form combined embodiments without violating the principle logic. Due to space limitations, this disclosure will not go into details. It is understood by those skilled in the art that in the above-mentioned methods of specific implementation, the specific execution order of each step should be determined by its function and possible internal logic.

[0220] In addition, the present disclosure also provides a temperature control device for a chip, an electronic device, a computer-readable storage medium, and a computer program product, all of which can be used to implement the temperature control method for any chip provided by the present disclosure. The corresponding technical solutions and technical effects can be found in the corresponding records in the method section and will not be repeated here.

[0221] Figure 2 FIG. 1 is a block diagram of a temperature control device for a chip according to an embodiment of the present disclosure. Figure 2 As shown, the temperature control device of the chip includes:

[0222] A first determining module 21 is configured to determine target power consumption of each computing core group in a target chip, wherein each computing core group includes at least one computing core, each computing core includes at least one processor group, and each processor group includes at least one processor;

[0223] A first adjustment module 22 is configured to adjust the operating voltage and operating frequency of any computing core group according to the target power consumption of the computing core group;

[0224] The second adjustment module 23 is configured to adjust the utilization rate of each processor group in any computing core group.

[0225] In a possible implementation, the second adjustment module 23 is configured to:

[0226] Collecting the current temperature of each processor group in the computing core group;

[0227] The utilization rate of each processor group is adjusted according to the current temperature of each processor group.

[0228] In a possible implementation, the second adjustment module 23 is configured to:

[0229] determining a temperature average of the computing core group based on the current temperature of each processor group;

[0230] For any processor group in the computing core group, determining a first target utilization rate of the processor group according to a difference between a current temperature of the processor group and an average temperature of the computing core group;

[0231] The utilization of each processor group is adjusted according to the first target utilization of each processor group.

[0232] In a possible implementation, the second adjustment module 23 is configured to:

[0233] determining a sum of first target utilizations of the respective processor groups;

[0234] In response to the sum of the first target utilizations being less than the lower utilization limit of the computing core group, determining a first difference between the lower utilization limit of the computing core group and the sum of the first target utilizations;

[0235] For any processor group in the computing core group, increasing the first target utilization of the processor group according to the first difference to obtain a second target utilization of the processor group;

[0236] The utilization of the processor group is adjusted according to the second target utilization of the processor group.

[0237] In a possible implementation, the second adjustment module 23 is configured to:

[0238] determining a ratio of the first difference to the number of processor groups in the computing core group;

[0239] For any processor group in the computing core group, the sum of the first target utilization of the processor group and the ratio is determined as the second target utilization of the processor group.

[0240] In a possible implementation, the second adjustment module 23 is configured to:

[0241] determining a leading processor group in the computing core group according to current temperatures of the respective processor groups;

[0242] For any non-dominant processor group in the computing core group, the utilization rate of the non-dominant processor group is adjusted according to the difference between the current temperature of the non-dominant processor group and the current temperature of the dominant processor group.

[0243] In a possible implementation, the second adjustment module 23 is configured to:

[0244] A processor group with the Nth lowest current temperature among the processor groups is determined as a leading processor group in the computing core group, where N is an integer greater than or equal to 1.

[0245] In a possible implementation, the second adjustment module 23 is configured to:

[0246] The utilization rate of the leading processor group is adjusted to a preset maximum utilization rate.

[0247] In a possible implementation, the second adjustment module 23 is configured to:

[0248] Obtaining current application scenario information of the target chip;

[0249] Obtaining a preset utilization rate corresponding to the current application scenario information;

[0250] According to the preset utilization rate, the utilization rate of each processor group in the computing core group is adjusted.

[0251] In one possible implementation,

[0252] The apparatus further includes: a second determining module configured to determine the length of a first adjustment period of the operating voltage and operating frequency of the computing core group based on the stabilization time of the temperature of each processor group in the computing core group; and determine the length of a second adjustment period of the target power consumption of the computing core group based on the stabilization time of the operating voltage and operating frequency of the computing core group;

[0253] The first determining module 21 is configured to: determine the target power consumption of each computing core group in the target chip in response to entering a new second adjustment cycle;

[0254] The first adjustment module 22 is configured to adjust the operating voltage and operating frequency of the computing core group according to the target power consumption of the computing core group in response to entering a new first adjustment cycle.

[0255] In a possible implementation, the first determining module 21 is configured to:

[0256] Determining a total target power consumption of the target chip;

[0257] Determining the required power consumption of each computing core group in the target chip;

[0258] The target power consumption of each computing core group is determined according to the total target power consumption and the required power consumption of each computing core group.

[0259] In a possible implementation, the first determining module 21 is configured to:

[0260] In response to the total target power consumption of the target chip being less than or equal to the total required power consumption of each computing core group, the total target power consumption of the target chip is evenly distributed to each computing core group to obtain the target power consumption of each computing core group;

[0261] or,

[0262] In response to the total target power consumption of the target chip being greater than the total required power consumption of the respective computing core groups, corresponding power consumption is allocated to the respective computing core groups according to the required power consumption of the respective computing core groups; and the remaining power consumption of the target chip is allocated to the M computing core groups with the largest required power consumption among the respective computing core groups, where M is an integer greater than or equal to 1.

[0263] In a possible implementation, the first adjustment module 22 is configured to:

[0264] Inputting the target power consumption of the computing core group and the current power consumption of the computing core group into a first proportional-integral-derivative controller, and outputting the target operating frequency of the computing core group via the first proportional-integral-derivative controller;

[0265] Determining a target operating voltage of the computing core group according to the target operating frequency of the computing core group and a correspondence between the operating voltage and the operating frequency;

[0266] The operating voltage and the operating frequency of the computing core group are adjusted according to the target operating voltage and the target operating frequency of the computing core group.

[0267] In a possible implementation, the target chip includes any one of the following:

[0268] Graphics processor, central processing unit, field programmable gate array, digital signal processor.

[0269] In some embodiments, the functions or modules included in the device provided by the embodiments of the present disclosure can be used to execute the method described in the above method embodiments. Its specific implementation and technical effects can refer to the description of the above method embodiments. For the sake of brevity, they will not be repeated here.

[0270] The present disclosure also provides a computer-readable storage medium having computer program instructions stored thereon, wherein the computer program instructions, when executed by a processor, implement the above method. The computer-readable storage medium may be a non-volatile computer-readable storage medium or a volatile computer-readable storage medium.

[0271] The embodiment of the present disclosure further provides a computer program, comprising a computer-readable code. When the computer-readable code is executed in an electronic device, a processor in the electronic device executes the above method.

[0272] An embodiment of the present disclosure further provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in an electronic device, a processor in the electronic device executes the above method.

[0273] An embodiment of the present disclosure also provides an electronic device, comprising: one or more processors; a memory for storing executable instructions; wherein the one or more processors are configured to call the executable instructions stored in the memory to execute the above method.

[0274] The electronic device may be provided as a terminal, a server, or other forms of devices.

[0275] Figure 3 FIG1 shows a block diagram of an electronic device 1900 provided by an embodiment of the present disclosure. For example, the electronic device 1900 can be provided as a server or a terminal. Figure 3 The electronic device 1900 includes a processing component 1922, which further includes one or more processors, and a memory resource represented by a memory 1932 for storing instructions executable by the processing component 1922, such as an application. The application stored in the memory 1932 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute the instructions to perform the above-described method.

[0276] The electronic device 1900 may further include a power supply component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input / output interface 1958 (I / O interface). The electronic device 1900 may operate based on an operating system stored in the memory 1932, such as a Microsoft Server operating system (Windows Server 2003). TM ), a graphical user interface operating system launched by Apple (MacOS X TM ), a multi-user, multi-process computer operating system (Unix TM), a free and open source Unix-like operating system (Linux TM ), an open-source Unix-like operating system (FreeBSD TM ) or similar.

[0277] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions that can be executed by the processing component 1922 of the electronic device 1900 to perform the above method.

[0278] The present disclosure may be a system, method and / or computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present disclosure.

[0279] A computer-readable storage medium can be a tangible device that can hold and store instructions for use by an instruction execution device. A computer-readable storage medium can be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or a raised structure in a groove on which instructions are stored, and any suitable combination thereof. As used herein, a computer-readable storage medium is not to be construed as a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse through a fiber optic cable), or an electrical signal transmitted through an electrical wire.

[0280] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in the computer-readable storage medium in each computing / processing device.

[0281] The computer program instructions for performing the operations of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, and conventional procedural programming languages ​​such as "C" language or similar programming languages. Computer-readable program instructions may be executed entirely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., utilizing an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be personalized by utilizing the state information of the computer-readable program instructions. The electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present disclosure.

[0282] Various aspects of the present disclosure are described herein with reference to flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present disclosure. It should be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0283] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device is generated that implements the functions / actions specified in one or more blocks in the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, where these instructions cause the computer, programmable data processing device, and / or other device to operate in a specific manner. Thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing various aspects of the functions / actions specified in one or more blocks in the flowchart and / or block diagram.

[0284] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operational steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more blocks in the flowchart and / or block diagram.

[0285] The flow charts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the systems, methods and computer program products according to multiple embodiments of the present disclosure. In this regard, each box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and the part of the module, program segment or instruction contains one or more executable instructions for realizing the prescribed logical function. In some alternative implementations, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs the prescribed function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0286] The computer program product may be implemented in hardware, software, or a combination thereof. In one embodiment, the computer program product is implemented as a computer storage medium. In another embodiment, the computer program product is implemented as a software product, such as a software development kit (SDK).

[0287] The above description of the various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced with each other and will not be repeated herein for the sake of brevity.

[0288] If the technical solutions of the embodiments of the present disclosure involve personal information, the products applying the technical solutions of the embodiments of the present disclosure have clearly informed the personal information processing rules and obtained the individual's voluntary consent before processing the personal information. If the technical solutions of the embodiments of the present disclosure involve sensitive personal information, the products applying the technical solutions of the embodiments of the present disclosure have obtained the individual's separate consent before processing the sensitive personal information, and at the same time meet the "explicit consent" requirement. For example, on personal information collection devices such as cameras, clear and prominent signs are set to inform that the personal information collection scope has been entered and personal information will be collected. If the individual voluntarily enters the collection scope, it is deemed that they agree to the collection of their personal information; or on the personal information processing device, when the personal information processing rules are notified by obvious signs / information, the individual's authorization is obtained through pop-up information or by asking the individual to upload their personal information. The personal information processing rules may include information such as the personal information processor, the purpose of personal information processing, the processing method, and the type of personal information processed.

[0289] While various embodiments of the present disclosure have been described above, the above descriptions are illustrative, non-exhaustive, and not intended to be limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or improvements to existing technologies, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A chip temperature control method, characterized in that: include: Determining target power consumption for each computing core group in the target chip, wherein any computing core group includes at least one computing core, any computing core includes at least one processor group, and any processor group includes at least one processor; For any computing core group, adjusting the operating voltage and operating frequency of the computing core group according to the target power consumption of the computing core group; For any computing core group, the utilization rate of each processor group in the computing core group is adjusted.

2. The method according to claim 1, characterized in that The adjusting the utilization of each processor group in the computing core group includes: Collecting the current temperature of each processor group in the computing core group; The utilization rate of each processor group is adjusted according to the current temperature of each processor group.

3. The method according to claim 2, characterized in that The adjusting the utilization rate of each processor group according to the current temperature of each processor group includes: determining a temperature average of the computing core group based on the current temperature of each processor group; For any processor group in the computing core group, determining a first target utilization rate of the processor group according to a difference between a current temperature of the processor group and an average temperature of the computing core group; The utilization of each processor group is adjusted according to the first target utilization of each processor group.

4. The method according to claim 3, characterized in that The adjusting the utilization of each processor group according to the first target utilization of each processor group includes: determining a sum of first target utilizations of the respective processor groups; In response to the sum of the first target utilizations being less than the lower utilization limit of the computing core group, determining a first difference between the lower utilization limit of the computing core group and the sum of the first target utilizations; For any processor group in the computing core group, increasing the first target utilization of the processor group according to the first difference to obtain a second target utilization of the processor group; The utilization of the processor group is adjusted according to the second target utilization of the processor group.

5. The method according to claim 4, characterized in that The step of increasing the first target utilization of the processor group according to the first difference to obtain the second target utilization of the processor group includes: determining a ratio of the first difference to the number of processor groups in the computing core group; For any processor group in the computing core group, the sum of the first target utilization of the processor group and the ratio is determined as the second target utilization of the processor group.

6. The method according to claim 2, characterized in that The adjusting the utilization rate of each processor group according to the current temperature of each processor group includes: determining a leading processor group in the computing core group according to current temperatures of the respective processor groups; For any non-dominant processor group in the computing core group, the utilization rate of the non-dominant processor group is adjusted according to the difference between the current temperature of the non-dominant processor group and the current temperature of the dominant processor group.

7. The method according to claim 6, characterized in that Determining the leading processor group in the computing core group according to the current temperature of each processor group in the computing core group includes: A processor group with the Nth lowest current temperature among the processor groups is determined as a leading processor group in the computing core group, where N is an integer greater than or equal to 1.

8. The method according to claim 6, characterized in that The adjusting the utilization of each processor group according to the current temperature of each processor group in the computing core group further includes: The utilization rate of the leading processor group is adjusted to a preset maximum utilization rate.

9. The method according to claim 1, characterized in that The adjusting the utilization of each processor group in the computing core group includes: Obtaining current application scenario information of the target chip; Obtaining a preset utilization rate corresponding to the current application scenario information; According to the preset utilization rate, the utilization rate of each processor group in the computing core group is adjusted.

10. The method according to claim 1, characterized in that The method further includes: determining the length of a first adjustment period of the operating voltage and operating frequency of the computing core group based on the stabilization time of the temperature of each processor group in the computing core group; determining the length of a second adjustment period of the target power consumption of the computing core group based on the stabilization time of the operating voltage and operating frequency of the computing core group; The determining the target power consumption of each computing core group in the target chip includes: in response to entering a new second adjustment cycle, determining the target power consumption of each computing core group in the target chip; Adjusting the operating voltage and operating frequency of the computing core group according to the target power consumption of the computing core group includes: in response to entering a new first adjustment cycle, adjusting the operating voltage and operating frequency of the computing core group according to the target power consumption of the computing core group.

11. The method according to any one of claims 1 to 10, characterized in that Determining the target power consumption of each computing core group in the target chip includes: Determining a total target power consumption of the target chip; Determining the required power consumption of each computing core group in the target chip; The target power consumption of each computing core group is determined according to the total target power consumption and the required power consumption of each computing core group.

12. The method according to claim 11, characterized in that The determining, based on the total target power consumption and the required power consumption of each computing core group, the target power consumption of each computing core group includes: In response to the total target power consumption of the target chip being less than or equal to the total required power consumption of each computing core group, the total target power consumption of the target chip is evenly distributed to each computing core group to obtain the target power consumption of each computing core group; or, In response to the total target power consumption of the target chip being greater than the total required power consumption of the respective computing core groups, corresponding power consumption is allocated to the respective computing core groups according to the required power consumption of the respective computing core groups; and the remaining power consumption of the target chip is allocated to the M computing core groups with the largest required power consumption among the respective computing core groups, where M is an integer greater than or equal to 1.

13. The method according to any one of claims 1 to 10, characterized in that The adjusting the operating voltage and operating frequency of the computing core group according to the target power consumption of the computing core group includes: Inputting the target power consumption of the computing core group and the current power consumption of the computing core group into a first proportional-integral-derivative controller, and outputting the target operating frequency of the computing core group via the first proportional-integral-derivative controller; Determining a target operating voltage of the computing core group according to the target operating frequency of the computing core group and a correspondence between the operating voltage and the operating frequency; The operating voltage and the operating frequency of the computing core group are adjusted according to the target operating voltage and the target operating frequency of the computing core group.

14. The method according to any one of claims 1 to 10, characterized in that The target chip includes any one of the following: Graphics processor, central processing unit, field programmable gate array, digital signal processor.

15. A temperature control device for a chip, characterized in that: include: A first determining module is configured to determine target power consumption of each computing core group in the target chip, wherein any computing core group includes at least one computing core, any computing core includes at least one processor group, and any processor group includes at least one processor; A first adjustment module is configured to adjust, for any computing core group, an operating voltage and an operating frequency of the computing core group according to a target power consumption of the computing core group; The second adjustment module is used to adjust the utilization rate of each processor group in any computing core group.

16. An electronic device, characterized in that: include: one or more processors; a memory for storing executable instructions; The one or more processors are configured to call the executable instructions stored in the memory to execute the method according to any one of claims 1 to 14.

17. A computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method according to any one of claims 1 to 14 is implemented.

18. A computer program product comprising computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, characterized in that: When the computer-readable code is executed in an electronic device, a processor in the electronic device executes the method according to any one of claims 1 to 14.

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