A high-speed interconnection interface system

Abstract

The present invention relates to the field of chip design technology, and in particular to a high-speed interconnection interface system, which includes an on-chip interface relay module supporting bidirectional data transmission, an interconnection protocol conversion module and a physical layer processing module, wherein the on-chip interface relay module is configured to receive instructions and generate transaction signals that comply with the on-chip interface protocol specification; the interconnection protocol conversion module is configured to receive the transaction signal and obtain user-defined information, insert the user-defined information into the user field of the transaction signal and encapsulate it into a data frame that complies with the custom transmission protocol specification of the physical layer processing module; wherein the user-defined information carries the address field of the physical transmission channel; the physical layer processing module includes N independent physical transmission channels, wherein N≥1; each physical transmission channel includes a transmitting end, and the transmitting end is configured to receive a data frame, process it, and then transmit it, thereby achieving the purpose of supporting N physical transmission channels and custom transmission protocols.

Description

Technical Field

[0001] The present invention relates to the technical field of chip design, and in particular to a high-speed interconnection interface system. Background Art

[0002] The rapid development of artificial intelligence (AI), particularly large language models (LLMs) and generative AI, has placed unprecedented demands on computing chips. From AlexNet's 60 million parameters to GPT-4's 1.8 trillion parameters, the number of model parameters has increased nearly 300,000-fold, and the amount of computation required has skyrocketed. A single GPU chip cannot meet this demand, necessitating interconnected GPUs to form clusters to improve overall performance. GPU interconnect technology enables collaborative training across multiple GPUs, achieving a combined computing power and storage capability. Therefore, GPU interconnect technology is crucial for pushing the boundaries of computing power and optimizing resource utilization.

[0003] The limited bandwidth of traditional high-speed interfaces creates bandwidth and latency bottlenecks in cluster interconnects, impacting cluster performance. Take PCIe (Peripheral Component Interconnect Express) as an example. PCIe is a high-speed serial computer expansion bus standard that has become one of the most important interface standards since its introduction. PCIe 5.0 achieves a single-lane bandwidth of 4 GB / s, and PCIe 6.0 increases this to 8 GB / s. Through continuous evolution, PCIe has established a standard, universal protocol stack with a mature ecosystem and good compatibility. It supports scalable bandwidth, achieving linear bandwidth growth through multi-lane configurations. Furthermore, with continuous evolution, each generation's bandwidth nearly doubles that of the previous one. After nearly 20 years of development, the PCIe interface has become an indispensable high-speed interconnect standard in modern computing systems. Its continuous bandwidth increases and feature enhancements enable it to meet the fundamental requirements of chip computing.

[0004] But there are two problems:

[0005] First, bandwidth has an upper limit, which limits the performance of GPU interconnection and thus affects the efficiency of cluster interconnection. Taking PCIe 5.0 as an example, the actual maximum number of used lanes is 16, and the theoretical maximum bandwidth is 64GB / s. This is difficult to meet the performance requirements of inter-GPU interconnection bandwidth.

[0006] Second, it lacks flexible support for custom protocols and lacks functional scalability. PCIe requires compatibility with all versions, namely 1.0 and 6.0, which complicates compatibility management and makes it difficult to flexibly support custom protocols. GPU chip interconnect clusters often require specific read and write transfer capabilities.

[0007] Therefore, there is an urgent need for a high-speed interconnect interface that supports extended bandwidth and custom protocols. Summary of the Invention

[0008] In order to solve the above technical problems, the present invention adopts a technical solution: a high-speed interconnection interface system, the system comprising:

[0009] The on-chip interface relay module is configured to: receive instructions and generate transaction signals that comply with the on-chip interface protocol specification, and transmit the transaction signals to the interconnection protocol conversion module.

[0010] The interconnection protocol conversion module is connected to the on-chip interface relay module and is configured to: receive the transaction signal of the on-chip interface relay module and obtain user-defined information, insert the user-defined information into the user field of the transaction signal and encapsulate it into a data frame that complies with the custom transmission protocol specification of the physical layer processing module, and transmit the data frame to the physical layer processing module; wherein the information carried by the user-defined information includes a custom read / write type and an address field segment of the physical transmission channel.

[0011] A physical layer processing module is connected to the interconnection protocol conversion module and includes N independent physical transmission channels, where N≥1; each physical transmission channel includes a transmitting end, and the transmitting end is configured to receive the data frame of the interconnection protocol conversion module and send it after processing.

[0012] Among them, each module interacts through a bidirectional data channel.

[0013] The present invention has at least the following beneficial effects:

[0014] The present invention provides a high-speed interconnect interface system. The system's physical layer processing module includes N physical transmission channels. By inserting user-defined information carrying the address fields of the physical transmission channels into the user field of transaction signals that comply with the on-chip interface protocol specification, the system supports N physical transmission channels. This significantly increases interconnect bandwidth and significantly improves the interconnect performance between GPU chips, achieving overall performance stacking for GPU chip clusters. The interconnect protocol conversion module supports bidirectional mapping between the on-chip interface protocol and the custom transmission protocol, achieving flexible support for custom transmission protocols. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0016] Figure 1 A flow chart of a high-speed interconnect interface system provided by an embodiment of the present invention;

[0017] Figure 2 A schematic structural diagram of an on-chip interface relay module provided in an embodiment of the present invention;

[0018] Figure 3 A schematic diagram of the structure of an interconnection protocol conversion module provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0019] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0020] Unless otherwise defined, all technical and scientific terms used in the embodiments of the present invention have the same meanings as commonly understood by those skilled in the art.

[0021] See also Figure 1 , which shows a high-speed interconnection interface system, the system includes: an on-chip interface relay module, an interconnection protocol conversion module and a physical layer processing module, and the modules interact with each other through a bidirectional data channel.

[0022] Furthermore, the on-chip interface relay module is configured to: receive instructions and generate transaction signals that comply with on-chip interface protocol specifications, and transmit the transaction signals to the interconnection protocol conversion module.

[0023] Among them, the on-chip interface relay module is the communication interface between the current high-speed chip interface system and the internal modules of the chip. It is responsible for processing the instructions sent from the current chip to the external chip and arbitrating the instructions.

[0024] In one embodiment, the instruction is a read instruction or a write instruction. Other types of instructions also fall within the protection scope of the present invention.

[0025] The instructions input to the read instruction module and the write instruction module are on-chip modules or user configurations.

[0026] In one embodiment, see Figure 2The on-chip interface relay module includes a read instruction module, a write instruction module, and an arbiter; wherein the output ends of the read instruction module and the write instruction module are respectively connected to the input channels of the arbiter, and when the instructions input to the read instruction module and the write instruction module are on-chip modules, the input ends of the read instruction module and the write instruction module are respectively connected to the system bus that complies with the on-chip interface protocol specification as slave devices.

[0027] In one embodiment, if the on-chip module of the current chip sends a read instruction to an external chip, the on-chip interface relay module encapsulates the read instruction into a read transaction signal that complies with the on-chip interface protocol specification and sends it to the arbitrator for arbitration; when the on-chip interface relay module receives the transaction response signal returned from the external chip, it returns the transaction response signal to the on-chip module.

[0028] In one embodiment, if the on-chip module of the current chip issues a write instruction to an external chip, the on-chip interface relay module encapsulates the write instruction into a write transaction signal that complies with the on-chip interface protocol specification and sends it to the arbitrator for arbitration.

[0029] In one embodiment, the on-chip interface protocol is AXI (Advanced eXtensible Interface), AHB (Advanced High-performance Bus), or HB (Hybrid Bus), etc. Other types of on-chip interface protocols also fall within the scope of protection of the present invention.

[0030] In one embodiment, see Figure 2 When the instructions input to the read instruction module and the write instruction module are user-configured, the on-chip interface relay module further includes a register access path control module. The input terminals of the read instruction module and the write instruction module are respectively connected to the output terminal of the register access path control module. The register access path control module is configured to receive and store the operation parameters entered by the user and, based on these operation parameters, generate instructions that comply with the on-chip interface protocol specification. It should be noted that users can flexibly configure the parameters of read and write operations according to specific application requirements, achieving highly customized data access.

[0031] Furthermore, the interconnection protocol conversion module is connected to the on-chip interface relay module and is configured to: receive the transaction signal of the on-chip interface relay module, and obtain user-defined information, insert the user-defined information into the user field of the transaction signal and encapsulate it into a data frame that complies with the custom transmission protocol specification of the physical layer processing module, and transmit the data frame to the physical layer processing module; wherein the information carried by the user-defined information includes the custom read and write type and the address field segment of the physical transmission channel.

[0032] The user field is one or more signal fields reserved for user-defined purposes within the on-chip interface protocol. The contents of the user field do not affect the basic transmission behavior of the protocol, but can be used to carry additional control information and routing parameters related to read and write operations. In this embodiment of the present invention, the user field is used to carry address field information of the physical transmission channel.

[0033] The user-defined information may also include other types of fields, and user-defined information including other types of fields also falls within the protection scope of the present invention. The read-write type includes a read operation type and a write operation type.

[0034] In one embodiment, the user field includes but is not limited to the awuser and aruser fields in the AXI protocol and the HUSER field in the AHB protocol. Extension fields with similar functions in other protocols also fall within the scope of protection of the present invention.

[0035] The physical transmission channel address field serves as a chip select signal, selecting the target physical transmission channel for data transmission based on the address field's contents. Specifically, the address field is a binary-coded field used to select between multiple physical transmission channels. The bit width of the address field is determined by the number of modules, with an n-bit field representing up to 2ⁿ different modules. For example, a 4-bit field can represent 16 physical transmission channels, and a 5-bit field can represent 32 physical transmission channels.

[0036] It should be noted that the interconnection protocol conversion module supports bidirectional data transmission.

[0037] In one embodiment, the interconnection protocol conversion module is further configured to: receive a bit stream including a data frame from the physical layer processing module, and perform parsing and domain mapping operations on the data frame, generate a transaction response signal that complies with the on-chip interface protocol specification, and transmit the transaction response signal to the on-chip interface relay module; wherein the domain mapping operation includes extracting user field information from the parsed payload, and mapping it into user-defined information based on the user field information.

[0038] It's important to note that data frames are transmitted from the physical layer to the system as bit streams. After parsing and verification, the useful portion of the data frame is extracted as the payload. The payload includes both data and control information. Control information includes the destination address, data length, and user-defined information.

[0039] In the uplink direction from the physical layer to the interconnection protocol conversion module, it is necessary to parse and map the data frames.

[0040] In one embodiment, see Figure 3 The interconnection protocol conversion module includes a link processing submodule, and the link processing submodule includes a protocol bridge and a communication processing module group, wherein: the communication processing module group is configured to parse the data frame in the bit stream sent by the physical layer processing module to obtain a payload; the protocol bridge is configured to receive the payload and preprocess the payload, and the preprocessing includes mapping the control information in the payload into control information that complies with the on-chip interface protocol specification.

[0041] The protocol bridge is used to implement bidirectional mapping between the control information in the on-chip interface protocol specification for on-chip transmission and the control information in the custom transmission protocol specification of the physical layer processing module, thereby supporting the custom transmission protocol specification of the custom physical layer processing module.

[0042] In the uplink direction, the communication processing module group parses the received data frames into payloads and sends them to the protocol bridge, which maps the payloads into a data format that conforms to the on-chip interface protocol specifications. In the downlink direction, the protocol bridge first maps the transaction signals into a basic data format that conforms to the physical layer processing module's custom transmission protocol specifications, and then the communication processing module group encapsulates them into a data frame format that conforms to the physical layer transmission specifications.

[0043] In one embodiment, see Figure 3 The interconnection protocol conversion module also includes a protocol conversion submodule, and the protocol conversion submodule includes a mapping submodule, wherein: the mapping submodule is configured to perform domain segment mapping operations on the user field and data part in the preprocessed payload respectively, and combine the control information to obtain a transaction response signal that complies with the on-chip interface protocol specification.

[0044] It should be noted that the mapping of the data part and the user field part is completed through the mapping submodule, and the mapping of the control information is completed through the protocol bridge. After all the mappings are completed, a transaction response signal is obtained.

[0045] In the downlink direction from the on-chip interface relay module to the interconnection protocol conversion module, the transaction signal needs to be processed and encapsulated into a data frame.

[0046] In one embodiment, see Figure 3 The interconnection protocol conversion module includes a protocol conversion sublayer, and the protocol conversion submodule also includes a user information insertion submodule, wherein: the user information insertion submodule is configured to insert the user-defined information into the user field of the transaction signal to obtain an updated transaction signal.

[0047] In one embodiment, the user-defined information carries the address field of the physical transmission channel, and the user-defined signal carrying other information inserted in the user field also falls within the protection scope of the present invention.

[0048] In one embodiment, the user field includes multiple preset fields, and each preset field is inserted to carry different types of user-defined information.

[0049] In one embodiment, the interconnection protocol conversion module also includes a link processing submodule, and the link processing submodule includes a protocol bridge and a communication processing module group, wherein: the protocol bridge is also configured to receive the updated transaction signal output by the user information insertion submodule, and perform reverse preprocessing on the transaction signal, and the reverse preprocessing includes mapping the control information in the transaction signal into control information that complies with the custom transmission protocol specification of the physical layer processing module; the communication processing module group is also configured to generate a data frame based on the transaction signal and its control information.

[0050] The upstream and downstream directions share the same protocol bridge and the same communication processing module group. The corresponding definitions have been described in detail in the upstream direction and will not be repeated here.

[0051] In one embodiment, the communication processing module group includes a communication physical layer, a data link layer, and a transaction layer. The transaction layer is responsible for encapsulating data information from the protocol bridge into data frames that conform to the transmission protocol of the physical layer processing module or parsing data frames from the physical layer processing module into payloads, while also handling certain types of events. The data link layer is an intermediate layer in the stack, acting as an intermediate state between the transaction layer and the physical layer. Its primary responsibilities include link management and data integrity, including error detection and correction. The communication physical layer is used to transmit received data to the physical layer processing module or the data link layer.

[0052] Furthermore, the physical layer processing module is connected to the interconnection protocol conversion module, and includes N independent physical transmission channels, where N≥1; each physical transmission channel includes a transmitting end, and the transmitting end is configured to: receive the data frame of the interconnection protocol conversion module and send it after processing.

[0053] In one embodiment, N is equal to 1, 2, 4, 8, 16, 17, 18, 19, 20, 32, 64, etc. Other values ​​of N also fall within the scope of protection of the present invention. In one embodiment, the value of N is greater than 16.

[0054] Among them, each independent physical transmission channel is a bidirectional transmission channel, including a transmitting end and a receiving end.

[0055] In one embodiment, each physical transmission channel in the physical layer processing module further includes a receiving end, which is configured to receive an external input signal, process the external input signal to generate a bit stream, and transmit the bit stream to the interconnection protocol conversion module.

[0056] In one embodiment, the receiving end is used to convert a received differential serial level signal into a digital signal, and the transmitting end is used to convert a digital signal to be transmitted into a differential serial level signal.

[0057] Among them, the coordination of the address domain of the physical transmission channel and the N independent physical transmission channels in the physical layer processing module enables the interface system provided by the present invention to support more physical transmission channels, no longer limited to 16 channels, and can simultaneously support N independent physical transmission channels, thereby improving the maximum bandwidth of the system.

[0058] In one embodiment, the physical layer processing module further includes an encoding module and a decoding module. The encoding module is configured to encode the data frames of the interconnection protocol conversion module into a data stream. The decoding module is configured to decode the original bit stream received by the receiving end into a bit stream. The encoding module supports advanced encoding formats, including but not limited to 64 / 66B and 128 / 130B. The decoding module flexibly supports advanced encoding formats, including but not limited to 64 / 66B and 128 / 130B.

[0059] In one embodiment, the on-chip interface relay module is further configured to receive a transaction response signal from the interconnection protocol conversion module.

[0060] In one embodiment, the system also includes: an interconnection clock management module, which is connected to the physical layer processing module, the interconnection protocol conversion module and the on-chip interface relay module respectively, and is configured to: provide a physical clock for the physical layer processing module, provide a protocol clock for the interconnection protocol conversion module, and provide an interface clock for the on-chip interface relay module.

[0061] In summary, the present invention provides a high-speed interconnect interface system. The system's physical layer processing module includes N physical transmission channels. By inserting user-defined information carrying the address fields of the physical transmission channels into the user field of a transaction signal that complies with the on-chip interface protocol specification, the system supports N physical transmission channels. This significantly increases interconnect bandwidth and interconnect performance between GPU chips, achieving overall performance stacking for GPU chip clusters. The interconnect protocol conversion module supports bidirectional mapping between the on-chip interface protocol and the custom transmission protocol, achieving flexible support for custom transmission protocols.

[0062] Those skilled in the art will clearly understand that for the sake of convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be distributed to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0063] Although some specific embodiments of the present invention have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A high-speed interconnect interface system, characterized in that: The system comprises: The on-chip interface relay module is configured to: receive instructions and generate transaction signals that comply with the on-chip interface protocol specification, and transmit the transaction signals to the interconnection protocol conversion module; an interconnection protocol conversion module connected to the on-chip interface relay module and configured to: receive a transaction signal from the on-chip interface relay module, obtain user-defined information, insert the user-defined information into a user field of the transaction signal, encapsulate the information into a data frame that complies with a custom transmission protocol specification of a physical layer processing module, and transmit the data frame to the physical layer processing module; wherein the user-defined information carries information including a custom read / write type and an address field of a physical transmission channel; A physical layer processing module, connected to the interconnection protocol conversion module, including N independent physical transmission channels, where N ≥ 1; each physical transmission channel includes a transmitting end, and the transmitting end is configured to receive data frames from the interconnection protocol conversion module and transmit them after processing; Among them, each module interacts through a bidirectional data channel.

2. The system according to claim 1, wherein: Each physical transmission channel in the physical layer processing module further includes a receiving end, which is configured to receive an external input signal, generate a bit stream after processing the external input signal, and transmit the bit stream to the interconnection protocol conversion module.

3. The system according to claim 1, wherein: The interconnection protocol conversion module is further configured to: receive a bit stream including a data frame from the physical layer processing module, perform parsing and domain segment mapping operations on the data frame, generate a transaction response signal that complies with the on-chip interface protocol specification, and transmit the transaction response signal to the on-chip interface relay module; wherein the domain segment mapping operation includes extracting user field information from the parsed payload and mapping the user field information to the user-defined information.

4. The system according to claim 3, characterized in that The interconnection protocol conversion module further includes a link processing submodule, which includes a protocol bridge and a communication processing module group, wherein: The communication processing module group is configured to parse the data frame in the bit stream sent by the physical layer processing module to obtain a payload; The protocol bridge is configured to receive the payload and pre-process the payload, wherein the pre-processing includes mapping control information in the payload into control information that complies with an intra-chip interface protocol specification.

5. The system according to claim 4, characterized in that The interconnection protocol conversion module includes a protocol conversion submodule, and the protocol conversion submodule includes a mapping submodule, wherein: The mapping submodule is configured to perform field segment mapping operations on the user field and the data part in the pre-processed payload respectively, and obtain a transaction response signal that complies with the on-chip interface protocol specification in combination with the control information.

6. The system according to claim 3, wherein: The interconnection protocol conversion module includes a protocol conversion submodule, and the protocol conversion submodule also includes a user information insertion submodule, wherein: The user information insertion submodule is configured to insert the user-defined information into the user field of the transaction signal to obtain an updated transaction signal.

7. The system according to claim 6, characterized in that The interconnection protocol conversion module further includes a link processing submodule, which includes a protocol bridge and a communication processing module group, wherein: The protocol bridge is further configured to receive the updated transaction signal output by the user information insertion submodule and perform reverse preprocessing on the transaction signal, wherein the reverse preprocessing includes mapping the control information in the transaction signal into control information that complies with the custom transmission protocol specification of the physical layer processing module; The communication processing module group is further configured to generate a data frame according to the transaction signal and its control information.

8. The system according to claim 1, wherein: The on-chip interface relay module is further configured to receive a transaction response signal from the interconnection protocol conversion module.

9. The system according to claim 1, wherein: The on-chip interface relay module includes a read instruction module, a write instruction module, and an arbitrator; wherein the output ends of the read instruction module and the write instruction module are respectively connected to the input channels of the arbitrator; when the instructions input to the read instruction module and the write instruction module are on-chip modules, the input ends of the read instruction module and the write instruction module are respectively connected as slave devices to the system bus that complies with the on-chip interface protocol specification.

10. The system according to claim 9, characterized in that When the instructions input into the read instruction module and the write instruction module are configured by the user, the on-chip interface relay module also includes a register access path control module, and the input ends of the read instruction module and the write instruction module are respectively connected to the output end of the register access path control module. The register access path control module is used to receive and store the operation parameters written by the user, and generate instructions that comply with the on-chip interface protocol specifications based on the operation parameters.

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