Word line driving circuit, memory and equipment

Abstract

The invention discloses a word line driving circuit, a memory and equipment, relates to the technical field of electronics, and is used for reducing the size of an SWD and reducing the load of word line driving. The word line driving circuit includes: a first word line; a first sub-word line and a second sub-word line; the first SWD comprises a first transistor and a second transistor; the second SWD comprises a third transistor and a fourth transistor; the two SWDs also share a fifth transistor; grid electrodes of the first transistor, the third transistor and the fifth transistor are all coupled with the first word line, one electrodes of the first transistor, the second transistor and the fifth transistor are all coupled with the first sub word line, and one electrodes of the third transistor and the fourth transistor and the other electrode of the fifth transistor are all coupled with the second sub word line; the other electrode of the first transistor and the other electrode of the third transistor are used for receiving two selection signals, the other electrode of the second transistor and the other electrode of the fourth transistor are both coupled with the ground terminal, and the grid electrodes of the second transistor and the fourth transistor are used for receiving inverted signals of the two selection signals.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a word line driving circuit, a memory, and a device. Background Art

[0002] Dynamic random access memory (DRAM), as the primary memory, has been widely used in various electronic devices, including mobile phones, computers, servers, and automotive electronic systems. The memory cell in DRAM is typically a 1T1C structure, consisting of one transistor and one capacitor.

[0003] Currently, demands for DRAM capacity and density are increasing. To this end, DRAM manufacturers are continuously developing technologies to shrink the area of ​​each memory cell to achieve higher storage density. However, in addition to shrinking the memory cell area, the corresponding peripheral circuits, such as the sub-word line driver (SWD) and sense amplifier (SA), also need to be scaled down to ensure overall storage density increases. Summary of the Invention

[0004] The present application provides a word line driving circuit, a memory and a device for reducing the size of a sub-word line driving circuit, improving the storage density of the memory and reducing the load of the word line driving.

[0005] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, a word line driving circuit is provided, which includes: a plurality of word lines (or main word lines), which can be used to provide a plurality of main selection signals, the plurality of word lines including a first word line, which provides a first main selection signal; a plurality of sub-word lines, including a first sub-word line and a second sub-word line, which are sub-word lines coupled to two sub-word line driving circuits in the same group; and a plurality of sub-word line driving circuits, including a first sub-word line driving circuit and a second sub-word line driving circuit, which are two sub-word line driving circuits in the same group. Among them, the first sub-word line drive circuit includes a first transistor and a second transistor, the second sub-word line drive circuit includes a third transistor and a fourth transistor, and the first sub-word line drive circuit and the second sub-word line drive circuit also share a fifth transistor; the gate of the first transistor, the gate of the third transistor and the gate of the fifth transistor are all coupled to the first word line (that is, all used to receive the first main selection signal), one electrode of the first transistor, one electrode of the second transistor and one electrode of the fifth transistor are all coupled to the first sub-word line, one electrode of the third transistor, one electrode of the fourth transistor and the other electrode of the fifth transistor are all coupled to the second sub-word line, the other electrode of the first transistor and the other electrode of the third transistor are respectively used to receive the first selection signal and the second selection signal, the other electrode of the second transistor and the other electrode of the fourth transistor are both coupled to the ground terminal, and the gate of the second transistor and the gate of the fourth transistor are used to receive the inverted signal of the first selection signal and the inverted signal of the second selection signal, respectively.

[0007] In the above technical solution, each sub-word line driving circuit in the first sub-word line driving circuit and the second sub-word line driving circuit each includes two independent transistors and the two also share one transistor. In this way, on average, each sub-word line driving circuit only requires 2.5 transistors. Compared with the traditional sub-word line driving circuit that requires 3 transistors, the area of ​​the sub-word line driving circuit can be reduced, and the overall storage density of the memory can be improved; in addition, the gate of the first transistor, the gate of the third transistor, and the gate of the fifth transistor in the above two sub-word line driving circuits are all coupled to the same word line. In this way, on average, the word line coupled to each sub-word line driving circuit is only used to drive 1.5 transistors. Compared with the traditional sub-word line driving circuit in which one word line is coupled to two transistors and requires driving 2 transistors, the load of the word line drive can be reduced, thereby reducing the power consumption of the circuit providing the word line signal.

[0008] In a possible implementation of the first aspect, the word line driver circuit further includes a plurality of select lines for providing select signals and inverted signals of the select signals. The plurality of word lines and the plurality of select lines are disposed in a wiring layer located on one side of a substrate, and the plurality of word lines extend in a first direction parallel to the substrate, and the plurality of select lines extend in a second direction parallel to the substrate, with the first direction being perpendicular to the second direction. In the above possible implementation, by arranging the plurality of word lines to extend in the first direction and the plurality of select lines to extend in the second direction, with the first direction being perpendicular to the second direction, coupling of the plurality of word lines and the plurality of select lines with corresponding sub-word line driver circuits can be facilitated, reducing routing difficulty for the plurality of word lines and the plurality of select lines, while improving coupling reliability.

[0009] In one possible implementation of the first aspect, the first and third transistors are PMOS transistors, and the second, fourth, and fifth transistors are NMOS transistors. In this possible implementation, by sharing the fifth NMOS transistor in the first and second sub-word line driver circuits, the area of ​​the sub-word line driver circuits can be reduced, thereby improving the overall storage density of the memory.

[0010] In a possible implementation of the first aspect, the word line driver circuit further includes: a PMOS region and an NMOS region, each disposed separately; wherein the PMOS region is provided with the multiple PMOS transistors in the multiple sub-word line driver circuits, and the NMOS region is provided with the multiple NMOS transistors in the multiple sub-word line driver circuits. In this possible implementation, by separately disposing the PMOS region for disposing the multiple PMOS transistors and the NMOS region for disposing the multiple NMOS transistors, the integration density of the multiple PMOS transistors and the multiple NMOS transistors in the word line driver circuit can be improved.

[0011] In one possible implementation of the first aspect, the PMOS region and the NMOS region include a gate layer, and at least some of the multiple word lines are discontinuous in the gate layer. Optionally, each of the at least some word lines includes a first word line segment and a second word line segment located in the gate layer, and the first word line segment is connected to the second word line segment via at least one wiring layer. In this possible implementation, while improving the integration density of multiple transistors in the word line driver circuit, at least some of the word lines can be connected to the gates of corresponding transistors in the PMOS region and the NMOS region in a discontinuous manner in the gate layer.

[0012] In a possible implementation of the first aspect, the NMOS region includes a first NMOS region and a second NMOS region disposed on either side of the PMOS region, with a portion of the plurality of NMOS transistors located in the first NMOS region and another portion located in the second NMOS region. In this possible implementation, by disposing the first NMOS region and the second NMOS region on either side of the PMOS region, the PMOS region and the NMOS region can be separately disposed, while also increasing flexibility in disposing the NMOS region.

[0013] In a possible implementation of the first aspect, the PMOS region and the NMOS region include a gate layer, and each of the multiple word lines is continuous in the gate layer. In this possible implementation, the complexity of coupling between the multiple word lines and the gates of the corresponding transistors can be reduced while increasing the integration density of the multiple transistors in the word line driver circuit.

[0014] In a second aspect, a memory is provided, comprising a memory array and a peripheral circuit coupled to the memory array, wherein the peripheral circuit comprises a word line driving circuit provided by the first aspect or any possible implementation of the first aspect.

[0015] In a possible implementation of the second aspect, the memory includes one of the following: dynamic random access memory DRAM, static random access memory SRAM, magnetic random access memory MRAM, resistive random access memory ReRAM, ferroelectric random access memory FeRAM, or phase change memory PCM.

[0016] According to a third aspect, a storage device is provided, comprising a controller and a memory provided by the second aspect or any possible implementation of the second aspect, wherein the controller is configured to control reading and writing of the memory.

[0017] In a fourth aspect, an electronic device is provided, comprising a processor and a memory coupled to each other, wherein the memory is the memory provided by the second aspect or any possible implementation manner of the second aspect.

[0018] It can be understood that the beneficial effects that can be achieved by any of the memories, storage devices, and electronic devices provided above can correspond to the beneficial effects of the word line driving circuit provided above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Schematic diagram of the structure of a sub-word line driving circuit;

[0020] Figure 2 is a structural schematic diagram of another sub-word line driving circuit;

[0021] Figure 3 A schematic diagram of the structure of a memory provided in an embodiment of the present application;

[0022] Figure 4 A schematic structural diagram of a word line driving circuit provided in an embodiment of the present application;

[0023] Figure 5 A schematic structural diagram of another word line driving circuit provided in an embodiment of the present application;

[0024] Figure 6 A layout of a word line driver circuit provided in an embodiment of the present application;

[0025] Figure 7 A layout of another word line driver circuit provided in an embodiment of the present application;

[0026] Figure 8 A schematic diagram of the structure of a storage device provided in an embodiment of the present application;

[0027] Figure 9 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. In the present application, "at least one" refers to one or more, and "more" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that there may be three relationships. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can represent: a, b, c, a and b, a and c, b and c, a, b and c; where a, b and c can be single or multiple.

[0029] The embodiments of this application use terms such as "first" and "second" to distinguish objects with similar names, functions, or effects. Those skilled in the art will understand that terms such as "first" and "second" do not limit the quantity or order of execution. The term "coupled" is used to indicate an electrical connection, including direct connection via wires or connectors or indirect connection via other devices. Therefore, "coupling" should be considered a broadly defined electronic communication connection.

[0030] In this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0031] Before introducing the embodiments of the present application, the relevant technologies and scenarios involved in the embodiments of the present application are first introduced and explained.

[0032] To increase the storage density of memory, it is often necessary to miniaturize the circuits in the memory's peripheral circuits to reduce the size of the peripheral circuits, thereby reducing the size of the memory. Sub-word line drivers (SWDs), a key component in these peripheral circuits, are numerous and large in size. Therefore, reducing the size of the sub-word line drivers can reduce the size of the peripheral circuits.

[0033] Figure 1 This is a schematic diagram of the structure of a sub-word line driver circuit SWD provided in this application. The sub-word line driver circuit SWD has a traditional structure and includes three transistors, designated TP, TN, and TK. The gates of transistors TP and TN are commonly connected to the inverted signal MWLB of the main word line; the source of transistor TP is connected to the sub-word line select signal FX; the sources of transistors TN and TK are connected to a low-level power supply terminal VKK; the gate of transistor TK is connected to the inverted signal FXB of the sub-word line select signal; and the drains of transistors TP, TN, and TK are connected as the output node of the sub-word line driver circuit SWD for coupling to the sub-word line SWL. The inverted signal can also be called a negated signal.

[0034] The above-mentioned transistor TP is a P-type field-effect transistor, and the transistor TN and transistor TK are N-type field-effect transistors. Specifically, when MWLB is low, FX is high, and FXB is low, SWL will be driven high, transistor TP is in the on state, and the sub-word line driver circuit SWD is selected. When MWLB is high, or FX and FXB are low and high, respectively, SWL will be driven low, transistor TP is in the off state, transistor TN is in the on state, and the sub-word line driver circuit SWD is selected. In this way, logically speaking, the sub-word line driver circuit SWD implements the logical AND operation of MWLB and FX, completing the final level of decoding of the sub-word line SWL.

[0035] above Figure 1In the conventional structure of the sub-word line driver circuit SWD provided, each SWD requires three transistors, which reduces the storage density of the memory when applied to a peripheral circuit and a memory.

[0036] Further, combined Figure 1 ,like Figure 2 As shown, this is a structural schematic diagram of a plurality of sub-word line driving circuits SWD provided by the present application, wherein the plurality of sub-word line driving circuits SWD are grouped together by two sub-word line driving circuits SWD controlled by two adjacent MWLBs, each sub-word line driving circuit SWD includes a transistor TP and a transistor TN, and the two sub-word line driving circuits SWD also share the same transistor TK. Figure 2 In the figure, 10 groups of SWD are taken as an example for explanation, and the corresponding MWLB, FX, FXB, and SWL are represented as MWLB0 to MWLB1, FX0 to FX2m, FXB0 to FXB2m, and SWL0 to SWL2n, respectively. The value range of m is 1 to 3, and the value range of n is 1 to 7.

[0037] Specifically, when a sub-word line driver circuit SWD is selected, the MWLB coupled to the sub-word line driver circuit SWD is at a low level, FX is at a high level, and FXB is at a low level, and the sub-word line SWL is pulled up to a high level via transistor TP. When a sub-word line driver circuit SWD is not selected, there are two cases: the first case is when the MWLB is at a high level, and the sub-word line SWL is pulled down to a low level via transistor TN; the second case is when the MWLB is at a low level, FX is at a low level, and FXB is at a high level, and the sub-word line SWL is pulled down to a low level via a shared transistor TK and transistor TN of another sub-word line driver circuit SWD in the same group (where the MWLB of the other sub-word line driver circuit SWD is at a high level because at most one of the adjacent MWLBs is at a low level).

[0038] above Figure 2 The proposed sub-wordline driver circuit SWD structure utilizes the characteristic that at most one of the MWLBs of a sub-wordline driver circuit SWD in the same group is at a low level, thus implementing the logic functions of two sub-wordline driver circuits SWD using five transistors. However, this solution introduces certain wiring difficulties during actual layout implementation because the two sub-wordline driver circuits SWD in the same group are coupled to different MWLBs. This results in a large number gap between the sub-wordlines SWL of the two sub-wordline driver circuits SWD, requiring certain adjustments during layout implementation.

[0039] Based on this, an embodiment of the present application provides a word line driving circuit having multiple sub-word line driving circuits SWD, in which each sub-word line driving circuit SWD in the word line driving circuit requires only 2.5 transistors on average, thereby reducing the area of ​​the sub-word line driving circuit SWD; in addition, in the word line driving circuit, three transistors in the first sub-word line driving circuit and the second sub-word line driving circuit that share the same transistor are coupled to the same word line, which does not increase the difficulty of winding. At the same time, on average, the word line coupled to each sub-word line driving circuit SWD is only used to drive 1.5 transistors. Compared with the traditional sub-word line driving circuit SWD in which one word line is coupled to two transistors and requires driving two transistors, the load of the word line drive can be reduced, thereby reducing the power consumption of the circuit providing the word line signal.

[0040] The word line driver circuit provided in the embodiment of the present application can be applied to a variety of memories, which may include but are not limited to: dynamic random access memory (DRAM), static random access memory (SRAM), magnetic random access memory (MRAM), resistive random access memory (ReRAM), ferroelectric random access memory (FeRAM), or phase change memory (PCM). Optionally, the DRAM may include synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM) and RAM bus dynamic random access memory (RDRAM). DDR SRAM may also be referred to as DDR. The embodiments of the present application will not be listed one by one for description.

[0041] For example, Figure 3A schematic diagram of the structure of a memory provided in an embodiment of the present application. The memory includes multiple memory arrays MAT and peripheral circuits coupled to the multiple memory arrays MAT. The peripheral circuits may include: a row decoder (R DEC), a column decoder (C DEC), a word line driver circuit, and multiple sense amplifier circuits (SA). The word line driver circuit may include multiple sub-word line driver circuits SWD, and the multiple sub-word line driver circuits SWD and the multiple sense amplifier circuits SA are respectively coupled to the multiple memory arrays MAT. Figure 3 In the description, an example is given in which each memory array MAT in the plurality of memory arrays MAT is coupled to a different sense amplifier circuit SA, and two adjacent memory arrays MAT share a sub-word line driver circuit SWD.

[0042] In this memory, the row decoder R DEC can be used to decode the row address of the data in the read and write operations corresponding to the multiple memory arrays MAT, and the column decoder (C DEC) can be used to decode the column address of the data in the read and write operations corresponding to the multiple memory arrays MAT. The sub-word line driver circuit SWD coupled to each memory array MAT can be used to control the selection or shutdown of the memory cells in the memory array MAT, and the sensing amplifier circuit SA coupled to each memory array MAT can be used to amplify the data read from the memory array MAT or drive the data to be written into the memory array MAT.

[0043] Furthermore, the word line driver circuit may include multiple word lines (or multiple main word lines) and multiple sub-word lines. Each sub-word line driver circuit SWD may be coupled to one word line and one sub-word line. Different word lines may be coupled to different sub-word lines. For example, each word line may be coupled to eight sub-word lines in each memory array. Figure 3 The multiple word lines and the multiple sub-word lines are not shown.

[0044] It is understandable that the above Figure 3 The structure of the memory provided does not constitute a limitation to the memory. In actual applications, the memory may also include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.

[0045] Figure 4This is a schematic diagram of the structure of a wordline driver circuit provided in an embodiment of the present application. The wordline driver circuit includes: multiple wordlines, multiple sub-wordlines, and multiple SWDs. The multiple SWDs may include multiple groups, each group including two SWDs, and the two SWDs in the same group may be coupled to one wordline and two sub-wordlines. The following describes the structure of the wordline driver circuit using one SWD group as an example.

[0046] In one possible embodiment, the multiple word lines include a first word line, the multiple sub-word lines include a first sub-word line and a second sub-word line, and the multiple SWDs include a first SWD and a second SWD. The first SWD includes a first transistor and a second transistor, the second SWD includes a third transistor and a fourth transistor, and the first and second SWDs also share a fifth transistor. The gates of the first transistor, the third transistor, and the fifth transistor are all coupled to the first word line. One electrode of the first transistor, one electrode of the second transistor, and one electrode of the fifth transistor are all coupled to the first sub-word line. One electrode of the third transistor, one electrode of the fourth transistor, and the other electrode of the fifth transistor are all coupled to the second sub-word line. The other electrodes of the first transistor and the third transistor are respectively configured to receive a first selection signal and a second selection signal. The other electrodes of the second transistor and the fourth transistor are both coupled to a ground terminal VKK. The gates of the second transistor and the fourth transistor are respectively configured to receive an inverted signal of the first selection signal and an inverted signal of the second selection signal. The first and second selection signals, as well as the inverted signal of the first selection signal and the inverted signal of the second selection signal, are provided by multiple selection lines.

[0047] The first word line may be any one of the plurality of word lines, each word line may be used to provide a different main selection signal MWLB, and each word line may be coupled to a different group of SWDs in the plurality of groups of SWDs. Figure 4 In the example, the multiple word lines include two word lines, and the main selection signals MWLB provided by the two word lines are MWLB0 and MWLB1 respectively, MWLB0 is coupled with 4 groups of SWD, and MWLB1 is coupled with another 4 groups of SWD. The first sub-word line and the second sub-word line are two SWD-coupled sub-word lines SWL of the same group, and the SWD-coupled sub-word lines SWL of different groups are different. For example, Figure 4 In this description, a word line driver circuit includes eight SWD groups, with the corresponding coupled sub-word lines SWL being denoted as SWL0 and SWL2, SWL4 and SWL6, SWL8 and SWL10, and SWL12 and SWL14, respectively. The first and second SWD groups are two SWDs in the same group, and the number of transistors and the coupling method between the transistors in different SWD groups are consistent.

[0048] Optionally, the transistor may be a metal oxide semiconductor (MOS) field effect transistor, or MOS transistor for short. One electrode of the transistor may be a source or a drain, and the other electrode of the transistor may be the other of the source or the drain. Exemplarily, the first and third transistors are PMOS transistors, and the second, fourth, and fifth transistors are NMOS transistors. Figure 4 In FIG, the first transistor and the third transistor in the two SWDs of the first group are denoted as TP1 and TP2, respectively, and the second transistor, the fourth transistor and the fifth transistor are denoted as TK1, TK2 and TN, respectively.

[0049] It is understandable that, in practical applications, the above-mentioned transistors may also be other transistors capable of achieving the same function, and the embodiments of the present application do not impose any specific limitation on this.

[0050] In this word line driver circuit, taking the first and second SWDs in the first group as an example, if the first SWD is selected (i.e., MWLB0 is low, FX0 is high, and FXB0 is low), SWL0 will be driven high via transistor TP1. If the first SWD is not selected, there are two situations: First, FX0 is not selected (i.e., FX0 is low) and FXB0 is high, in which case SWL0 can be pulled down to a low level via transistor TK1. Second, FX0 is selected and MWLB0 is not selected (i.e., FX0 is high, FXB0 is low, and MWLB0 is high). Since FX2 corresponding to the second SWD in the same group is necessarily low, and FXB2 is necessarily high, SWL0 can be pulled down to a low level via transistor TN and transistor TK2 of the second SWD. That is, the solution of the present application utilizes the characteristics that at most only one of the sub-selection signals of the two SWDs in the same group is at a high level and at least one is at a low level, so that the transistor TN can be shared and still achieve the same logical function, thereby achieving the purpose of reducing the number of transistors.

[0051] Furthermore, the multiple word lines in the word line driving circuit may adopt a hierarchical word line structure, in which the multiple word lines traverse multiple memory arrays, and the SWDs on both sides of each memory array perform AND logic on the selection signals corresponding to the word lines and sub-word lines to form a driving circuit for the sub-word lines of each memory array. For example, Figure 5 As shown, the multiple word lines and the multiple selection lines are arranged in a wiring layer (or metal layer) located on one side of the substrate, and the multiple word lines extend along a first direction parallel to the substrate, and the multiple selection lines extend along a second direction parallel to the substrate, and the first direction is perpendicular to the second direction. Figure 5Each word line in each memory array corresponds to 8 sub-word lines, and the selection signals of the 8 groups of sub-word lines (i.e., FX0-FX7, FXB0-FXB7) are used to select which of the 8 sub-word lines corresponding to the selected word line is selected. The 8 groups of word lines are represented as SWL0 to SWL15, and the multiple word lines are represented as MWLB0 and MWLB1. Figure 5 The specific structure of multiple SWDs is not shown.

[0052] Furthermore, the layout corresponding to the word line driver circuit may include a PMOS region and an NMOS region that are separately arranged, wherein the PMOS region is provided with a plurality of PMOS transistors in the plurality of SWDs, and the NMOS region is provided with a plurality of NMOS transistors in the plurality of SWDs.

[0053] In one possible embodiment, the PMOS region and the NMOS region include a gate layer, which may include the gates of the plurality of PMOS transistors and the gates of the plurality of NMOS transistors. At least some of the plurality of word lines are discontinuous in the gate layer, that is, each of the at least some word lines is disconnected in the gate layer. Optionally, each of the at least some word lines includes a first word line segment and a second word line segment located in the gate layer, the first word line segment and the second word line segment being unconnected in the gate layer, and the first word line segment being connected to the second word line segment via at least one wiring layer.

[0054] For example, Figure 6 As shown in the figure, the layout includes a PMOS region and an NMOS region, and the PMOS region is located to the right of the NMOS region. There are 16 SWDs (corresponding to 4 groups of MWLB signals and 4 groups of FX and FXB signals) in the layout, totaling 40 transistors. Among them, the PMOS region includes 16 PMOS transistors, and the NMOS region includes 24 NMOS transistors. The gray shown in the figure represents the bottom metal layer M0, which is used to realize the wiring of SWL and the upward lead-out of MWLB, FX and FXB. The metal layer M0 is connected to the active area and gate through metal contacts. Figure 6The multiple horizontal traces in medium gray represent the 16 SWLs, and the remaining square-shaped graphics represent the metal pads extending upward from the MWLB, FX, and FXB. In this layout, for the multiple SWD groups corresponding to the same MWLB signal, the MWLB ports of half of the SWD groups are disconnected at the gate layer. The two separated parts are connected to the metal layer M0 via gate contacts and then to the upper metal layer via jumpers to connect to the MWLB signals running through the higher metal layer. The MWLB ports of the other half of the SWD groups can be directly connected together through a continuous gate metal layer, connected to the metal layer M0 via gate contacts and then to the upper metal layer via jumpers to connect to the MWLB signals running through the higher metal layer.

[0055] In another possible embodiment, the NMOS region includes a first NMOS region and a second NMOS region disposed on either side of the PMOS region, with a portion of the plurality of NMOS transistors located in the first NMOS region and another portion located in the second NMOS region. Optionally, the PMOS region, the first NMOS region, and the second NMOS region include a gate layer, and each of the plurality of word lines is continuous within the gate layer, i.e., each word line is a complete transmission line segment within the gate layer.

[0056] For example, Figure 7 As shown, the layout includes a PMOS region, and a first NMOS region and a second NMOS region arranged on both sides of the PMOS region. There are 16 SWDs (corresponding to 4 groups of MWLB signals and 4 groups of FX and FXB signals) arranged in the layout, totaling 40 transistors. The PMOS region includes 16 PMOS transistors, the first NMOS region includes 12 NMOS transistors, and the second NMOS region includes 12 NMOS transistors, for a total of 24 NMOS transistors (the count of 24 here ignores the top and bottom 8 NMOS transistors in the left and right columns, which belong to other SWDs that extend up and down and are not drawn). The gray shown in the figure represents the bottom metal layer M0, which is used to realize the routing of the SWL and the upward lead-out of the MWLB, FX, and FXB. The metal layer M0 is connected to the active area and gate through metal contacts. The multiple gray horizontal traces in the figure represent the 16 SWLs, and the remaining square-shaped figures represent the metal pads that lead upward from the MWLB, FX, and FXB. This layout differs from the other layout provided above in that the PMOS transistor is located in the middle and the NMOS transistors are located on both sides of the PMOS transistor. In addition, for multiple groups of SWDs corresponding to the same MWLB signal, the MWLB ports of these multiple groups of SWDs are all connected together at the gate layer.

[0057] In the wordline driver circuit provided in an embodiment of the present application, each SWD in the first and second SWDs belonging to the same group includes two independent transistors and shares one transistor. This means that each SWD requires only 2.5 transistors on average, compared to a conventional SWD requiring three transistors. This reduces the SWD area and improves the overall storage density of the memory. In addition, the gates of the first transistor, the third transistor, and the fifth transistor in the two SWDs are all coupled to the same wordline. This means that, on average, each wordline coupled to the sub-wordline driver circuit only drives 1.5 transistors. This reduces the load on the wordline driver, thereby reducing the power consumption of the circuit providing the wordline signal, compared to a conventional SWD in which one wordline is coupled to two transistors and requires driving two transistors. Furthermore, the numbering interval between the first and second sub-wordlines corresponding to the two SWDs is small, for example, the first and second sub-wordlines are SWL0 and SWL2, or SWL4 and SWL6, respectively. This reduces the layout area while also reducing the minimum pitch of the required winding metal layer, thereby reducing the difficulty of winding.

[0058] Based on this, an embodiment of the present application further provides a memory, which includes a memory array and a peripheral circuit coupled to the memory array. The peripheral circuit may include any one of the word line driver circuits provided above. Further, the peripheral circuit may also include at least one of a row decoder R DEC, a column decoder C DEC, or a sense amplifier circuit SA. For example, the structure of the memory may be as described above. Figure 3 As stated.

[0059] Optionally, the memory may include any one of the following: dynamic random access memory DRAM, static random access memory SRAM, magnetic random access memory MRAM, resistive random access memory ReRAM, ferroelectric random access memory FeRAM, or phase change memory PCM.

[0060] It is understood that for a detailed description of the memory, please refer to the above description of the word line drive circuit and Figure 3 The relevant description of the memory provided, namely the above-mentioned word line driver circuit and Figure 3 The contents of the provided memory embodiments can all be referred to in the embodiments of this memory, and the embodiments of this application will not be repeated here.

[0061] In another aspect of the present application, Figure 8 As shown, a storage device is also provided, which includes a controller and the memory provided above, and the controller can be used to control the reading and writing of the memory.

[0062] In another aspect of this application, Figure 9As shown, an electronic device is also provided, the electronic device including a processor and a memory coupled to each other, the memory being the memory provided above. Optionally, the processor may include, but is not limited to: a central processing unit (CPU), a general-purpose processor, a graphics processing unit (GPU), an image signal processor (ISP), a digital signal processor (DSP), a network processing unit (NPU), an artificial intelligence (AI) processor, and a controller, etc.

[0063] Furthermore, the electronic device may also include: a cache and / or a controller; wherein the processor, the cache, the controller and the memory may be integrated together or set separately, and the memory may be coupled to the cache through the controller, and coupled to the processor through the cache.

[0064] In this application, the electronic device can be used as a terminal device or as a server. Optionally, the electronic device includes but is not limited to: mobile phones, tablet computers, laptops, desktop computers, PDAs, ultra-mobile personal computers (umPCs), mobile internet devices (MIDs), netbooks, camcorders, cameras, wearable devices (such as smart watches and smart bracelets, etc.), vehicle-mounted equipment (such as cars, bicycles, electric vehicles, airplanes, ships, trains, high-speed railways, etc.), virtual reality (VR) equipment, augmented reality (AR) equipment, wireless terminals in industrial control, smart home devices (such as refrigerators, televisions, air conditioners, electricity meters, etc.), intelligent robots, workshop equipment, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, or wireless terminals in smart homes, flying equipment (such as intelligent robots, hot air balloons, drones, airplanes), etc.

[0065] It can be understood that the relevant descriptions of the memory and word line driving circuit provided above can all be referred to the embodiments of the electronic device, and the embodiments of the present application will not be repeated here.

[0066] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A word line driving circuit, characterized in that: The word line driving circuit includes: a plurality of word lines including a first word line; a plurality of sub-wordlines, including a first sub-wordline and a second sub-wordline; a plurality of sub-word line driving circuits, including a first sub-word line driving circuit and a second sub-word line driving circuit; The first sub-word line driving circuit includes a first transistor and a second transistor, the second sub-word line driving circuit includes a third transistor and a fourth transistor, and the first sub-word line driving circuit and the second sub-word line driving circuit also share a fifth transistor; The gate of the first transistor, the gate of the third transistor and the gate of the fifth transistor are all coupled to the first word line, one electrode of the first transistor, one electrode of the second transistor and one electrode of the fifth transistor are all coupled to the first sub-word line, one electrode of the third transistor, one electrode of the fourth transistor and the other electrode of the fifth transistor are all coupled to the second sub-word line, the other electrode of the first transistor and the other electrode of the third transistor are respectively used to receive a first selection signal and a second selection signal, the other electrode of the second transistor and the other electrode of the fourth transistor are both coupled to the ground terminal, and the gate of the second transistor and the gate of the fourth transistor are used to receive an inverted signal of the first selection signal and an inverted signal of the second selection signal, respectively.

2. The word line driving circuit according to claim 1, wherein: The word line driving circuit also includes a plurality of selection lines for providing the selection signal and the inverted signal. The plurality of word lines and the plurality of selection lines are arranged in a wiring layer located on one side of the substrate, and the plurality of word lines extend along a first direction parallel to the substrate, and the plurality of selection lines extend along a second direction parallel to the substrate, and the first direction is perpendicular to the second direction.

3. The word line driving circuit according to claim 1 or 2, wherein: The first transistor and the third transistor are PMOS transistors, and the second transistor, the fourth transistor and the fifth transistor are NMOS transistors.

4. The word line driving circuit according to claim 3, wherein: The word line driving circuit further includes: a PMOS region and an NMOS region which are separately arranged; wherein the PMOS region is provided with a plurality of PMOS transistors in the plurality of sub-word line driving circuits, and the NMOS region is provided with a plurality of NMOS transistors in the plurality of sub-word line driving circuits.

5. The word line driving circuit according to claim 4, wherein: The PMOS region and the NMOS region include a gate layer, and at least some of the word lines among the plurality of word lines are discontinuous in the gate layer.

6. The word line driving circuit according to claim 5, wherein: Each word line of the at least part of the word lines includes a first word line segment and a second word line segment located in the gate layer, and the first word line segment is connected to the second word line segment through at least one wiring layer.

7. The word line driving circuit according to claim 4, wherein: The NMOS region includes a first NMOS region and a second NMOS region disposed on both sides of the PMOS region. A portion of the plurality of NMOS transistors is located in the first NMOS region, and another portion is located in the second NMOS region.

8. The word line driving circuit according to claim 7, wherein: The PMOS region and the NMOS region include a gate layer, and each of the plurality of word lines is continuous in the gate layer.

9. A memory, characterized in that: The memory includes a memory array and a peripheral circuit coupled to the memory array, wherein the peripheral circuit includes the word line driving circuit according to any one of claims 1 to 8.

10. The memory according to claim 9, wherein: The memory includes one of the following: dynamic random access memory DRAM, static random access memory SRAM, magnetic random access memory MRAM, resistive random access memory ReRAM, ferroelectric random access memory FeRAM, or phase change memory PCM.

11. A storage device, characterized in that: The storage device includes a controller and the memory according to claim 9 or 10, wherein the controller controls reading and writing of the memory.

12. An electronic device, characterized in that: The electronic device includes a processor and a memory coupled to each other, and the memory is the memory according to claim 9 or 10.

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