FPGA-based SLVS-EC to eDP interface conversion method

Abstract

The invention provides an SLVS-EC to eDP interface conversion method based on an FPGA, and the method comprises the steps: receiving a configuration parameter, carrying out the link training of a data transmission link according to the configuration parameter, and determining at least one transmitting channel and a receiving channel. And receiving the to-be-transmitted data sent by the acquisition device through the receiving channel, unpacking the to-be-transmitted data according to the SLVS-EC interface protocol to obtain a plurality of unpacked data, and caching each unpacked data. And performing packet processing on the unpacked data according to an eDP interface protocol to obtain a plurality of pieces of data to be sent. And sending the data to be sent to an eDP interface protocol serial deserializing module through the sending channel, serializing the data to be sent by the eDP interface protocol serial deserializing module, and outputting the serialized data to a display device according to an eDP interface protocol. Data transmission is carried out through the FPGA chip, the flexibility is high, and the cost is low.

Description

Technical Field

[0001] The present application relates to the technical field of data transmission, and in particular to a method for converting an SLVS-EC to an eDP interface based on an FPGA. Background Art

[0002] With the continuous advancement of technology, image sensors and display devices have been widely used in various fields. The Scalable Low Voltage Signaling with Embedded Clock (SLVS-EC) interface protocol is a high-speed interface protocol suitable for high-pixel and high-speed image sensors. Display devices or processing equipment typically use DisplayPort (DP) or Embedded DisplayPort (eDP) as a video input interface. Because the SLVS-EC interface protocol is inconsistent with the DP / eDP interface protocol and cannot be directly interconnected, how to connect the SLVS-EC interface protocol with the DP / eDP interface protocol has become a pressing technical problem.

[0003] In the prior art, a dedicated interface conversion chip, such as an Application-Specific Integrated Circuit (ASIC) chip, is used to enable data transmission between an image sensor and a display device.

[0004] However, the dedicated interface conversion chip in the prior art is expensive and has poor flexibility. It can usually only perform signal conversion according to a pre-set mode, which makes it difficult to meet the flexibility requirements. Summary of the Invention

[0005] The purpose of this application is to provide an FPGA-based SLVS-EC to eDP interface conversion method to address the deficiencies in the above-mentioned prior art, so as to solve the problem of poor flexibility of the interface conversion chip in the prior art.

[0006] To achieve the above objectives, the technical solutions adopted in this application are as follows: In a first aspect, the present application provides an FPGA-based SLVS-EC to eDP interface conversion method, which is applied to an FPGA chip. The method includes: receiving configuration parameters sent by a display device, wherein the configuration parameters include display parameters of the display device; Performing link training on the data transmission link in the FPGA chip according to the configuration parameters to determine at least one transmitting channel and at least one receiving channel; receiving the data to be transmitted sent by the acquisition device through the corresponding receiving channel, unpacking the data to be transmitted according to the SLVS-EC interface protocol corresponding to the acquisition device to obtain multiple unpacked data, and caching each unpacked data; Extracting each of the unpacked data, and performing packet processing on each of the unpacked data according to the eDP interface protocol corresponding to the display device to obtain a plurality of data to be sent; Each of the data to be sent is sent to the eDP interface protocol serial deserialization module in the FPGA chip through the corresponding sending channel, and the eDP interface protocol serial deserialization module serializes each of the data to be sent and outputs it to the display device according to the eDP interface protocol.

[0007] Optionally, the receiving configuration parameters sent by the display device includes: detecting a hot plug signal of the display device; determining whether the display device is in a valid connection state according to the hot plug signal; If yes, the configuration parameters sent by the display device are received.

[0008] Optionally, performing link training on the data transmission link in the FPGA chip according to the configuration parameters includes: Determining acquisition parameters of the acquisition device according to the display parameters, and sending the acquisition parameters to the acquisition device; Link training is performed according to the configuration parameters and the acquisition parameters to determine at least one sending channel and at least one receiving channel.

[0009] Optionally, the unpacking of the data to be transmitted according to the SLVS-EC interface protocol corresponding to the acquisition device to obtain a plurality of unpacked data includes: Serializing the data to be transmitted according to the SLVS-EC interface protocol to obtain serial data; The serial data is disassembled to obtain a plurality of unpacked data.

[0010] Optionally, before packaging the unpacked data according to the eDP interface protocol corresponding to the display device, the method further includes: Based on the preset frame rate of the display device and the frame rate of the acquisition device, frame deletion and supplementation processing is performed on the plurality of unpacked data.

[0011] Optionally, the performing frame deletion and padding processing on the plurality of unpacked data based on a preset frame rate of the display device and a frame rate of the acquisition device includes: If the frame rate of the display device is higher than the frame rate of the acquisition device, performing frame filling processing on the plurality of unpacked data; If the frame rate of the display device is lower than the frame rate of the acquisition device, frame deletion processing is performed on the multiple unpacked data.

[0012] Optionally, the step of performing packet processing on each unpacked data to obtain a plurality of data to be sent includes: Packaging the unpacked data; The processed data is segmented according to a transmission channel, and a skew code is added to each segment of data to obtain the plurality of data to be transmitted, wherein the skew codes added to each unpacked data are different.

[0013] Optionally, the method further includes: When the data to be transmitted sent by the acquisition device is not received within a preset time, the current state is set to a dormant state.

[0014] In a second aspect, the present application provides an FPGA chip, which is used to execute the steps of the FPGA-based SLVS-EC to eDP interface conversion method as described in the first aspect to transmit data from an acquisition device to a display device.

[0015] In a third aspect, the present application provides a video transmission system, comprising: the FPGA chip, acquisition device, and display device as described in the second aspect; The FPGA chip is communicatively connected to the acquisition device and the display device respectively; The acquisition device is used to collect data and send the collected data to the FPGA chip; The FPGA chip is used to transmit the data from the acquisition device to the display device; The display device is used to display the data transmitted by the FPGA chip.

[0016] The beneficial effects of the present application are: link training is performed on the data transmission link in the FPGA chip according to the configuration parameters sent by the display device, thereby ensuring the data transmission quality and transmission efficiency. After the training is completed, the data to be transmitted is received, and it is cached after being unpacked according to the SLVS-EC interface protocol. During the sending process, each extracted unpacked data is packaged according to the eDP interface protocol, and each data to be sent is sent to the eDP interface protocol serial deserialization module through the sending channel. The eDP interface protocol serial deserialization module serializes each data to be sent and outputs it to the display device according to the eDP interface protocol. This process is executed based on the FPGA chip and is not limited to the SLVS-EC interface protocol of the SLVS-EC interface of the acquisition device and the eDP interface protocol of the eDP interface of the display device, so it has high flexibility. In addition, this embodiment does not involve other chips for data transmission, so the cost is relatively low. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 This is a schematic structural diagram of a video transmission system provided in an embodiment of the present application; Figure 2 This is a functional structure diagram of an FPGA chip provided in an embodiment of the present application; Figure 3 This is a flow chart of a method for converting an SLVS-EC to an eDP interface based on FPGA provided in an embodiment of the present application; Figure 4 This is a flow chart of receiving a configuration request provided in an embodiment of the present application. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of illustration and description and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn to scale. The flowcharts used in this application illustrate the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowcharts can be implemented out of sequence, and steps without logical context can be reversed or implemented simultaneously. In addition, those skilled in the art, under the guidance of the contents of this application, can add one or more other operations to the flowchart, or remove one or more operations from the flowchart.

[0020] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application generally described and shown in the drawings here can be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.

[0021] It should be noted that the term "comprising" will be used in the embodiments of the present application to indicate the existence of the features declared thereafter, but does not exclude the addition of other features.

[0022] To solve the problem of connecting the SLVS-EC interface protocol with the DP / eDP interface protocol, existing technologies use dedicated interface conversion chips to enable data transmission between image sensors and display devices. However, these dedicated interface conversion chips lack flexibility and are typically limited to performing signal conversion according to pre-defined patterns, making them inadequate for meeting the required flexibility. Alternatively, existing technologies offer a solution that combines a Field Programmable Gate Array (FPGA) chip with an external interface chip. While this solution improves flexibility, it also increases system complexity and cost.

[0023] Based on this, the present application proposes an FPGA-based SLVS-EC to eDP interface conversion method applied to an FPGA chip. The method first trains the data transmission link based on the configuration request sent by the display device. After the training is completed, after receiving the data to be transmitted, the data to be transmitted is processed and cached according to the SLVS-EC interface protocol. During the sending process, each unpacked data is extracted and processed according to the eDP interface protocol and output to the display device. The present application is applied to an FPGA chip and converts and forwards data based on the preset SLVS-EC interface protocol and eDP interface protocol, which has high flexibility. In addition, the FPGA-based SLVS-EC to eDP interface conversion method is only applied to the FPGA chip, and there is no need to connect to other external interface chips, so the cost is low.

[0024] In this application, the FPGA-based SLVS-EC to eDP interface conversion method can be applied to the FPGA chip in the video transmission system. Figure 1 This is a schematic diagram of the structure of a video transmission system provided by an embodiment of the present application. Figure 1 The structure of the video transmission system is introduced. Figure 1 As shown, the video transmission system includes an FPGA chip, an acquisition device, and a display device. The FPGA chip is communicatively connected to the acquisition device and the display device, respectively. The acquisition device can be, for example, an industrial camera, medical imaging equipment, or a video signal processing device in an autonomous driving system. The display device can be, for example, an LCD screen.

[0025] Optionally, the acquisition device is used to acquire data and send the acquired data to the FPGA chip, the FPGA chip is used to transmit the data from the acquisition device to the display device, and the display device is used to display the data transmitted by the FPGA chip.

[0026] After introducing the structure of the video transmission system, refer to Figure 2 This paper introduces the functional structure of FPGA chip. Figure 2 This is a functional structure diagram of an FPGA chip provided in an embodiment of the present application.

[0027] like Figure 2 As shown, the FPGA chip includes an SLVS-EC interface protocol serial deserialization module, an SLVS-EC interface protocol receiving and decoding module, a cache module, an eDP interface protocol sending encoding module, an eDP interface protocol serial deserialization module, a main control module, an auxiliary interface request module, a hot plug detection module, a parameter configuration module, a clock module, and a reset module.

[0028] The SLVS-EC interface protocol serial deserialization module can be, for example, a Gowin SerDes module, the SLVS-EC interface protocol receiving and decoding module can be, for example, a Gowin SLVS-ES IP receiving module, the cache module can be, for example, a video buffer process module, the eDP interface protocol transmitting and encoding module can be, for example, a Gowin eDP IP decoding module, and the eDP interface protocol serial deserialization module can be, for example, a Gowin SerDes module. The SLVS-EC interface protocol serial deserialization module receives data to be transmitted from the acquisition device via the SLVS-EC interface. The cache module is configured to receive and cache data sent by the SLVS-EC interface protocol receiving and decoding module, and during transmission, send the cached data to the eDP interface protocol transmitting and encoding module.

[0029] The caching process of the cache module may include sending the data to be cached to an external cache.

[0030] The eDP interface protocol serial deserialization module is used to send the received data to the display device through the eDP interface.

[0031] It is worth noting that the eDP interface protocol sending encoding module can also be the DP interface protocol sending encoding module, the eDP interface protocol serial deserialization module can also be the DP interface protocol serial deserialization module, and the processing process of the DP interface protocol sending encoding module and the DP interface protocol serial deserialization module is the same as the processing process of the eDP interface protocol sending encoding module and the eDP interface protocol serial deserialization module, which is used for data conversion from the SLVS-EC interface to the DP interface. In this conversion method, the eDP interface can also be a DP interface. This embodiment describes in detail the data conversion method from the SLVS-EC interface to the eDP interface. For the data conversion method from the SLVS-EC interface to the DP interface with the same processing method, this embodiment will not repeat it here.

[0032] Alternatively, the FPGA chip can be based on the GW5AST series FPGA and designed using the Transceiver Quad resource. The Transceiver Quad resource supports up to four transceivers, each with a receive and transmit interface, enabling independent data transmission and reception, supporting data rates from 270Mbps to 12.5Gbps.

[0033] It is worth noting that the FPGA chip used in this application can realize online firmware upgrades, avoiding time delays caused by hardware replacement.

[0034] The FPGA chip is connected to the acquisition device via an SLVS-EC interface, and the FPGA chip is connected to the display device via an eDP interface. The auxiliary interface request module is configured to request configuration of the display device via the auxiliary interface connected to the display device. The hot plug detection module is configured to detect hot plug signals from the display device via the hot plug interface. The parameter configuration module is configured to connect to the acquisition device via an Inter-Integrated Circuit (I2C) bus.

[0035] In the FPGA chip, the link consisting of the SLVS-EC interface protocol serial-to-deserialization module, the SLVS-EC interface protocol receive-decode module, the cache module, the eDP interface protocol transmit-encode module, and the eDP interface protocol serial-to-deserialization module is the data transmission link. This is a high-speed link that can be used for high-speed data transmission. The link consisting of the main control module, the auxiliary interface request module, the hot-plug detection module, and the parameter configuration module serves as a low-speed configuration link, which is used to receive and send configuration data and control data.

[0036] Next, refer to Figure 3 The process of the FPGA-based SLVS-EC to eDP interface conversion method in this application is introduced, and the specific functions of the above-mentioned functional modules are introduced in the process of introducing the process. Among them, Figure 3 This is a flowchart of an FPGA-based SLVS-EC to eDP interface conversion method provided in an embodiment of the present application.

[0037] S301: Receive configuration parameters sent by a display device, where the configuration parameters include display parameters of the display device.

[0038] Specifically, the auxiliary interface request module may send a configuration request to the display device via the auxiliary interface in real time, where the configuration request is used to request the display device to send configuration parameters.

[0039] The display parameters in the configuration parameters may include, for example, parameters such as the maximum communication rate, number of channels, and maximum receiving voltage amplitude supported by the display device.

[0040] Optionally, in addition to display parameters, the configuration parameters may also include parameters for responding to request transactions, including data such as link status, etc. The link status is used to represent the link training results so that the main control module can monitor the performance and stability of the link.

[0041] S302 : Perform link training on the data transmission link in the FPGA chip according to the configuration parameters to determine at least one transmitting channel and at least one receiving channel.

[0042] Specifically, first, the main control module determines the initial acquisition parameters of the acquisition device based on the display parameters in the configuration parameters sent by the display device, and sends the initial acquisition parameters to the acquisition device through the parameter configuration module and the integrated circuit interconnect bus, so that the acquisition device can send training data based on the initial acquisition parameters. The initial acquisition parameters can be camera serial interface (CIS) image sensor parameters, which may include initial transmission channels, initial reception channels, initial signal rate, initial signal output amplitude, and initial pre-emphasis value.

[0043] After the data transmission link converts the training data and sends it to the display device, the display device evaluates the signal quality based on the received training data and, via the auxiliary interface and the auxiliary interface request module, provides feedback on the link status to the main control device. This allows the main control device to adjust the initial acquisition parameters based on the link status and display parameters to obtain intermediate acquisition parameters. The intermediate acquisition parameters are then sent to the acquisition device via the parameter configuration module and the I2C bus, causing the acquisition device to send training data based on the intermediate acquisition parameters. The training data sent this time may differ from the training data sent based on the initial acquisition parameters.

[0044] The acquisition device sends training data based on the intermediate acquisition parameters. After the data transmission link converts the training data and sends it to the display device, the display device evaluates the signal quality based on the received training data and feeds back the link status to the main control device through the auxiliary interface and the auxiliary interface request module, so that the main control device adjusts the intermediate acquisition parameters according to the link status and display parameters, and continues configuration and data transmission.

[0045] When the link status data quality reaches optimality, link training is successful. Specifically, link training determines at least one transmit channel and at least one receive channel. The transmit channel determined through link training can be one or more of all transmit channels, and the receive channel determined through link training can be one or more of all receive channels. Furthermore, the signal rate, signal output amplitude, and pre-emphasis value can also be determined. During the transmission of data to be transmitted, data is transmitted according to the acquisition parameters determined after training. These acquisition parameters may include at least one transmit channel, at least one receive channel, signal rate, signal output amplitude, and pre-emphasis value.

[0046] In addition, the data transmission link may include multiple transmit channels and multiple receive channels. The receive channel is the transmission path for data from the SLVS-EC interface protocol serial deserialization module to the SLVS-EC interface protocol receiver and decoder module. Each receive channel is responsible for transmitting a portion of the data, and multiple receive channels can operate in parallel, thereby improving the data transmission rate and efficiency. The transmit channel is the transmission path for data from the eDP interface protocol transmitter encoding module to the eDP interface protocol serial deserialization module. Each transmit channel is responsible for transmitting a portion of the data, and multiple transmit channels can operate in parallel, thereby improving the data transmission rate and efficiency.

[0047] For example, the data transmission delay of a traditional chip is at the millisecond level, while the data transmission delay in the FPGA-based SLVS-EC to eDP interface conversion method applied on the FPGA chip in this application is controlled at the microsecond level.

[0048] The sending channel and the receiving channel can be composed of the corresponding parts of the physical layer and the link layer. Among them, the physical layer is responsible for the transmission, reception and sending of signals, and the link layer is responsible for data encoding, decoding and error detection.

[0049] S303: Receive the data to be transmitted sent by the acquisition device through the corresponding receiving channel, unpack the data to be transmitted according to the SLVS-EC interface protocol corresponding to the acquisition device, obtain multiple unpacked data, and cache each unpacked data.

[0050] Optionally, the acquisition device sends the data to be transmitted according to the acquisition parameters obtained by link training, wherein the data to be transmitted may be image data or video data.

[0051] Specifically, the SLVS-EC interface protocol serial deserialization module receives data to be transmitted from the acquisition device via the SLVS-EC interface, serializes the data, and then sends the serial data to the SLVS-EC interface protocol receiver and decoder module via at least one receive channel. The SLVS-EC interface protocol receiver and decoder module depacketizes the received serial data to obtain multiple unpacked data items, each of which is then cached. The receive channel used for data transmission is determined during link training.

[0052] The unpacking process may specifically be a process of disassembling the received serial data according to the SLVS-EC interface protocol to extract the original data.

[0053] Optionally, each unpacked data can be cached in a buffer connected to the FPGA chip, which is external to the FPGA chip. There can be multiple buffers to store multiple unpacked data. The specific storage process is: each frame of data is stored line by line in the memory.

[0054] For example, the buffer may be a third-generation double-data-rate synchronous dynamic random access memory (DDR3 SDRAM), which can transmit data twice in each clock cycle, thereby increasing the data transmission rate.

[0055] S304 , extracting each unpacked data, and performing packet processing on each unpacked data according to the eDP interface protocol corresponding to the display device, to obtain a plurality of data to be sent.

[0056] During the sending process, the eDP interface protocol sending encoding module can extract each unpacked data according to the eDP interface protocol, and perform packet processing on the unpacked data according to the eDP interface protocol to obtain multiple data to be sent.

[0057] Packet processing refers to the process of packaging data according to the eDP interface protocol for transmission over the transmission medium. Specifically, this process includes adding protocol header information and checksum information. Header information includes source address, destination address, and data length, while checksum information includes a cyclic redundancy check (CRC) code. This information helps the receiver correctly identify and process the data.

[0058] S305. Send each data to be sent to the eDP interface protocol serial deserialization module in the FPGA chip through the corresponding sending channel, and the eDP interface protocol serial deserialization module serializes each data to be sent and outputs it to the display device according to the eDP interface protocol.

[0059] Specifically, the eDP interface protocol transmission encoding module sends each data to be transmitted to the eDP interface protocol serial deserialization module through the corresponding transmission channel. The transmission channel used for transmitting data is determined by link training. The eDP interface protocol transmission encoding module can be configured as a physical layer transmission mode and an application layer transmission module.

[0060] Specifically, the eDP interface protocol serialization and deserialization module encodes and serializes the data to be transmitted from each transmission channel and outputs it to the display device through the eDP interface according to the eDP interface protocol. The serialization process may include 8b10b encoding. 8b10b encoding is a technology that encodes 8-bit data into 10-bit data, which is used to ensure the reliability and stability of data transmission in high-speed serial communication.

[0061] Optionally, the eDP interface may be a Transceiver Quad transmitter resource, and the eDP interface protocol serial deserialization module may be configured as a physical layer receiving mode of the eDP interface protocol.

[0062] In this embodiment, the data transmission link in the FPGA chip is trained according to the configuration parameters sent by the display device, thereby ensuring the data transmission quality and efficiency. After the training is completed, the data to be transmitted is received, and it is cached after being unpacked according to the SLVS-EC interface protocol. During the transmission process, each extracted unpacked data is packaged according to the eDP interface protocol, and each data to be sent is sent to the eDP interface protocol serial deserialization module through the transmission channel. The eDP interface protocol serial deserialization module serializes each data to be sent and outputs it to the display device according to the eDP interface protocol. This process is executed based on the FPGA chip and is not limited to the SLVS-EC interface protocol of the SLVS-EC interface of the acquisition device and the eDP interface protocol of the eDP interface of the display device, so it has high flexibility. In addition, this embodiment does not involve other chips for data transmission, so the cost is relatively low.

[0063] Next, refer to Figure 4 The specific steps of receiving the configuration parameters sent by the display device in the above step S301 are introduced. Figure 4 This is a flow chart of receiving a configuration request provided in an embodiment of the present application.

[0064] S401 , detecting a hot plug signal of a display device.

[0065] Specifically, the hot plug detection module may detect a hot plug signal sent by the display device through the hot plug interface.

[0066] Among them, when the display device and the FPGA chip are in a hot-swappable state, the voltage may be unstable, thereby damaging the circuit inside the device. When not in a hot-swappable state, the display device and the FPGA chip are effectively connected, and the display device generates and sends a hot-swappable signal.

[0067] S402: Determine whether the display device is in a valid connection state according to the hot plug signal.

[0068] Specifically, if a hot plug signal is received, the display device and the FPGA chip are in an effectively connected state; if no hot plug signal is received, the display device and the FPGA chip are not connected.

[0069] S403: If yes, receive the configuration parameters sent by the display device.

[0070] Specifically, if yes, the hot-plug detection module may send confirmation information to the main control module, so that the main control module receives the configuration parameters sent by the display device.

[0071] Optionally, when it is determined that the display device and the FPGA chip are in an effectively connected state, it can be ensured that the acquisition device can normally send the data to be transmitted to the display device through the FPGA chip.

[0072] In this embodiment, by detecting the hot plug signal, it is determined whether the configuration parameters sent by the display device are received, thereby improving system availability and flexibility and reducing downtime.

[0073] After introducing how to receive the configuration parameters sent by the display device, the following describes the specific steps of how to perform link training on the data transmission link in the FPGA chip according to the configuration parameters in the above step S302.

[0074] Optionally, acquisition parameters of the acquisition device are determined according to the display parameters, and the acquisition parameters are sent to the acquisition device.

[0075] Specifically, the auxiliary channel request module obtains configuration parameters sent by the acquisition device through the auxiliary interface and sends the configuration parameters to the main control module. The main control module determines the acquisition parameters of the acquisition device based on the display parameters in the configuration parameters. Exemplarily, the acquisition parameters of the acquisition device can be determined by enumeration or random selection.

[0076] Optionally, link training is performed according to the configuration parameters and the acquisition parameters to determine at least one sending channel and at least one receiving channel.

[0077] Specifically, the acquisition device sends training data to the SLVS-EC interface based on acquisition parameters, so that the training data is transmitted based on the receiving and transmitting channels represented by the acquisition data. After receiving the training data, the display device detects the quality of the training data and generates a link status based on the detection results. The link status and display parameters are sent to the main control module as configuration parameters. The main control module then adjusts the acquisition parameters based on the link status in the configuration parameters until the link status represents the optimal data quality, completing the link training. The final determined acquisition parameters are used by the acquisition device to transmit the data to be transmitted.

[0078] It's worth noting that during data transmission, the auxiliary channel request module can periodically request configuration parameters, allowing the main control module to continuously monitor the link status determined by the display device and dynamically adjust signal parameters as needed to address changes in link quality. Specifically, if the link status indicates a degradation in link quality or an error, the link training process can be restarted to restore the data transmission link to an optimal transmission state.

[0079] After link training is completed, the following describes how to perform data transmission under different protocols through the data transmission link.

[0080] In the above step S303, the specific steps of unpacking the data to be transmitted according to the SLVS-EC interface protocol corresponding to the acquisition device to obtain a plurality of unpacked data are as follows.

[0081] Optionally, the data to be transmitted is serialized according to the SLVS-EC interface protocol to obtain serial data.

[0082] Specifically, the SLVS-EC interface protocol serial deserialization module receives data to be transmitted from the SLVS-EC interface. The SLVS-EC interface may be a Transceiver Quad receiver resource. The SLVS-EC interface protocol serial deserialization module may be configured in a physical layer receive mode of the SLVS-EC interface protocol.

[0083] The SLVS-EC interface protocol serial deserialization module serializes the data to be transmitted, that is, converts the parallel data to be transmitted from a parallel format to a serial format so as to be transmitted in the transmission channel.

[0084] Optionally, the serial data is disassembled to obtain a plurality of unpacked data.

[0085] Specifically, the SLVS-EC interface protocol serial deserialization module distributes the serial data to the corresponding receiving channel, so that the receiving channel sends the serial data to the SLVS-EC interface protocol receiving and decoding module. Transmitting data through at least one receiving channel can increase data transmission rate and bandwidth.

[0086] The SLVS-EC interface protocol receiving and decoding module can be configured as a physical layer receiving mode and an application layer receiving module. Specifically, the physical layer receiving mode is used to sort and splice data transmitted by each receiving channel. The application layer receiving mode is used to generate clock information required by the application based on the timing sequence and process the spliced ​​data in the physical layer receiving mode to obtain multiple unpacked data. The multiple unpacked data can be the original data after disassembly, that is, the data collected by the acquisition device. For example, the multiple unpacked data can be individual frames of image data in the video data.

[0087] In this embodiment, the data to be transmitted is serialized according to the SLVS-EC interface protocol to obtain serial data, and then the serial data is disassembled to obtain unpacked data, so that the data to be transmitted is parsed according to the SLVS-EC interface protocol data so that the cache module can store the unpacked data.

[0088] As an optional implementation, before the above step S304, that is, before packaging the unpacked data according to the eDP interface protocol corresponding to the display device, the following steps can also be performed to deal with the situation where the frame rate of the display device and the frame rate of the acquisition device do not match.

[0089] Optionally, based on a preset frame rate of the display device and a preset frame rate of the acquisition device, frame deletion and supplementation processing is performed on the plurality of unpacked data.

[0090] Specifically, the frame rate of the display device and the frame rate of the acquisition device can be pre-set and will not change during the data transmission process. If the frame rate of the display device is different from the frame rate of the acquisition device, the display device may not be able to properly display the data sent by the acquisition device. Therefore, the cache module can delete or add frames to the multiple unpacked data and send them to the eDP interface protocol sending encoding module, so that the eDP interface protocol sending encoding module can package each unpacked data according to the eDP interface protocol corresponding to the display device.

[0091] As another optional implementation, after the SLVS-EC interface protocol receiving and decoding module determines multiple unpacked data, it may perform frame deletion or frame addition processing on the multiple unpacked data and store the processed data in a buffer.

[0092] In this embodiment, multiple unpacked data are subjected to frame deletion and supplementation processing based on the frame rate of the display device and the frame rate of the acquisition device, so that the frame rate of the data received by the display device matches the frame rate of the data sent by the acquisition device, thereby displaying the data transmitted by the FPGA chip.

[0093] Next, how to perform frame deletion and padding processing on multiple unpacked data in the above steps is introduced.

[0094] Optionally, if the frame rate of the display device is higher than the frame rate of the acquisition device, frame interpolation processing is performed on the multiple unpacked data.

[0095] Specifically, the difference between the frame rate of the display device and the frame rate of the acquisition device is calculated, and frame interpolation processing is performed on multiple unpacked videos based on the difference. For example, if a piece of unpacked data is a frame of data and the frame rate of the display device is twice the frame rate of the acquisition device, it is necessary to copy each piece of unpacked data and insert it after the current data position to implement frame interpolation processing.

[0096] Optionally, if the frame rate of the display device is lower than the frame rate of the acquisition device, frame deletion processing is performed on the multiple unpacked data.

[0097] Specifically, the difference between the frame rate of the display device and the frame rate of the acquisition device is calculated, and frames are deleted from multiple unpacked videos based on the difference. For example, if a piece of unpacked data is a frame of data and the frame rate of the display device is half the frame rate of the acquisition device, the unpacked data is filtered according to a preset strategy, retaining half of the unpacked data. The preset strategy may be to select every other piece of unpacked data.

[0098] In this embodiment, by determining whether to perform frame addition or frame deletion on the plurality of unpacked data according to the frame rate of the display device and the frame rate of the acquisition device, the data frame rates of the display device and the acquisition device are matched.

[0099] Next, the specific steps of performing packet processing on each unpacked data in the above step S304 to obtain a plurality of data to be sent are introduced.

[0100] Optionally, each unpacked data is packaged.

[0101] Specifically, the eDP interface protocol sending encoding module packages the unpacked data according to the eDP interface protocol to obtain processed data.

[0102] Optionally, the processed data is segmented according to a transmission channel, and a skew code is added to each segment of data to obtain a plurality of data to be transmitted, wherein the skew code added to each unpacked data is different.

[0103] Specifically, the eDP interface protocol sending encoding module adds a skew code to each segment of data to obtain multiple data to be sent.

[0104] Optionally, different skew codes are added to each segment of data so that each channel transmits data in a staggered manner and does not send data at the same time, thereby avoiding interference between the transmission channels.

[0105] In this embodiment, by adding skew codes to each segment of data, interference between transmission channels during data transmission is avoided, thereby ensuring transmission stability.

[0106] As an optional implementation, the FPGA-based SLVS-EC to eDP interface conversion method further includes the following steps: when no data to be transmitted sent by the acquisition device is received within a preset time, setting the current state to a sleep state.

[0107] Optionally, when no data to be transmitted is received from the acquisition device within a preset time, the current state can be set to a dormant state by controlling the gating and partial re-control of the clock module.

[0108] In addition, the clock module is used to synchronize data and control signals, provide timing signals for each functional module, and ensure stable data transmission.

[0109] In this embodiment, by setting the current state to a sleep state when no data to be transmitted from the acquisition device is received within a preset time, power consumption is reduced.

[0110] Optionally, in the FPGA chip, the reset module is used to reset all logic modules after power-on, so that each logic module has an accurate initialization state, and reset related logic modules in time for abnormal situations that occur during the processing process.

[0111] An embodiment of the present application further provides an FPGA chip, which is used to execute the above-mentioned FPGA-based SLVS-EC to eDP interface conversion method steps to transmit data from the acquisition device to the display device.

[0112] An embodiment of the present application also provides a video transmission system, which includes the above-mentioned FPGA chip, an acquisition device and a display device.

[0113] The FPGA chip is connected to a data acquisition device and a display device. The data acquisition device is used to collect data and send the collected data to the FPGA chip. The FPGA chip is used to transmit the data from the data acquisition device to the display device. The display device is used to display the data transmitted by the FPGA chip.

[0114] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system and device described above can refer to the corresponding process in the method embodiment, and will not be repeated in this application. In the several embodiments provided in this application, it should be understood that the disclosed system, device and method can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation. For example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0115] In addition, the functional units in the various embodiments of the present application can be integrated into a single processing unit, each unit can exist physically separately, or two or more units can be integrated into a single unit. If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in the various embodiments of the present invention. The aforementioned storage medium includes various media that can store program code, such as a USB flash drive, a mobile hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0116] The above is only a specific implementation method of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed in this application, which should be covered by the protection scope of the present application.

Claims

1. A method for converting SLVS-EC to eDP interface based on FPGA, characterized in that: The FPGA-based SLVS-EC to eDP interface conversion method is applied to a field programmable gate array (FPGA) chip, and the method includes: receiving configuration parameters sent by a display device, wherein the configuration parameters include display parameters of the display device; Performing link training on the data transmission link in the FPGA chip according to the configuration parameters to determine at least one transmitting channel and at least one receiving channel; receiving the data to be transmitted sent by the acquisition device through the corresponding receiving channel, unpacking the data to be transmitted according to the SLVS-EC interface protocol corresponding to the acquisition device to obtain multiple unpacked data, and caching each unpacked data; Extracting each of the unpacked data, and performing packet processing on each of the unpacked data according to the eDP interface protocol corresponding to the display device to obtain a plurality of data to be sent; Each of the data to be sent is sent to the eDP interface protocol serial deserialization module in the FPGA chip through the corresponding sending channel, and the eDP interface protocol serial deserialization module serializes each of the data to be sent and outputs it to the display device according to the eDP interface protocol.

2. The FPGA-based SLVS-EC to eDP interface conversion method according to claim 1, characterized in that: The receiving configuration parameters sent by the display device includes: detecting a hot plug signal of the display device; determining whether the display device is in a valid connection state according to the hot plug signal; If yes, the configuration parameters sent by the display device are received.

3. The FPGA-based SLVS-EC to eDP interface conversion method according to claim 1, characterized in that: The performing link training on the data transmission link in the FPGA chip according to the configuration parameters includes: Determining acquisition parameters of the acquisition device according to the display parameters, and sending the acquisition parameters to the acquisition device; Link training is performed according to the configuration parameters and the acquisition parameters to determine at least one sending channel and at least one receiving channel.

4. The FPGA-based SLVS-EC to eDP interface conversion method according to claim 1, characterized in that: The unpacking of the data to be transmitted according to the SLVS-EC interface protocol corresponding to the acquisition device to obtain a plurality of unpacked data includes: Serializing the data to be transmitted according to the SLVS-EC interface protocol to obtain serial data; The serial data is disassembled to obtain a plurality of unpacked data.

5. The FPGA-based SLVS-EC to eDP interface conversion method according to claim 1, characterized in that: Before packaging the unpacked data according to the eDP interface protocol corresponding to the display device, the method further includes: Based on the preset frame rate of the display device and the frame rate of the acquisition device, frame deletion and supplementation processing is performed on the plurality of unpacked data.

6. The FPGA-based SLVS-EC to eDP interface conversion method according to claim 5, characterized in that: The deleting and supplementing frame processing of the plurality of unpacked data based on the preset frame rate of the display device and the frame rate of the acquisition device includes: If the frame rate of the display device is higher than the frame rate of the acquisition device, performing frame filling processing on the plurality of unpacked data; If the frame rate of the display device is lower than the frame rate of the acquisition device, frame deletion processing is performed on the multiple unpacked data.

7. The FPGA-based SLVS-EC to eDP interface conversion method according to claim 1, characterized in that: The unpacked data are packaged to obtain a plurality of data to be sent, including: Packaging the unpacked data; The processed data is segmented according to a transmission channel, and a skew code is added to each segment of data to obtain the plurality of data to be transmitted, wherein the skew codes added to each unpacked data are different.

8. The FPGA-based SLVS-EC to eDP interface conversion method according to claim 1, characterized in that: The method further comprises: When the data to be transmitted sent by the acquisition device is not received within a preset time, the current state is set to a dormant state.

9. An FPGA chip, characterized in that: The FPGA chip is used to execute the steps of the FPGA-based SLVS-EC to eDP interface conversion method as described in any one of claims 1 to 8 to transmit data from the acquisition device to the display device.

10. A video transmission system, characterized in that: The video transmission system comprises: the FPGA chip, the acquisition device and the display device according to claim 9; The FPGA chip is communicatively connected to the acquisition device and the display device respectively; The acquisition device is used to collect data and send the collected data to the FPGA chip; The FPGA chip is used to transmit the data from the acquisition device to the display device; The display device is used to display the data transmitted by the FPGA chip.

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