A chip-level current sensor packaging method and Hall chip structure

Abstract

A chip-level current sensor packaging method and a Hall chip structure, wherein the chip-level current sensor packaging method packages an isolating plate, a lead frame, bonding wires, and a Hall chip structure through a plastic package. The side of the Hall chip structure where the Hall element is located is defined as the back of the Hall chip structure, and the pads in the Hall chip structure are located on the front of the Hall chip structure. The shape of the isolating plate is circular. First, the isolating plate is bonded and fixed to the lead frame, and then the Hall chip structure is bonded to the surface of the isolating plate, and then the pads are connected to the secondary side pins of the lead frame through bonding wires. Finally, a plastic package is used to package the Hall chip structure, isolating plate, bonding wires, and lead frame. The Hall chip structure of the present invention can make the lead frame as close as possible during packaging, and is not limited to the Hall chip structure to reduce the risk of insulation withstand voltage failure, and has the performance advantages of high precision and low noise.

Description

Technical Field

[0001] The present invention relates to the technical field of Hall devices, and in particular to a chip-level current sensor packaging method and a Hall chip structure. Background Art

[0002] Chip-level current sensors, with their advantages of miniaturization, high precision, and low cost, are gradually replacing traditional module-level current sensor products. The chip-level current sensor packaging structure primarily includes a Hall effect chip, lead frame, spacer, adhesive, molding compound, bonding wires, and other components. The lead frame includes the primary busbar and secondary pins.

[0003] Existing chip-level current sensors have the following disadvantages: the closer the Hall element of the Hall chip is to the sensor's busbar frame, the lower the detection noise and the higher the accuracy. Therefore, flip-chip Hall package chips have better electrical performance than face-up soldering. However, existing flip-chip technology is limited by chip area. When the Hall element and solder joints need to be aligned simultaneously with the primary busbar frame groove and the secondary pin solder joints, the distance between the primary and secondary sides is too small, which can easily lead to insulation breakdown. In addition, the isolation plate of existing chip-level current sensors is generally rectangular or fan-shaped. As an organic film material bonded to the plastic package, the current shape has problems such as large area and right angles, which will reduce the bonding strength between the isolation plate and the plastic package and easily lead to delamination.

[0004] Therefore, in view of the shortcomings of the existing technology, it is necessary to provide a chip-level current sensor packaging method and a Hall chip structure to solve the shortcomings of the existing technology. Summary of the Invention

[0005] The first object of the present invention is to avoid the shortcomings of the prior art and provide a chip-level current sensor packaging method that can improve detection accuracy and ensure safe insulation, withstand voltage, distance, and reliability.

[0006] The above-mentioned purpose of the present invention is achieved through the following technical measures:

[0007] A chip-level current sensor packaging method is provided. A plastic encapsulation body is used to encapsulate an isolating plate, a lead frame, bonding wires, and a Hall chip structure. Unlike conventional Hall chip structures, the present invention defines the side of the Hall chip structure where the Hall element is located as the back side of the Hall chip structure, and the solder pads in the Hall chip structure are located on the front side of the Hall chip structure. Unlike conventional rectangular or fan-shaped isolating plate structures, the isolating plate of the present invention has a circular structure. This circular isolating plate design facilitates the diffusion of die-bonding glue and facilitates complete glue filling and coverage. During the plastic encapsulation process, each contact point between the circular isolating plate and the plastic encapsulation body is subjected to uniform force, making warping less likely and improving the bonding strength between the plastic encapsulation body and the isolating plate after curing.

[0008] The chip-level current sensor packaging method of the present invention first adheres and fixes the isolation sheet to the primary busbar of the lead frame, then adheres the Hall chip structure to the surface of the isolation sheet, and then connects the pad to the secondary pin of the lead frame through the bonding wire; finally, the Hall chip structure, the isolation sheet, the bonding wire and the lead frame are packaged using the plastic package.

[0009] Preferably, the above-mentioned primary busbar is provided with a top structure for carrying the Hall chip structure and realizing the electromagnetic conversion function, and a bottom structure for carrying large current to reduce power consumption and realize heat dissipation. The top structure is integrally connected to the bottom structure; all or most of the Hall chip structure is located directly above the top structure.

[0010] Preferably, the area of ​​the top structure is smaller than the area of ​​the bottom structure.

[0011] Preferably, the primary busbar is further provided with a slot, which extends from the edge of the bottom structure to the top structure, and the end of the slot is located inside the top structure.

[0012] The side that integrally connects the top structure and the bottom structure defines a lower side, and the groove divides the lower side into a left lower side and a right lower side.

[0013] Define the length perpendicular to the lower side as the height of the top structure, define the height of the top structure as a, define the length of the lower left side as b, and define the length of the lower right side as c, and a=b=c.

[0014] Preferably, the end of the slot is in an arc shape, and the end of the slot is defined as an arc slot.

[0015] Preferably, the strongest point of the magnetic field signal to be detected of the primary busbar is located inside the circular arc slot, and the Hall element is located directly above the circular arc slot.

[0016] Preferably, the bottom edge structure is provided with a plurality of glue locking holes.

[0017] The bottom edge structure is divided into a high current density area and a low current density area according to the current density, and the glue locking hole is located in the low current density area.

[0018] Preferably, the high current density region is the region covered by projection from the top structure toward the lower side, and the low current density region is located on the left and right sides of the bottom structure.

[0019] Preferably, the above-mentioned glue locking holes are provided in two groups, and the two groups of glue locking holes are symmetrically distributed on both sides of the bottom edge structure.

[0020] Each group of glue locking holes is provided with 3.

[0021] Preferably, the above-mentioned glue locking holes are all circular.

[0022] In the same group of glue locking holes, the lengths of the lines connecting the centers of any two of the glue locking holes are equal.

[0023] Preferably, the diameter of the glue locking hole is equal to the thickness of the lead frame.

[0024] The width of the Hall chip structure is defined as d, and a=d.

[0025] Preferably, the preparation method of the Hall chip structure is carried out by the following steps:

[0026] S1. Using a silicon-based Hall wafer as a raw material, the silicon-based Hall wafer has a Hall element, a pre-pad, a wafer substrate, and a passivation layer, wherein the Hall element and the pre-pad are located on the surface of the wafer substrate, the surface where the Hall element and the pre-pad are located is defined as the front side of the silicon-based Hall wafer, and the passivation layer is stacked on the front side of the silicon-based Hall wafer, and then proceeding to S2;

[0027] S2, bonding a bare silicon wafer to the surface of the passivation layer by wafer bonding, and then proceeding to S3;

[0028] S3, thinning the wafer substrate, and proceeding to S4;

[0029] S4, exposing the pre-pad through a TSV process to obtain a TSV hole, and then proceeding to S5;

[0030] S5, entering wafer tape-out processing to manufacture a signal conditioning chip, then interconnecting the signal line with the Hall element through the TSV hole, and forming the pad on the front side of the silicon-based Hall wafer, and entering S6;

[0031] S6. Thinning the bare silicon wafer to obtain the Hall chip structure.

[0032] A second object of the present invention is to provide a Hall chip structure that overcomes the shortcomings of the prior art and can improve detection accuracy during packaging while ensuring safe insulation, withstand voltage, and reliability.

[0033] The above-mentioned purpose of the present invention is achieved through the following technical measures:

[0034] Provided is a Hall chip structure used in the above chip-level current sensor packaging method.

[0035] The present invention provides a chip-level current sensor packaging method and Hall chip structure, wherein the chip-level current sensor packaging method encapsulates an isolating plate, a lead frame, a bonding wire, and a Hall chip structure through a plastic package, wherein the side where the Hall element in the Hall chip structure is located is defined as the back side of the Hall chip structure, and the pad in the Hall chip structure is located on the front side of the Hall chip structure; the shape of the isolating plate is circular. First, the isolating plate is bonded and fixed to the primary busbar of the lead frame, then the Hall chip structure is bonded to the surface of the isolating plate, and then the pad is connected to the secondary pin of the lead frame through the bonding wire; finally, the Hall chip structure, the isolating plate, the bonding wire, and the lead frame are encapsulated using the plastic package. The Hall element of the Hall chip structure of the present invention is located on the back side of the Hall chip structure, and the pad is located on the front side of the Hall chip structure. During packaging, the lead frame can be as close as possible, and the risk of insulation withstand voltage failure is reduced without being limited by the Hall chip structure. It has the performance advantages of high precision and low noise, and the spacing design between the primary busbar and the secondary pin is not affected by the size of the Hall chip structure. The separator of the present invention can avoid the delamination problem while ensuring the insulation performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The present invention is further described with reference to the accompanying drawings, but the contents in the accompanying drawings do not constitute any limitation to the present invention.

[0037] Figure 1 This is a schematic diagram of a chip-level current sensor obtained by the chip-level current sensor packaging method of the present invention.

[0038] Figure 2 This is a schematic diagram of the primary busbar.

[0039] Figure 3 Schematic diagram of the top and bottom structures in the primary busbar.

[0040] Figure 4 Schematic diagram of the top structure.

[0041] Figure 5 Schematic diagram of the high current density area and low current density area of ​​the primary busbar.

[0042] Figure 6 This is a schematic diagram of the process steps S1 to S5 in the method for preparing a Hall chip structure.

[0043] Figure 7 This is a schematic diagram of the process from S5 to S6 in the method for preparing the Hall chip structure.

[0044] Figure 8 Schematic diagram of the isolation sheet and primary busbar.

[0045] Figure 9The exploded diagram of the chip-level current sensor is obtained by the chip-level current sensor packaging method.

[0046] exist Figures 1 to 9 Including:

[0047] Plastic package 10,

[0048] Solid crystal glue 20,

[0049] Lead frame 30,

[0050] Secondary pin 31,

[0051] Primary busbar 32, top structure 321, bottom structure 322, slot 323, arc slot 324, glue lock hole 325, high current density area 326, low current density area 327, lower side 328,

[0052] Bonding wire 40,

[0053] Hall chip structure 50,

[0054] Silicon-based Hall wafer 51, Hall element 511, pre-pad 512, wafer substrate 513, passivation layer 514,

[0055] Bare silicon wafer 52, TSV hole 53, pad 54, signal conditioning circuit module 55, dielectric layer 56,

[0056] Spacer 60. DETAILED DESCRIPTION

[0057] The technical solution of the present invention is further described with reference to the following examples.

[0058] Example 1

[0059] A chip-level current sensor packaging method, such as Figure 1 As shown, the isolation sheet 60, the lead frame 30, the bonding wire 40 and the Hall chip structure 50 are packaged by the plastic package 10, and the side where the Hall element 511 in the Hall chip structure 50 is located is defined as the back side of the Hall chip structure 50, and the pad 54 in the Hall chip structure 50 is located on the front side of the Hall chip structure 50.

[0060] It should be noted that the Hall element 511 in the Hall chip structure 50 of the present invention is located on the back of the Hall chip structure 50 , while the pad 54 is located on the front of the Hall chip structure 50 . This structure is different from the traditional Hall chip structure.

[0061] The chip-level current sensor packaging method of the present invention first adheres and fixes the isolation sheet 60 to the primary busbar 32 of the lead frame 30, then adheres the Hall chip structure 50 to the surface of the isolation sheet 60, and then connects the pad 54 to the secondary pin 31 of the lead frame 30 through the bonding wire 40; finally, the Hall chip structure 50, isolation sheet 60, bonding wire 40 and lead frame 30 are packaged using a plastic package 10.

[0062] It should be noted that the isolation sheet 60 and the Hall chip structure 50 are bonded together by the die-bonding glue 20. The isolation sheet 60 of the present invention is used to improve the insulation isolation effect between the high current of the primary busbar 32 and the low potential of the Hall chip structure 50.

[0063] The Hall element 511 of the present invention is located on the back of the Hall chip structure 50, and the pad 54 is located on the front, thus ensuring both high detection accuracy and safe insulation withstand voltage distance.

[0064] Furthermore, the detection accuracy and reliability of chip-level current sensors are important indicators for evaluating product quality. During product development, these design elements often balance each other. This is particularly true for the lead frame 30 structure. The present invention utilizes an innovative structural design of the primary busbar 32 to ensure high detection accuracy while maintaining good reliability. The details are as follows:

[0065] like Figure 2 and Figure 3 As shown, the primary busbar 32 is provided with a top structure 321 for supporting the Hall chip structure 50 and realizing the electromagnetic conversion function, and a bottom structure 322 for carrying large currents to reduce power consumption and achieve heat dissipation. The top structure 321 is integrally connected to the bottom structure 322; all or most of the Hall chip structure 50 is located directly above the top structure 321. The area of ​​the top structure 321 is smaller than that of the bottom structure 322.

[0066] It should be noted that the majority of the Hall chip structure 50 mentioned in the present invention is located within the range of the top structure 321, which means that when more than 50% of the area of ​​the Hall chip structure 50 is located directly above the top structure 321, most of it is located within the range of the top structure 321.

[0067] like Figure 5 As shown, the primary busbar 32 is further provided with a slot 323 , which extends from the edge of the bottom structure 322 to the top structure 321 .

[0068] The end of slot 323 is located inside top structure 321 and is arc-shaped, defining the end of slot 323 as arc slot 324. The strongest point of the magnetic field signal to be detected on primary busbar 32 is located inside arc slot 324, and Hall element 511 is located directly above arc slot 324.

[0069] The side that integrally connects the top structure 321 and the bottom structure 322 is defined as the lower side 328. The arc groove 324 separates the lower side 328 into a left lower side 328 and a right lower side 328. The length perpendicular to the lower side 328 is defined as the height of the top structure 321, the height of the top structure 321 is defined as a, the length of the left lower side 328 is defined as b, and the length of the right lower side 328 is defined as c. If a=b=c, Figure 4 The width of the Hall chip structure 50 is defined as d, and a=d. The maximum width of the top structure 321 is defined as A, and the maximum width of the bottom structure 322 is defined as B, and B / 5≤A≤B / 3.

[0070] It should be noted that the secondary pin 31 serves only as a signal output terminal, while the primary busbar 32 carries high current, carries the Hall effect chip, and implements electromagnetic conversion. The primary busbar 32 is the core functional component. The top structure 321 is much smaller than the bottom structure 322. The top structure 321 has the highest current density, and the magnetic field strength is the highest within the slot 323. The magnetic field signal to be detected is strongest within the arc slot 324, and the Hall effect element 511 is located directly above the arc slot 324. Here, the smaller the metal width, the greater the current density and the stronger the magnetic field signal to be detected.

[0071] In the prior art, the overly narrow metal width affects the reliability of chip bonding. Therefore, in the present invention, the height of the top structure 321, the length of the lower left side 328, and the length of the lower right side 328 are all equal. As a result, the magnetic field generated in all directions by the annular metal of the top structure 321 is symmetrical about the inner center of the arc groove 324, thereby improving the detection accuracy of the Hall element 511 and reducing linearity error. Moreover, since this location is the main loading area of ​​the Hall chip structure 50, the height of the top structure 321, the length of the lower left side 328, and the length of the lower right side 328 are all equal, making the lateral dimension approximately twice the longitudinal dimension, which conforms to the aspect ratio of the Hall chip structure 50. In addition, the a / b / c of ​​the present invention is equal to the width dimension of the Hall chip structure 50, which can ensure that the Hall chip structure 50 is fully bonded to the top structure 321 and improve the reliability of the packaging process.

[0072] like Figure 2As shown, the bottom edge structure 322 of the present invention is provided with a plurality of glue locking holes 325; the bottom edge structure 322 is divided into a high current density area 326 and a low current density area 327 according to the current density, and the glue locking holes 325 are located in the low current density area 327; Figure 5 As shown, the high current density region 326 is the region covered by the projection from the top structure 321 toward the lower side 328 , and the low current density region 327 is located on the left and right sides of the bottom structure 322 .

[0073] It should be noted that the low current density region 327 is the area of ​​the bottom edge structure 322 excluding the high current density region 326. From the perspective of chip-level current sensor performance, the bottom edge structure 322 is designed to provide low power consumption and high heat dissipation under high current conditions, requiring a large structural area. From the perspective of chip-level current sensor reliability, the large metal block in the bottom edge structure 322 can easily cause package delamination. To address this issue, the present invention adds a glue lock hole 325 structure to the bottom edge structure 322 to improve delamination.

[0074] Because the glue lock hole 325 reduces the metal copper area of ​​the bottom structure 322, interferes with the current path, and affects the magnetic field signal to be detected, the present invention is based on the current density distribution within the primary busbar 32 under actual working conditions. The current density is maximum near the Hall detection point and the groove in the frame, which is the high current density area 326 and gradually weakens to the surrounding area. The present invention defines this area as the high current density area 326. The high current density area 326 is the area covered by the lower projection of the top structure 321. The area outside the high current density area 326 is the low current density area 327. The glue lock hole 325 of the present invention is located in the area with weaker current density, that is, the low current density area 327, so that the impact of the glue lock hole 325 on the electromagnetic field is minimized.

[0075] Two groups of adhesive holes 325 are symmetrically distributed on either side of the bottom structure 322. Each group of adhesive holes 325 contains three adhesive holes. All of the adhesive holes 325 are circular, and within each group, the length of the line connecting the centers of each of the two adhesive holes 325 is equal. The diameter of the adhesive holes 325 of the present invention is equal to the thickness of the lead frame 30.

[0076] It should be noted that since the plastic encapsulation body 10 passes through the locking holes 325 after plastic encapsulation, when external stress acts on the frame, stress is generated between the plastic encapsulation body 10 and the lead frame 30. Therefore, in the same group of locking holes 325 of the present invention, the length of the line connecting the centers of the circles of two locking holes 325 is equal, so that the stress of the plastic encapsulation body 10 and the lead frame 30 in the three locking holes 325 is balanced, thereby improving the reliability of the package.

[0077] like Figure 6 and Figure 7As shown, the preparation method of the Hall chip structure 50 of the present invention is carried out by the following steps:

[0078] S1. Use a silicon-based Hall wafer 51 as a raw material. The silicon-based Hall wafer 51 has a Hall element 511, a pre-welding pad 512, a wafer substrate 513, and a passivation layer 514. The Hall element 511 and the pre-welding pad 512 are located on the surface of the wafer substrate 513. The surface where the Hall element 511 and the pre-welding pad 512 are located is defined as the front surface of the silicon-based Hall wafer 51. The passivation layer 514 is stacked on the front surface of the silicon-based Hall wafer 51. Then proceed to S2.

[0079] S2. Bond a bare silicon wafer 52 to the surface of the passivation layer 514 by wafer bonding, and then proceed to S3.

[0080] S3, thinning the wafer substrate 513, and proceeding to S4;

[0081] S4, expose the pre-solder pad 512 through the TSV process and obtain the TSV hole 53, and then proceed to S5;

[0082] S5, entering wafer tape-out processing to manufacture signal conditioning chips, then interconnecting the signal lines with the Hall element 511 through the TSV holes 53, and forming pads 54 on the front side of the silicon-based Hall wafer 51, and entering S6;

[0083] S6. Thinning the bare silicon wafer 52 to obtain the Hall chip structure 50.

[0084] It should be noted that the wafer taping process for manufacturing a signal conditioning chip is to prepare a signal conditioning circuit module 55, etc., and the wafer taping process for manufacturing a signal conditioning chip in the present invention is a conventional process in the art and is not the focus of the present invention, and will not be described in detail here. The silicon-based Hall wafer of the present invention is a silicon-based Hall wafer obtained by conventional processing, and the preparation method of the silicon-based Hall wafer is also common knowledge in the art and will not be described in detail here.

[0085] In actual use, the chip-scale current sensor packaging method of the present invention uses a typical thickness of 25 μm for the die-bonding adhesive 20 and 50 μm for the spacer 60. Therefore, the closest distance between the Hall element 511 and the primary busbar 32 is 7 μm. This compares to 300 μm for conventional flip-chip soldering. This significantly reduces the distance between the Hall element 511 and the primary busbar 32. Furthermore, compared to conventional flip-chip soldering, the present invention eliminates the safety distance restriction between the primary busbar 32 and the secondary pin 31, ensuring that insulation withstand voltage performance is not compromised.

[0086] like Figure 8 and Figure 9As shown, the spacer 60 of the present invention is a circular structure; the top structure 321 is entirely located directly above the spacer 60. Furthermore, the circular spacer 60 of the present invention is completely different from conventional rectangular or fan-shaped spacers. Its circular structure facilitates the diffusion of the die-bonding adhesive, facilitating complete filling and coverage. During the encapsulation process, each contact point between the circular spacer and the encapsulated body is evenly stressed, making warping less likely and improving the bonding strength between the encapsulated body and the spacer after curing.

[0087] It should be noted that the addition of the spacer 60 in the present invention introduces the risk of reliability delamination, such as delamination between the lead frame 30 and the spacer 60, and between the spacer 60 and the plastic package 10. Therefore, the present invention solves the delamination problem while ensuring insulation performance by designing the spacer 60 into a circular shape. The functions of the circular spacer 60 are: 1. Improving the full coverage of the glue and optimizing the impact of the mold flow on the spacer 60, thereby reducing the delamination risk; 2. Under the same insulation withstand voltage performance, the circular spacer 60 has a more compact design area than the rectangular spacer 60, which reduces the area of ​​the heterogeneous film in the package and can effectively improve the delamination problem.

[0088] The circular separator 60 of the present invention does not produce delamination for the following reasons:

[0089] 1. The spacer 60 is glued to the surface of the lead frame 30. Because the rectangular spacer 60 has right-angled corners, glue is difficult to fill, which easily forms voids at the corners. The edges of the circular spacer 60 are more consistent with the glue diffusion trajectory, thereby improving the full coverage of glue and optimizing the impact of mold flow on the spacer 60, thereby reducing the risk of delamination.

[0090] 2. The isolation sheet 60 is usually wrapped by the molding compound during the mold flow process and forms a dense structure after high-temperature curing. The circular isolation sheet 60 and the molding fluid are subjected to uniform force at each contact point, making it less likely to warp or delaminate.

[0091] In this chip-scale current sensor packaging method, the Hall element 511 of the Hall chip structure 50 is located on the back of the Hall chip structure 50, and the solder pad 54 is located on the front of the Hall chip structure 50. This allows the lead frame 30 to be as close as possible during packaging, while also being independent of the Hall chip structure 50, thus preventing insulation withstand voltage failure. This method offers the advantages of high precision and low noise. Furthermore, the spacing between the primary busbar 32 and the secondary pins 31 is not affected by the size of the Hall chip structure 50. The spacer of the present invention not only ensures insulation performance but also further resolves the delamination issue.

[0092] Example 2

[0093] A Hall chip structure 50 is provided. The Hall chip structure 50 is the Hall chip structure 50 used in the chip-level current sensor packaging method of embodiment 1.

[0094] The Hall element 511 of the Hall chip structure 50 is located on the back of the Hall chip structure 50, and the solder pad 54 is located on the front of the Hall chip structure 50. During packaging, the lead frame 30 can be made as close as possible. At the same time, it is not limited by the Hall chip structure 50, so that the insulation withstand voltage failure will not occur. It has the performance advantages of high precision and low noise, and at the same time, the distance between the primary busbar 32 and the secondary pin 31 is not affected by the size of the Hall chip structure 50.

[0095] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the scope of protection of the present invention. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the essence and scope of the technical solutions of the present invention.

Claims

1. A chip-level current sensor packaging method, characterized in that: The isolation sheet, lead frame, bonding wires and Hall chip structure are encapsulated by a plastic package, wherein the side where the Hall element in the Hall chip structure is located is defined as the back side of the Hall chip structure, and the pads in the Hall chip structure are located on the front side of the Hall chip structure; the isolation sheet is a circular structure; First, the isolation plate is bonded and fixed to the primary busbar of the lead frame, and then the Hall chip structure is bonded to the surface of the isolation plate, and then the pad is connected to the secondary pin of the lead frame through the bonding wire; finally, the Hall chip structure, the isolation plate, the bonding wire and the lead frame are encapsulated using the plastic package.

2. The chip-level current sensor packaging method according to claim 1, wherein: The primary busbar is provided with a top structure for carrying the Hall chip structure and realizing the electromagnetic conversion function, and a bottom structure for carrying large current to reduce power consumption and realize heat dissipation, and the top structure is integrally connected to the bottom structure; All or most of the Hall chip structure is located directly above the top structure; The area of ​​the top structure is smaller than the area of ​​the bottom structure.

3. The chip-level current sensor packaging method according to claim 2, wherein: The primary busbar is further provided with a slot, the slot extending from the edge of the bottom structure to the top structure, and the end of the slot is located inside the top structure; The side integrally connecting the top structure and the bottom structure defines a lower side, and the groove divides the lower side into a left lower side and a right lower side; Define the length perpendicular to the lower side as the height of the top structure, define the height of the top structure as a, define the length of the lower left side as b, and define the length of the lower right side as c, and a=b=c.

4. The chip-level current sensor packaging method according to claim 3, wherein: The end of the slot is in an arc shape, and the end of the slot is defined as an arc slot; The strongest point of the magnetic field signal to be detected of the primary busbar is located inside the circular arc slot, and the Hall element is located directly above the circular arc slot.

5. The chip-level current sensor packaging method according to claim 3, wherein: The bottom edge structure is provided with a plurality of glue locking holes; The bottom edge structure is divided into a high current density area and a low current density area according to the current density, and the glue locking hole is located in the low current density area; The high current density region is the region covered by projection from the top structure toward the lower side, and the low current density region is located on the left and right sides of the bottom structure.

6. The chip-level current sensor packaging method according to claim 5, wherein: There are two groups of glue locking holes, which are symmetrically distributed on both sides of the bottom edge structure; Each group of glue lock holes is provided with 3; the glue lock holes are all circular; In the same group of glue locking holes, the lengths of the lines connecting the centers of any two of the glue locking holes are equal.

7. The chip-level current sensor packaging method according to claim 6, wherein: The diameter of the glue locking hole is equal to the thickness of the lead frame.

8. The chip-level current sensor packaging method according to claim 3, wherein: The width of the Hall chip structure is defined as d, and a=d.

9. The chip-level current sensor packaging method according to any one of claims 1 to 6, characterized in that: The preparation method of the Hall chip structure is carried out by the following steps: S1. Using a silicon-based Hall wafer as a raw material, the silicon-based Hall wafer has a Hall element, a pre-pad, a wafer substrate, and a passivation layer, wherein the Hall element and the pre-pad are located on the surface of the wafer substrate, the surface where the Hall element and the pre-pad are located is defined as the front side of the silicon-based Hall wafer, and the passivation layer is stacked on the front side of the silicon-based Hall wafer, and then proceeding to S2; S2, bonding a bare silicon wafer to the surface of the passivation layer by wafer bonding, and then proceeding to S3; S3, thinning the wafer substrate, and proceeding to S4; S4, exposing the pre-pad through a TSV process to obtain a TSV hole, and then proceeding to S5; S5, entering wafer tape-out processing to manufacture a signal conditioning chip, then interconnecting the signal line with the Hall element through the TSV hole, and forming the pad on the front side of the silicon-based Hall wafer, and entering S6; S6. Thinning the bare silicon wafer to obtain the Hall chip structure.

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