Hybrid flip-flop disk including different fin size flip-flops

Abstract

A hybrid flip-flop disk includes a set of flip-flops cascaded along a scan path wherein a first subset of one or more of the flip-flops of the set includes fin field effect transistors (FinFETs) each sized to have a first number of fins, and a second subset of one or more of the triggers of the set includes FinFETs each sized to have a second number of fins, wherein the first number of fins is different from the second number of fins; and a control circuit configured to provide a control signal to the set of triggers.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to pending U.S. non-provisional application No. 18 / 156,975, filed on January 19, 2023, which is assigned to the assignee of the present application and is hereby expressly incorporated herein by reference as if fully set forth below and for all applicable purposes. Technical Field

[0003] Aspects of the present disclosure relate generally to sequential circuits, and particularly to a hybrid flip-flop disk including flip-flops (F / F) of different fin sizes. Background Art

[0004] Integrated circuits (ICs) often include a flip-flop disk to sequentially move function and / or test data to and from functional circuits (such as combinational logic). In many cases, the flip-flop disk occupies a significant portion of the IC's footprint (e.g., approximately 80% or more of the IC's area). While providing the same functionality, a reduction in the size of the flip-flop disk results in significant savings in the IC's footprint. Furthermore, the flip-flop disk also consumes a significant portion of the power consumed by the IC. Therefore, while providing the same functionality, a reduction in the power consumed by the flip-flop disk results in significant power savings for the IC. Summary of the Invention

[0005] The following content presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an exhaustive overview of all contemplated implementations and is not intended to identify key or important elements of all implementations, nor is it intended to delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description that will be presented later.

[0006] One aspect of the present disclosure relates to a hybrid flip-flop disk. The hybrid flip-flop disk includes: a set of flip-flops cascaded along a scan path, wherein a first subset of one or more of the flip-flops in the set include fin field-effect transistors (FinFETs) each sized to have a first number of fins, and a second subset of one or more of the flip-flops in the set include FinFETs each sized to have a second number of fins, wherein the first number of fins is different from the second number of fins; and a control circuit configured to provide control signals to the set of flip-flops.

[0007] Another aspect of the present disclosure relates to a wireless communication device. The wireless communication device includes: at least one antenna; a transceiver coupled to the at least one antenna; one or more signal processing cores coupled to the transceiver, wherein the one or more processing cores include a flip-flop disk, the flip-flop disk including: a set of flip-flops cascaded along a scan path, wherein a first subset of one or more of the flip-flops in the set include fin field effect transistors (FinFETs) each sized to have a first number of fins, and a second subset of one or more of the flip-flops in the set include FinFETs each sized to have a second number of fins, wherein the first number of fins is different from the second number of fins; and control circuitry configured to provide control signals to the set of flip-flops.

[0008] To accomplish the foregoing and related objectives, one or more implementations include the features fully described below and particularly pointed out in the claims. The following description and the accompanying figures set forth in detail certain illustrative aspects of one or more implementations. However, these aspects are merely indicative of a few of the various ways in which the principles of various implementations may be employed, and the description of an implementation is intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A block diagram illustrating an example trigger disk according to one aspect of the present disclosure is illustrated.

[0010] Figure 2 A schematic diagram illustrating an example trigger according to another aspect of the present disclosure is shown.

[0011] Figure 3 A block diagram illustrating an example hybrid trigger disk according to another aspect of the present disclosure is illustrated.

[0012] Figure 4 A block diagram / schematic diagram illustrating another example hybrid trigger disk according to another aspect of the present disclosure is illustrated.

[0013] Figure 5A A layout view of another example hybrid trigger tray according to another aspect of the present disclosure is illustrated.

[0014] Figure 5B A layout view of another example hybrid trigger tray according to another aspect of the present disclosure is illustrated.

[0015] Figure 6 A block diagram illustrating an example wireless communication device according to another aspect of the disclosure is illustrated. DETAILED DESCRIPTION

[0016] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details to provide a comprehensive understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0017] Figure 1 A block diagram of an example flip-flop disk 100 according to one aspect of the present disclosure is illustrated. The flip-flop disk 100 is an example sequential circuit for propagating functional and / or test data to and from one or more functional circuits 150 (e.g., combinational logic). For example, the flip-flop disk 100 can be configured to propagate functional data to one or more functional circuits or cores 150 of an integrated circuit (IC), such as a system on a chip (SOC). The flip-flop disk 100 can also be configured to propagate test data to the inputs of the one or more functional circuits 150 in a scan-in mode, and to propagate the resulting test data (obtained in a capture mode) out of the one or more functional circuits 150 in a scan-out mode.

[0018] Specifically, flip-flop disk 100 includes a set of flip-flops (F / Fs) 110-0 through 110-n-1. The set of F / Fs 110-0 through 110-n-1 is cascaded relative to test data or a scan path. For example, each of F / Fs 110-0 through 110-n-1 includes a scan-in (sin) input and a scan-out (sou) output. The sou output of an F / F is coupled to the sin input of the next adjacent F / F. For example, F / F 110-0 includes a sou output coupled to the sin input of the next adjacent F / F 110-1; F / F 110-1 includes a sou output coupled to the sin input of the next adjacent F / F 110-2; and so on, where F / F 110-n-2 (not explicitly shown) includes a sou output coupled to the sin input of the next adjacent F / F 110-n-1.

[0019] Each of the set of F / Fs 110-0 to 110-n-1 includes a data input (D) and a data output (Q). The input (D) of the set of F / Fs 110-0 to 110-n-1 is configured to receive functional and / or test data d0 to dn-1, respectively, from one or more functional circuits 150. The data output (Q) of the set of F / Fs 110-0 to 110-n-1 is configured to provide functional and / or test data q0 to qn-1 to one or more functional circuits 150.

[0020] For example, in functional mode, the set of F / Fs 110-0 to 110-n-1 may receive functional data d0 to dn-1 from one or more functional circuits 150 and provide functional data q0 to qn-1 to the one or more functional circuits 150. In scan-in mode, a pattern of test data s0 to sn-1 may be provided to the sin inputs of the set of F / Fs 110-0 to 110-n-1, respectively. The set of F / Fs 110-0 to 110-n-1 may then operate in capture mode to provide a pattern of test data q0 to qn-1 to the one or more functional circuits 150 and receive the resulting test data d0 to dn-1 from the one or more functional circuits 150. The resulting test data d0 to dn-1 may then be clocked out via the sou output of the F / F 110-n-1 in scan-out mode.

[0021] Each of the set of F / Fs 110-0 to 110-n-1 includes a signal processor configured to receive and output complementary shift signals sft and sft, respectively. For example, the complementary shift signals sft and can be provided to the left complementary shift port of F / F 110-0. The right complementary shift ports of F / Fs 110-0 to 110-n-2 are coupled to the left complementary shift ports of F / Fs 110-1 to 110-n-1, respectively. Therefore, the complementary shift signal sft and the complementary shift signal sft provided to the left complementary shift port of F / F 110-0 are respectively coupled to the left complementary shift port of F / F 110-n-1. is relayed or propagated to other F / Fs 110-1 to 110-n-1. The flip-flop disk 100 may further include a circuit configured to invert the non-complementary shift signal sft to generate a complementary shift signal Inverter 120.

[0022] When the complementary shift signal sft and Not asserted (e.g., sft=0, ), the set of F / Fs 110-0 propagates data d0 to dn-1 at the data (D) input to the data (Q) output as q0 to qn-1 and to the sou output as s1 to sn, respectively, in response to the clock (clk) signal. is asserted (e.g., sft=1, ), the set of F / Fs 110-0 responds to a clock (clk) signal to propagate test data s0 through sn-1 at the sin input to the data (Q) outputs as q0 through qn-1 and to the sou outputs as s1 through sn, respectively.

[0023] Each of the set of F / Fs 110-0 to 110-n-1 includes a clock source configured to receive and output complementary clock signals clk and clk, respectively. A pair of complementary clock ports. For example, the complementary clock signals clk and can be provided to the left complementary clock port of F / F 110-0. The right complementary clock ports of F / Fs 110-0 to 110-n-2 are coupled to the left complementary clock ports of F / Fs 110-1 to 110-n-1, respectively. Therefore, the complementary clock signals clk and clk provided to the left complementary clock port of F / F 110-0 are respectively coupled to the left complementary clock ports of F / F 110-n-1. The flip-flop disk 100 may further include a circuit configured to invert the non-complementary clock signal clk to generate a complementary clock signal. The set of F / Fs 110-0 to 110-n-1 responds to the complementary clock signals clk and The data is propagated along the transition.

[0024] Each of the set of F / Fs 110-0 to 110-n-1 includes a pair of reset (rst) ports configured to receive and output a reset (rst) signal. For example, the reset signal can be provided to the left rst port of F / F 110-0. The right rst ports of F / Fs 110-0 to 110-n-2 are coupled to the left rst ports of F / Fs 110-1 to 110-n-1, respectively. Thus, the reset signal provided to the left rst port of F / F 110-0 is relayed or propagated to the other F / Fs 110-1 to 110-n-1. When asserted (e.g., rst=1), the reset signal resets or anchors the data (Q) and sou outputs to logic zero (0); when not asserted, the data at the data (Q) and sou outputs is controlled by the remaining data, scan, shift, and clock signals.

[0025] Figure 2 A schematic diagram of an example flip-flop (F / F) 200 according to another aspect of the present disclosure is illustrated. The F / F 200 may be an example detailed implementation of one of the set of F / Fs 110-0 through 110-n-1 of the flip-flop disk 100. The F / F 200 includes a multiplexer (Mux) 210, a master latch (M-latch) 220, and a slave latch (S-latch) 230.

[0026] The multiplexer 210 is configured to generate a plurality of shift signals based on the complementary shift signals sft and The multiplexer 210 outputs the selected one of the input data (d) or the scan data (sin) at the node n1. Specifically, the multiplexer 210 includes an upper voltage rail V ddA first FET M1 (e.g., which may be implemented as a p-channel metal oxide semiconductor FET or a PMOS FET) is coupled in series with a second field effect transistor (FET) M2 (e.g., a PMOS FET) between the first and second FETs and the node n1. That is, the first FET M1 includes a first FET M1 coupled to an upper voltage rail V dd The second FET M2 includes a gate configured to receive the data signal (d) and a drain coupled to the node n1.

[0027] Multiplexer 210 also includes an upper voltage rail V dd and a third FET M3 (eg, a PMOS FET) coupled in series with a fourth FET M4 (eg, a PMOSFET) between the upper voltage rail V and the node n1. That is, the third FET M3 includes a first FET coupled to the upper voltage rail V dd The source is configured to receive the complementary shift signal The fourth FET M4 includes a gate configured to receive a scan signal (sin) and a drain coupled to the node n1.

[0028] In addition, the multiplexer 210 includes a voltage rail V ss The fifth FET M5 (e.g., which may be implemented as an n-channel metal oxide semiconductor FET or an NMOS FET) is coupled in series with the sixth FET M6 (e.g., an NMOS FET) between the first and second terminals of the power supply MOSFET and the power supply MOSFET. That is, the fifth FET M5 includes a drain coupled to the node n1, a gate configured to receive the data signal (d), and a source coupled to the drain of the sixth FET M6. The sixth FET M6 includes a gate configured to receive the complementary shift signal (d). The gate is coupled to the lower voltage rail V ss The source.

[0029] The multiplexer 210 also includes a circuit between node n1 and the lower voltage rail V ss The seventh FET M7 (e.g., NMOS FET) is coupled in series with the eighth FET M8 (e.g., NMOSFET). That is, the seventh FET M7 includes a drain coupled to the node n1, a gate configured to receive the scan signal (sin), and a source coupled to the drain of the eighth FET M8. The eighth FET M8 includes a gate configured to receive the non-complementary shift signal sft and a source coupled to the lower voltage rail V ss The source.

[0030] In the operation of the multiplexer 210, when the shift signal is not asserted (eg, sft=0, ), the first FET M1 is turned on, the third FET M3 is turned off, the sixth FET M6 is turned on, and the eighth FET M8 is turned off. In this configuration, the electrical path responsive to the data signal (d) exists via the FETs M1, M2, M5, and M6 on the upper voltage rail V dd and the lower voltage rail V ss (e.g., when FETs M3 and M8 are off, no electrical path exists between V dd and V ss Thus, the multiplexer 210 outputs the data signal (d) at the node n1 (eg, although inverted).

[0031] When the shift signal is asserted (e.g., sft=1, ), the first FET M1 is off, the third FET M3 is on, the sixth FET M6 is off, and the eighth FET M8 is on. In this configuration, the electrical path responsive to the scan signal (sin) exists via the FETs M3, M4, M7, and M8 to the upper voltage rail V dd and the lower voltage rail V ss (For example, when FETs M1 and M6 are off, no electrical path exists between V dd and V ss Thus, the multiplexer 210 outputs the scan signal (sin) at the node n1 (eg, although inverted).

[0032] The master latch 220 is configured to be switched on and off at the complementary clock signals clk and is transparent when logically low and high (e.g., receives the (d) or (sin) signal output by multiplexer 210), and is transparent when the complementary clock signals clk and It is opaque when logically high and low (e.g., it closes and latches the previously received (d) or (sin) signal). Specifically, the master latch 220 includes a transmission gate 222, which includes a FET M9 (e.g., a PMOS FET) and a FET M10 (e.g., an NMOS FET) coupled in parallel between node n1 and node n2. That is, FET M9 includes a source / drain coupled to node n1 and a drain / source coupled to node n2. Similarly, FET M10 includes a drain / source coupled to node n1 and a source / drain coupled to node n2.

[0033] FETs M9 and M10 are referred to as having drain / source and source / drain because these terms depend on which voltage is higher at nodes n1 and n2. For example, if the voltage at node n1 (e.g., logic one (1)) is higher than the voltage at node n2 (e.g., logic zero (0)), FET M9 includes a source coupled to node n1 and a drain coupled to node n2, and FET M10 includes a drain coupled to node n1 and a source coupled to node n2. Conversely, if the voltage at node n1 (e.g., logic zero (0)) is lower than the voltage at node n2 (e.g., logic one (1)), FET M9 includes a drain coupled to node n1 and a source coupled to node n2, and FET M10 includes a source coupled to node n1 and a drain coupled to node n2.

[0034] The master latch 220 also includes a latch 224 that includes a latch on the upper voltage rail V dd and node n2, and a FET M11 (eg, a PMOS FET) coupled in series with FET M12 (eg, a PMOS FET). That is, FET M11 includes a FET coupled to an upper voltage rail V dd The source of the FET M12 is coupled to the drain of the FET M12. The FET M12 includes a FET configured to receive a complementary clock signal The latch 224 also includes a gate coupled to the node n2 and a drain coupled to the node n2. ss FET M13 (e.g., an NMOS FET) is coupled in series with FET M14 (e.g., an NMOS FET). That is, FET M13 includes a drain coupled to node n2, a gate configured to receive the non-complementary clock signal clk, and a source coupled to the drain of FET M14. FET M14 includes a gate coupled to the lower voltage rail V ss The latch 224 also includes a NOR gate 226 including a first input coupled to the node n2, a second input configured to receive a reset (rst) signal, and an output coupled to the gates of the FETs M11 and M14.

[0035] In operation with respect to the master latch 220, when the reset signal is not asserted (e.g., logic zero (0)), the NOR gate 226 operates as an inverter. During this mode, when the complementary clock signals clk and When logically low and high, the transmission gate 222 is turned on; thereby allowing the (d) or (sin) signal output by the multiplexer 210 to propagate to the node n2 of the latch 224. In addition, when the complementary clock signals clk and When logically low and high, respectively, FETs M12 and M13 are turned off to disable latch 224. Conversely, when the complementary clock signals clk and When logically high and low, respectively, the transmission gate 222 is off, thereby preventing the (d) or (sin) signal output by the multiplexer 210 from propagating to the node n2 of the latch 224. In addition, when the complementary clock signals clk and When logically high and low, respectively, FETs M12 and M13 are turned on to enable latch 224 to hold the (d) or (sin) signal previously received from multiplexer 210. When the reset signal is asserted (e.g., logic one (1)), NOR gate 226 outputs logic zero (0); this causes node n2 to be at logic one (1); which is then inverted by slave latch 230 to cause data out (q) and scan out (sou) to be at logic zero (0).

[0036] The slave latch 230 is configured to receive the complementary clock signals clk and It is transparent when logically high and low (e.g., receives the (d) or (sin) signal output by the master latch 220) and is transparent when the complementary clock signals clk and Opaque when logically low and high (eg, closes and latches the previously received (d) or (sin) signal).

[0037] Specifically, the slave latch 230 includes a gated inverter 232 and a latch 234. The gated inverter 232 includes an upper voltage rail V dd and node n3, and a FET M15 (eg, a PMOS FET) coupled in series with a FET M16 (eg, a PMOS FET). That is, the FET M15 includes a FET coupled to an upper voltage rail V dd , a gate coupled to node n2, and a drain coupled to the source of FET M16. FET M16 includes a transistor configured to receive a complementary clock signal The gate of the gated inverter 232 is coupled to the drain of the node n3. The gated inverter 232 also includes a gate of the gated inverter 232 and a drain coupled to the node n3. ss FET M17 (e.g., an NMOS FET) is coupled in series with FET M18 (e.g., an NMOS FET). That is, FET M17 includes a drain coupled to node n3, a gate configured to receive the non-complementary clock signal clk, and a source coupled to the drain of FET M18. FET M18 includes a gate coupled to node n2 and a source coupled to the lower voltage rail V ss The source.

[0038] Then, latch 234 includes an upper voltage rail V ddand node n3, and FET M19 (eg, a PMOS FET) is coupled in series with FET M20 (eg, a PMOS FET). That is, FET M19 includes a FET coupled to an upper voltage rail V dd The latch 234 further includes a gate configured to receive the non-complementary clock signal clk and a drain coupled to the node n3. ss FET M21 (eg, NMOS FET) is coupled in series with FET M22 (eg, NMOSFET). That is, FET M21 includes a drain coupled to node n3, a gate configured to receive a complementary clock signal The gate of the FET M22 is coupled to the drain of the FET M22. The FET M22 includes a gate coupled to the lower voltage rail V ss The latch 234 further includes a first inverter 236 having an input coupled to the node n3 and an output coupled to the gates of the FETs M19 and M22. Additionally, the latch 234 may include a second inverter 238 having an input coupled to the output of the first inverter 236 and an output configured to generate a data output signal (q). A scan output signal (sou) is generated at the node n3.

[0039] In the operation of the slave latch 230, when the complementary clock signals clk and When logically high and low, the gated inverter 232 is turned on; thereby allowing the (d) or (sin) signal at node n2 to propagate to node n3 of latch 234 and be inverted there. In addition, when the complementary clock signals clk and When logically high and low, respectively, FETs M20 and M21 are turned off to disable latch 234. Conversely, when the complementary clock signals clk and When logically low and high, respectively, the gated inverter 232 is off, thereby preventing the (d) or (sin) signal output by the master latch 220 from propagating to the node n3 of the latch 234. In addition, when the complementary clock signals clk and When logically low and high, respectively, FETs M20 and M21 are turned on to enable latch 234 to hold the (d) or (sin) signal previously received from master latch 220 .

[0040] In summary, when the clock signal clk experiences a rising edge, the master latch 220 becomes opaque and latches the current signal previously received from the multiplexer 210, and the slave latch 230 becomes transparent and receives the current signal at the node n3. When the clock signal clk experiences a falling edge, the master latch 220 becomes transparent and receives a new signal at the node n2, and the slave latch 230 becomes opaque and latches the current signal previously received from the master latch 220.

[0041] FETs M1 to M22, including the NOT gate 226 of the OR F / F 200 and the FETs in the inverters 236 and 238, can be implemented with the same size or the same channel width to length ratio (W / L). For example, if such FETs are implemented as FinFETs, the FETs can be sized to have the same number of fins (e.g., two (2) fins). Thus, the set of F / Fs 110-0 to 110-n-1 of the flip-flop disk 100 can each be implemented using the same 2-fin FinFET.

[0042] However, as the technology nodes in ICs using trigger pads continue to decrease, the percentage of trigger pads used in such ICs tends to increase. As the percentage of trigger pads used increases, the IC footprint used to implement the trigger pads also increases. Furthermore, as the percentage of trigger pads used in an IC continues to increase, the amount of power consumed by the trigger pads also increases. Therefore, there is a need to meet the preference for increased trigger pads at newer technology nodes while effectively utilizing the IC footprint to implement the increased number of trigger pads and to implement the trigger pads for improved power efficiency.

[0043] Figure 3 A block diagram of an example hybrid trigger disk 300 according to one aspect of the present disclosure is illustrated. The hybrid trigger disk 300 includes a set of triggers (F / Fs) 310-0 through 310-n-1, similar to the set of F / Fs 110-0 through 110-n-1 discussed previously. Similar to the set of F / Fs 110-0 through 110-n-1, the set of F / Fs 310-0 through 310-n-1 includes a set of data inputs (D) configured to receive data signals (e.g., functions or scans) d0 through dn-1, respectively. The set of F / Fs 310-0 through 310-n-1 includes a set of data outputs (Q) configured to output data signals (e.g., functions or scans) q0 through qn-1, respectively. The set of F / Fs 310-0 to 310-n-1 are cascaded with respect to a scan path, with scan outputs (sou) of F / Fs 310-0 to 310-n-2 electrically coupled to scan inputs (sin) of F / Fs 310-1 to 310-n-1, respectively.

[0044] The set of F / Fs 310-0 to 310-n-1 includes ports configured to receive various control signals, such as complementary shift signals Reset (rst) signal and complementary clock signal Shift of the set of F / F 310-0 to 310-n1 Reset, Clock The ports are electrically coupled to each other. In addition, the hybrid flip-flop disk 300 includes a circuit configured to receive the non-complementary shift signal sft and invert it to generate a complementary shift signal Similarly, the hybrid flip-flop disk 300 further includes a first inverter 320 configured to receive the non-complementary clock signal clk and invert it to generate a complementary clock signal The second inverter 330.

[0045] In the hybrid flip-flop disk 300, the set of F / Fs 310-0 through 310-n-1 includes a set of hybrid F / Fs implemented using FinFETs sized to have different numbers of fins. For example, a first subset of at least F / Fs 310-0 and 310-2 in the set of F / Fs 310-0 through 310-n-1 each includes a set of FinFETs, such as a set of FinFETs M1 through M22 sized to have J fins (including the FinFETs in the NOR gate 226 and inverters 236 and 238 of the F / F 200), where J is a positive integer. A second subset of at least another F / F 310-1 and 310-n-1 in the set of F / Fs 310-0 through 310-n-1 each includes a set of FinFETs, such as a set of FinFETs M1 through M22 sized to have K fins (including the FinFETs in NOR gate 226 and inverters 236 and 238 of F / F 200), where K is a positive integer different from J.

[0046] That is, instead of implementing a set of F / Fs 310-0 to 310-n-1, each of which has a FinFET sized to have the same number of fins, the hybrid flip-flop disk 300 includes a mixed set of F / Fs 310-0 to 310-n-1, each of which has a FinFET sized to have a different number of fins. As an example, the flip-flop disk can include a set of F / Fs with FinFETs sized to have a uniform minimum number of fins (e.g., 2 fins) to meet timing closure requirements. The D2Q propagation delay of an F / F (the delay associated with the propagation of data from the data (D) input to the data (Q) output) can be directly related to the number of fins in its FinFET set. For example, the D2Q of an F / F implemented with 2-fin FinFETs can have a D2Q delay of 103 picoseconds (ps). If the flip-flop pad is implemented with a F / F set having a FinFET sized to have a uniformly small number of fins (e.g., 1 fin), the flip-flop pad may not be able to meet the timing closure requirements due to the high D2Q delay of the 1-fin F / F. For example, the D2Q of the F / F implemented with 1-fin FinFET may have a D2Q delay of 145 ps.

[0047] However, if the D2Q of each of the F / Fs is 135 ps, the timing closure requirement of the trigger disk can be met. Therefore, the hybrid trigger disk 300 can be implemented using a first subset of half of the set of F / Fs 310-0, 310-2, 310-4, and 310-6 (where n=8) using single-fin FinFETs, and a second subset of the other half of the set of F / Fs 310-1, 310-3, 310-5, and 310-7 using two-fin FinFETs. In this configuration, the average D2Q of each F / F of the hybrid trigger disk 300 will be substantially the average of the D2Q of the single-fin F / F (e.g., 145 ps) and the D2Q of the two-fin F / F (e.g., 103 ps), which is 124 ps. The 124 average D2Q of the hybrid trigger disk 300 will meet the timing closure requirement of 135 ps.

[0048] An advantage of the hybrid flip-flop disk 300 is that by replacing some of the flip-flop disk's 2-fin F / Fs with 1-fin F / Fs, the IC footprint used to implement the flip-flop disk can be significantly saved. For example, a 1-fin IC cell can have a height of 117 nanometers (nm), while a 2-fin IC cell can have a height of 169 nm. Thus, considering the above example, instead of having a flip-flop disk with eight (8) F / F cells with uniform 2-fin FETs, the flip-flop disk can be implemented with four (4) F / Fs using 1-fin FETs and four (4) F / Fs using 2-fin FETs, thereby saving significant IC footprint.

[0049] Another advantage of the hybrid trigger disk 300 is that higher fin FinFETs consume more power than lower fin FinFETs. For example, a 2-fin F / F can consume 21% more power than a 1-fin F / F. Therefore, by using the hybrid trigger disk 300 instead of a trigger disk that uses a uniformly higher number of fin devices, a significant amount of power can be saved. In the example hybrid trigger disk 300, the set of F / Fs 310-0 to 310-n-1 is implemented using two different fin number FETs J and K. However, it should be understood that the trigger disk can be implemented using F / Fs of devices that use more than two different numbers of fin devices (for example, one or more F / Fs using a 1-fin device, one or more F / Fs using a 2-fin device, and one or more F / Fs using a 3-fin device).

[0050] Figure 4 A block diagram / schematic diagram of another example hybrid flip-flop disk 400 according to another aspect of the present disclosure is illustrated. Hybrid flip-flop disk 400 is an example configuration of the previously discussed hybrid flip-flop disk 300. Hybrid flip-flop disk 400 includes a set of flip-flops (F / Fs) 410-0 through 410-n7. F / Fs 410-0, 410-1, 410-4, and 410-5 use FinFETs with a fin size of 1, and F / Fs 410-2, 410-3, 410-6, and 410-7 use FinFETs with a fin size of 2.

[0051] Similar to hybrid flip-flop disk 300, the set of F / Fs 410-0 through 410-7 includes a set of data inputs (D) configured to receive data signals (e.g., functions or scans) d0 through d7, respectively. The set of F / Fs 410-0 through 410-7 includes a set of data outputs (Q) configured to output data signals (e.g., functions or scans) q0 through q7, respectively. The set of F / Fs 410-0 through 410-7 is cascaded relative to a scan path, with the scan outputs (sou) of F / Fs 410-0 through 410-6 coupled to the scan inputs (sin) of F / Fs 410-1 through 410-7, respectively.

[0052] The hybrid flip-flop disk 400 includes a control circuit 420 configured to generate various control signals for the set of F / Fs 410-0 to 410-7. For example, the control circuit 420 includes a NOR gate 422 that includes inputs configured to receive a non-complementary clock signal clk and a reset (rst) signal, respectively. When the reset signal is not asserted (e.g., a logic zero (0)), the NOR gate 422 is configured to output a complementary clock signal for the complementary clock ports of the set of F / Fs 410-0 to 410-7. That is, the NOR gate 422 includes an output coupled to a complementary clock port of at least one of the set of F / Fs 410-0 to 410-7 (eg, F / Fs 410-0, 410-3, 410-7, and 410-4), and the complementary clock signal The signals are respectively relayed by at least one F / F to at least another F / F (eg, from F / Fs 410 - 0 , 410 - 3 , 410 - 7 , and 410 - 4 to F / Fs 410 - 1 , 410 - 2 , 410 - 6 , and 410 - 5 ).

[0053] The control circuit 420 also includes an inverter 424 including an input coupled to the output of the NOR gate 422. When the reset signal is not asserted, the inverter 424 is configured to convert the complementary clock signal Inverting to generate a non-complementary clock signal clk. Inverter 424 includes an output coupled to a non-complementary clock port of at least one of the set of F / Fs 410-0 to 410-7 (e.g., F / Fs 410-0, 410-3, 410-7, and 410-4), and the non-complementary clock signal clk is relayed by at least one F / F to at least another F / F (e.g., from F / Fs 410-0, 410-3, 410-7, and 410-4 to F / Fs 410-1, 410-2, 410-6, and 410-5).

[0054] When the reset signal is asserted (eg, logic one (1)), the NOR gate 422 outputs a logic zero (0) for the complementary clock ports of the set of F / Fs 410-0 through 410-7 (eg, effectively disabling the complementary clock signal). 4. Inverter 424 inverts the logic zero (0) generated by NOR gate 422 to generate a logic one (1) for the non-complementary ports of the set of F / Fs 410-0 through 410-7 (e.g., effectively disabling the generation of the non-complementary clock signal clk). The asserted reset signal is also provided to the reset port of at least one of the set of F / Fs 410-0 through 410-7 (e.g., F / Fs 410-0, 410-3, 410-7, and 410-4), and the reset signal is relayed by at least one F / F to at least another F / F (e.g., from F / Fs 410-0, 410-3, 410-7, and 410-4 to F / Fs 410-1, 410-2, 410-6, and 410-5), respectively. The asserted reset signal anchors the data outputs q0 through q7 and the sou output of the set 410 - 0 through 410 - 7 each at logic zero (0).

[0055] The control circuit 420 further includes an inverter 426 including an input configured to receive the non-complementary shift signal sft and an input configured to generate a complementary shift signal sft. The non-complementary shift signal sft is also provided to the non-complementary shift signal port of at least one of the set of F / Fs 410-0 to 410-7 (e.g., F / Fs 410-0, 410-3, 410-7, and 410-4), and the non-complementary shift signal sft is relayed by at least one F / F to at least another F / F (e.g., from F / Fs 410-0, 410-3, 410-7, and 410-4 to F / Fs 410-1, 410-2, 410-6, and 410-5). The inverter 426 includes an output coupled to the complementary shift signal port of at least one of the set of F / Fs 410-0 to 410-7 (e.g., F / Fs 410-0, 410-3, 410-7, and 410-4), and the complementary shift signal sft is relayed by at least one F / F to at least another F / F (e.g., from F / Fs 410-0, 410-3, 410-7, and 410-4). The signals are respectively relayed by at least one F / F to at least another F / F (eg, from F / Fs 410 - 0 , 410 - 3 , 410 - 7 , and 410 - 4 to F / Fs 410 - 1 , 410 - 2 , 410 - 6 , and 410 - 5 ).

[0056] In addition, the control circuit 420 includes another inverter 428 and a NAND gate 430. The inverter 428 includes an input coupled to the sou output of the F / F 410-7 and an output coupled to a first input of the NAND gate 430. The NAND gate 430 includes a second input configured to receive the non-complementary shift signal sft and an output configured to generate the sou signal. When the non-complementary shift signal sft is not asserted (e.g., logic zero (0)), the NAND gate 430 anchors its output at logic one (1) (e.g., disabling the shift mode). When the non-complementary shift signal sft is asserted (e.g., logic one (1)), the NAND gate 430 outputs the scan data via the sou output (e.g., enabling the shift mode).

[0057] The devices of control circuit 420 (e.g., NOR gate 422, inverters 424, 426 and 428, and NAND gate 430) can each be implemented using higher fin count (e.g., 2-fin) FinFETs because they may be more critical to timing control of the set of F / Fs 410-0 to 410-7.

[0058] Figure 5A1 and 2 illustrate a layout view of another example hybrid trigger disk 500 according to another aspect of the present disclosure. The hybrid trigger disk 500 can be an example layout of a set of F / Fs 410-0 to 410-7 of the previously discussed hybrid trigger disk 400. The hybrid trigger disk 500 can be implemented on four (4) integrated circuit (IC) cell rows ROW-1 to ROW-4. IC cell rows ROW-1 and ROW-3 can have a height of 1 fin IC cell (e.g., 117 nm), and IC cell rows ROW-2 and ROW-4 can have a height of 2 fin IC cells (e.g., 169 nm).

[0059] According to the layout, the hybrid flip-flop disk 500 includes sequentially adjacent bits "0" and "1" (1-fin) flip-flops (F / F) 510-0 and F / F 510-1 in the row direction in IC unit ROW-1. Sequentially adjacent bits means that the bits are numerically sequential (ascending or descending) or consecutive, such as 0 and 1, or 3 and 2, or 4 and 5, etc. The hybrid flip-flop disk 500 may also include sequentially adjacent bits "2" and "3" (2-fin) F / F 510-2 and F / F 510-3 in the row direction in IC unit ROW-2, which are adjacent or abutting each other and are substantially aligned with the 1-fin F / F 510-0 and 510-1, respectively, in the column direction. In addition, the hybrid flip-flop disk 500 includes sequentially adjacent bits "4" and "5" (1-fin) F / Fs 510-4 and 510-5 in the IC unit ROW-3 that are adjacent or abutting each other in the row direction and are substantially aligned with the 2-fin F / Fs 510-2 and 510-3, respectively, in the column direction. In addition, the hybrid flip-flop disk 500 includes sequentially adjacent bits "6" and "7" (2-fin) F / Fs 510-6 and 510-7 in the IC unit ROW-4 that are adjacent or abutting each other in the row direction and are substantially aligned with the 2-fin F / Fs 510-4 and 510-5, respectively, in the column direction.

[0060] It should be understood that the layout configuration of the hybrid trigger disk 500 can be different, and the cascade arrangement of F / Fs 510-0 to 510-7 need not be two 1-fin F / Fs, two 2-fin F / Fs, two 1-fin F / Fs, and two 2-fin F / Fs, but can be in other cascade arrangements. In addition, the layout of the hybrid trigger disk 500 does not need to be distributed over four (4) rows, but rather distributed over two rows of one fin and two fin heights. For layout diversity, another example layout of the hybrid trigger disk is described below.

[0061] Figure 5B1 and 2 illustrate another example layout view of a hybrid trigger disk 5500 according to another aspect of the present disclosure. The hybrid trigger disk 550 may be another example layout of a set of F / Fs 410-0 to 410-7 of the previously discussed hybrid trigger disk 400. The hybrid trigger disk 550 may be implemented on four (4) integrated circuit (IC) cell rows ROW-1 to ROW-4. The IC cell rows ROW-1 and ROW-3 may have a height of 1 fin IC cell (e.g., 117 nm), and the IC cell rows ROW-2 and ROW-4 may have a height of 2 fin IC cells (e.g., 169 nm).

[0062] According to the layout, the hybrid flip-flop disk 550 includes sequentially adjacent bits "3" and "4" (1-fin) flip-flops (F / Fs) 560-3 and F / Fs 560-4 in the row direction in IC cell ROW-1. The hybrid flip-flop disk 550 may also include non-sequential bits "2" and "5" (2-fin) F / Fs 560-2 and F / Fs 560-3 in the row direction in IC cell ROW-2, and substantially aligned with the 1-fin F / Fs 560-3 and 560-4, respectively, in the column direction. In addition, the hybrid flip-flop disk 550 includes non-sequential bits "1" and "6" (1-fin) F / Fs 560-1 and 560-6 in the row direction in IC cell ROW-3, and substantially aligned with the 2-fin F / Fs 560-2 and 560-5, respectively, in the column direction. In addition, the hybrid flip-flop disk 550 includes non-sequential bits "0" and "7" (2-fin) F / Fs 560-0 and 560-7 in the IC unit ROW-4 that are adjacent or abutting each other in the row direction, and are substantially aligned with the 2-fin F / Fs 560-1 and 560-6, respectively, in the column direction.

[0063] Figure 6 A block diagram of an example wireless communication device 600 according to another aspect of the present disclosure is illustrated. The wireless communication device 600 may be a smartphone, a desktop computer, a laptop computer, a tablet device, an Internet of Things (IoT), a wearable wireless device (e.g., a wireless watch), and other types of wireless devices.

[0064] Specifically, the wireless communication device 600 includes an integrated circuit (IC) 610, which can be implemented as a system on a chip (SOC). The IC 610 includes one or more signal processing cores 620, which in turn can include one or more trigger disks 630. Each of the one or more trigger disks 630 can be implemented according to any of the hybrid trigger disks 300, 400, or 500 described herein. The one or more signal processing cores 620 can be configured to generate transmit (Tx) baseband (BB) signals and process receive (Rx) baseband (BB) signals.

[0065] The wireless communication device 600 may also include a transceiver 650 and at least one antenna 660 (e.g., an antenna array). The transceiver 650 is coupled to one or more signal processing cores 620 to receive Tx BB signals therefrom and provide Rx BB signals thereto. The transceiver 650 is configured to convert the Tx BB signals into Tx radio frequency (RF) signals and convert the Rx RF signals into Rx BB signals. The transceiver 650 is coupled to at least one antenna 660 to provide the Tx RF signals thereto for electromagnetic radiation into a wireless medium for wireless transmission, and to receive Rx RF signals electromagnetically picked up from the wireless medium by the at least one antenna 660.

[0066] The following provides an overview of various aspects of the disclosure:

[0067] Aspect 1: A hybrid trigger disk, comprising: a set of triggers, the set of triggers being cascaded along a scan path, wherein a first subset of one or more of the triggers in the set includes fin field effect transistors (FinFETs) each sized to have a first number of fins, and a second subset of one or more of the triggers in the set includes FinFETs each sized to have a second number of fins, wherein the first number of fins is different from the second number of fins; and a control circuit configured to provide a control signal to the set of triggers.

[0068] Aspect 2: The hybrid trigger tray of aspect 2, wherein the first number is one (1) and the second number is two (2).

[0069] Aspect 3: The hybrid trigger disk of aspect 2, wherein the first subset of one or more triggers is associated with a first pair of adjacent sequential bits, and wherein the second subset of one or more triggers is associated with a second pair of adjacent sequential bits.

[0070] Aspect 4: The hybrid trigger disk of aspect 3, wherein the first pair of adjacent sequential bits are sequentially adjacent to the second pair of adjacent sequential bits.

[0071] Aspect 5: A hybrid trigger disk according to Aspect 4, wherein: the first subset of one or more triggers associated with the first pair of adjacent sequential bits are positioned adjacent to each other in a first row of an integrated circuit (IC) unit; and the second subset of one or more triggers associated with the second pair of adjacent sequential bits are positioned adjacent to each other in a second row of the IC unit.

[0072] Aspect 6: The hybrid flip-flop disk of aspect 5, wherein the first subset of one or more flip-flops associated with the first pair of adjacent sequential bits is substantially aligned in a column direction with the second subset of one or more flip-flops associated with the second pair of adjacent sequential bits.

[0073] Aspect 7: The hybrid trigger disk of any one of aspects 2 to 6, wherein the first subset of one or more triggers is further associated with a third pair of adjacent sequential bits, and wherein the second subset of one or more triggers is associated with a fourth pair of adjacent sequential bits.

[0074] Aspect 8: The hybrid trigger disk according to aspect 7, wherein: the second pair of adjacent sequential bits is sequentially adjacent to the first pair of adjacent sequential bits and the third pair of adjacent sequential bits; and the third pair of adjacent sequential bits is sequentially adjacent to the fourth pair of adjacent sequential bits.

[0075] Aspect 9: A hybrid trigger disk according to Aspect 8, wherein: the first subset of one or more triggers associated with the first pair of adjacent sequential bits are positioned adjacent to each other in a first row of an integrated circuit (IC) unit; the second subset of one or more triggers associated with the second pair of adjacent sequential bits are positioned adjacent to each other in a second row of the IC unit; the first subset of one or more triggers associated with the third pair of adjacent sequential bits are positioned adjacent to each other in a third row of the IC unit; and the second subset of one or more triggers associated with the fourth pair of adjacent sequential bits are positioned adjacent to each other in a fourth row of the IC unit.

[0076] Aspect 10: A hybrid trigger disk according to Aspect 9, wherein the first subset, the second subset, the third subset and the fourth subset of one or more triggers associated with the first pair of adjacent sequential bits, the second pair of adjacent sequential bits, the third pair of adjacent sequential bits and the fourth pair of adjacent sequential bits are respectively substantially aligned in the column direction.

[0077] Aspect 11: The hybrid flip-flop disk of any of Aspects 1 to 10, wherein the control circuit comprises FinFETs each sized to have the second number of fins.

[0078] Aspect 12: The hybrid flip-flop disk of any one of aspects 1 to 11, wherein the control circuit is configured to provide a non-complementary clock signal and a complementary clock signal to the set of flip-flops.

[0079] Aspect 13: A hybrid flip-flop disk according to Aspect 12, wherein the control circuit comprises: a NOR gate, the NOR gate comprising a first input configured to receive the first clock signal, a second input configured to receive a reset signal, and an output coupled to the first clock port of each of the flip-flop set; and an inverter, the inverter comprising an input coupled to the output of the NOR gate and an output coupled to the second clock port of each of the flip-flop set.

[0080] Aspect 14: The hybrid flip-flop disk of aspect 13, wherein at least one of the NOR gate or the inverter each comprises a set of FinFETs each sized to have the second number of fins.

[0081] Aspect 15: The hybrid flip-flop disk of any one of aspects 1 to 14, wherein the control circuit is configured to provide a first shift signal and a second shift signal to the set of flip-flops, wherein the first shift signal is complementary to the second shift signal.

[0082] Aspect 16: A hybrid trigger disk according to Aspect 15, wherein each of the trigger sets includes a first shift port configured to receive the first shift signal, and wherein the control circuit includes a first inverter, the first inverter including an input configured to receive the first shift signal and an output coupled to a second shift port of each of the trigger sets.

[0083] Aspect 17: The hybrid flop disk of aspect 16, wherein the first inverter comprises a set of FinFETs each sized to have the second number of fins.

[0084] Aspect 18: A hybrid trigger disk according to any one of Aspects 15 to 17, wherein the control circuit includes: a second inverter, the second inverter including an input coupled to a scan output of one of the trigger sets; and a NAND gate, the NAND gate including a first input coupled to the output of the second inverter, a second input configured to receive the first shift signal, and an output configured to generate a scan output signal.

[0085] Aspect 19: The hybrid flip-flop disk of aspect 18, wherein at least one of the second inverter or the NAND gate each comprises a set of FinFETs each sized to have the second number of fins.

[0086] Aspect 20: A wireless communication device, comprising: at least one antenna; a transceiver coupled to the at least one antenna; one or more signal processing cores coupled to the transceiver, wherein the one or more processing cores include a trigger disk, the trigger disk comprising: a set of triggers, the trigger set cascaded along a scan path, wherein a first subset of one or more of the triggers in the set includes fin field effect transistors (FinFETs) each sized to have a first number of fins, and a second subset of one or more of the triggers in the set includes FinFETs each sized to have a second number of fins, wherein the first number of fins is different from the second number of fins; and a control circuit configured to provide control signals to the set of triggers.

[0087] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein, but rather to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A hybrid trigger tray, comprising: a set of flip-flops cascaded along a scan path, wherein a first subset of one or more of the flip-flops in the set include fin field effect transistors (FinFETs) each sized to have a first number of fins, and a second subset of one or more of the flip-flops in the set include FinFETs each sized to have a second number of fins, wherein the first number of fins is different from the second number of fins; and A control circuit is configured to provide a control signal to the set of flip-flops.

2. The hybrid trigger tray of claim 1, wherein the first number is one (1) and the second number is two (2).

3. The hybrid trigger disk of claim 2, wherein the first subset of one or more triggers is associated with a first pair of adjacent sequential bits, and wherein the second subset of one or more triggers is associated with a second pair of adjacent sequential bits.

4. The hybrid trigger disk of claim 3, wherein the first pair of adjacent sequential bits are sequentially adjacent to the second pair of adjacent sequential bits.

5. The hybrid trigger tray of claim 4, wherein: the first subset of one or more flip-flops associated with the first pair of adjacent sequential bits are positioned adjacent to each other in a first row of an integrated circuit (IC) cell; and The second subset of one or more flip-flops associated with the second pair of adjacent sequential bits are positioned adjacent to each other in a second row of IC cells.

6. The hybrid flip-flop disk of claim 5 , wherein the first subset of one or more flip-flops associated with the first pair of adjacent sequential bits are substantially aligned in a column direction with the second subset of one or more flip-flops associated with the second pair of adjacent sequential bits, respectively.

7. The hybrid trigger disk of claim 2, wherein the first subset of one or more triggers is further associated with a third pair of adjacent sequential bits, and wherein the second subset of one or more triggers is associated with a fourth pair of adjacent sequential bits.

8. The hybrid trigger tray of claim 7, wherein: The second pair of adjacent sequential bits is sequentially adjacent to the first pair of adjacent sequential bits and the third pair of adjacent sequential bits; and The third pair of adjacent sequence bits is sequentially adjacent to the fourth pair of adjacent sequence bits.

9. The hybrid trigger tray of claim 8, wherein: the first subset of one or more flip-flops associated with the first pair of adjacent sequential bits being positioned adjacent to one another in a first row of an integrated circuit (IC) cell; said second subset of one or more flip-flops associated with said second pair of adjacent sequential bits being positioned adjacent to one another in a second row of IC cells; said first subset of one or more flip-flops associated with said third pair of adjacent sequential bits are positioned adjacent to one another in a third row of IC cells; and The second subset of one or more flip-flops associated with the fourth pair of adjacent sequential bits are positioned adjacent to each other in a fourth row of the IC cell.

10. The hybrid flip-flop disk of claim 9 , wherein the first subset, the second subset, the third subset, and the fourth subset of one or more flip-flops associated with the first pair of adjacent sequential bits, the second pair of adjacent sequential bits, the third pair of adjacent sequential bits, and the fourth pair of adjacent sequential bits, respectively, are substantially aligned in a column direction. 11 . The hybrid flip-flop disk of claim 1 , wherein the control circuit comprises FinFETs each sized to have the second number of fins.

12. The hybrid flip-flop disk of claim 1, wherein the control circuit is configured to provide a first clock signal and a second clock signal to the set of flip-flops, wherein the first clock signal is complementary to the second clock signal.

13. The hybrid trigger disk of claim 12, wherein the control circuit comprises: a NOR gate comprising a first input configured to receive the first clock signal, a second input configured to receive a reset signal, and an output coupled to a first clock port of each of the set of flip-flops; and An inverter includes an input coupled to the output of the NOR gate and an output coupled to a second clock port of each of the set of flip-flops. 14 . The hybrid flip-flop disk of claim 13 , wherein at least one of the NOR gate or the inverter each comprises a set of FinFETs each sized to have the second number of fins.

15. The hybrid flip-flop disk of claim 1, wherein the control circuit is configured to provide a first shift signal and a second shift signal to the set of flip-flops, wherein the first shift signal is complementary to the second shift signal.

16. The hybrid flip-flop disk of claim 15 , wherein each of the set of flip-flops includes a first shift port configured to receive the first shift signal, and wherein the control circuit includes a first inverter including an input configured to receive the first shift signal and an output coupled to a second shift port of each of the set of flip-flops. 17 . The hybrid flop disk of claim 16 , wherein the first inverter comprises a set of FinFETs each sized to have the second number of fins.

18. The hybrid trigger disk of claim 15, wherein the control circuit comprises: a second inverter including an input coupled to a scan output of one of the set of flip-flops; and A NAND gate includes a first input coupled to the output of the second inverter, a second input configured to receive the first shift signal, and an output configured to generate a scan-out signal. 19 . The hybrid flip-flop disk of claim 18 , wherein at least one of the second inverter or the NAND gate each comprises a set of FinFETs each sized to have the second number of fins.

20. A wireless communication device, comprising: at least one antenna; a transceiver coupled to the at least one antenna; One or more signal processing cores coupled to the transceiver, wherein the one or more processing cores include a flip-flop disk comprising: a set of flip-flops cascaded along a scan path, wherein a first subset of one or more of the flip-flops in the set include fin field effect transistors (FinFETs) each sized to have a first number of fins, and a second subset of one or more of the flip-flops in the set include FinFETs each sized to have a second number of fins, wherein the first number of fins is different from the second number of fins; and A control circuit is configured to provide a control signal to the set of flip-flops.

Images