Memory resource allocation method, device, electronic device and storage medium

Abstract

The present application discloses a memory resource allocation method, device, electronic device and storage medium, relating to the field of computer technology, including: for each multi-core central processing unit, the affinity memory of the central processing unit is partitioned to obtain a plurality of memory areas equal to the number of physical cores of the central processing unit, and then, a memory area on the affinity memory is bound to each physical core of the central processing unit, so that the physical core can access the bound memory area, thereby avoiding the resource consumption and high load problems caused by the inter-core data synchronization operation caused by shared memory.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a memory resource allocation method, device, electronic device, and storage medium. Background Art

[0002] In the field of computer technology, computers use a central processing unit (CPU) to process data. Current technology generally uses multiple cores to share a single physical memory for data processing. Consequently, access to the same physical memory by different cores triggers inter-core data synchronization operations, increasing the CPU load. For example, one inter-core data synchronization operation involves different physical cores accessing different variables within the same memory cell. However, consistency is implemented per memory cell. Therefore, when a physical core modifies a variable in that memory cell, the data at the corresponding location in other cores becomes invalid. Subsequent accesses require the latest data from the physical core that performed the modification. Summary of the Invention

[0003] The present application provides a memory resource allocation method, device, electronic device, storage medium, and program product to avoid the problem of high central processing unit load caused by inter-core data synchronization.

[0004] This application provides a memory resource allocation method, including:

[0005] Obtain identification information of at least one node, and physical core configuration information and memory configuration information corresponding to each of the at least one node;

[0006] Determining the number of physical cores included in a target central processing unit corresponding to the target node according to the physical core configuration information corresponding to the identification information of the target node, wherein the target node is any one of the at least one node;

[0007] According to the number of physical cores, the preset memory page size, and the target memory configuration information corresponding to the target node, the memory corresponding to the target memory configuration information is divided into a plurality of memory areas whose number is equal to the number of physical cores;

[0008] Multiple memory areas are bound to multiple physical cores included in the target central processor one by one to allocate memory resources of the memory area to the physical cores bound to the memory area, wherein any physical core only accesses the memory area bound to itself.

[0009] The present application also provides a memory resource allocation device, comprising:

[0010] an acquisition module, configured to acquire identification information of at least one node, and physical core configuration information and memory configuration information corresponding to each of the at least one node;

[0011] a determination module, configured to determine the number of physical cores included in a target central processing unit corresponding to the target node according to the physical core configuration information corresponding to the identification information of the target node, wherein the target node is any one of the at least one node;

[0012] a partitioning module, configured to partition the memory corresponding to the target memory configuration information into a plurality of memory areas equal in number to the number of physical cores based on the number of physical cores, a preset memory page size, and the target memory configuration information corresponding to the target node;

[0013] The allocation module is used to bind multiple memory areas to multiple physical cores included in the target central processing unit one by one, so as to allocate memory resources of the memory area to the physical cores bound to the memory area, wherein any physical core only accesses the memory area bound to itself.

[0014] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned memory resource allocation methods when executing the computer program.

[0015] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned memory resource allocation methods are implemented.

[0016] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above-mentioned memory resource allocation methods when executed by a processor.

[0017] Through the present application, for each multi-core central processing unit, the affinity memory of the central processing unit (for example, the memory corresponding to the target memory configuration information) is partitioned to obtain multiple memory areas equal to the number of physical cores of the central processing unit. Then, a memory area on the affinity memory is bound to each physical core of the central processing unit, so that the physical core can access the bound memory area, thereby avoiding the resource consumption and high load problems caused by inter-core data synchronization operations due to shared memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0019] Figure 1 A schematic diagram of the architecture of a computer device provided in an embodiment of the present application;

[0020] Figure 2 A flowchart of a memory resource allocation method provided in an embodiment of the present application;

[0021] Figure 3 A schematic diagram of binding memory areas and physical cores provided in an embodiment of the present application;

[0022] Figure 4 A flowchart of another memory resource allocation method provided in an embodiment of the present application;

[0023] Figure 5 A flowchart of another memory resource allocation method provided in an embodiment of the present application;

[0024] Figure 6 A flowchart of a method for monitoring an instruction control block provided in an embodiment of the present application;

[0025] Figure 7 A schematic diagram of the interaction of functional components of a memory resource allocation process provided in an embodiment of the present application;

[0026] Figure 8 A schematic diagram of state switching of an instruction control block provided in an embodiment of the present application;

[0027] Figure 9 A schematic diagram of the structure of a memory resource allocation device provided in an embodiment of the present application;

[0028] Figure 10 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0030] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0031] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0032] The memory resource allocation method provided in this application can be implemented by a computer device, which may include at least one central processing unit (CPU) and at least one memory. In the case where the computer device includes multiple CPUs and multiple memories, and each of the CPUs is a multi-core CPU, the architecture of the computer device may be as follows: Figure 1 As shown. The computer device includes a first central processing unit, a second central processing unit, a first memory, and a second memory. The first central processing unit may include a first physical core and a second physical core, and the second central processing unit may include a third physical core and a fourth physical core. One central processing unit and one memory constitute a node. For example, the node may be called a non-uniform memory access architecture (NUMA) node. Figure 1 In the embodiment, the first central processing unit and the first memory constitute a first node, and the second central processing unit and the second memory constitute a second node.

[0033] The embodiment of the present application provides a memory resource allocation method, which can be executed by the above-mentioned computer device, such as Figure 2 As shown, the specific processing steps of the memory resource allocation method may include:

[0034] Step S201: Acquire identification information of at least one node, and physical core configuration information and memory configuration information corresponding to each of the at least one node.

[0035] The physical core configuration information may include identification information of multiple physical cores included in the central processing unit corresponding to the node identification information. The memory configuration information may be memory identification information or a physical address range of the memory.

[0036] Specifically, after booting the operating system, the computer device can obtain the system firmware table generated during the firmware startup phase and use the operating system to parse the system firmware table to obtain node topology information. The node topology information may include mapping information between node identification information and physical core configuration information, as well as mapping information between node identification information and memory configuration information. This means that the identification information of at least one node, as well as the physical core configuration information and memory configuration information corresponding to at least one node, are obtained. For example, the system firmware table may be an Advanced Configuration and Power Interface (ACPI) System Resource Affinity table.

[0037] Step S202 : determining the number of physical cores included in the target central processing unit corresponding to the target node according to the physical core configuration information corresponding to the identification information of the target node.

[0038] The target node may be any one of the at least one node.

[0039] Specifically, for any central processing unit, the computer device may determine the number of physical core identification information included in the physical core configuration information corresponding to the identification information of the node to which the central processing unit belongs as the number of physical cores included in the central processing unit.

[0040] Step S203 , based on the number of physical cores, the preset memory page size, and the target memory configuration information corresponding to the target node, divide the memory corresponding to the target memory configuration information into a plurality of memory areas whose number is equal to the number of physical cores.

[0041] Specifically, for any central processing unit (CPU), the computer device can partition the memory belonging to the same node as the CPU (i.e., the CPU's affinity memory) based on the number of physical cores included in the CPU, the preset memory page size, and the target memory configuration information, resulting in multiple memory sections (Memory Sections). In this way, the number of memory sections obtained by partitioning is equal to the number of physical cores. For example, when the target memory configuration information is a physical address range, during the partitioning process, the computer device can first partition the memory corresponding to the target memory configuration information into multiple memory pages of the preset memory size based on the preset memory page size. Furthermore, based on the number of partitioned memory pages and the number of processing cores included in the target CPU, the computer device can divide the partitioned memory pages into multiple memory page groups (which can be evenly divided) equal to the number of processing cores. Each memory page group constitutes a memory section. In other words, each memory section can include at least one memory page, each of which has a size of the preset memory page size. By pre-partitioning the memory pages, each memory section can include multiple complete memory pages, reducing memory resource waste and facilitating subsequent use of memory resources.

[0042] In step S204 , the plurality of memory areas are bound one by one to the plurality of physical cores included in the target central processing unit.

[0043] Among them, any physical core can only access the memory area bound to itself.

[0044] Specifically, for any central processing unit, the computer device can bind a physical core to a memory area. Specifically, the identification information of the physical core can be recorded in correspondence with the physical address range of the memory area, and the access rights of the physical address range of the memory area can be set to be accessible only to the physical core, so that any physical core in the central processing unit can only access the memory area bound to itself.

[0045] like Figure 3 As shown, the first physical core of the first central processor is bound to the memory area 0 of the first memory, the second physical core of the first central processor is bound to the memory area 1 of the first memory, the third physical core of the second central processor is bound to the memory area 2 of the second memory, and the fourth physical core of the second central processor is bound to the memory area 3 of the second memory.

[0046] The memory resource allocation method of the embodiment of the present application allocates the affinity memory (for example, Figure 1The affinity memory of the first central processing unit in the CPU is partitioned (the first memory) to obtain multiple memory areas of the same number as the number of physical cores of the CPU. Then, a memory area on the affinity memory is bound to each physical core of the CPU, so that the physical core can access the bound memory area, which can avoid the resource consumption and high load problems caused by the inter-core data synchronization operation caused by shared memory. Moreover, the efficiency of accessing the affinity memory is higher. In addition, in the related art, in order to ensure the isolation of memory resources of the same physical memory (for example, the first memory or the second memory mentioned above), each physical core needs to lock the physical memory before accessing the physical memory, and can only unlock the physical memory after the access is completed. When the physical memory is locked, other physical cores cannot access the memory in time to perform business processing, resulting in low access efficiency. However, under the solution of the present application, each physical core can only access the memory area bound to itself, without the need for locking, and the access efficiency is higher.

[0047] After performing the above-mentioned binding operation on the physical core and the memory area, the threads running on the physical core can be further bound to the memory resources, so that each thread can use the memory resources bound to itself to execute related services. Accordingly, the embodiment of the present application also provides a memory resource allocation method that can be executed by the above-mentioned computer device, such as Figure 4 As shown, the specific processing steps of the memory resource allocation method may include:

[0048] Step S401: Obtain the instruction queue size of the target thread running on the target physical core.

[0049] The target physical core is any one of the multiple physical cores included in the target central processing unit.

[0050] Specifically, during the protocol initialization phase of a target protocol type (any protocol type), the computer device may first obtain, based on the target protocol type, the instruction queue size (which may be pre-specified) of the target thread corresponding to the target protocol type. For example, the target protocol type may be a Non-Volatile Memory Express (NVME) storage access protocol type or a Small Computer System Interface (SCSI) protocol.

[0051] Step S402 : determining the amount of memory resources required by the target thread according to the instruction queue size and the preset instruction control block size.

[0052] Specifically, after obtaining the target protocol type's command queue size and a preset command control block (CCB) size, the computer device calculates the amount of memory resources required by the target thread based on the target protocol type's command queue size and the preset CCB size. Specifically, when the command queue size is the number of CCBs, the computer device may determine the amount of memory resources required by the target thread as the product of the target protocol type's command queue size and the preset CCB size.

[0053] For example, the instruction queue size of the target protocol type is DEPTH=10000 (that is, 10,000 instruction control blocks), and the preset instruction control block size CCB_SIZE=1k (that is, 1024 bytes). Accordingly, the amount of memory resources required by the target thread is DEPTH×CCB_SIZE=10000K, which is about 10M.

[0054] Step S403 : According to the memory resource amount, a memory page to be used that matches the memory resource amount is selected from the memory pages included in the target memory area bound to the target physical core.

[0055] Specifically, the computer device may select one or more to-be-used memory pages that match the memory resource amount from the memory pages included in the target memory area bound to the target physical core according to the memory resource amount and the preset memory page size. Accordingly, this step may specifically include:

[0056] Step 1: Determine the number of memory pages based on the amount of memory resources and the preset memory page size.

[0057] Step 2: According to the number of memory pages, one or more memory pages having the same number as the number of memory pages are selected from the memory pages included in the target memory area as memory pages to be used.

[0058] The computer device may determine the ratio of the amount of memory resources to the preset memory page size as the number of memory pages, and select one or more memory pages equal to the number of memory pages from the memory pages included in the target memory area as memory pages to be used based on the number of memory pages.

[0059] Step S404: Bind the memory page to be used to the target thread.

[0060] Specifically, the computer device may use multiple methods to bind the memory page to be used to the target thread.

[0061] Method 1: obtain the physical address information of the memory page to be used, record the mapping relationship information between the identification information of the target thread and the physical address information of the memory page to be used, and bind the target thread to the physical address information of the memory page to be used.

[0062] Method 2: Obtain the physical address information of the memory page to be used. Perform an address translation operation on the physical address information of the memory page to be used to obtain the virtual address information of the memory page to be used. Record the mapping relationship between the identification information of the target thread and the virtual address information of the memory page to be used, and use it to bind the target thread to the virtual address information of the memory page to be used.

[0063] Method 3: Obtain the virtual address information of the memory page to be used. Record the mapping relationship between the identification information of the target thread and the virtual address information of the memory page to be used, so as to bind the target thread with the virtual address information of the memory page to be used. The virtual address information of the memory page to be used can be predetermined by the following method:

[0064] After the computer device completes the binding operation between the memory area and the physical core, it performs an address translation operation on the physical address information of each memory page in the memory area to obtain the virtual address information of each memory page. It also records the identification information of each physical core and the mapping information of the virtual address information of the memory page assigned to the physical core. This way, when binding the memory page to be used, there is no need to perform an address translation operation. The virtual address information of the memory page to be used can be directly obtained from the above mapping information, and the target thread can be bound to the virtual address information of the memory page to be used, which is more efficient.

[0065] By pre-binding the virtual address information of the thread and the memory page through the above-mentioned methods, the corresponding memory resources can be used according to the virtual address information when processing the operation instruction subsequently, without the need for temporary application, thereby improving the processing efficiency of the operation instruction.

[0066] The physical address information may include an offset address and a length.

[0067] In the above three methods, the operation of obtaining the physical address information may specifically be that the computer device obtains the physical address information of each memory page to be used according to the determined identification information of each memory page to be used.

[0068] In the above three methods, the address translation operation can specifically be that the computer device can call an address translation function (for example, it can be an Mmap interface) to perform an address translation operation on the physical address information of each memory page to be used, and obtain the virtual address information of each memory page to be used.

[0069] In this way, after completing the binding operation between the thread and the memory page to be used, the memory resources bound to the target thread can be used when the target thread is used to execute related business. That is, the target physical core can use the virtual address information bound to the target thread to access the memory area bound to the target physical core.

[0070] In some optional implementations, since the processing of operation instructions requires the use of an instruction control block, to improve the efficiency of processing subsequent operation instructions, the computer device can pre-create an instruction control block in each memory page to be used. Accordingly, the computer device can separately create an instruction control block in each of the memory pages to be used. This eliminates the need for temporary creation of instruction control blocks, and can greatly improve the efficiency of processing operation instructions in the protocol thread.

[0071] The memory resource allocation method of the embodiment of the present application allocates memory resources to each thread, allowing the thread to use its own resources for related business operations, thereby avoiding the problem of resource competition caused by multiple threads accessing the same memory resource. In addition, the present application does not require locking operations; each thread only needs to access its own bound memory, which improves efficiency.

[0072] After completing the binding operation of the target thread and the virtual address information of the memory page and creating the instruction control block, the computer device can allocate memory resources for the operation instruction on this basis and perform business processing on the operation instruction. Accordingly, the embodiment of the present application also provides a memory resource allocation method that can be executed by the above-mentioned computer device, such as Figure 5 As shown, the specific processing steps of the memory resource allocation method may include:

[0073] Step S501 : When an operation instruction of a target protocol type is received, it is determined whether there is an unused instruction control block in the memory page to be used according to identification information of the target thread.

[0074] The target protocol type is the protocol type of the target thread.

[0075] Specifically, when a computer device receives an operation instruction of a target protocol type using a target thread, the computer device may determine, based on the identification information of the target thread, a memory page to be used corresponding to the identification information of the target thread in the memory pages bound to the target physical core, and determine whether there is an unused instruction control block in the memory page to be used. Accordingly, the computer device may determine whether there is an unused instruction control block in the memory page to be used according to the following steps, including:

[0076] Step 1: According to the identification information of the target thread, obtain the virtual address information of the memory page to be used corresponding to the target thread.

[0077] Step 2: Determine whether there is an unused instruction control block among the instruction control blocks included in the memory page to be used according to the virtual address information of the memory page to be used.

[0078] In step 1, the computer device may determine the virtual address information of the to-be-used memory page corresponding to the target thread from the virtual address information of the to-be-used memory pages corresponding to the plurality of threads according to the identification information of the target thread.

[0079] In step 2, the computer device can obtain the status corresponding to each instruction control block included in the memory page to be used based on the virtual address information of the memory page to be used. When it is determined that the state of any instruction control block is a third preset state, it is determined that there are unused instruction control blocks in the instruction control blocks included in the memory page to be used. Alternatively, when it is determined that the state of no instruction control block is a third preset state, it is determined that there are no unused instruction control blocks in the instruction control blocks included in the memory page to be used. The third preset state can be an idle state, that is, the instruction control block is not in use.

[0080] Step S502 : When it is determined that there are unused instruction control blocks in the memory page to be used, an instruction control block is selected from the unused instruction control blocks as a target instruction control block.

[0081] Specifically, when the computer device determines that there are unused instruction control blocks in the memory page to be used, it can select an instruction control block from the unused instruction control blocks as the target instruction control block according to a preset allocation rule, which can be specifically done in the following ways:

[0082] Method 1: randomly select an instruction control block from unused instruction control blocks as the target instruction control block.

[0083] Method 2: Since each instruction control block corresponds to a number, the instruction control block with the smallest number can be selected from the unused instruction control blocks as the target instruction control block.

[0084] Step S503 : encapsulate the target instruction control block in the target thread according to the target protocol type and the operation instruction to obtain an encapsulated target instruction control block.

[0085] Specifically, the computer device can use the target thread to parse the operation instructions, obtain the operation information, and fill the operation information into the specified field of the target instruction control block. Further, according to the target protocol type, the encapsulation code corresponding to the target protocol type is obtained, and based on this encapsulation code, the target instruction control block after filling in the operation information is encapsulated to obtain the encapsulated target instruction control block.

[0086] Step S504 : When it is determined that the state of the target device corresponding to the target thread is the first preset state and the state of the target port corresponding to the target thread is the second preset state, the encapsulated target instruction control block is sent to the target device in the target thread.

[0087] The first preset state is used to indicate that the remaining load of the target device is sufficient to process the target instruction control block, and the second preset state is used to indicate that the target port is in a normal working state.

[0088] Specifically, the computer device can first determine whether the number of operation instructions sent to the target device that have not returned processing results has reached a preset queue depth. If so, it can be determined that the state of the target device is not the first preset state. At this time, the target device is operating at full capacity and cannot process the target instruction control block. The encapsulated target instruction control block can be added to a pre-established waiting queue. If not, it indicates that the target device has remaining load to process the target instruction control block, and the state of the target device can be changed to the first preset state. Furthermore, if it is determined that the target device has remaining load to process the target instruction control block, the computer device also needs to determine whether the state of the target port corresponding to the target device is the second preset state (generally also referred to as the available state). If so, the encapsulated target instruction control block can be sent to the target port, and then the target port will send the target instruction control block to the target device. If not, the encapsulated target instruction control block can be added to the pre-established waiting queue. For example, this waiting queue can also be generally named the received queue.

[0089] After the computer device sends the target instruction control block to the target device, the target device processes the encapsulated target instruction control block, obtains a processing result, and feeds it back to the computer device.

[0090] Step S505: When the processing result fed back by the target device is received, a processing operation corresponding to the processing result is executed according to the processing result.

[0091] Specifically, when the computer device receives the processing result fed back by the target device, it can perform corresponding operations according to the content included in the processing result. Accordingly, the computer device can perform processing in various situations:

[0092] In case 1, when it is determined that the processing result does not include an error code, the processing result is directly determined as the final processing result.

[0093] In case 2, when it is determined that the processing result includes an error code, the level corresponding to the error code is obtained according to the error code and the target protocol type, and the error processing operation corresponding to the level is performed according to the level corresponding to the error code.

[0094] When it is determined that the processing result does not include an error code, the computer device may directly determine the processing result as the final processing result, and feed back the error code in the processing result to an upper layer (for example, a data processing software).

[0095] When the error code's corresponding level is level one, indicating a serious error, the computer device may release the target instruction control block and set the target instruction control block's state to a third preset state. Furthermore, when the computer device determines that the error code matches a preset error code, indicating that the error may result in serious consequences, the computer device may directly remove the storage path corresponding to the target device and set the target device's state to offline to prevent more serious problems from the error. When the error code is determined not to match the preset error code, the error code in the processing result is directly fed back to the upper layer, the target instruction control block is released, and the target instruction control block's state is set to a third preset state. Alternatively, when the error code's corresponding level is level two, the target instruction control block's state is set to a fifth preset state (indicating that the target instruction control block is in a retry state), and the target instruction control block is added to a pre-established retry queue for re-issuance to the target device for service processing. Level one error severity is higher than level two error severity.

[0096] The memory resource allocation method of the embodiment of the present application can encapsulate and issue a target instruction control block in a target thread for any type of protocol operation instruction, such as the target protocol type mentioned above. There is no need to switch threads back and forth during the processing of the target instruction control block, which can improve the processing efficiency of the target instruction control block.

[0097] In the process of processing operation instructions, in order to ensure that each operation instruction can be completed on time, the computer device can monitor the status of each instruction control block. Accordingly, the embodiment of the present application also provides a monitoring method of the instruction control block, which can be executed by the above-mentioned computer device, such as Figure 6 As shown, the specific processing steps of the monitoring method of the instruction control block may include:

[0098] Step S601: After starting the monitoring task on the target thread, the status of the instruction control blocks included in the memory page to be used bound to the target thread are monitored respectively.

[0099] Specifically, the computer device may create a monitoring task on each thread, and monitor the status of the instruction control block in the to-be-used memory page bound to the thread through the monitoring task.

[0100] Taking the target thread as an example, after starting a monitoring task on the target thread, the computer device can use this monitoring task to periodically traverse the status of each instruction control block included in the memory page to be used. For example, the length of the cycle can be 10 seconds. Alternatively, when the computer device monitors that the status of any instruction control block switches from another state to a fourth preset state, it can start timing to monitor the length of time the instruction control block is in the fourth preset state. The fourth preset state is used to indicate that the target device is processing the target instruction control block.

[0101] Step S602: When it is monitored that the duration of the target instruction control block being in the fourth preset state reaches a preset duration threshold, the target instruction control block is withdrawn.

[0102] Specifically, when the computer device uses the monitoring task on the target thread to monitor that the state of the target instruction control block is in the fourth preset state for multiple consecutive cycles, it can be determined that the processing operation of the target instruction control block has timed out. Alternatively, when the timing duration of the computer device and the target instruction control block in the fourth preset state reaches a preset timing duration threshold, it can be determined that the processing operation of the target instruction control block has timed out. In the case of determining that the target instruction control processing operation has timed out, the computer device can withdraw the target instruction control block through the target thread. For example, a stop processing instruction corresponding to the target instruction control block can be sent to the target device. After receiving the stop processing instruction, the target device stops operating on the target instruction control block.

[0103] The instruction control block monitoring method of the embodiment of the present application monitors the status of each instruction control block, which can facilitate the management of the instruction processing process. Furthermore, monitoring is performed on the target thread, eliminating the need for a separate thread to monitor the status of the instruction control block, which can save computing resources.

[0104] The following is a detailed description of the execution process of the above memory resource allocation method using a specific example. Figure 7 The process shown performs memory allocation operations.

[0105] A computer device may include a memory management (MM) module and a protocol manager (PROTO_MGR) module. The memory management module may include an operating system memory management (OS_MM) module and a memory management manager (MM_MGR) submodule. The protocol management module may include a protocol initialization (PROTO_INIT) submodule, a command packaging (CMD_PACK) submodule, a command timeout monitoring (CMD_TIMOUT) submodule, and a command transfer (CMD_XFER) submodule.

[0106] First, after the computer device boots up its central processing unit (CPU), it loads memory resources. The memory management submodule initializes the memory resources. Specifically, this can involve enabling NUMA configuration, binding memory to node identification information, and binding physical cores to node identification information. Furthermore, after partitioning the memory into memory zones, it then individually binds each memory zone to each physical core.

[0107] Then, during the initialization process of the protocol initialization submodule, the amount of memory resources required by the target thread can be determined based on the instruction queue size and the preset instruction control block size corresponding to the target thread of the target protocol type, and based on the amount of memory resources, the memory page on the memory area bound to the target physical core where the target thread is located is allocated to the target thread, and the target thread is bound to the physical address information of the memory page. Further, the Mmap interface in the operating system management submodule is called to perform an address conversion operation on the physical address information of the memory page to obtain the virtual address information fed back by the Mmap interface. The protocol initialization submodule binds the target thread to the virtual address information of the memory page. For any thread, memory resources can be allocated in a similar manner.

[0108] After completing the above memory resource allocation operation for each thread, the command timeout monitoring submodule can perform initialization operation and start monitoring tasks on each thread respectively to monitor the status of the instruction control block in the memory page of the physical core corresponding to the thread.

[0109] When the target thread receives an operation instruction, the command encapsulation submodule can select a target instruction control block from the memory page of the memory area associated with the target thread (for example, the target thread runs on physical core 1 of central processing unit 1, and the memory area associated with the target thread is memory area 1 in memory 1) and assign it to the operation instruction, encapsulate the target instruction control block into the format of the target protocol type, and use the command transmission submodule to send the target instruction control block to the target device.

[0110] The computer device monitors whether there is an instruction control block in the target thread that has timed out in the fourth preset state. If so, the command transmission submodule is used to withdraw the target instruction control block and perform error processing on the target instruction control block.

[0111] The memory resource allocation method of the embodiment of the present application processes the target instruction control block, and the encapsulation, issuance, and monitoring of the target instruction control block are all processed in one thread, without switching threads and locking, which can improve the processing efficiency of the instruction control block.

[0112] In the process of processing the instruction control block, the memory resources can be managed by setting the state of the instruction control block. Accordingly, the state of the instruction control block can be Figure 8 Transformation.

[0113] The state of the instruction control block may be one of the following: spare, received, sending, active, aborted, aborting, completing, completed, or retry. The spare state may be the third preset state, the active state may be the fourth preset state, and the retry state may be the fifth preset state.

[0114] When an instruction control block is unused, its status is Idle. Upon receiving an operation instruction of the target protocol type, the computer device may allocate an unused instruction control block in the memory area corresponding to the target thread of the target protocol type to the operation instruction. The target instruction control block is encapsulated based on the target protocol type and the operation instruction. Upon determining that the target device queue is full, the computer device may add the target instruction control block to the Received Queue of the protocol management module and set the target instruction control block's status to Received. Alternatively, upon determining that the target device queue is not full, the computer device may add the target instruction control block to the Active Queue and set the target instruction control block's status to Sending. The computer device uses the target thread to send the target instruction control block to the target device and sets the target instruction control block's status to Running. If the target thread receives the processing result from the target device within a timeout, the computer device sets the target instruction control block's status to Completing. Furthermore, the computer device can parse the processing result. When it is determined that the processing result does not include an error code, it can feed the processing result back to the upper layer and set the status of the target instruction control block to the completed state. Then, the target instruction control block is released and the status of the target instruction control block is set to the idle state. In this way, the target device queue will be free, and the instruction control block in the received state can continue to be processed. Alternatively, when it is determined that the processing result includes an error code, and the error code is a general error code (i.e., a second-level error code), the status of the target instruction control block can be set to the retry state and placed in the retry queue. After the error processing is completed, the target instruction control block can be reprocessed, sent to the target device using the target thread, and the status of the target instruction control block can be set to the sending state.

[0115] When the computer device monitors that the target instruction control block has been in the running state for a period exceeding a preset time threshold, the state of the target instruction control block can be set to the suspended state, and then the target thread can be switched to withdraw the target instruction control block, and then the state of the target instruction control block can be set to the suspending state. After withdrawing the target instruction control block, the state of the target instruction control block can be set to the completing state. At this time, the target instruction control block can be added to the retry queue, and the state of the target instruction control block can be set to the retry state to wait until the next cycle (i.e., the previously monitored cycle length) to reprocess the target instruction control block.

[0116] The memory resource allocation method of the embodiment of the present application can understand the execution status of the operation instructions by managing the status of the instruction control block, and manage memory resources more conveniently.

[0117] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0118] The embodiment of the present application also provides a memory resource allocation device, such as Figure 9 Shown, including:

[0119] An acquisition module 910 is configured to acquire identification information of at least one node, and physical core configuration information and memory configuration information corresponding to each of the at least one node;

[0120] a determination module 920 configured to determine the number of physical cores included in a target central processing unit corresponding to the target node based on the physical core configuration information corresponding to the identification information of the target node, wherein the target node is any one of the at least one node;

[0121] a partitioning module 930 for partitioning the memory corresponding to the target memory configuration information into a plurality of memory areas equal in number to the number of physical cores based on the number of physical cores, a preset memory page size, and the target memory configuration information corresponding to the target node;

[0122] The allocation module 940 is used to bind multiple memory areas to multiple physical cores included in the target central processor one by one, so as to allocate memory resources of the memory area to the physical cores bound to the memory area, wherein any physical core only accesses the memory area bound to itself.

[0123] In some optional implementations, each memory area includes at least one memory page; the allocation module 940 is further configured to:

[0124] Obtaining an instruction queue size of a target thread running on a target physical core, wherein the target physical core is any one of a plurality of physical cores included in a target central processing unit;

[0125] Determine the amount of memory resources required by the target thread based on the instruction queue size and the preset instruction control block size;

[0126] According to the memory resource amount, selecting a to-be-used memory page that matches the memory resource amount from memory pages included in the target memory area bound to the target physical core;

[0127] Bind the memory page to be used to the target thread to allocate the memory resources corresponding to the memory page to be used to the target thread.

[0128] In some optional implementations, the allocation module 940 is specifically configured to:

[0129] Get the physical address information of the memory page to be used;

[0130] Performing an address translation operation on the physical address information of the memory page to be used to obtain the virtual address information of the memory page to be used;

[0131] The mapping relationship information between the identification information of the target thread and the virtual address information of the memory page to be used is recorded to bind the target thread with the virtual address information of the memory page to be used.

[0132] In some optional implementations, the memory page to be used includes an instruction control block; and the allocation module 940 is further configured to:

[0133] When receiving an operation instruction of a target protocol type, determining whether there is an unused instruction control block in the memory page to be used according to the identification information of the target thread, wherein the target protocol type is the protocol type of the target thread;

[0134] When it is determined that there are unused instruction control blocks in the memory page to be used, selecting an instruction control block from the unused instruction control blocks as a target instruction control block;

[0135] encapsulating the target instruction control block in the target thread according to the target protocol type and the operation instruction to obtain an encapsulated target instruction control block;

[0136] When it is determined that the state of the target device corresponding to the target thread is the first preset state, and the state of the target port corresponding to the target thread is the second preset state, sending the encapsulated target instruction control block to the target device in the target thread, so that the target device processes the encapsulated target instruction control block and obtains a processing result;

[0137] When the processing result fed back by the target device is received, a processing operation corresponding to the processing result is executed according to the processing result.

[0138] In some optional implementations, the allocation module 940 is specifically configured to:

[0139] According to the identification information of the target thread, obtain the virtual address information of the memory page to be used corresponding to the target thread;

[0140] According to the virtual address information of the memory page to be used, it is determined whether there is an unused instruction control block in the instruction control blocks included in the memory page to be used.

[0141] In some optional implementations, the allocation module 940 is specifically configured to:

[0142] According to the virtual address information of the memory to be used, the state corresponding to each instruction control block included in the memory page to be used is obtained;

[0143] When it is determined that the state of any instruction control block is the third preset state, determining that there is an unused instruction control block among the instruction control blocks included in the memory page to be used;

[0144] or,

[0145] When it is determined that the state in which no instruction control block exists is the third preset state, it is determined that no unused instruction control block exists among the instruction control blocks included in the memory page to be used.

[0146] In some optional implementations, the allocation module 940 is specifically configured to:

[0147] When it is determined that the processing result does not include an error code, the processing result is directly determined as the final processing result;

[0148] or,

[0149] When it is determined that the processing result includes an error code, obtaining a level corresponding to the error code according to the error code and the target protocol type;

[0150] According to the level corresponding to the error code, an error handling operation corresponding to the level is performed.

[0151] For the description of the features in the embodiment corresponding to the memory resource allocation device, reference can be made to the relevant description of the embodiment corresponding to the memory resource allocation method, which will not be repeated here.

[0152] The acquisition module 910 , determination module 920 , division module 930 , and allocation module 940 may be modules obtained by re-dividing and renaming the memory management module and the protocol management module.

[0153] The embodiment of the present application also provides an electronic device, such as Figure 10 As shown, it includes a memory 10 and a processor 20. The memory 10 stores a computer program, and the processor 20 is configured to run the computer program to execute the steps in any of the above-mentioned memory resource allocation method embodiments. The electronic device can be the above-mentioned computer device.

[0154] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any of the above-mentioned memory resource allocation method embodiments when running.

[0155] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0156] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of any of the above-mentioned memory resource allocation method embodiments are implemented.

[0157] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of any of the above-mentioned memory resource allocation method embodiments are implemented.

[0158] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0159] The above is a detailed introduction to a memory resource allocation method, device, electronic device, storage medium, and program product provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core ideas of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A memory resource allocation method, characterized in that: include: Obtaining identification information of at least one node, and physical core configuration information and memory configuration information corresponding to each of the at least one node; Determining the number of physical cores included in a target central processing unit corresponding to the target node according to the physical core configuration information corresponding to the identification information of the target node, wherein the target node is any one of the at least one nodes; According to the number of the physical cores, the preset memory page size, and the target memory configuration information corresponding to the target node, the memory corresponding to the target memory configuration information is divided into a plurality of memory areas whose number is equal to the number of the physical cores, each of the memory areas including at least one memory page; Binding the plurality of memory areas to the plurality of physical cores included in the target central processing unit one by one, so as to allocate memory resources of the memory areas to the physical cores bound to the memory areas, wherein any physical core only accesses the memory areas bound to itself; Obtaining an instruction queue size of a target thread running on a target physical core, the target physical core being any one of a plurality of physical cores included in the target central processing unit; determining an amount of memory resources required by the target thread based on the instruction queue size and a preset instruction control block size; selecting, based on the amount of memory resources, a to-be-used memory page that matches the amount of memory resources from memory pages included in a target memory area bound to the target physical core, the to-be-used memory page including an instruction control block; binding the to-be-used memory page to the target thread to allocate memory resources corresponding to the to-be-used memory page to the target thread; When an operation instruction of a target protocol type is received and, based on the identification information of the target thread, it is determined that there are unused instruction control blocks in the memory page to be used, an instruction control block is selected from the unused instruction control blocks as a target instruction control block, and the target protocol type is the protocol type of the target thread; based on the target protocol type and the operation instruction, the target instruction control block is encapsulated in the target thread to obtain an encapsulated target instruction control block; when it is determined that the state of the target device corresponding to the target thread is a first preset state, and the state of the target port corresponding to the target thread is a second preset state, the encapsulated target instruction control block is sent to the target device in the target thread, so that the target device processes the encapsulated target instruction control block to obtain a processing result; when the processing result fed back by the target device is received, a processing operation corresponding to the processing result is executed based on the processing result.

2. The memory resource allocation method according to claim 1, wherein: Binding the memory page to be used with the target thread includes: Obtaining physical address information of the memory page to be used; Performing an address conversion operation on the physical address information of the memory page to be used to obtain virtual address information of the memory page to be used; The mapping relationship information between the identification information of the target thread and the virtual address information of the memory page to be used is recorded to bind the target thread with the virtual address information of the memory page to be used.

3. The memory resource allocation method according to claim 1, wherein: Determining, according to the identification information of the target thread, whether there is an unused instruction control block in the memory page to be used includes: Acquire, according to the identification information of the target thread, virtual address information of the to-be-used memory page corresponding to the target thread; According to the virtual address information of the memory page to be used, it is determined whether there is an unused instruction control block in the instruction control blocks included in the memory page to be used.

4. The memory resource allocation method according to claim 3, wherein: The determining, based on the virtual address information of the memory page to be used, whether there is an unused instruction control block in the instruction control blocks included in the memory page to be used comprises: According to the virtual address information of the memory page to be used, obtaining the status corresponding to each instruction control block included in the memory page to be used; When it is determined that the state of any instruction control block is the third preset state, determining that there is an unused instruction control block among the instruction control blocks included in the memory page to be used; or, When it is determined that the state in which no instruction control block exists is the third preset state, it is determined that no unused instruction control block exists among the instruction control blocks included in the memory page to be used.

5. The memory resource allocation method according to any one of claims 1 to 4, characterized in that: When receiving the processing result fed back by the target device, performing a processing operation corresponding to the processing result according to the processing result includes: When it is determined that the processing result does not include an error code, directly determining the processing result as the final processing result; or, When it is determined that the processing result includes an error code, obtaining a level corresponding to the error code according to the error code and the target protocol type; According to the level corresponding to the error code, an error handling operation corresponding to the level is performed.

6. A memory resource allocation device, characterized in that: include: an acquisition module, configured to acquire identification information of at least one node, and physical core configuration information and memory configuration information corresponding to each of the at least one node; a determination module, configured to determine the number of physical cores included in a target central processing unit corresponding to the target node according to the physical core configuration information corresponding to the identification information of the target node, wherein the target node is any one of the at least one nodes; a partitioning module, configured to partition the memory corresponding to the target memory configuration information into a plurality of memory areas equal in number to the number of the physical cores, based on the number of the physical cores, a preset memory page size, and the target memory configuration information corresponding to the target node; An allocation module is used to bind the multiple memory areas to the multiple physical cores included in the target central processing unit one by one, so as to allocate the memory resources of the memory area to the physical core bound to the memory area, wherein any physical core only performs access operations on the memory area bound to itself; obtain the instruction queue size of the target thread running on the target physical core, wherein the target physical core is any physical core among the multiple physical cores included in the target central processing unit; determine the amount of memory resources required by the target thread according to the instruction queue size and the preset instruction control block size; according to the memory resource amount, select a to-be-used memory page that matches the memory resource amount from the memory pages included in the target memory area bound to the target physical core, wherein the to-be-used memory page includes an instruction control block; bind the to-be-used memory page to the target thread, so as to allocate the memory resources corresponding to the to-be-used memory page to the target thread; when an operation of the target protocol type is received, The method comprises the steps of: performing an instruction and determining, based on the identification information of the target thread, that there is an unused instruction control block in the memory page to be used, selecting an instruction control block from the unused instruction control blocks as a target instruction control block, and the target protocol type is the protocol type of the target thread; encapsulating the target instruction control block in the target thread according to the target protocol type and the operation instruction to obtain an encapsulated target instruction control block; when it is determined that the state of the target device corresponding to the target thread is a first preset state, and the state of the target port corresponding to the target thread is a second preset state, sending the encapsulated target instruction control block to the target device in the target thread, so that the target device processes the encapsulated target instruction control block to obtain a processing result; and when the processing result fed back by the target device is received, executing a processing operation corresponding to the processing result according to the processing result.

7. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the memory resource allocation method according to any one of claims 1 to 5 when executing the computer program.

8. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the memory resource allocation method according to any one of claims 1 to 5.

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