Backplane test apparatus, method, system, device, storage medium and program product

Abstract

The application discloses a backboard testing device, method, system, equipment, storage medium and program product, relates to the technical field of servers, and significantly reduces testing cost and improves testing efficiency by simulating the communication protocol and hot plug behavior of a real hard disk. The device uses an interface module and a controller to support multiple hard disk communication protocols and adapt to different types of backboard testing requirements. Through automated testing, manual operation is reduced, testing speed is accelerated, signal integrity and power supply stability are ensured, hot plug operation is simulated, physical wear is reduced, and equipment life is prolonged.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of servers, and in particular to a backboard testing device, method, system, equipment, storage medium and program product. BACKGROUND

[0002] With the development of artificial intelligence, large-scale data centers and high-performance computing, the bandwidth and performance requirements of storage devices have increased dramatically. Enterprise and Data Center Standard Form Factor (EDSFF) hard drives have become the preferred solution for modern data centers and enterprise-level storage due to their higher bandwidth, scalability and power efficiency. The EDSFF hard drive backboard, as a key component for connecting and managing multiple EDSFF hard drives in a server, its function test is crucial.

[0003] In related technologies, real hard drives are usually used to test the backboard of the hard drive. However, due to the high cost of EDSFF hard drives, even some cutting-edge products have not been mass-marketed, resulting in high cost and low efficiency of backboard testing. SUMMARY

[0004] The present application provides a backboard testing device, method, system, equipment, storage medium and program product to at least solve the problem of high cost and low efficiency of backboard testing in related technologies.

[0005] The present application provides a backboard testing device, comprising: an interface module supporting a preset hard drive communication protocol, a controller and a connector;

[0006] The interface module and the controller are both used to connect the to-be-tested backboard through the connector;

[0007] The interface module is used to communicate with the to-be-tested backboard based on the preset hard drive communication protocol, and to realize function testing of the to-be-tested backboard;

[0008] The controller is used to test the hot plug function of the to-be-tested backboard in response to the received hot plug simulation test instruction.

[0009] The present application also provides a backboard testing system, comprising: a test host and a backboard testing device as any of the above; the backboard testing device comprises: an interface module supporting a preset hard drive communication protocol, a controller and a connector;

[0010] The test host is connected to the to-be-tested backboard; the interface module and the controller are both used to connect the to-be-tested backboard through the connector;

[0011] The test host is used to send a test instruction to the to-be-tested backboard to make the to-be-tested backboard communicate with the interface module;

[0012] The interface module is configured to communicate with the to-be-tested backboard based on a preset hard disk communication protocol, and implement the function test on the to-be-tested backboard.

[0013] The controller is configured to test the hot plug function of the to-be-tested backboard in response to receiving the hot plug simulation test instruction issued by the test host.

[0014] The application further provides a backboard test method applied to a backboard test device.

[0015] The method comprises the following steps.

[0016] In response to receiving the simulation pull-out instruction, a first level signal is output to the reset pin of the to-be-tested backboard to trigger the disconnection.

[0017] If the power supply output of the interface module is 0 and the in-position detection signal indicates that it is not in position, it is determined that the pull-out function of the hot plug of the to-be-tested backboard is normal.

[0018] And / or,

[0019] In response to receiving the simulation insertion instruction, a second level signal is output to the in-position detection pin of the to-be-tested backboard to trigger the power-on of the to-be-tested backboard.

[0020] If the power supply output of the interface module is normal, the bandwidth rate is normal, and the reset signal indicates that it is not reset, it is determined that the insertion function of the hot plug of the to-be-tested backboard is normal.

[0021] The application further provides an electronic device comprising a memory for storing a computer program and a processor for executing the computer program to implement the steps of any of the above backboard test methods.

[0022] The application further provides a computer readable storage medium having a computer program stored therein, wherein the computer program is executed by a processor to implement the steps of any of the above backboard test methods.

[0023] The application further provides a computer program product comprising a computer program, wherein the computer program is executed by a processor to implement the steps of any of the above backboard test methods.

[0024] By simulating the communication protocol and hot plug behavior of real hard drives, the application significantly reduces testing costs and improves testing efficiency. The device uses interface modules and controllers to support multiple hard drive communication protocols and adapt to different types of backplane testing needs. Through automated testing, manual operations are reduced, testing speed is accelerated, and signal integrity and power stability are ensured. Simulating hot plug operations reduces physical wear and tear and extends equipment life. BRIEF DESCRIPTION OF DRAWINGS

[0025] To more clearly illustrate the embodiments of the present application, the following will be a brief introduction to the drawings needed in the embodiments, obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative labor on the basis of these drawings.

[0026] Figure 1 The architecture schematic diagram of the backplane test system provided by the embodiments of the present application is shown in the figure.

[0027] Figure 2 The structure schematic of the backplane test device provided by the embodiments of the present application is shown in the figure. Figure 1 ;

[0028] Figure 3 The structure schematic of the backplane test device provided by the embodiments of the present application is shown in the figure. Figure 2 ;

[0029] Figure 4 The structure schematic of the indicator module in the backplane test device provided by the embodiments of the present application is shown in the figure.

[0030] Figure 5 The flow schematic of the backplane test method provided by the embodiments of the present application is shown in the figure. Figure 1 ;

[0031] Figure 6 The flow schematic of the backplane test method provided by the embodiments of the present application is shown in the figure. Figure 2 ;

[0032] Figure 7 The structure schematic of the backplane test device provided by the embodiments of the present application is shown in the figure.

[0033] Figure 8 The structure schematic of the electronic device provided by the embodiments of the present application is shown in the figure.

[0034] Reference signs:

[0035] 201: interface module; 202: controller; 203: connector; 204: clock generator; 205: voltage converter; 206: indicator module; 207: temperature sensor; 208: power supply module. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0037] It should be noted that, in the description of the present application, the terms “comprise”, “contain” or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. The terms “first”, “second” and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0038] Enterprise and Data Center Standard Form Factor (EDSFF) is a standard form factor for Solid State Drives (SSDs) designed specifically for enterprise and data center use. It aims to meet the needs of high-performance computing, large-scale data storage, and high-speed data transmission. The EDSFF standard provides multiple connector types (such as 1C, 2C, 4C, 4C+) and form factors (such as E1.S, E3.S) to accommodate the storage needs of different server architectures.

[0039] Among them, the meaning of each connector type:

[0040] 1C: Basic connector, supports 4 pairs of high-speed differential pairs (PCIe lanes), 80W power (12V main power and 3.3V auxiliary power) and sideband signals (such as SMBUS).

[0041] 2C: Add 4 pairs of high-speed differential pairs to 1C, totaling 8 pairs.

[0042] 4C: Add another 8 pairs of high-speed differential pairs to 2C, totaling 16 pairs, supporting higher bandwidth (such as PCIe Gen5).

[0043] The meaning of each form factor:

[0044] E1.S: Compact design (110.0mm × 31.5mm), suitable for high-density storage scenarios.

[0045] E3.S: Larger size (110.0mm x 76.0mm) provides more space to accommodate high-performance storage components.

[0046] EDSFF hard disk backplane is a key component in servers for connecting and managing multiple EDSFF hard disks, responsible for providing interfaces for power supply, data transmission (Peripheral Component Interconnect Express (PCIE) channel) and sideband signals (such as hot plug, temperature monitoring). With the popularity of high-speed interfaces such as PCIe 5.0, traditional U.2 / M.2 backplanes have been unable to meet the demand in terms of bandwidth and electrical performance, and EDSFF backplanes have become the preferred choice for high-performance storage solutions.

[0047] With the development of artificial intelligence, large-scale data centers, and high-performance computing, especially after PCIe 5.0, U.2 and M.2 solid state drives (SSDs) can support bandwidth and performance as well as electrical characteristics that are difficult to meet requirements, EDSFF hard drives have become the ideal choice for modern data centers and enterprise-level storage solutions due to their higher bandwidth, outstanding performance, scalability, and power efficiency, etc. and thus have spawned the widespread application of EDSFF hard disk backplanes in the server field.

[0048] For customers who pursue high performance and high reliability, EDSFF can support multiple PCIE channels, providing high-speed data transmission rates and larger storage capacities, making it more suitable for high-performance computing, large-scale data analysis, and other applications that require large-capacity high-speed storage. By adopting EDSFF backplane technology, enterprises and data centers can obtain more efficient storage solutions, not only improving storage density and performance, but also enhancing system maintainability and expansion capabilities, so EDSFF backplanes have broad application prospects.

[0049] Due to the high price of EDSFF hard drives, as the demand for EDSFF backplanes increases, the use of a large number of EDSFF hard drives for batch production testing by Printed Circuit Board Assembly (PCBA) factories results in high testing costs, especially for fifth-generation (Generation 5, Gen5) EDSFF-4C, 4C+ hard drives, which are expensive and difficult to find on the market. Therefore, how to provide a backplane testing device with low testing cost is a technical problem to be solved.

[0050] To solve the above technical problems, the present inventors have found that the communication protocol of the EDSFF solid state disk can be simulated by the PCIE conversion module, the PCIE, the system management bus (SMBus) and other signals of the backboard are connected, the function test verification is realized, the cost of purchasing real hard disks is avoided, the backboard test cost is reduced, and the new generation of hard disks that are difficult to buy can be conveniently pre-researched. In addition, the hot plug signal corresponding to the controller such as the field programmable gate array (FPGA) or the complex programmable logic device (CPLD) can be simulated, the signal integrity and power supply stability are verified, the loss of repeated plugging is avoided, and the backboard test cost is further reduced. Based on this, the embodiment of the present application provides a backboard test device.

[0051] In order for those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0052] The specific application environment architecture or the specific hardware architecture is described here. Refer to Figure 1 , Figure 1 The architecture schematic diagram of the backboard test system provided by the embodiment of the present application is shown. As shown in Figure 1 , the system includes a test host, a backboard test device and a backboard to be tested. The test host is connected with the backboard to be tested, and the test host is used to issue test instructions to the backboard to be tested, and test each signal of the backboard to be tested (such as power supply signal, PCIE signal and sideband signal). The backboard to be tested is connected with the backboard test device, and is used to transmit data with the backboard test device during the test to complete the test. The backboard test device can include an interface module, a controller and a connector. The interface module and the controller are both connected with the backboard to be tested through the connector.

[0053] In the implementation process, the backboard testing device is plugged into the backboard to be tested. The test host sends a test instruction to the backboard to be tested, so that the backboard to be tested communicates with the interface module, the interface module communicates with the backboard to be tested based on a preset hard disk communication protocol, and the function test of the backboard to be tested is realized. The test host is also used to issue a hot plug simulation test instruction to the controller in the backboard testing device, and the controller tests the hot plug function of the backboard to be tested in response to receiving the hot plug simulation test instruction issued by the test host. The backboard testing device provided by the embodiment of the application significantly reduces the test cost and improves the test efficiency by simulating the communication protocol and hot plug behavior of the real hard disk. The device uses the interface module and the controller to support multiple hard disk communication protocols and adapt to different types of backboard test requirements. Through automatic testing, manual operation is reduced, the test speed is accelerated, and the signal integrity and power supply stability are ensured. Simulating the hot plug operation reduces physical wear and tear and prolongs the service life of the equipment.

[0054] Figure 2 Structure diagram of the backboard testing device provided by the embodiment of the application Figure 1 As shown in Figure 2 The embodiment of the application provides a backboard testing device, which is described in detail as follows: the backboard testing device comprises an interface module 201 supporting a preset hard disk communication protocol, a controller 202 and a connector 203.

[0055] The interface module 201 and the controller 202 are both used to connect with the backboard to be tested through the connector 203.

[0056] The interface module 201 is used to communicate with the backboard to be tested based on the preset hard disk communication protocol, and obtain the function test result of the backboard to be tested.

[0057] The controller 202 is used to test the hot plug function of the backboard to be tested in response to the received hot plug simulation test instruction.

[0058] In the embodiment, the interface module 201 refers to a circuit module capable of supporting the communication protocol used for data transmission between the backboard to be tested and the hard disk, for example, a Switch chip supporting PCIE Gen5.

[0059] The function test result can be the result corresponding to the test of field replaceable unit (FRU) information inspection, device identification, bandwidth rate inspection, lighting inspection, sensor inspection, PCIE link exception detection, system exception log inspection, etc.

[0060] In some embodiments, the size of the backplane test device can be designed to be the same as the simulated hard disk, so as to facilitate stress testing and improve assembly convenience. For example, the outer shape of the device can conform to the E3.s standard size of 110.0mm x 76.0mm, integrate SFF-TA-1002 gold finger connectors, support EDSFF-4C interface, and be compatible with EDSFF-1C, EDSFF-2C.

[0061] The controller 202 can be a programmable logic device such as an FPGA or a CPLD.

[0062] In this embodiment, the connector 203 can be a gold finger connector 203, and the EDSFF interface signals can include power supply, PCIE signals, and sideband signals. The pinout of the connector 203 is shown in the following table.

[0063] Table 1

[0064]

[0065] The detailed pin definitions are shown in Tables 2-1, 2-2, and 2-3 as follows:

[0066] Table 2-1

[0067]

[0068] Table 2-2

[0069]

[0070] Table 2-3

[0071]

[0072] In some embodiments, taking the interface module 201 as an example of a built-in PCIE Gen5 supporting Switch chip, 16 groups of EDSFF PCIE TX signals of the backplane under test can be interconnected with the RX of the Switch chip through the connector 203, and 16 groups of EDSFF PCIE RX signals of the backplane under test can be interconnected with the TX of the Switch chip through the connector 203. Then, by detecting the bandwidth rate of the Switch chip, the detection of the interface bandwidth rate of the EDSFF backplane under test can be realized.

[0073] In the implementation process, first, the backplane testing device can be connected to the backplane under test through the connector 203. The connector 203 is used for physical connection, ensuring that the interface module 201 and the controller 202 can communicate with the backplane under test. Then the interface module 201 is initialized and configured to support the preset hard disk communication protocol (such as PCIe Gen5). This step ensures that the interface module 201 can correctly communicate data with the backplane under test. The interface module 201 communicates with the backplane under test based on the preset hard disk communication protocol. This process includes sending and receiving data to verify the functionality of the backplane under normal operating conditions. The interface module 201 (or the test host corresponding to the mainboard connected to the backplane under test) can collect and record the results of the functional test, ensuring that the functions of the backplane (such as data transmission, error handling, etc.) meet expectations. The controller 202 receives the hot plug simulation test instruction. The instruction can be triggered manually by the tester or generated by an automatic test script. The controller 202 generates signals related to hot plug, simulating the insertion and removal process of the hard disk. This includes simulating the establishment and disconnection of electrical connections, as well as the corresponding signal changes. During the simulation of hot plug, the controller 202 monitors the response of the backplane, verifying its functionality and stability under hot plug operation. Verify the integrity of the signal to ensure that there is no signal loss or interference during the hot plug process, and test the power supply stability of the backplane to ensure that the backplane can maintain stable power supply during the simulated hot plug operation. The data and results generated during the test process can be collected and analyzed by the test host. Record any abnormalities or failures for further analysis and improvement. According to the test results, evaluate the performance and reliability of the backplane under test to ensure that it meets design and usage requirements.

[0074] The backplane testing device provided by the embodiments of the present application significantly reduces testing costs and improves testing efficiency by simulating the communication protocol and hot plug behavior of real hard disks. The device uses the interface module 201 and the controller 202 to support multiple hard disk communication protocols, adapting to different types of backplane testing needs. Through automated testing, manual operations are reduced, testing speed is accelerated, and signal integrity and power supply stability are ensured. Simulating hot plug operation reduces physical wear and tear and extends equipment life. In addition, the device supports pre-research of new technologies, helping enterprises to maintain technological leadership.

[0075] In some embodiments, as Figure 3As shown, the device further comprises a clock generator 204 and a voltage converter 205; the voltage converter is connected with the to-be-tested backplane and the clock generator 204, and is configured to perform voltage conversion on the first power supply voltage output by the to-be-tested backplane, so as to provide a second power supply voltage for the clock generator 204; the clock generator 204 is connected with the interface module 201, and is configured to send a clock signal to the interface module 201 under the power supply of the second power supply voltage. In this embodiment, by integrating the voltage converter 205 and the clock generator 204, efficient power management and precise timing control are achieved. The voltage converter 205 reduces the high voltage of the to-be-tested backplane to a low voltage suitable for the clock generator 204, so as to ensure stable operation of the clock generator 204. The high-precision clock signal provided by the clock generator 204 improves the data transmission stability and synchronization of the interface module 201.

[0076] In some embodiments, the voltage converter 205 can be a voltage converter.

[0077] For example, the clock generator 204 can provide a preset frequency (for example, 100 MHz) differential reference clock. The precise timing reference is provided for the PCIE high-speed signal, so as to ensure the stability and synchronization of high-speed data transmission. The voltage converter 205 can convert a 12V voltage into a 1.8V voltage for power supply of the clock generator 204.

[0078] In some embodiments, the device further comprises a first indicator light and / or a second indicator light; the first indicator light is connected with the interface module 201, and is configured to indicate the bandwidth state of the interface module 201; and / or, the second indicator light is connected with the interface module 201, and is configured to indicate the power supply state of the interface module 201. In this embodiment, by setting the first indicator light and the second indicator light, the user can intuitively monitor the working state of the interface module 201 during the backplane test.

[0079] For example, as shown in FIG. 6, the device further comprises a first indicator light 206a and a second indicator light 206b. Figure 3 As shown, the indicator light module 206 comprises a first indicator light and / or a second indicator light.

[0080] In some embodiments, the connector 203 supports multiple hard disk sizes; the first indicator light comprises multiple sub-indicator lights; the multiple sub-indicator lights correspond to the multiple hard disk sizes one by one; and different sub-indicator lights are used to indicate the bandwidth states corresponding to different hard disk sizes. In this embodiment, by intuitively displaying the bandwidth states of different hard disk sizes through the multiple sub-indicator lights, the user can quickly identify the working state and bandwidth effectiveness of the device.

[0081] For example, as shown in FIG. 6, the device further comprises a first indicator light 206a and a second indicator light 206b. Figure 4As shown, the first indicator light in the indicator light module 206 can include a plurality of sub-indicator lights for identifying whether different device bandwidths of 1C, 2C, 4C, etc. are valid, and the second indicator light can be used to identify whether the power input of the device is normal. Specifically, when the X4 PCIE channel is valid, 1C light-emitting diode (LED) light in the plurality of sub-indicator lights is lit, when the X8 PCIE channel is valid, 2C LED light in the plurality of sub-indicator lights is lit, when the X16 PCIE channel is valid, 4C LED light in the plurality of sub-indicator lights is lit, and when the power input is valid, the Power LED is lit, directly showing the valid bandwidth of the device and facilitating abnormality analysis.

[0082] In some embodiments, the device further comprises a temperature sensor 207; the temperature sensor 207 is connected with the interface module 201, and is used to acquire temperature information of the interface module 201 and send the temperature information to the interface module 201; the interface module 201 is used to send the temperature information to the backboard to be tested based on the sideband signal. In this embodiment, the temperature of the switching module is monitored in real time through the integrated temperature sensor 207, and the temperature information is fed back through the GPIO simulated SMBUS signal, so as to realize temperature monitoring of the backboard and sideband signal test coverage.

[0083] As shown in the example, Figure 3 As shown in the example,

[0084] In some embodiments, the device further comprises a power supply module 208; the power supply module 208 is connected with the controller 202, and is used to supply power for the controller 202 in the case of disconnection with the backboard to be tested. In this embodiment, the controller 202 is powered by using an independent power supply module 208, instead of relying on the voltage of the backboard to be tested, so as to ensure that the controller 202 can still work continuously when the hot plug operation causes the power supply of the backboard to be interrupted. This effectively avoids signal simulation interruption caused by power failure, improves the stability and reliability of the system, and ensures the continuity and accuracy of the test process.

[0085] Specifically, external power supply can be used instead of the voltage output by the backboard to be tested, which can solve the problem of EDSFF interface 12V and 3.3V power failure after the hot plug signal is triggered, and signal simulation interruption of the controller 202 (such as FPGA).

[0086] In some embodiments, the power supply module 208 includes a voltage conversion unit; the voltage conversion unit and the controller 202 are used to connect with the test host; the controller 202 is connected with the voltage conversion unit and the backboard to be tested; the voltage conversion unit is used to receive a third power voltage provided by the test host, perform voltage conversion on the third power voltage, and provide a fourth power voltage for the controller 202; the controller 202 is used to output a first level signal to a reset pin of the backboard to be tested in response to receiving a simulated pull-out instruction issued by the test host, and trigger disconnection; if the power supply output of the interface module 201 is 0, and the in-place detection signal indicates that it is not in place, it is determined that the pull-out function of the hot plug of the backboard to be tested is normal; and / or, in response to receiving a simulated insertion instruction issued by the test host, a second level signal is output to the in-place detection pin of the backboard to be tested, and the backboard to be tested is powered on; if the power supply output of the interface module 201 is normal, and the reset signal indicates that it is not reset, and the operating system of the test host detects that the bandwidth rate is normal, and there is no abnormal warning in the system log, it is determined that the insertion function of the hot plug of the backboard to be tested is normal. In the embodiment, the controller 202 (such as FPGA) integrated with independent power supply is used to simulate the hot plug signal response of the backboard to be tested, so that the controller 202 can still work normally during the hot plug operation, even if the backboard power supply is powered off. Through external power supply and the voltage conversion unit, the problem of signal simulation interruption caused by interruption of the backboard voltage is solved. The system can receive the hot plug simulation test instruction of the host end through the serial port, and automatically determine whether the pull-out and insertion operations are normal. In this way, not only the automation degree and accuracy of the test are improved, but also the manual intervention is reduced, and the test efficiency and the reliability of the system are improved.

[0087] For example, the device integrates a controller 202 (such as FPGA) with independent power supply to simulate the hot plug signal response of the backboard to be tested (such as EDSFF hard disk backboard). By using external power supply FPGA, the problem of FPGA signal simulation interruption caused by power failure of EDSFF interface 12V and 3.3V after hot plug signal triggering can be solved.

[0088] In the embodiment, the hot plug simulation test instruction issued by the host end can be received through the serial port.

[0089] The simulation process for the pull-out operation is as follows: when the FPGA (that is, the controller 202) receives a simulation pull-out instruction issued by the test host end, the FPGA simulates output of a low level to the PERST# pin of the EDSFF backboard (that is, the backboard to be tested), triggers assertion, and after the backboard to be tested completes pull-out signal processing (PERST# assertion-low level, power off, PRSNT# reset-high level), whether the power supply voltage 12V, 3.3V output by the backboard to be tested to the device is 0 and whether the PRSNT# information is high level are detected, and if both conditions are yes, it is determined that the backboard hot plug pull-out function is normal, and if one of the two conditions is no, it is determined that the backboard hot plug pull-out function is not normal.

[0090] The simulation process for the insertion operation is as follows: when the FPGA (that is, the controller 202) receives a simulation insertion instruction issued by the test host end, the FPGA simulates output of a low level to the PRSNT# pin of the EDSFF backboard (that is, the backboard to be tested), triggers power-on, and after the backboard to be tested completes insertion signal processing (PRSNT# detection-low level, power enable, PERST# release-high level), whether the power supply voltage 12V, 3.3V output by the backboard to be tested to the device is restored to the corresponding 12V, 3.3V, whether the PERST # information is high level, whether the bandwidth and rate of the interface module 201 are normal under the OS system, and whether there is an abnormal alarm in the system log are detected to determine whether the backboard hot plug insertion function is normal. Specifically, if the PERST # information is high level, the bandwidth and rate of the interface module 201 are normal under the OS system, and there is no abnormal alarm in the system log, it is determined that the backboard hot plug insertion function is normal, otherwise, it is determined that the backboard hot plug insertion function is not normal.

[0091] For the EDSFF backboard test that does not support the hot plug function, the FPGA power supply and serial data line can not be matched, and the hot plug test is not performed.

[0092] The backboard test device provided by the embodiment of the application simulates a real EDSFF hard disk. The communication protocol of the EDSFF solid state hard disk is simulated through a PCIE Switch chip, PCIE link, sideband, power supply and other signal detection are realized, the hot plug signal response is simulated through an integrated independent power supply FPGA, the signal integrity and power supply stability are verified, the loss caused by repeated insertion and removal of the hard disk is avoided, and the test cost is reduced. Specifically, the real EDSFF hard disk is replaced, and the problem of high cost of the EDSFF hard disk backboard test tool is solved. The effective bandwidth of the device is directly displayed through the LED lamp, and the abnormality is quickly located. The hot plug signal response is simulated through the integrated independent power supply FPGA, the signal integrity and power supply stability are verified, the test coverage is improved, and the loss problem caused by repeated insertion and removal in the test process is avoided.

[0093] The backboard testing system provided in the embodiment of the application comprises a test host and the backboard testing device provided in the above embodiment, and the backboard testing device comprises an interface module supporting a preset hard disk communication protocol, a controller and a connector. The test host is connected with the backboard under test. The interface module and the controller are both used to connect the backboard under test through the connector. The test host is used to send a test instruction to the backboard under test, so that the backboard under test communicates with the interface module based on the test instruction. The interface module is used to communicate with the backboard under test based on the preset hard disk communication protocol, so as to realize the function test of the backboard under test. The controller is used to test the hot plug function of the backboard under test in response to receiving the hot plug simulation test instruction issued by the test host. In the embodiment, the backboard testing system integrates the test host and the backboard testing device, so as to realize the comprehensive function test of the backboard under test. The test host is responsible for sending the test instruction, so as to ensure that the communication between the backboard under test and the interface module conforms to the preset hard disk communication protocol. The interface module is responsible for the specific communication operation, so as to ensure the accuracy of the function test. The controller is specially used to simulate the hot plug operation, so as to automatically test the hot plug function of the backboard. The system design improves the automation degree and efficiency of the test process, reduces the manual intervention, ensures the reliability and consistency of the test result, and helps to quickly identify and solve the potential problems of the backboard. Specifically, the real EDSFF hard disk is simulated. The communication protocol of the EDSFF solid state hard disk is simulated through the PCIE Switch chip, so as to realize the signal detection of the PCIE link, the sideband and the power supply. The signal integrity and the power supply stability are verified through the simulation of the hot plug signal response of the integrated independent power supply FPGA, so as to avoid the loss caused by repeatedly plugging the hard disk and reduce the test cost.

[0094] Figure 5 Flowchart of the backboard testing method provided for the embodiment of the application Figure 1 As shown in Figure 5 , the backboard testing method provided in the embodiment of the application specifically comprises the following steps:

[0095] 501, in response to receiving the simulation pull-out instruction, outputting a first level signal to the reset pin of the backboard under test to trigger the disconnection.

[0096] In the embodiment, the first level signal can be a low level signal (for example, 0~0.3V), which represents that the hard disk is pulled out and needs to be reset.

[0097] 502, if the power supply output of the interface module 201 is 0 and the in-place detection signal indicates that it is not in place, it is determined that the pull-out function of the hot plug of the backboard under test is normal.

[0098] 503, in response to receiving the simulation insertion instruction, outputting a second level signal to the in-place detection pin of the backboard under test to trigger the power-on of the backboard under test.

[0099] In this embodiment, the second level signal can be a low level signal (e.g., 0~0.3V), indicating that the hard drive is inserted and the backplane needs to be powered on.

[0100] 504. If the power supply output and bandwidth rate of the interface module are normal, and the reset signal does not reset, then the hot-swap insertion function of the backplane under test is determined to be normal.

[0101] For example, such as Figure 6 As shown, the test process may include the following steps: 601. Assemble the backplane under test (e.g., an EDSFF backplane) onto the test host. 602. Connect the backplane test device to the backplane under test, replacing the actual EDSFF hard drive. Connect the device to its USB serial port using a serial cable and provide external power to the backplane test device from the test host. 603. Perform standard backplane tests for the interface module 201, such as FRU information check, device identification, bandwidth rate check, LED check, sensor check, PCIE link anomaly detection, system anomaly log check, etc. 604. For EDSFF backplanes that do not support hot-swapping, determine whether the test is successful based on the check results obtained in step 603. If the test is successful, the process ends; if the test fails, the test is repeated. 605. For backplanes that support hot-swapping, send a pull-out / insertion simulation command from the test host to the controller (e.g., FPGA) in this device via USB serial port. Based on the response processing result of the backplane under test after the command is sent, check whether the hot-swapping simulation is successful to determine whether the hot-swapping function of the backplane is normal. If the test results of steps 603 and 605 are both successful, the process ends; otherwise, the test is repeated.

[0102] It should be noted that in this embodiment, steps 501 and 502 are the first test for the pull-out function, and steps 503 and 504 are the second test for the insertion function. In this embodiment, the order of the first and second tests can be adjusted, and both tests can be performed, or one can be selected. This embodiment does not limit this.

[0103] The backplane testing method provided in this application achieves automated testing of the hot-swapping function of the backplane under test through precise level signal control. By outputting a low-level signal to simulate the insertion and removal of a hard drive, the system can effectively trigger the backplane's reset and power-on process. For the removal operation, the power supply output and presence signal are detected to ensure normal function; for the insertion operation, the power supply, bandwidth rate, and reset signal are verified to ensure the system returns to normal operating status. This improves the accuracy and efficiency of testing, reduces the need for human intervention, and ensures the reliability and stability of the backplane in practical applications.

[0104] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be realized by means of software on a necessary general hardware platform, and of course can also be realized by hardware, but in many cases the former is a better embodiment.

[0105] Figure 7 A structural schematic diagram of the backboard test equipment provided by the embodiments of the present application is shown in FIG. 1. As shown in the figure, the embodiments of the present application also provide a backboard test equipment, which comprises an output module 701 and a determination module 702. Figure 7

[0106] The output module 701 is configured to output a first level signal to a reset pin of the backboard under test to trigger disconnection in response to receiving a simulated pull-out instruction.

[0107] In the embodiment, the first level signal can be a low level signal (for example, 0-0.3V), which represents that the hard disk is pulled out and needs to be reset.

[0108] The determination module 702 is configured to determine that the pull-out function of the hot plug of the backboard under test is normal if the power supply output of the interface module 201 is 0 and the in-place detection signal indicates that it is not in place.

[0109] The output module 701 is also configured to output a second level signal to the in-place detection pin of the backboard under test to trigger power-on of the backboard under test in response to receiving a simulated insertion instruction.

[0110] In the embodiment, the second level signal can be a low level signal (for example, 0-0.3V), which represents that the hard disk is inserted and the backboard needs to be powered on.

[0111] The determination module 702 is also configured to determine that the insertion function of the hot plug of the backboard under test is normal if the power supply output of the interface module 201 is normal, the bandwidth rate is normal, and the reset signal indicates that it is not reset.

[0112] The backboard test equipment provided by the embodiments of the present application realizes the automatic test of the hot plug function of the backboard under test through accurate level signal control. By outputting a low level signal to simulate the insertion and pull-out state of the hard disk, the system can effectively trigger the reset and power-on process of the backboard. For the pull-out operation, the power supply output and in-place signal are detected to ensure that the function is normal; for the insertion operation, the power supply, bandwidth rate and reset signal are verified to ensure that the system returns to the normal working state. The accuracy and efficiency of the test are improved, the need for human intervention is reduced, and the reliability and stability of the backboard in actual application are ensured.

[0113] The description of the features in the embodiments of the backboard test equipment can be referred to the related description of the embodiments of the backboard test method, which will not be repeated here.

[0114] ​Figure 8 A structural schematic diagram of an electronic device is provided in the embodiments of the present application. As shown in the figure, the electronic device 80 provided in the embodiments includes at least one processor 801 and a memory 802. Optionally, the electronic device 80 further includes a communication component 803. The processor 801, the memory 802 and the communication component 803 are connected through a bus. Figure 5

[0115] In the implementation process, the at least one processor 801 executes the computer-executed instructions stored in the memory 802, so that the at least one processor 801 executes the backboard test method embodiments described above.

[0116] The specific implementation process of the processor 801 can refer to the method embodiments described above, which has similar implementation principles and technical effects, and will not be described here in detail.

[0117] In the above embodiments, it should be understood that the processor can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC) and the like. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor and the like. The steps of the method disclosed in the application can be directly embodied as hardware processor execution, or executed by a combination of hardware and software modules in the processor.

[0118] The memory can include a random access memory (RAM), and can also include a non-volatile memory (NVM), for example, at least one disk memory.

[0119] The bus can be an industry standard architecture (ISA) bus, a peripheral component (PCI) bus or an extended industry standard architecture (EISA) bus and the like. The bus can be divided into an address bus, a data bus, a control bus and the like. For the convenience of representation, the bus in the drawings of the present application does not limit to only one bus or one type of bus.

[0120] ​The embodiment of the present application further provides a computer readable storage medium, which stores a computer program, and the computer program is configured to execute the steps in any of the above backplane test method embodiments when running. In the embodiment, the communication protocol and hot plug behavior of a real hard disk are simulated, so that the test cost is significantly reduced and the test efficiency is improved. The device supports multiple hard disk communication protocols by using the interface module 201 and the controller, and adapts to different types of backplane test requirements. Through automatic testing, manual operation is reduced, the test speed is accelerated, and the signal integrity and power supply stability are ensured. The simulation of the hot plug operation reduces physical wear and tear and prolongs the service life of the equipment. In addition, the device supports pre-research of new technologies and helps enterprises to keep leading in technology.

[0121] In an example embodiment, the computer readable storage medium can include, but is not limited to, a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.

[0122] The embodiment of the present application further provides a computer program product, which includes a computer program, and the computer program is executed by a processor to implement the steps in any of the above backplane test method embodiments. In the embodiment, the communication protocol and hot plug behavior of a real hard disk are simulated, so that the test cost is significantly reduced and the test efficiency is improved. The device supports multiple hard disk communication protocols by using the interface module 201 and the controller, and adapts to different types of backplane test requirements. Through automatic testing, manual operation is reduced, the test speed is accelerated, and the signal integrity and power supply stability are ensured. The simulation of the hot plug operation reduces physical wear and tear and prolongs the service life of the equipment. In addition, the device supports pre-research of new technologies and helps enterprises to keep leading in technology.

[0123] The embodiment of the present application further provides another computer program product, which includes a non-volatile computer readable storage medium storing a computer program, and the computer program is executed by a processor to implement the steps in any of the above backplane test method embodiments. In the embodiment, the communication protocol and hot plug behavior of a real hard disk are simulated, so that the test cost is significantly reduced and the test efficiency is improved. The device supports multiple hard disk communication protocols by using the interface module 201 and the controller, and adapts to different types of backplane test requirements. Through automatic testing, manual operation is reduced, the test speed is accelerated, and the signal integrity and power supply stability are ensured. The simulation of the hot plug operation reduces physical wear and tear and prolongs the service life of the equipment. In addition, the device supports pre-research of new technologies and helps enterprises to keep leading in technology.

[0124] Those skilled in the art will further appreciate that the units and algorithms described in connection with the examples disclosed herein can be implemented in electronic hardware, computer software, or both. As described above, the disclosure is directed to each individual feature, algorithm, etc. described herein. In addition, any combination of two or more such features, algorithms, etc. can be made and still be within the scope of the disclosure. Unless otherwise stated, the order and arrangement of various example steps presented herein are illustrative and not limiting in their scope. Other procedures can be used without departing from the scope of the examples as set forth herein. Also, the various steps need not be implemented in the order presented.

[0125] The backplane test method provided by the present application is described in detail above. The principles and implementation modes of the present application are described herein by applying specific examples, and the above description of the examples is only used to help understand the method of the present application and its core idea. It should be pointed out that, for those skilled in the art, some improvements and modifications can be made to the present application without departing from the principles of the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A backplane test apparatus, characterized by, The backboard testing device is used for replacing a real hard disk to be connected with a to-be-tested backboard, and the backboard testing device comprises an interface module supporting a preset hard disk communication protocol, a power supply module, a controller and a connector; the connector is a single connector; The interface module and the controller are both used for being connected with the to-be-tested backboard through the connector; The interface module is used for communicating with the to-be-tested backboard based on the preset hard disk communication protocol, so as to realize function testing of the to-be-tested backboard; The power supply module is connected with the controller and is used for supplying power for the controller in the case that the to-be-tested backboard is disconnected; The controller is used for outputting a first level signal to a reset pin of the to-be-tested backboard to trigger disconnection under the continuous power supply of the power supply module and in response to receiving an analog pull-out instruction issued by a test host; If the power supply output of the interface module is 0 and the in-place detection signal indicates that it is not in place, it is determined that the pull-out function of the hot plug of the to-be-tested backboard is normal; and / or, In response to receiving an analog insertion instruction issued by the test host, a second level signal is output to the in-place detection pin of the to-be-tested backboard to trigger power-on of the to-be-tested backboard; If the power supply output of the interface module is normal, the reset signal indicates that it is not reset, and the operating system of the test host detects that the bandwidth rate is normal and there is no abnormal warning in the system log, it is determined that the insertion function of the hot plug of the to-be-tested backboard is normal.

2. The backplane test apparatus of claim 1, wherein, Further comprising a clock generator and a voltage converter; The voltage converter is connected with the to-be-tested backboard and the clock generator and is used for converting the first power supply voltage output by the to-be-tested backboard to provide a second power supply voltage for the clock generator; The clock generator is connected with the interface module and is used for sending a clock signal to the interface module under the power supply of the second power supply voltage.

3. The backplane test apparatus of claim 1, wherein, Further comprising: A first indicator light and / or a second indicator light; The first indicator light is connected with the interface module and is used for indicating the bandwidth state of the interface module; and / or, The second indicator light is connected with the interface module and is used for indicating the power supply state of the interface module.

4. The backplane test apparatus of claim 1, wherein, Further comprising a temperature sensor; The temperature sensor is connected with the interface module and is used for acquiring temperature information of the interface module and sending the temperature information to the interface module; The interface module is used for sending the temperature information to the to-be-tested backboard based on a sideband signal.

5. The backplane test apparatus of any of claims 1-4, wherein, The power supply module comprises a voltage conversion unit; The voltage conversion unit and the controller are used for being connected with a test host; the controller is connected with the voltage conversion unit and the to-be-tested backboard; The voltage conversion unit is used for receiving a third power supply voltage provided by the test host, converting the third power supply voltage and providing a fourth power supply voltage for the controller.

6. A backplane test system, comprising: Comprising: A test host and a backboard testing device according to any one of claims 1-5; The backboard testing device is used for replacing a real hard disk to be connected with a to-be-tested backboard, and the backboard testing device comprises an interface module supporting a preset hard disk communication protocol, a power supply module, a controller and a connector; the connector is a single connector; The test host is connected with the to-be-tested backboard; the interface module and the controller are both used for connecting with the to-be-tested backboard through the connector; The test host is used for sending a test instruction to the to-be-tested backboard, so that the to-be-tested backboard communicates with the interface module based on the test instruction; The interface module is used for communicating with the to-be-tested backboard based on the preset hard disk communication protocol, so as to realize the function test of the to-be-tested backboard; The power supply module is connected with the controller, and is used for supplying power for the controller in the case of disconnection with the to-be-tested backboard; The controller is used for outputting a first level signal to a reset pin of the to-be-tested backboard to trigger disconnection under the continuous power supply of the power supply module and in response to receiving a simulated pull-out instruction issued by the test host; If the power supply output of the interface module is 0, and the in-place detection signal indicates that it is not in place, it is determined that the pull-out function of the hot plug of the to-be-tested backboard is normal. And / or, In response to receiving a simulated insertion instruction issued by the test host, a second level signal is output to the in-place detection pin of the to-be-tested backboard to trigger power-on of the to-be-tested backboard; If the power supply output of the interface module is normal, the reset signal indicates that it is not reset, and the operating system of the test host detects that the bandwidth rate is normal and the system log has no abnormal warning, it is determined that the insertion function of the hot plug of the to-be-tested backboard is normal.

7. A backplane testing method, characterized by, The backboard testing device of any one of claims 1-6; The backboard testing device is used for replacing a real hard disk to be connected with the to-be-tested backboard, and the backboard testing device comprises an interface module supporting a preset hard disk communication protocol, a power supply module, a controller and a connector, the interface module and the controller are both used for connecting with the to-be-tested backboard through the connector; the power supply module is connected with the controller; The method comprises: In response to receiving a simulated pull-out instruction, a first level signal is output to a reset pin of the to-be-tested backboard to trigger disconnection under the continuous power supply of the power supply module; If the power supply output of the interface module is 0, and the in-place detection signal indicates that it is not in place, it is determined that the pull-out function of the hot plug of the to-be-tested backboard is normal. And / or, In response to receiving a simulated insertion instruction, a second level signal is output to an in-place detection pin of the to-be-tested backboard to trigger power-on of the to-be-tested backboard under the continuous power supply of the power supply module; If the power supply output of the interface module is normal, the bandwidth rate is normal, and the reset signal indicates that it is not reset, it is determined that the insertion function of the hot plug of the to-be-tested backboard is normal.

8. An electronic device, comprising: Comprise: A memory is used for storing a computer program; A processor is used for executing the computer program to realize the steps of the backboard testing method of claim 7.

9. A computer-readable storage medium, characterized in that, The computer program is stored in the computer readable storage medium, and when the computer program is executed by the processor, the steps of the backboard testing method of claim 7 are realized.

10. A computer program product comprising a computer program, characterized in that, The computer program is executed by the processor to realize the steps of the backboard testing method of claim 7.

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