Isolation unit detection method, electronic device, and medium

Abstract

The present invention relates to the field of chip technology, and in particular to a method for detecting an isolation unit, an electronic device, and a medium. The method comprises steps S1, obtaining an isolation unit {A1, A2, ..., A n ,...,A N}; Step S2, get each A n Corresponding information to be tested (B1 n ,B2 n ,B3 n ,B4 n ); Step S3, based on B1 n ,B2 n ,B3 n ,B4 n Generate the isolation checker C corresponding to the nth isolation unit n , and C n Bound to A n ; Step S4, if E n Power on, D n Power on or D n Power off, based on C n For B1 n ,B2 n ,B3 n ,B4 n The present invention improves the accuracy of isolation unit detection.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to an isolation unit detection method, electronic equipment, and a medium. Background Art

[0002] Low-power chip designs include a shutdown domain and an always-on domain. The shutdown domain is a power domain that can be powered off (such as when entering sleep mode), while the always-on domain is a power domain that is always powered on (such as for critical system logic). To prevent floating signals in the shutdown domain from interfering with the always-on domain when powered off, an isolation unit is required between the shutdown and always-on domains. This isolation unit controls data transmission between the two domains. Existing hardware simulation verification tools only check the clamping and isolation logic of the isolation unit. This is not comprehensive and cannot adapt to different scenarios, such as fixed power-on or random power-on and power-off of the shutdown domain. Therefore, the accuracy of isolation unit detection cannot be guaranteed. Therefore, improving the accuracy of isolation unit detection has become a technical problem that needs to be solved urgently. Summary of the Invention

[0003] The present invention aims to provide an isolation unit detection method, electronic equipment and medium, thereby improving the accuracy of isolation unit detection.

[0004] According to a first aspect of the present invention, there is provided a method for detecting an isolation unit, comprising:

[0005] Step S1: Obtain the isolation unit {A1, A2, ..., A n ,...,A N}, A n is the nth isolation unit, the value range of n is 1 to N, N is the total number of isolation units in the chip, A n The input power domain is D n , D n A n The corresponding shutdown domain module, A n The output power domain is E n , E n A n Corresponding normally open domain module;

[0006] Step S2: Get each A n Corresponding information to be tested (B1 n ,B2 n ,B3 n ,B4 n ), B1 n A n Corresponding isolation enable signal name, B2 nB1 n The corresponding isolation enable effective value, B3 n A n Corresponding output signal name, B4 n A n The corresponding clamp value;

[0007] Step S3: Based on B1 n ,B2 n ,B3 n ,B4 n Generate the isolation checker C corresponding to the nth isolation unit n , and C n Bound to A n ;

[0008] Step S4: If E n Power on, D n Power on or D n Power off, based on C n For B1 n ,B2 n ,B3 n ,B4 n Conduct testing.

[0009] According to a second aspect of the present invention, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executed by the at least one processor, the instructions being configured to execute the method described in the first aspect of the present invention.

[0010] According to a third aspect of the present invention, a computer-readable storage medium is provided, storing computer-executable instructions, wherein the computer instructions are used to execute the method according to the first aspect of the present invention.

[0011] The present invention has significant advantages and beneficial effects compared to the prior art. By utilizing the above technical solution, the isolation unit detection method, electronic device, and medium provided by the present invention can achieve considerable technological advancement and practicality, and have wide industrial application value, with at least the following beneficial effects:

[0012] The present invention obtains the information to be tested corresponding to each isolation unit, and sets an isolation checker for each isolation unit based on the information to be tested corresponding to each isolation unit. When the shutdown domain module corresponding to the isolation unit is powered on or off, the isolation unit is tested based on the isolation checker. This method is applicable to scenarios such as fixed power-on or random power-on and power-off of the shutdown domain, thereby improving the accuracy of isolation unit detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0014] Figure 1 A schematic diagram of an isolation unit detection method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0015] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0016] The embodiment of the present invention provides an isolation unit detection method, such as Figure 1 As shown, including:

[0017] Step S1: Obtain the isolation unit {A1, A2, ..., A n ,...,A N}, A n is the nth isolation unit, the value range of n is 1 to N, N is the total number of isolation units in the chip, A n The input power domain is D n , D n A n The corresponding shutdown domain module, A n The output power domain is E n , E n A n Corresponding normally open domain module.

[0018] The shutdown domain is a power domain that can be powered off (for example, when entering sleep mode). Output signals may become floating due to power outages. The always-on domain is a power domain that is always powered (for example, critical system logic) and requires stable inputs to avoid interference from floating signals.

[0019] Step S2: Get each A n Corresponding information to be tested (B1 n ,B2 n ,B3 n ,B4 n ), B1 n A nCorresponding isolation enable signal name, B2 n B1 n The corresponding isolation enable effective value, B3 n A n Corresponding output signal name, B4 n A n The corresponding clamp value;

[0020] Step S3: Based on B1 n ,B2 n ,B3 n ,B4 n Generate the isolation checker C corresponding to the nth isolation unit n , and C n Bound to A n .

[0021] Step S4: If E n Power on, D n Power on or D n Power off, based on C n For B1 n ,B2 n ,B3 n ,B4 n Conduct testing.

[0022] It should be noted that the existing hardware simulation verification tools can only check the clamping and isolation logic of the isolation unit, and during the simulation process, D n There may be multiple power-on and power-off situations, such as fixed power-on, random power-on and power-off, etc. The prior art does not have a check applicable to the above multiple scenarios. In the embodiment of the present invention, by obtaining each A n Corresponding information to be tested (B1 n ,B2 n ,B3 n ,B4 n ), based on obtaining each A n Corresponding information to be tested (B1 n ,B2 n ,B3 n ,B4 n ) Establish the corresponding isolation checker C n , in D n Accurate and comprehensive inspection can be performed during each power-on and power-off process.

[0023] As an embodiment, step S2 includes:

[0024] Step S21 : Obtain a chip design register transfer level (RTL) code file and a unified power format (UPF) file corresponding to the chip. The unified power format file is used to define chip power management policy information.

[0025] Among them, the chip design register transfer level code file is a key abstract level in the chip design process, which is used to describe the interconnection relationship between the chip components and the chip components. Specifically, it can be the data flow and logical operation between registers in the digital circuit. Based on the chip design register transfer level code file, the correspondence between the interfaces can be directly determined. The chip power management strategy information defined by the unified power consumption format file includes power domain, power consumption mode, isolation logic, retention logic and other information. The unified power consumption format file records each A n Corresponding B1 n 、B2 n and B4 n .

[0026] Step S22: parse the unified power consumption format file to obtain each A n Corresponding B1 n 、B2 n and B4 n .

[0027] Step S23: parse the chip design RTL code file to obtain each B1 n Corresponding B3 n , generate each A n Corresponding information to be tested (B1 n ,B2 n ,B3 n ,B4 n ).

[0028] As an embodiment, step S3 includes:

[0029] Step S31: When E n After power on, C n Monitor and obtain B1 n The initial effective value of B1 n The initial effective value is equal to B2 n , then execute step S32, otherwise execute step S33.

[0030] It should be noted that fixed power-on means that the power supply is supplied to the module in a strictly predetermined sequence, voltage ramp rate, and delay time, so that the circuit enters a stable working state during the startup phase. Fixed power-on of the chip corresponds to the chip initialization phase. When the chip is fixedly powered on, A n Need to be in isolation mode, when B1n Equal to B2 n When A n In isolation mode, during fixed power-on, E n Power on, therefore, when E n After power on, you need to check B1 first n Is it equal to B2? n .

[0031] Step S32, C n Check B3 n Is the value of equal to X? If so, execute step S33. Otherwise, determine A n No abnormalities.

[0032] It should be noted that in E n Before power on, B3 n The value of is X (indeterminate state), E n After power on A n Need to be isolated, B3 n Set the value to B4 n , so if E n Fixed B3 after power on n The value of is X, then A n There is an exception in the isolation.

[0033] Step S33: Determine A n Isolate the exception and generate A n Isolate abnormal prompts.

[0034] It should be noted that E n After power on, A n In isolation mode, but may encounter D n In the case of power-on, as an embodiment, step S3 includes:

[0035] Step C31, D n After power on, C n Check B1 n Whether the value of is flipped, if so, execute step C32, otherwise execute step C33.

[0036] Among them, when D n In the power-on state, B1 n The moment of value reversal, A n It is necessary to switch from the isolation state to the through state. n Power on can be D n Random power on, if B2 n is equal to 0, then B1 n When the value of B1 becomes 1, n The value of B2 is reversed. n is equal to 1, then B1n When the value of B1 becomes 0, n The value of is flipped.

[0037] Step C32: Get B1 n B3 in the tth preset window corresponding to the moment of value flipping n The value of G1 tn , and B1 n B3 in the tth preset window corresponding to the moment of value reversal n The value of G2 tn , if G1 tn =G2 tn =B4 n , then determine A n No exception, otherwise, execute step C33, the tth preset window is equal to an integer multiple of the chip clock cycle, different tth preset windows have different sizes, and the value range of t is 1 to T, T≥1.

[0038] It should be noted that A n After switching to the through state, B3 n The value should still be B4 n , after stabilization, D n The output value is based on D n This time period is usually greater than 5 chip clock cycles. After this time period, D n The output value is based on D n The operation status of B3 n The value is based on D n Set the tth preset window to detect D n B3 in the tth preset window before and after power-on n The value of B1 can prevent n The glitch error during the transition affects A n 's test results.

[0039] Step C33: Determine A n Through exception, generate A n Direct abnormal prompt.

[0040] It should be noted that if there is B3 n is the data signal, and B3 n If there is no reset signal, A n After switching to direct mode, B3 n If the value of is X, then steps C31 to C33 will cause misjudgment. Therefore, if there is B3 in the chip design n is the data signal, and B3 nIf there is no reset signal, the following embodiment is used to detect A n To improve the accuracy of the detection result, as an embodiment, step S3 includes:

[0041] Step E31, D n After power on, C n Check B1 n Is the value of flipped? If so, execute step E32; otherwise, execute step E34.

[0042] Among them, when D n In the power-on state, B1 n The moment of value reversal, A n It is necessary to switch from the isolation state to the through state. n Power on can be D n Random power on, if B2 n is equal to 0, then B1 n When the value of B1 becomes 1, n The value of B2 is reversed. n is equal to 1, then B1 n When the value of B1 becomes 0, n The value of is flipped.

[0043] Step E32: Get B1 n B3 in the tth preset window corresponding to the moment of value reversal n The value of G1 tn , and B1 n B3 in the tth preset window corresponding to the moment of value reversal n The value of G2 tn , if G1 tn =G2 tn =B4 n , then determine A n No abnormality, if G1 tn =B4 n , G2 tn =X, then execute step E33, otherwise, execute step E35, the tth preset window is equal to an integer multiple of the chip clock period, different tth preset windows have different sizes, and the value range of t is 1 to T, T≥1.

[0044] Among them, if G1 tn =B4 n , G2 tn =X, then we need to further determine whether B3 n is the data signal, and B3 n This is the case where there is no reset signal.

[0045] Step E33, judgment B3 nIs it a data signal? If B3 n If it is a data signal, execute step E34; otherwise, execute step E35.

[0046] Step E34, judgment B3 n Is there no reset signal? If so, determine A n No exception, otherwise, go to step E35.

[0047] It should be noted that if B3 n is a data signal and B3 n If there is no reset signal, B1 n During a period of time after the value flips, A n In straight-through state, B3 n The value of is X. This time period is usually greater than 5 chip clock cycles. After this time period, D n The output value is based on D n The operation status of B3 n The value is based on D n to determine the operation status.

[0048] Step E35: Determine A n Through exception, generate A n Direct abnormal prompt.

[0049] As a preferred embodiment, the value of T is 2, and the size of the first preset window is larger than the size of the second preset window. The first preset window is equal to 5 times the chip clock cycle, and the second preset window is equal to 1 times the chip clock cycle. It should be noted that in some application scenarios, anomalies are easier to detect within the first preset window size, and in some application scenarios, anomalies are easier to detect within the second preset window. By setting different preset windows, missed detection can be effectively avoided and detection accuracy can be improved. However, it is understandable that if the specific application scenario is more likely to detect anomalies within the first preset window size, then only one first preset window can be set for detection. If the specific application scenario is more likely to detect anomalies within the second preset window size, then only one second preset window can be set for detection. It can be flexibly set according to specific application requirements.

[0050] As an embodiment, step S3 includes:

[0051] Step F31: When D n When power is off, C n Check B1 n Is it equal to B2? n If so, execute step F32, otherwise execute step F33.

[0052] Among them, D nIt can be a random power off. n When power is off, A n It is necessary to switch from the through state to the isolated state immediately and n Set the value to B4 n , to achieve clamping.

[0053] Step F32: Get D n Power-off time B3 n Is the value equal to B4? n If so, then determine A n No exception, otherwise, go to step F33.

[0054] Step F33: Determine A n The lower power isolation is abnormal, generating A n Power isolation abnormality prompt.

[0055] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the steps as sequential processes, many of the steps can be performed in parallel, concurrently, or simultaneously. In addition, the order of the steps can be rearranged. A process can be terminated when its operation is completed, but can also have additional steps not included in the accompanying drawings. A process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0056] An embodiment of the present invention also provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executed by the at least one processor, and the instructions are configured to execute the method described in the embodiment of the present invention.

[0057] An embodiment of the present invention further provides a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the embodiment of the present invention.

[0058] The embodiment of the present invention obtains the information to be tested corresponding to each isolation unit, and sets an isolation checker for each isolation unit based on the information to be tested corresponding to each isolation unit. When the shutdown domain module corresponding to the isolation unit is powered on or off, the isolation unit is tested based on the isolation checker. This can be applied to scenarios such as fixed power-on or random power-on and power-off of the shutdown domain, thereby improving the accuracy of isolation unit detection.

[0059] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Any technician familiar with the present profession can make slight changes or modifications to equivalent embodiments using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A method for detecting an isolation unit, characterized in that: include: Step S1: Obtain the isolation unit {A1, A2, ..., A n ,...,A N }, A n is the nth isolation unit, the value range of n is 1 to N, N is the total number of isolation units in the chip, A n The input power domain is D n , D n A n The corresponding shutdown domain module, A n The output power domain is E n , E n A n Corresponding normally open domain module; Step S2: Get each A n Corresponding test information B1 n ,B2 n ,B3 n ,B4 n , B1 n A n Corresponding isolation enable signal name, B2 n B1 n The corresponding isolation enable effective value, B3 n A n Corresponding output signal name, B4 n A n The corresponding clamp value; Step S3: Based on B1 n ,B2 n ,B3 n ,B4 n Generate the isolation checker C corresponding to the nth isolation unit n , and C n Bound to A n ; Step S31: When E n After power on, C n Monitor and obtain B1 n The initial effective value of B1 n The initial effective value is equal to B2 n , then execute step S32, otherwise execute step S33; Step S32, C n Check B3 n Is the value of equal to X? If so, execute step S33. Otherwise, determine A n No abnormalities; Step S33: Determine A n Isolate the exception and generate A n Isolation abnormality prompt; Step S4: If E n Power on, D n Power on or D n Power off, based on C n For B1 n ,B2 n ,B3 n ,B4 n Conduct testing.

2. The method according to claim 1, characterized in that The step S2 comprises: Step S21: Obtain a chip design RTL code file and a unified power consumption format file corresponding to the chip, wherein the unified power consumption format file is used to define chip power management policy information; Step S22: parse the unified power consumption format file to obtain each A n Corresponding B1 n 、B2 n and B4 n ; Step S23: parse the chip design RTL code file to obtain each B1 n Corresponding B3 n , generate each A n Corresponding test information B1 n ,B2 n ,B3 n ,B4 n .

3. The method according to claim 1, characterized in that The step S3 comprises: Step C31, D n After power on, C n Check B1 n Is the value of flipped? If so, execute step C32; otherwise, execute step C33; Step C32: Get B1 n B3 in the tth preset window corresponding to the moment of value flipping n The value of G1 tn , and B1 n B3 in the tth preset window corresponding to the moment of value reversal n The value of G2 tn , if G1 tn =G2 tn =B4 n , then determine A n No exception, otherwise, execute step C33, the t-th preset window is equal to an integer multiple of the chip clock period, different t-th preset windows have different sizes, and the value range of t is 1 to T, T ≥ 1; Step C33: Determine A n Through exception, generate A n Direct abnormal prompt.

4. The method according to claim 1, wherein The step S3 comprises: Step E31, D n After power on, C n Check B1 n Is the value of flipped? If so, execute step E32; otherwise, execute step E34; Step E32: Get B1 n B3 in the tth preset window corresponding to the moment of value reversal n The value of G1 tn , and B1 n B3 in the tth preset window corresponding to the moment of value reversal n The value of G2 tn , if G1 tn =G2 tn =B4 n , then determine A n No abnormality, if G1 tn =B4 n , G2 tn =X, then execute step E33; otherwise, execute step E35, the t-th preset window is equal to an integer multiple of the chip clock period, and different t-th preset windows have different sizes. The value range of t is 1 to T, and T ≥ 1; Step E33, judgment B3 n Is it a data signal? If B3 n If it is a data signal, execute step E34; otherwise, execute step E35; Step E34, judgment B3 n Is there no reset signal? If so, determine A n No exception, otherwise, go to step E35; Step E35: Determine A n Through exception, generate A n Direct abnormal prompt.

5. The method according to claim 3 or 4, characterized in that The value of T is 2, and the size of the first preset window is larger than the size of the second preset window.

6. The method according to claim 5, characterized in that The first preset window is equal to 5 times the chip clock cycle, and the second preset window is equal to 1 times the chip clock cycle.

7. The method according to claim 1, characterized in that The step S3 comprises: Step F31: When D n When power is off, C n Check B1 n Is it equal to B2? n If yes, go to step F32, otherwise go to step F33; Step F32: Get D n Power-off time B3 n Is the value equal to B4? n If so, then determine A n No exception, otherwise, go to step F33 Step F33: Determine A n The lower power isolation is abnormal, generating A n Power isolation abnormality prompt.

8. An electronic device, characterized in that: include: at least one processor; and, a memory communicatively coupled to the at least one processor; The memory stores instructions to be executed by the at least one processor, wherein the instructions are configured to execute the method according to any one of claims 1 to 7.

9. A computer-readable storage medium, characterized in that The computer-executable instructions are stored, and the computer-executable instructions are used to execute the method according to any one of the preceding claims 1 to 7.

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