A fault-tolerant inverter based on topology reconfiguration and a control method thereof

Abstract

This invention discloses a fault-tolerant inverter based on topology reconfiguration and its control method. Based on the location and type of the faulty switch, the topology is adjusted to the corresponding reconfiguration state by controlling the switching of bidirectional thyristors and relays. A two-level modulation method is used to re-divide sectors, reconstruct the basic voltage vector, and calculate the duration and sequence of action of the basic voltage vector. The duty cycle of each switch is determined, and a PWM pulse signal is generated by comparing it with a triangular carrier wave. This signal is then output to the gate of the IGBT power switch to control its on / off state, thus completing the fault-tolerant control of the topology-reconfiguration-based fault-tolerant inverter. This invention enables the inverter to recover distorted three-phase current and motor electromagnetic torque to the greatest extent possible after a fault, improving the reliability and stability of the inverter system.

Description

Technical Field

[0001] This invention belongs to the field of power generation technology, specifically relating to a fault-tolerant inverter based on topology reconfiguration and its control method. Background Technology

[0002] With the rapid development of power electronics technology, inverters, as core energy conversion devices, are widely used in new energy power generation, motor drives, uninterruptible power supplies, and other fields. However, power switching devices (such as IGBTs and MOSFETs) in inverters are prone to open-circuit or short-circuit faults under high-voltage, high-current, and high-frequency operating conditions, leading to system performance degradation or even shutdown. Especially in medium- and high-voltage applications such as wind power generation, inverter failures will directly affect grid stability and cause significant economic losses. Therefore, improving the fault tolerance of inverter systems and achieving continuous and reliable operation under fault conditions has become a research focus for both academia and industry.

[0003] Currently, fault-tolerance technologies for open-circuit faults in inverter switching transistors are mainly divided into two categories: hardware fault tolerance and software fault tolerance. Hardware fault tolerance achieves fault isolation and replacement by adding redundant components or bridge arms. For example, the literature (Li Y, Xiang P, Chen Y. A secondary reconfigurable inverter and its control strategy[J].Applied Sciences, 2020, 10(20): 7021.) proposes a topology reconfiguration fault-tolerance scheme, which, in some cases, switches the topology to make it operate as a three-phase four-switch topology. However, this type of method does not cover all fault conditions, is limited in scope, and is difficult to cope with complex operating conditions where multiple levels of faults occur, resulting in insufficient overall system reliability.

[0004] In existing technologies, the synergy between fault-tolerant topologies and control algorithms is insufficient, leading to frequent adjustments to modulation strategies during topology reconfiguration. This increases the computational burden on the system and reduces dynamic response speed. Traditional topology reconfiguration schemes often rely on complex mechanical switches or high-cost semiconductor devices, resulting in slow response speed and increased losses. Furthermore, existing control algorithms require frequent adjustments to modulation strategies during switching, increasing computational burden and reducing system dynamic performance. For example, some schemes require re-dividing vector sectors and generating new PWM signals during secondary faults, leading to control delays and output waveform distortion. Summary of the Invention

[0005] The purpose of this invention is to propose a fault-tolerant inverter based on topology reconfiguration and its control method.

[0006] The technical solution to achieve the purpose of this invention is: a fault-tolerant inverter based on topology reconfiguration, comprising a DC-side voltage structure, three-phase bridge arms (A-phase, B-phase, and C-phase), a single redundant bridge arm, a set of topology switching circuits, and a load, wherein:

[0007] (1) DC side voltage structure

[0008] The DC-side voltage structure consists of capacitors C1 and C2 connected in series, with the midpoint of the two capacitors at point n. The input DC voltage is U. dc It is applied between the positive terminal of capacitor C1 and the negative terminal of capacitor C2;

[0009] (2) Three-phase bridge arm of phase A, phase B and phase C

[0010] The three-phase bridge arms (A, B, and C) consist of IGBT power switches S1-S6 and fuses F1-F6. IGBT power switches S1, S3, and S5 are the upper switches, and IGBT power switches S2, S4, and S6 are the lower switches. Fuse F1 is connected in series with IGBT power switches S1 and S4 to form phase A. Fuse F3 is connected in series with IGBT power switches S3 and S6 to form phase B. Fuse F5 is connected in series with IGBT power switches S1, S4, and F6 to form phase C. The C-phase bridge arm is composed of power switch S5, IGBT power switch S2, and fuse F2. The collectors of IGBT power switches S1, S3, and S5 are connected to the positive terminal of capacitor C1 through fuses F1, F3, and F5, respectively. The emitters of IGBT power switches S2, S4, and S6 are connected to the negative terminal of capacitor C2 through fuses F2, F4, and F6, respectively. The upper and lower tube connection points of the A, B, and C phase bridge arms are the midpoints a, b, and c of the corresponding bridge arms, respectively. The loads of phases A, B, and C are connected to the midpoints a, b, and c of the three-phase bridge arms, respectively.

[0011] (3) One-phase redundant bridge arm

[0012] One phase redundant bridge arm is controlled by relay K S Relay K X Connected in series with IGBT power switch S7, relay K S The common terminal is connected to the collector of the IGBT power switch S7, and the relay K X The common terminal is connected to the emitter of the IGBT power switch S7, and the relay K S Contact 1 is connected to the positive terminal of capacitor C1, and relay K... X Contact 1 is connected to the negative terminal of capacitor C2, and relay K S Contact 2 and relay K X Contact 2 is connected to the bidirectional thyristor TR A TR B TR CConnect to the midpoints a, b, and c of the three-phase bridge arms of phases A, B, and C, respectively;

[0013] (4) A set of topology switching circuits

[0014] A set of topology switching circuits consists of bidirectional thyristors TR AB TR AC and a relay K M Composition, bidirectional thyristor TR AB The bidirectional thyristor TR is connected between the midpoint a of phase A bridge arm and the midpoint b of phase B bridge arm. AC Relay K is connected between the midpoint a of phase A bridge arm and the midpoint c of phase C bridge arm. M Contact 1 is connected to the midpoint a of phase A bridge arm, contact 2 is connected to the midpoint n of capacitors C1 and C2, and relay K... M The common terminal is connected to the load of phase A.

[0015] Furthermore, IGBT power switch failures are classified into primary single-transistor failures and secondary single-transistor failures based on the order of occurrence.

[0016] (1) Under normal operating conditions, relay K S Relay K remains at contact 1. X Relay K remains at contact 2. M With contact 1 maintained, the IGBT power switch S7 receives no drive signal and remains off, while the bidirectional thyristor TR... A TR B TR C TR AB TR AC All remain off, bidirectional thyristor TR A TR B TR C TR AB TR AC All connected pathways are in an open circuit state;

[0017] (2) In the event of a primary single-tube fault, determine the corresponding primary fault-tolerant topology based on the fault location, and adjust the relay K in the redundant bridge arm. S Relay K X Contact position, and the conduction of the bidirectional thyristor TR A TR B TR C To perform topology switching, the fault-tolerant inverter based on topology reconfiguration remains in three-phase six-switch mode.

[0018] When an open-circuit fault occurs in the IGBT power switch S1 of the upper arm of phase A, relay K... S Relay K remains at contact 1.X Relay K remains at contact 2. M Maintaining contact 1, bidirectional thyristor TR A On, bidirectional thyristor TR B TR C TR AB TR AC Keep it off; at this time, the upper end of the IGBT power switch S7 in the redundant bridge arm is connected to the input DC voltage U. dc The positive terminal of the IGBT power switch S7 is connected to the bidirectional thyristor TR. A Connect to the midpoint a of phase A bridge arm. At this time, the original upper bridge arm of phase A is replaced by the IGBT power switch S7 in the redundant bridge arm.

[0019] When an open-circuit fault occurs in the IGBT power switch S4 of the lower arm of phase A, relay K... S Switch to contact 2, relay K X Switch to contact 1, relay K M Maintaining contact 1, bidirectional thyristor TR A On, bidirectional thyristor TR B TR C TR AB TR AC Keep it off. At this time, the upper end of the IGBT power switch S7 in the redundant bridge arm is connected to the bidirectional thyristor TR. A Connect to the midpoint a of phase A bridge arm, and connect the lower end of the IGBT power switch S7 to the input DC voltage U. dc The negative terminal of the original A-phase lower bridge arm is replaced by the IGBT power switch S7 in the redundant bridge arm.

[0020] When the IGBT power switch S3 of the upper arm of phase B experiences an open-circuit fault, relay K... S Relay K remains at contact 1. X Relay K remains at contact 2. M Maintaining contact 1, bidirectional thyristor TR B On, bidirectional thyristor TR A TR C TR AB TR AC Keep it off; at this time, the upper end of the IGBT power switch S7 in the redundant bridge arm is connected to the input DC voltage U. dc The positive terminal of the IGBT power switch S7 is connected to the bidirectional thyristor TR. B Connect to the midpoint b of the B phase bridge arm. At this time, the original upper bridge arm of the B phase is replaced by the IGBT power switch S7 in the redundant bridge arm.

[0021] When an open-circuit fault occurs in the IGBT power switch S6 of the lower arm of phase B, relay K... S Switch to contact 2, relay K X Switch to contact 1, relay K M Maintaining contact 1, bidirectional thyristor TR B On, bidirectional thyristor TR A TR C TR AB TR AC Keep it off. At this time, the upper end of the IGBT power switch S7 in the redundant bridge arm is connected to the bidirectional thyristor TR. B Connect to the midpoint b of phase B bridge arm, and connect the lower end of IGBT power switch S7 to the input DC voltage U. dc The negative terminal of the original B-phase lower bridge arm is replaced by the IGBT power switch S7 in the redundant bridge arm.

[0022] When the IGBT power switch S5 of the upper arm of phase C experiences an open-circuit fault, relay K... S Relay K remains at contact 1. X Relay K remains at contact 2. M Maintaining contact 1, bidirectional thyristor TR C On, bidirectional thyristor TR A TR B TR AB TR AC Keep it off; at this time, the upper end of the IGBT power switch S7 in the redundant bridge arm is connected to the input DC voltage U. dc The positive terminal of the IGBT power switch S7 is connected to the bidirectional thyristor TR. C Connect to the midpoint c of the C-phase bridge arm. At this time, the original upper C-phase bridge arm is replaced by the IGBT power switch S7 in the redundant bridge arm.

[0023] When the IGBT power switch S2 of the lower arm of phase C experiences an open-circuit fault, relay K... S Switch to contact 2, relay K X Switch to contact 1, relay K M Maintaining contact 1, bidirectional thyristor TR C On, bidirectional thyristor TR A TR B TR AB TR AC Keep it off. At this time, the upper end of the IGBT power switch S7 in the redundant bridge arm is connected to the bidirectional thyristor TR. C Connected to the midpoint c of phase C bridge arm, the lower end of IGBT power switch S7 is connected to the input DC voltage U. dcThe negative terminal of the original C-phase lower bridge arm is replaced by the IGBT power switch S7 in the redundant bridge arm.

[0024] (3) After fault tolerance is implemented in the event of a primary single-transistor fault, if a secondary single-transistor fault occurs, the corresponding secondary fault-tolerant topology is determined according to the fault location, and the relay K in the redundant bridge arm is determined. S K X and bidirectional thyristor TR A TR B TR C To maintain the fault-tolerant state of the primary single-tube circuit, the relay K in the topology switching circuit is adjusted. M Contact position and control of bidirectional thyristor TR AB TR AC To perform topology switching, the fault-tolerant inverter operating mode based on topology reconfiguration is switched to three-phase four-switch derating operation;

[0025] When any IGBT power switch in phase A bridge arm experiences a secondary single-transistor fault, relay K... M Switching to contact 2, phase A of the load side passes through relay K. M Connected to the midpoint n of capacitors C1 and C2, the bidirectional thyristor TR AB TR AC Keep off. The two IGBT power switches of phase A bridge arm are turned off. At this time, the three-phase four-switch derating operation mode is controlled by phases B and C bridge arms.

[0026] When any IGBT power switch in phase B bridge arm experiences a secondary single-transistor fault, relay K... M Switching to contact 2, phase A of the load side passes through relay K. M Connected to the midpoint n of capacitors C1 and C2, the bidirectional thyristor TR AB On, bidirectional thyristor TR AC Keep off, the two IGBT power switches of phase B bridge arm are turned off. At this time, the midpoint a of phase A bridge arm is connected to the midpoint b of phase B bridge arm. The midpoint a of phase A bridge arm is the midpoint of phase B bridge arm. At this time, the three-phase four-switch derating operation mode is controlled by phases A and C bridge arms.

[0027] When any IGBT power switch in phase C bridge arm experiences a secondary single-transistor fault, relay K... M Switching to contact 2, phase A of the load side passes through relay K. M Connected to the midpoint n of capacitors C1 and C2, the bidirectional thyristor TR AC On, bidirectional thyristor TR ABWhen the phase C bridge arm is turned off, the two IGBT power switches are turned off. At this time, the midpoint a of the phase A bridge arm is connected to the midpoint c of the phase C bridge arm. The midpoint a of the phase A bridge arm is the midpoint of the phase C bridge arm. At this time, the three-phase four-switch derating operation mode is controlled by the phase A and B bridge arms.

[0028] A control method for a topology-reconfiguration-based fault-tolerant inverter, used for the fault-tolerant control of the topology-reconfiguration-based fault-tolerant inverter, includes the following steps:

[0029] (a) Determine the SVPWM control under normal operating conditions

[0030] Determine the switching state and basic voltage vector under normal operating conditions, divide the sector, determine the action time and action sequence of the basic voltage vector under normal operating conditions, and complete SVPWM control;

[0031] (ii) Determining SVPWM control under primary single-transistor fault-tolerant operation.

[0032] When a primary single-transistor fault occurs, adjust relay K in the redundant bridge arm according to the fault location of the IGBT power switch. S Relay K X Contact position, and the bidirectional thyristor TR that is connected. A TR B TR C To perform topology switching, the fault-tolerant inverter based on topology reconstruction operates in three-phase six-switch mode, that is, reconstructed to the corresponding primary fault-tolerant topology; by using the action time and action sequence of the basic voltage vector under normal operation, the effective IGBT power switching transistors used under primary single-transistor fault-tolerant operation are determined, and SVPWM control is completed.

[0033] (III) Determining SVPWM control under fault-tolerant operation of secondary single transistor

[0034] When a secondary single-tube fault occurs, relay K in the redundant bridge arm... S K X and bidirectional thyristor TR A TR B TR C Maintaining the fault-tolerant state after primary single-transistor failure, adjust relay K in the topology switching circuit according to the fault location of the IGBT power switch. M Contact position and control of bidirectional thyristor TR AB TR ACTo perform topology switching, the fault-tolerant inverter operating mode based on topology reconstruction is switched to three-phase four-switch derating operation, that is, reconstructed to the corresponding secondary fault-tolerant topology; the effective phases under secondary single-transistor fault-tolerant operation are determined, the switching states and basic voltage vectors under secondary single-transistor fault-tolerant operation are determined, sector division is performed, the action time and action sequence of the basic voltage vectors under secondary single-transistor fault-tolerant operation are determined, and SVPWM control is completed.

[0035] Furthermore, (ii) in determining the SVPWM control under fault-tolerant operation under primary single-transistor fault conditions, when a primary single-transistor fault occurs, the relay K in the redundant bridge arm is adjusted according to the fault location of the IGBT power switch. S Relay K X Contact position, and the bidirectional thyristor TR that is connected. A TR B TR C To perform topology switching, the fault-tolerant inverter based on topology reconfiguration maintains operation in three-phase six-switch mode, i.e., reconfigured to the corresponding primary fault-tolerant topology. Utilizing the duration and sequence of the basic voltage vector under normal operating conditions, the effective IGBT power switches for primary single-transistor fault-tolerant operation are determined, and SVPWM control is completed. The specific method is as follows:

[0036] (1) Adjust relay K in the redundant bridge arm according to the fault location of the IGBT power switch. S Relay K X Contact position, and the bidirectional thyristor TR that is connected. A TR B TR C To perform topology switching, the fault-tolerant inverter based on topology reconfiguration operates in three-phase six-switch mode, that is, reconfigured to the corresponding primary fault-tolerant topology;

[0037] When an open-circuit fault is diagnosed in the IGBT power switch S1 of the upper arm of phase A, the bidirectional thyristor TR... A When the control electrode signal input is high, the bidirectional thyristor TR... B TR C TR AB TR AC When the control electrode signal input is low, the bidirectional thyristor TR... A On, bidirectional thyristor TR B TR C TR AB TR AC Off, relay K S Relay K remains at contact 1. XRelay K remains at contact 2. M Maintain contact 1; so that the IGBT power switch S7 in the redundant bridge arm is reconstituted into the upper bridge arm of phase A; at this time, stop the signal input to the faulty phase IGBT power switch S1, and control the on / off of the faulty phase IGBT power switch S4 and IGBT power switch S7.

[0038] When an open-circuit fault is diagnosed in the IGBT power switch S4 of the lower arm of phase A, the bidirectional thyristor TR... A When the control electrode signal input is high, the bidirectional thyristor TR... B TR C TR AB TR AC The control electrode signal input is in a low-level state; relay K S K X When a current signal is applied, relay K... S Switch to contact 2, relay K X Switch to contact 1, relay K M Maintain contact 1; so that the IGBT power switch S7 in the redundant bridge arm is reconstituted into the lower bridge arm of phase A; at this time, stop the signal input to the faulty phase IGBT power switch S4, and control the on / off of the faulty phase IGBT power switch S1 and IGBT power switch S7.

[0039] When an open-circuit fault is diagnosed in the IGBT power switch S3 of the upper arm of phase B, the bidirectional thyristor TR... B When the control electrode signal input is high, the bidirectional thyristor TR... A TR C TR AB TR AC The control electrode signal input is at a low level; at this time, the bidirectional thyristor TR B On, bidirectional thyristor TR A TR C TR AB TR AC Off, relay K S Relay K remains at contact 1. X Relay K remains at contact 2. M Maintain contact 1; so that the IGBT power switch S7 in the redundant bridge arm is reconstituted into the upper bridge arm of phase B; at this time, stop the signal input to the faulty phase IGBT power switch S3, and control the on / off of the faulty phase IGBT power switch S6 and IGBT power switch S7.

[0040] When an open-circuit fault is diagnosed in the IGBT power switch S6 of the lower arm of phase B, the bidirectional thyristor TR... BWhen the control electrode signal input is high, the bidirectional thyristor TR... A TR C TR AB TR AC The control electrode signal input is at a low level; at this time, the bidirectional thyristor TR B On, bidirectional thyristor TR A TR C TR AB TR AC Off, relay K S K X When a current signal is applied, relay K... S Switch to contact 2, relay K X Switch to contact 1, relay K M Maintain contact 1; so that the IGBT power switch S7 in the redundant bridge arm is reconstituted into the lower bridge arm of phase B; at this time, stop the signal input to the faulty phase IGBT power switch S6, and control the on / off of the faulty phase IGBT power switch S3 and IGBT power switch S7.

[0041] When an open-circuit fault is diagnosed in the IGBT power switch S5 of the upper arm of phase C, the bidirectional thyristor TR... C When the control electrode signal input is high, the bidirectional thyristor TR... A TR B TR AB TR AC The control electrode signal input is at a low level; at this time, the bidirectional thyristor TR C On, bidirectional thyristor TR A TR B TR AB TR AC Off, relay K S Relay K remains at contact 1. X Relay K remains at contact 2. M Maintain contact 1; so that the IGBT power switch S7 in the redundant bridge arm is reconstituted into the upper bridge arm of phase C; at this time, stop the signal input to the faulty phase IGBT power switch S5, and control the on / off of the faulty phase IGBT power switch S2 and IGBT power switch S7.

[0042] When an open-circuit fault is diagnosed in the IGBT power switch S2 of the lower arm of phase C, the bidirectional thyristor TR... C When the control electrode signal input is high, the bidirectional thyristor TR... A TR B TR AB TR ACThe control electrode signal input is at a low level; at this time, the bidirectional thyristor TR C On, bidirectional thyristor TR A TR B TR AB TR AC Off, relay K S K X When a current signal is applied, relay K... S Switch to contact 2, relay K X Switch to contact 1, relay K M Maintain contact 1; so that the IGBT power switch S7 in the redundant bridge arm is reconstituted into the lower bridge arm of phase C; at this time, stop the signal input to the faulty phase IGBT power switch S2, and control the on / off of the faulty phase IGBT power switch S5 and IGBT power switch S7.

[0043] (2) By utilizing the action time and action sequence of the basic voltage vector under normal operating conditions, determine the IGBT power switching transistors that are effectively used under primary single-transistor fault-tolerant operating conditions, and complete SVPWM control;

[0044] When an open-circuit fault occurs in the IGBT power switch S1 of the upper arm of phase A, after fault tolerance, the IGBT power switches that can be effectively used in the primary single-tube fault tolerance operation state are: IGBT power switches S7, S2, S3, S4, S5, and S6.

[0045] When an open-circuit fault occurs in the IGBT power switch S4 of the lower arm of phase A, after fault tolerance, the IGBT power switches that can be effectively used in the primary single-tube fault-tolerant operation state are: IGBT power switches S1, S2, S3, S7, S5, and S6.

[0046] When an open-circuit fault occurs in the IGBT power switch S3 of the upper arm of phase B, after fault tolerance, the IGBT power switches that can be effectively used in the primary single-tube fault tolerance operation state are: IGBT power switches S1, S2, S7, S4, S5, and S6.

[0047] When an open-circuit fault occurs in the IGBT power switch S6 of the lower arm of phase B, after fault tolerance, the IGBT power switches that are effectively used in the primary single-tube fault-tolerant operation state are: IGBT power switches S1, S2, S3, S4, S5, and S7.

[0048] When an open-circuit fault occurs in the IGBT power switch S5 of the upper arm of phase C, after fault tolerance, the IGBT power switches that can be effectively used in the primary single-tube fault tolerance operation state are: IGBT power switches S1, S2, S3, S4, S7, and S6.

[0049] When an open-circuit fault occurs in the IGBT power switch S2 of the lower arm of phase C, after fault tolerance, the IGBT power switches that can be effectively used in the primary single-tube fault-tolerant operation state are: IGBT power switches S1, S7, S3, S4, S5, and S6.

[0050] Based on the action time and sequence of the basic voltage vector under normal operating conditions, the conduction time of the effectively used IGBT power switches is determined, and a PWM signal is generated and input to the gate of the effectively used IGBT power switches to control the on / off state of the effectively used IGBT power switches, thus completing the control of the fault-tolerant inverter based on topology reconfiguration under the fault-tolerant operation state of the primary single-tube fault.

[0051] Furthermore, (iii) in the SVPWM control under the fault-tolerant operation state of the secondary single transistor fault, when a secondary single transistor fault occurs, the relay K in the redundant bridge arm... S K X and bidirectional thyristor TR A TR B TR C Maintaining the fault-tolerant state after primary single-transistor failure, adjust relay K in the topology switching circuit according to the fault location of the IGBT power switch. M Contact position and control of bidirectional thyristor TR AB TR AC To perform topology switching, the fault-tolerant inverter operating mode based on topology reconstruction is switched to three-phase four-switch derating operation, i.e., reconstructed to the corresponding secondary fault-tolerant topology; the effectively used phases under secondary single-transistor fault-tolerant operation are determined, as are the switching states and basic voltage vectors under secondary single-transistor fault-tolerant operation. Sector division is performed, and the action time and sequence of the basic voltage vectors under secondary single-transistor fault-tolerant operation are determined to complete SVPWM control, wherein:

[0052] When a secondary single-tube fault occurs, relay K in the redundant bridge arm... S K X and bidirectional thyristor TR A TR B TR C Maintaining the fault-tolerant state after primary single-transistor failure, adjust relay K in the topology switching circuit according to the fault location of the IGBT power switch. M Contact position and control of bidirectional thyristor TR AB TR AC To perform topology switching, the fault-tolerant inverter operating mode based on topology reconfiguration is switched to three-phase four-switch derating operation, that is, reconfigured to the corresponding secondary fault-tolerant topology. The specific method is as follows:

[0053] When an open-circuit fault is diagnosed in the upper or lower IGBT power switch connected to the A-phase load, the bidirectional thyristor TR... AB TR AC When the control electrode signal input is low, the bidirectional thyristor TR... AB TR AC Keep off; Relay K M When a current signal is applied, relay K... M The contact switches to contact 2, allowing the load of phase A to pass through relay K. M Connect the load to the midpoint n of capacitors C1 and C2, connect the load of phase B to the midpoint b of phase B bridge arm, and connect the load of phase C to the midpoint c of phase C bridge arm.

[0054] When an open-circuit fault is diagnosed in the upper arm IGBT power switch or the lower arm IGBT power switch connected to the B-phase load, the bidirectional thyristor TR... AB When the control electrode signal input is high, TR AC When the control electrode signal input is low, the bidirectional thyristor TR... AB On, bidirectional thyristor TR AC Off; Relay K M When a current signal is applied, relay K... M The contact switches to contact 2, allowing the load of phase A to pass through relay K. M Connected to the midpoint n of capacitors C1 and C2, the B-phase load is connected through the bidirectional thyristor TR. AB Connect the load to the midpoint a of phase A bridge arm, and connect the load to the midpoint c of phase C bridge arm;

[0055] When an open-circuit fault is diagnosed in the upper arm IGBT power switch or the lower arm IGBT power switch connected to the C-phase load, TR AB When the control electrode signal input is low, TR AC When the control electrode signal input is high, the bidirectional thyristor TR... AB Turn off, bidirectional thyristor TR AC On; Relay K M When a current signal is applied, relay K... M The contact switches to contact 2, allowing the load of phase A to pass through relay K. M The load of phase B is connected to the midpoint n of capacitors C1 and C2, the load of phase B is connected to the midpoint b of phase B bridge arm, and the load of phase C is connected through the bidirectional thyristor TR. AC Connect to the midpoint a of phase A bridge arm.

[0056] Furthermore, (iii) in the SVPWM control under the fault-tolerant operation state of the secondary single transistor fault, when a secondary single transistor fault occurs, the relay K in the redundant bridge arm...S K X and bidirectional thyristor TR A TR B TR C Maintaining the fault-tolerant state after primary single-transistor failure, adjust relay K in the topology switching circuit according to the fault location of the IGBT power switch. M Contact position and control of bidirectional thyristor TR AB TR AC To perform topology switching, the fault-tolerant inverter operating mode based on topology reconstruction is switched to three-phase four-switch derating operation, i.e., reconstructed to the corresponding secondary fault-tolerant topology; the effectively used phases under secondary single-transistor fault-tolerant operation are determined, as are the switching states and basic voltage vectors under secondary single-transistor fault-tolerant operation. Sector division is performed, and the action time and sequence of the basic voltage vectors under secondary single-transistor fault-tolerant operation are determined to complete SVPWM control, wherein:

[0057] Determine the effective phases under the fault-tolerant operation state of the secondary single transistor, determine the switching state and basic voltage vector under the fault-tolerant operation state of the secondary single transistor, divide the sector, determine the action time and action sequence of the basic voltage vector under the fault-tolerant operation state of the secondary single transistor, and complete SVPWM control;

[0058] (a) Determine the effective phase to be used under fault-tolerant operation of the secondary single-tube fault, specifically by:

[0059] When a secondary single-tube fault occurs in the IGBT power switch of the upper or lower bridge arm connected to the load of phase A, after fault tolerance, the load of phase B is connected to the midpoint b of the phase B bridge arm, and the load of phase C is connected to the midpoint c of the phase C bridge arm. Under the fault-tolerant operation state of secondary single-tube fault, the effective phases are phase B and phase C bridge arms.

[0060] When a secondary single-tube fault occurs in the IGBT power switch of the upper or lower bridge arm connected to the load of phase B, after fault tolerance, the load of phase B is connected to the midpoint a of the bridge arm of phase A, and the load of phase C is connected to the midpoint c of the bridge arm of phase C. Under the fault tolerance operation state of secondary single-tube fault, the effective phases are: bridge arms of phases A and C.

[0061] When a secondary single-tube fault occurs in the IGBT power switch of the upper or lower bridge arm connected to the C-phase load, after fault tolerance, the B-phase load is connected to the midpoint b of the B-phase bridge arm, and the C-phase load is connected to the midpoint a of the A-phase bridge arm. Under the fault-tolerant operation state of the secondary single-tube fault, the effective phases are: the A and B phase bridge arms.

[0062] (b) Determine the switching state and basic voltage vector under fault-tolerant operation of the secondary single-transistor;

[0063] After switching the secondary fault-tolerant topology, the three-phase bridge arms are always connected to the loads of phases B and C, and the load of phase A is always connected to the midpoint n of the capacitor. Only the bridge arms connected to the loads of phases B and C need to be controlled, resulting in a total output of 2. 2 =4 voltage state combinations, i.e. 4 switching states, corresponding to 4 basic voltage vectors, V1(00), V2(10), V3(11), V4(01); The two numbers 0 and 1 in the parentheses of the switching function represent the switching states of the bridge arms connected to the B and C phase loads, respectively. The first number represents the switching state of the bridge arm connected to the B phase load. Switching state "0" means that the upper bridge arm IGBT power switch connected to the B phase load is off and the lower bridge arm IGBT power switch connected to the B phase load is on. Switching state "1" means that the upper bridge arm IGBT power switch connected to the B phase load is on and the lower bridge arm IGBT power switch connected to the B phase load is off. The second number represents the switching state of the bridge arm connected to the C phase load. Switching state "0" means that the upper bridge arm IGBT power switch connected to the C phase load is off and the lower bridge arm IGBT power switch connected to the C phase load is on. Switching state "1" means that the upper bridge arm IGBT power switch connected to the C phase load is on and the lower bridge arm IGBT power switch connected to the C phase load is off.

[0064] (c) Determine the sector division under the fault-tolerant operation state of the secondary single-tube fault;

[0065] Define a function:

[0066] ; ;

[0067] Determine the correspondence between the A value, B value and the actual sector number to complete the sector division; when the A value is greater than 0 and the B value is greater than 0, it corresponds to sector I; when the A value is less than 0 and the B value is greater than 0, it corresponds to sector II; when the A value is less than 0 and the B value is less than 0, it corresponds to sector III; when the A value is greater than 0 and the B value is less than 0, it corresponds to sector IV.

[0068] The basic voltage vectors correspond to the sectors as follows: the basic voltage vectors corresponding to sector I are: V1(00), V2(10), the basic voltage vectors corresponding to sector II are: V2(10), V3(11), the basic voltage vectors corresponding to sector III are: V3(11), V4(01), and the basic voltage vectors corresponding to sector IV are: V4(01), V1(00).

[0069] (d) Determine the duration and sequence of action of the basic voltage vector in the fault-tolerant operation state of the secondary single-transistor;

[0070] Define intermediate variable T x T y Tz These represent the durations of action of the two effective vectors and the total zero vector within the fundamental voltage vector of the synthesized reference vector over one period:

[0071] ; ; ;

[0072] In sector I, the two effective vectors are V1(00) and V2(10), and the zero vector is synthesized from V1(00) and V3(11). The duration of action of V1(00) is T1 = T x +T z / 2, the duration of action of V2(10) is T2=T y The duration of action of V3(11) is T3=T z / 2; The order of action is V1(00), V2(10), V3(11), V2(10), V1(00);

[0073] In sector II, the two effective vectors are V2(10) and V3(11), and the zero vector is synthesized from V1(00) and V3(11), where the duration of action of V1(00) is T1=T z / 2, the duration of action of V2(10) is T2=T x The duration of action of V3(11) is T3=T y +T z / 2; The order of action is V1(00), V2(10), V3(11), V2(10), V1(00);

[0074] In sector III, the two effective vectors are V3(11) and V4(01), and the zero vector is synthesized from V1(00) and V3(11), where the duration of action of V1(00) is T1=T z / 2, the duration of V4(01) is T2=T y The duration of action of V3(11) is T3=T x +T z / 2; The order of action is V1(00), V4(01), V3(11), V4(01), V1(00);

[0075] In sector IV, the two effective vectors are V4(01) and V1(00), and the zero vector is synthesized from V1(00) and V3(11). The duration of action of V1(00) is T1 = T y +T z / 2, the duration of V4(01) is T2=T x The duration of action of V3(11) is T3=T z / 2; The order of action is V1(00), V4(01), V3(11), V4(01), V1(00);

[0076] (e) Complete SVPWM control;

[0077] Based on the action time and sequence of the basic voltage vector under the fault-tolerant operation state of the secondary single-transistor fault, the conduction time of the IGBT power switch in the effectively used phase under the fault-tolerant operation state of the secondary single-transistor fault is determined. A PWM signal is generated and input to the gate of the IGBT power switch in the effectively used phase under the fault-tolerant operation state of the secondary single-transistor fault, controlling the on and off of the IGBT power switch in the effectively used phase under the fault-tolerant operation state of the secondary single-transistor fault, thus completing the control of the fault-tolerant inverter based on topology reconfiguration under the fault-tolerant operation state of the secondary single-transistor fault.

[0078] A control system for a fault-tolerant inverter based on topology reconfiguration is provided. The control method for the fault-tolerant inverter based on topology reconfiguration is implemented to realize the control of the fault-tolerant inverter based on topology reconfiguration. The control is divided into three modules, which respectively execute SVPWM control under normal operation, SVPWM control under primary single-tube fault-tolerant operation, and SVPWM control under secondary single-tube fault-tolerant operation.

[0079] A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the control method for a fault-tolerant inverter based on topology reconfiguration, thereby realizing the control of the fault-tolerant inverter based on topology reconfiguration.

[0080] A computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the control method for a fault-tolerant inverter based on topology reconfiguration is implemented, thereby realizing the control of the fault-tolerant inverter based on topology reconfiguration.

[0081] Compared with existing technologies, the significant advantages of this invention are: 1) The proposed fault-tolerant topology only adds thyristors and relays, resulting in lower cost and easier control; 2) The proposed fault-tolerant control algorithm has simple modulation, and the same control algorithm is used for all secondary fault cases; 3) This invention can complete fault-tolerant control for all primary and secondary single-tube open-circuit faults, allowing full-power operation for primary faults and derating operation for secondary faults; 4) The fault-tolerant topology and fault-tolerant control method proposed in this invention can be used as a separate module, making it easy to integrate into the motor system, and the system can operate continuously and stably. Attached Figure Description

[0082] Figure 1 This is a topology diagram of a fault-tolerant inverter based on topology reconfiguration.

[0083] Figure 2 This is a block diagram of the fault-tolerant control for a topology-reconfigurable fault-tolerant inverter.

[0084] Figure 3 This is a basic voltage vector diagram of a fault-tolerant inverter based on topology reconfiguration under normal operating conditions.

[0085] Figure 4 This is a basic voltage vector diagram for the fault-tolerant operation under secondary single-tube fault conditions.

[0086] Figure 5 This is a fault-tolerant topology reconstruction diagram when a primary fault occurs in the IGBT power switch S1 of the upper arm of phase A.

[0087] Figure 6 This is a fault-tolerant topology reconstruction diagram when a primary fault occurs in the IGBT power switch S4 of the lower arm of phase A.

[0088] Figure 7 This is a fault-tolerant topology reconstruction diagram for when the primary fault occurs in IGBT power switch S1 and the secondary fault occurs in IGBT power switch S4 of the lower arm of phase A.

[0089] Figure 8 This is a fault-tolerant topology reconstruction diagram for when the primary fault occurs in IGBT power switch S1 and the secondary fault occurs in IGBT power switch S6 of the lower arm of phase B.

[0090] Figure 9 The diagram shows the three-phase current waveforms after the primary fault, the open circuit fault of power switch S1 on phase A, and the fault tolerance.

[0091] Figure 10 The waveform diagram shows the electromagnetic torque after the primary fault, the open circuit fault of the power switch S1 on phase A, and the fault tolerance.

[0092] Figure 11 The diagram shows the three-phase current waveforms after a secondary fault, specifically an open-circuit fault in the power switch S3 of phase B.

[0093] Figure 12 The waveform diagram shows the electromagnetic torque after the secondary fault, the open circuit fault of the power switch S3 on phase B, and the fault tolerance. Detailed Implementation

[0094] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0095] Figure 1 This is a topology diagram of a fault-tolerant inverter based on topology reconfiguration. U dcThe input DC voltage is represented by C1 and C2, which are capacitors. S1, S2, S3, S4, S5, S6, and S7 are IGBT power switching transistors. TR A TR B TR C TR AB TR AC It is a bidirectional thyristor; K S K X K M F1, F2, F3, F4, F5, and F6 are relays; a, b, and c are fuses; a, b, and c are the midpoints of the three-phase bridge arms (A, B, and C phases), respectively. Capacitors C1 and C2 are connected in series to form the DC-side voltage structure, with the midpoint of the two capacitors at point n. The input DC voltage U... dc It is applied between the positive terminal of capacitor C1 and the negative terminal of capacitor C2. IGBT power switches S1-S6 and fuses F1-F6 form three-phase bridge arms (A, B, and C). The connection points of the upper and lower transistors of the three-phase bridge arms are the midpoints a, b, and c of the corresponding bridge arms, respectively. The loads of phases A, B, and C are connected to the midpoints a, b, and c of the three-phase bridge arms, respectively. Relay K S Relay K X It forms a redundant bridge arm in series with the IGBT power switch S7, and the relay K S The common terminal is connected to the collector of the IGBT power switch S7, and the relay K X The common terminal is connected to the emitter of the IGBT power switch S7, and the relay K S Contact 1 is connected to the positive terminal of capacitor C1, and relay K... X Contact 1 is connected to the negative terminal of capacitor C2, and relay K S Contact 2 and relay K X Contact 2 is connected to the bidirectional thyristor TR A TR B TR C Connect to the midpoints a, b, and c of the three-phase bridge arms of phases A, B, and C, respectively. Bidirectional thyristor TR AB TR AC and a relay K M This constitutes a topology switching circuit, with bidirectional thyristor TR AB The bidirectional thyristor TR is connected between the midpoint a of phase A bridge arm and the midpoint b of phase B bridge arm. AC Relay K is connected between the midpoint a of phase A bridge arm and the midpoint c of phase C bridge arm. M Contact 1 is connected to the midpoint a of phase A bridge arm, contact 2 is connected to the midpoint n of capacitors C1 and C2, and relay K... M The common terminal is connected to the load of phase A.

[0096] Figure 2This is a block diagram of fault-tolerant control for a topology-reconfigurable fault-tolerant inverter. The three-phase current i generated by the inverter... a i b i c The d-axis and q-axis currents i are obtained through the Parker transformation. d i q , respectively with the given d-axis and q-axis reference currents i d * i q * The differential input PI controller obtains the d-axis and q-axis voltage reference values ​​U. d U q The reference values ​​of the α and β axis voltages are obtained by the Parker inverse transform. ;Will The input six-switch SVPWM algorithm module generates signals to control the gate on / off state of the IGBT power switches. During fault-tolerant operation, different fault-tolerant topologies and different SVPWM fault-tolerant algorithm modules are switched according to different fault types. Different SVPWM fault-tolerant algorithm modules are input to generate signals that control the gate on / off state of the IGBT power switches, thus completing fault-tolerant control. This invention considers all fault scenarios, including primary single-transistor faults and secondary single-transistor faults.

[0097] Based on the above topology and fault-tolerant control block diagram, the present invention provides a control method for a fault-tolerant inverter based on topology reconfiguration, comprising the following steps:

[0098] (a) Determine the SVPWM control under normal operating conditions

[0099] Determine the switching states and basic voltage vector under normal operating conditions, divide the system into sectors, determine the activation time and sequence of the basic voltage vector under normal operating conditions, and complete SVPWM control:

[0100] (1) Determine the switching state and basic voltage vector under normal operating conditions;

[0101] In a three-phase bridge arm, each phase contains two switching states: 0 and 1. Under normal operating conditions, the "0" state indicates that the IGBT power switch of the upper bridge arm in a phase bridge arm is turned off and the IGBT power switch of the lower bridge arm is turned on, while the "1" state indicates that the IGBT power switch of the upper bridge arm in a phase bridge arm is turned on and the IGBT power switch of the lower bridge arm is turned off.

[0102] Define the switching function S x :

[0103]

[0104] Total output 2 3=8 voltage state combinations, i.e. 8 switching states, corresponding to 8 basic voltage vectors, V0(000), V1(100), V2(110), V3(010), V4(011), V5(001), V6(101), V7(111). The three numbers in parentheses represent the switching states of phase A, B, and C bridge arms respectively. The first number represents the switching state of phase A bridge arm, the second number represents the switching state of phase B bridge arm, and the third number represents the switching state of phase C bridge arm.

[0105] (2) Determine the sector division under normal operating conditions;

[0106] Figure 3 This is a spatial vector diagram of a three-phase, six-switch, two-level inverter.

[0107] Define a function:

[0108] ; C ;

[0109] In the formula, , The voltage components of the reference voltage vector in the α and β phase stationary coordinate systems;

[0110] Define symbolic functions:

[0111] ;

[0112] Define the sector number calculation value N:

[0113] ;

[0114] Determine the correspondence between the N value and the actual sector number to complete the sector division; when the calculated sector number N is 5, it corresponds to sector I; when the calculated sector number N is 4, it corresponds to sector II; when the calculated sector number N is 6, it corresponds to sector III; when the calculated sector number N is 2, it corresponds to sector IV; when the calculated sector number N is 3, it corresponds to sector V; when the calculated sector number N is 1, it corresponds to sector VI; Table 1 shows the correspondence between the calculated sector number N and the sectors.

[0115] Table 1. Correspondence between the calculated sector number N and the sectors

[0116]

[0117] The basic voltage vectors correspond to the following sectors: Sector I corresponds to the basic voltage vectors V0(000), V1(100), V2(110), and V7(111); Sector II corresponds to the basic voltage vectors V0(000), V2(110), V3(010), and V7(111); Sector III corresponds to the basic voltage vectors V0(000), V3(010), V4(011), and V7(111); Sector IV corresponds to the basic voltage vectors V0(000), V4(011), V5(001), and V7(111); Sector V corresponds to the basic voltage vectors V0(000), V5(001), V6(101), and V7(111); and Sector VI corresponds to the basic voltage vectors V0(000), V6(101), V1(100), and V7(111).

[0118] (3) Determine the duration and sequence of action of the basic voltage vector under normal operating conditions;

[0119] Define the intermediate variable as:

[0120] ; ; ;

[0121] In the formula, U dc For the input DC voltage, T s For the switching period, T1, T2, and T0 are defined as the durations of action of the two effective vectors and the total zero vector in the basic voltage vector of the synthesized reference vector within one period, respectively.

[0122] In sector I, the two effective vectors are V1(100) and V2(110), where the duration of action of V1(100) is T1=-Z and the duration of action of V2(110) is T2=X. The durations of action of the zero vector V0(000) and the zero vector V7(111) are both... The order of action is V0(000), V1(100), V2(110), V7(111), V2(110), V1(100), V0(000);

[0123] In sector II, the two effective vectors are V2(110) and V3(010), with the action time of V2(110) being T1=Z and the action time of V3(010) being T2=Y. The action times of the zero vector V0(000) and the zero vector V7(111) are both... The order of action is V0(000), V3(010), V2(110), V7(111), V2(110), V3(010), V0(000);

[0124] In sector III, the two effective vectors are V3(010) and V4(011), with the action time of V3(010) being T1=X and the action time of V4(011) being T2=-Y. The action times of the zero vectors V0(000) and V7(111) are also [missing information]. The order of action is V0(000), V3(010), V4(011), V7(111), V4(011), V3(010), V0(000);

[0125] In sector IV, the two effective vectors are V4(011) and V5(001), with the action time of V4(011) being T1=-X and the action time of V5(001) being T2=Z. The action times of the zero vector V0(000) and the zero vector V7(111) are both... The order of action is V0(000), V5(001), V4(011), V7(111), V4(011), V5(001), V0(000);

[0126] In sector V, the two effective vectors are V5(001) and V6(101), with the action time of V5(001) being T1=-Y and the action time of V6(101) being T2=-Z. The action times of the zero vectors V0(000) and V7(111) are both... The order of action is V0(000), V5(001), V6(101), V7(111), V6(101), V5(001), V0(000);

[0127] In sector VI, the two effective vectors are V6(101) and V1(100), with the action time of V6(101) being T1=Y and the action time of V1(100) being T2=-X. The action times of the zero vectors V0(000) and V7(111) are both... The order of action is V0(000), V1(100), V6(101), V7(111), V6(101), V1(100), V0(000);

[0128] The voltage vector V is synthesized according to the seven-segment vector synthesis principle. ref The order of action of the basic vectors in each sector is shown in Table 2.

[0129] Table 2. Order of Action of Basic Voltage Vectors under Normal Operating Conditions

[0130]

[0131] Figure 3This is a basic voltage vector diagram of a fault-tolerant inverter based on topology reconfiguration under normal operating conditions. The basic voltage vectors correspond to the following sectors: Sector I corresponds to basic voltage vectors V0(000), V1(100), V2(110), V7(111); Sector II corresponds to basic voltage vectors V0(000), V2(110), V3(010), V7(111); Sector III corresponds to basic voltage vectors V0(000), V3(010), V4(011), V7(111); Sector IV corresponds to basic voltage vectors V0(000), V4(011), V5(001), V7(111); Sector V corresponds to basic voltage vectors V0(000), V5(001), V6(101), V7(111); Sector VI corresponds to basic voltage vectors V0(000), V6(101), V1(100), V7(111).

[0132] (4) Based on the action time and action sequence of the basic voltage vector during normal operation, determine the conduction time of the IGBT power switch in the three-phase bridge arm, generate a PWM signal and input it to the gate of the IGBT power switch in the three-phase bridge arm to control the on and off of the IGBT power switch in the three-phase bridge arm, and complete the control of the fault-tolerant inverter based on topology reconfiguration under normal operation.

[0133] (ii) Determining SVPWM control under primary single-transistor fault-tolerant operation.

[0134] When a primary single-transistor fault occurs, adjust relay K in the redundant bridge arm according to the fault location of the IGBT power switch. S Relay K X Contact position, and the bidirectional thyristor TR that is connected. A TR B TR C To perform topology switching, the fault-tolerant inverter based on topology reconstruction operates in three-phase six-switch mode, that is, reconstructed to the corresponding primary fault-tolerant topology; by using the action time and action sequence of the basic voltage vector under normal operation, the effective IGBT power switching transistors used under primary single-transistor fault-tolerant operation are determined, and SVPWM control is completed.

[0135] (1) Adjust relay K in the redundant bridge arm according to the fault location of the IGBT power switch. S Relay K X Contact position, and the bidirectional thyristor TR that is connected. A TR B TR CTopology switching is performed, as detailed in Table 3. The fault-tolerant inverter based on topology reconfiguration operates in three-phase six-switch mode, i.e., reconfigured to the corresponding primary fault-tolerant topology.

[0136] Table 3. Switching Table for Bidirectional Thyristors and Relays Corresponding to Different IGBT Power Switch Faults

[0137]

[0138] When an open-circuit fault is diagnosed in the IGBT power switch S1 of the upper arm of phase A, the bidirectional thyristor TR... A When the control electrode signal input is high, the bidirectional thyristor TR... B TR C TR AB TR AC When the control electrode signal input is low, the bidirectional thyristor TR... A On, bidirectional thyristor TR B TR C TR AB TR AC Off, relay K S Relay K remains at contact 1. X Relay K remains at contact 2. M Maintain contact 1; this allows the IGBT power switch S7 in the redundant bridge arm to reconfigure as the upper bridge arm of phase A; at this time, stop the signal input to the faulty phase IGBT power switch S1, and control the on / off state of the faulty phase IGBT power switch S4 and IGBT power switch S7, such as... Figure 5 As shown;

[0139] When an open-circuit fault is diagnosed in the IGBT power switch S4 of the lower arm of phase A, the bidirectional thyristor TR... A When the control electrode signal input is high, the bidirectional thyristor TR... B TR C TR AB TR AC When the control electrode signal input is low, the bidirectional thyristor TR... A On, bidirectional thyristor TR B TR C TR AB TR AC Off, relay K S K X When a current signal is applied, relay K... S Switch to contact 2, relay K X Switch to contact 1, relay K MMaintain contact 1; this allows the IGBT power switch S7 in the redundant bridge arm to reconfigure as the lower bridge arm of phase A; at this time, stop the signal input to the faulty phase IGBT power switch S4, and control the on / off state of the faulty phase IGBT power switch S1 and IGBT power switch S7, as follows. Figure 6 As shown;

[0140] When an open-circuit fault is diagnosed in the IGBT power switch S3 of the upper arm of phase B, the bidirectional thyristor TR... B When the control electrode signal input is high, the bidirectional thyristor TR... A TR C TR AB TR AC When the control electrode signal input is low, the bidirectional thyristor TR... B On, bidirectional thyristor TR A TR C TR AB TR AC Off, relay K S Relay K remains at contact 1. X Relay K remains at contact 2. M Maintain contact 1; so that the IGBT power switch S7 in the redundant bridge arm is reconstituted into the upper bridge arm of phase B; at this time, stop the signal input to the faulty phase IGBT power switch S3, and control the on / off of the faulty phase IGBT power switch S6 and IGBT power switch S7.

[0141] When an open-circuit fault is diagnosed in the IGBT power switch S6 of the lower arm of phase B, the bidirectional thyristor TR... B When the control electrode signal input is high, the bidirectional thyristor TR... A TR C TR AB TR AC When the control electrode signal input is low, the bidirectional thyristor TR... B On, bidirectional thyristor TR A TR C TR AB TR AC Off, relay K S K X When a current signal is applied, relay K... S Switch to contact 2, relay K X Switch to contact 1, relay K MMaintain contact 1; so that the IGBT power switch S7 in the redundant bridge arm is reconstituted into the lower bridge arm of phase B; at this time, stop the signal input to the faulty phase IGBT power switch S6, and control the on / off of the faulty phase IGBT power switch S3 and IGBT power switch S7.

[0142] When an open-circuit fault is diagnosed in the IGBT power switch S5 of the upper arm of phase C, the bidirectional thyristor TR... C When the control electrode signal input is high, the bidirectional thyristor TR... A TR B TR AB TR AC When the control electrode signal input is low, the bidirectional thyristor TR... C On, bidirectional thyristor TR A TR B TR AB TR AC Off, relay K S Relay K remains at contact 1. X Relay K remains at contact 2. M Maintain contact 1; so that the IGBT power switch S7 in the redundant bridge arm is reconstituted into the upper bridge arm of phase C; at this time, stop the signal input to the faulty phase IGBT power switch S5, and control the on / off of the faulty phase IGBT power switch S2 and IGBT power switch S7.

[0143] When an open-circuit fault is diagnosed in the IGBT power switch S2 of the lower arm of phase C, the bidirectional thyristor TR... C When the control electrode signal input is high, the bidirectional thyristor TR... A TR B TR AB TR AC When the control electrode signal input is low, the bidirectional thyristor TR... C On, bidirectional thyristor TR A TR B TR AB TR AC Off, relay K S K X When a current signal is applied, relay K... S Switch to contact 2, relay K X Switch to contact 1, relay K M Maintain contact 1; so that the IGBT power switch S7 in the redundant bridge arm is reconstituted into the lower bridge arm of phase C; at this time, stop the signal input to the faulty phase IGBT power switch S2, and control the on / off of the faulty phase IGBT power switch S5 and IGBT power switch S7.

[0144] (2) By utilizing the action time and action sequence of the basic voltage vector under normal operating conditions, determine the IGBT power switching transistors that are effectively used under primary single-transistor fault-tolerant operating conditions, and complete SVPWM control;

[0145] When an open-circuit fault occurs in the IGBT power switch S1 of the upper arm of phase A, after fault tolerance, the IGBT power switches that can be effectively used in the primary single-tube fault tolerance operation state are: IGBT power switches S7, S2, S3, S4, S5, and S6.

[0146] When an open-circuit fault occurs in the IGBT power switch S4 of the lower arm of phase A, after fault tolerance, the IGBT power switches that are effectively used in the primary single-tube fault-tolerant operation state are: IGBT power switches S1, S2, S3, S7, S5, and S6.

[0147] When an open-circuit fault occurs in the IGBT power switch S3 of the upper arm of phase B, after fault tolerance, the IGBT power switches that can be effectively used in the primary single-tube fault tolerance operation state are: IGBT power switches S1, S2, S7, S4, S5, and S6.

[0148] When an open-circuit fault occurs in the IGBT power switch S6 of the lower arm of phase B, after fault tolerance, the IGBT power switches that are effectively used in the primary single-tube fault-tolerant operation state are: IGBT power switches S1, S2, S3, S4, S5, and S7.

[0149] When an open-circuit fault occurs in the IGBT power switch S5 of the upper arm of phase C, after fault tolerance, the IGBT power switches that can be effectively used in the primary single-tube fault tolerance operation state are: IGBT power switches S1, S2, S3, S4, S7, and S6.

[0150] When an open-circuit fault occurs in the IGBT power switch S2 of the lower arm of phase C, after fault tolerance, the IGBT power switches that can be effectively used in the primary single-tube fault-tolerant operation state are: IGBT power switches S1, S7, S3, S4, S5, and S6.

[0151] Based on the action time and sequence of the basic voltage vector under normal operating conditions, the conduction time of the effectively used IGBT power switches is determined, and a PWM signal is generated and input to the gate of the effectively used IGBT power switches to control the on / off state of the effectively used IGBT power switches, thus completing the control of the fault-tolerant inverter based on topology reconfiguration under the fault-tolerant operation state of the primary single-tube fault.

[0152] (III) Determining SVPWM control under fault-tolerant operation of secondary single transistor

[0153] When a secondary single-tube fault occurs, relay K in the redundant bridge arm... S K X and bidirectional thyristor TR A TR B TR C Maintaining the fault-tolerant state after primary single-transistor failure, adjust relay K in the topology switching circuit according to the fault location of the IGBT power switch. M Contact position and control of bidirectional thyristor TR AB TR AC To perform topology switching, the fault-tolerant inverter operating mode based on topology reconstruction is switched to three-phase four-switch derating operation, that is, reconstructed to the corresponding secondary fault-tolerant topology; the effective phases under secondary single-transistor fault-tolerant operation are determined, the switching states and basic voltage vectors under secondary single-transistor fault-tolerant operation are determined, sector division is performed, the action time and action sequence of the basic voltage vectors under secondary single-transistor fault-tolerant operation are determined, and SVPWM control is completed.

[0154] (1) When a secondary single-tube fault occurs, the relay K in the redundant bridge arm S K X and bidirectional thyristor TR A TR B TR C Maintaining the fault-tolerant state after primary single-transistor failure, adjust relay K in the topology switching circuit according to the fault location of the IGBT power switch. M Contact position and control of bidirectional thyristor TR AB TR AC To perform topology switching, the fault-tolerant inverter operating mode based on topology reconstruction is switched to three-phase four-switch derating operation, that is, reconstructed to the corresponding secondary fault-tolerant topology;

[0155] When an open-circuit fault is diagnosed in the upper or lower IGBT power switch connected to the A-phase load, the bidirectional thyristor TR... AB TR AC When the control electrode signal input is low, the bidirectional thyristor TR... AB TR AC Keep off; Relay K M When a current signal is applied, relay K... M The contact switches to contact 2, allowing the load of phase A to pass through relay K. M Connect the load to the midpoint n of capacitors C1 and C2, connect the B-phase load to the midpoint b of the B-phase bridge arm, and connect the C-phase load to the midpoint c of the C-phase bridge arm. Figure 7 As shown;

[0156] When an open-circuit fault is diagnosed in the upper arm IGBT power switch or the lower arm IGBT power switch connected to the B-phase load, the bidirectional thyristor TR... AB When the control electrode signal input is high, TR AC When the control electrode signal input is low, the bidirectional thyristor TR... AB On, bidirectional thyristor TR AC Off; Relay K M When a current signal is applied, relay K... M The contact switches to contact 2, allowing the load of phase A to pass through relay K. M Connected to the midpoint n of capacitors C1 and C2, the B-phase load is connected through the bidirectional thyristor TR. AB Connect the load to the midpoint a of phase A bridge arm, and connect the load to the midpoint c of phase C bridge arm, as follows: Figure 8 As shown;

[0157] When an open-circuit fault is diagnosed in the upper arm IGBT power switch or the lower arm IGBT power switch connected to the C-phase load, TR AB When the control electrode signal input is low, TR AC When the control electrode signal input is high, the bidirectional thyristor TR... AB Turn off, bidirectional thyristor TR AC On; Relay K M When a current signal is applied, relay K... M The contact switches to contact 2, allowing the load of phase A to pass through relay K. M The load of phase B is connected to the midpoint n of capacitors C1 and C2, the load of phase B is connected to the midpoint b of phase B bridge arm, and the load of phase C is connected through the bidirectional thyristor TR. AC Connect to the midpoint a of phase A bridge arm.

[0158] (2) Determine the effective phase to be used under the fault-tolerant operation state of the secondary single tube;

[0159] When a secondary single-tube fault occurs in the IGBT power switch of the upper or lower bridge arm connected to the load of phase A, after fault tolerance, the load of phase B is connected to the midpoint b of the phase B bridge arm, and the load of phase C is connected to the midpoint c of the phase C bridge arm. Under the fault-tolerant operation state of secondary single-tube fault, the effective phases are phase B and phase C bridge arms.

[0160] When a secondary single-tube fault occurs in the IGBT power switch of the upper or lower bridge arm connected to the load of phase B, after fault tolerance, the load of phase B is connected to the midpoint a of the bridge arm of phase A, and the load of phase C is connected to the midpoint c of the bridge arm of phase C. Under the fault tolerance operation state of secondary single-tube fault, the effective phases are: bridge arms of phases A and C.

[0161] When a secondary single-tube fault occurs in the IGBT power switch of the upper or lower bridge arm connected to the C-phase load, after fault tolerance, the B-phase load is connected to the midpoint b of the B-phase bridge arm, and the C-phase load is connected to the midpoint a of the A-phase bridge arm. Under the fault-tolerant operation state of the secondary single-tube fault, the effective phases are: the A and B phase bridge arms.

[0162] (3) Determine the switching state and basic voltage vector under the fault-tolerant operation state of the secondary single tube;

[0163] Figure 4 This is a spatial vector diagram of a fault-tolerant inverter based on topology reconfiguration after a secondary fault occurs. In the secondary fault-tolerant topology, after switching the secondary fault-tolerant topology, the three-phase bridge arms are always connected to the loads of phases B and C, and the load of phase A is always connected to the midpoint n of the capacitor. Only the bridge arms connected to the loads of phases B and C need to be controlled, resulting in a total output of 2. 2 =4 voltage state combinations, i.e. 4 switching states, corresponding to 4 basic voltage vectors, V1(00), V2(10), V3(11), V4(01); The two numbers 0 and 1 in the parentheses of the switching function represent the switching states of the bridge arms connected to the B and C phase loads, respectively. The first number represents the switching state of the bridge arm connected to the B phase load. Switching state "0" means that the upper bridge arm IGBT power switch connected to the B phase load is off and the lower bridge arm IGBT power switch connected to the B phase load is on. Switching state "1" means that the upper bridge arm IGBT power switch connected to the B phase load is on and the lower bridge arm IGBT power switch connected to the B phase load is off. The second number represents the switching state of the bridge arm connected to the C phase load. Switching state "0" means that the upper bridge arm IGBT power switch connected to the C phase load is off and the lower bridge arm IGBT power switch connected to the C phase load is on. Switching state "1" means that the upper bridge arm IGBT power switch connected to the C phase load is on and the lower bridge arm IGBT power switch connected to the C phase load is off.

[0164] (4) Determine the sector division under the fault-tolerant operation state of the secondary single tube;

[0165] Define a function:

[0166] ; ;

[0167] Determine the correspondence between the A1 value, B1 value and the actual sector number to complete the sector division; when the A1 value is greater than 0 and the B1 value is greater than 0, it corresponds to sector I; when the A1 value is less than 0 and the B1 value is greater than 0, it corresponds to sector II; when the A1 value is less than 0 and the B1 value is less than 0, it corresponds to sector III; when the A1 value is greater than 0 and the B1 value is less than 0, it corresponds to sector IV.

[0168] The basic voltage vectors correspond to the sectors as follows: the basic voltage vectors corresponding to sector I are: V1(00), V2(10), the basic voltage vectors corresponding to sector II are: V2(10), V3(11), the basic voltage vectors corresponding to sector III are: V3(11), V4(01), and the basic voltage vectors corresponding to sector IV are: V4(01), V1(00).

[0169] (5) Determine the action time and action sequence of the basic voltage vector under the fault-tolerant operation state of the secondary single tube, and complete the SVPWM control;

[0170] Define intermediate variable T x T y T z T represents the duration of action of the two effective vectors and the total zero vector within the applied voltage vector of the synthesized reference vector, respectively, during one cycle. s The time for one cycle:

[0171]

[0172] In sector I, the two effective vectors are V1(00) and V2(10), and the zero vector is synthesized from V1(00) and V3(11). The duration of action of V1(00) is T1 = T x +T z / 2, the duration of action of V2(10) is T2=T y The duration of action of V3(11) is T3=T z / 2; The order of action is V1(00), V2(10), V3(11), V2(10), V1(00);

[0173] In sector II, the two effective vectors are V2(10) and V3(11), and the zero vector is synthesized from V1(00) and V3(11), where the duration of action of V1(00) is T1=T z / 2, the duration of action of V2(10) is T2=T x The duration of action of V3(11) is T3=T y +T z / 2; The order of action is V1(00), V2(10), V3(11), V2(10), V1(00);

[0174] In sector III, the two effective vectors are V3(11) and V4(01), and the zero vector is synthesized from V1(00) and V3(11), where the duration of action of V1(00) is T1=T z / 2, the duration of V4(01) is T2=T y The duration of action of V3(11) is T3=Tx +T z / 2; The order of action is V1(00), V4(01), V3(11), V4(01), V1(00);

[0175] In sector IV, the two effective vectors are V4(01) and V1(00), and the zero vector is synthesized from V1(00) and V3(11). The duration of action of V1(00) is T1 = T y +T z / 2, the duration of V4(01) is T2=T x The duration of action of V3(11) is T3=T z / 2; The order of action is V1(00), V4(01), V3(11), V4(01), V1(00);

[0176] Table 4. Order of Action of Basic Voltage Vectors under Fault-Tolerant Operation of Secondary Single Transistor

[0177]

[0178] Based on the action time and sequence of the basic voltage vector under the fault-tolerant operation state of the secondary single-transistor fault, the conduction time of the IGBT power switch in the effectively used phase under the fault-tolerant operation state of the secondary single-transistor fault is determined. A PWM signal is generated and input to the gate of the IGBT power switch in the effectively used phase under the fault-tolerant operation state of the secondary single-transistor fault, controlling the on and off of the IGBT power switch in the effectively used phase under the fault-tolerant operation state of the secondary single-transistor fault, thus completing the control of the fault-tolerant inverter based on topology reconfiguration under the fault-tolerant operation state of the secondary single-transistor fault.

[0179] This invention also proposes a control system for a fault-tolerant inverter based on topology reconfiguration. The control method for the fault-tolerant inverter based on topology reconfiguration is implemented to realize the control of the fault-tolerant inverter based on topology reconfiguration. The control is divided into three modules, which respectively execute SVPWM control under normal operation, SVPWM control under primary single-tube fault-tolerant operation, and SVPWM control under secondary single-tube fault-tolerant operation.

[0180] A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the control method for a fault-tolerant inverter based on topology reconfiguration, thereby realizing the control of the fault-tolerant inverter based on topology reconfiguration.

[0181] A computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the control method for a fault-tolerant inverter based on topology reconfiguration is implemented, thereby realizing the control of the fault-tolerant inverter based on topology reconfiguration.

[0182] In summary, the fault-tolerant topology proposed in this invention only adds thyristors and relays, resulting in lower cost and simpler control. Furthermore, the proposed fault-tolerant control algorithm is simple to modulate, employing the same algorithm for all secondary fault scenarios. This invention can achieve fault-tolerant control for all primary and secondary single-transistor open-circuit faults, allowing full-power operation during primary faults and derating operation during secondary faults. Moreover, the fault-tolerant topology and control method proposed in this invention can be used as a standalone module for easy integration into motor systems, enabling continuous and stable system operation.

[0183] Example 1

[0184] To verify the effectiveness of the present invention, this embodiment mainly performs simulation analysis on the fault-tolerant processing after an open-circuit fault in the power switch S1 of phase A, which is a primary fault. The open-circuit fault occurs in switch S1 at 0.2s. After determining the fault type, fault tolerance is achieved by reconstructing the topology at 0.25s, restoring it to normal operation. For example... Figure 9 It can be seen that during the first 0 to 0.2 seconds, the system operates normally with a sinusoidal three-phase current waveform. At 0.2 seconds, an open-circuit fault occurs in the power switch S1 of phase A, causing severe distortion of the phase A current and a rapid increase in the currents of phases B and C. After switching to a fault-tolerant topology and fault-tolerant algorithm at 0.25 seconds, the phase A current recovers, and the three-phase current returns to an approximately sinusoidal state. The three-phase six-switch system continues to operate normally. Figure 10 It can be seen that the switch S1 has an open circuit fault at 0.2s. After judging the fault type, the topology is reconstructed for fault tolerance at 0.25s. The system operates normally from 0 to 0.2s, and the electromagnetic torque is stable at around 13N*m. At 0.2s, the power switch S1 on phase A has an open circuit fault. At this time, the electromagnetic torque pulsation is severe. The torque pulsation will be converted into periodic mechanical vibration, which will cause abnormal vibration of the motor body and transmission system, and will damage the power grid or the motor and other loads. After switching the fault-tolerant topology and fault-tolerant algorithm at 0.25s, the electromagnetic torque returns to the stable state during normal operation and remains near the value of the electromagnetic torque during normal operation.

[0185] Example 2

[0186] To verify the effectiveness of the present invention, this embodiment mainly performs simulation analysis on the fault-tolerant processing after an open-circuit fault in the power switch S3 of phase B in the secondary fault. The open-circuit fault occurs in switch S3 within 0.2 seconds. After determining the fault type, fault tolerance is achieved by reconstructing the topology within 0.25 seconds, restoring it to normal operation. For example... Figure 11It can be seen that during the normal operation from 0 to 0.2 seconds, the three-phase current waveform is sinusoidal. At 0.2 seconds, an open-circuit fault occurs in the power switch S3 of phase B. At this time, the phase B current disappears, and the phase A and C currents are severely distorted. After switching to a fault-tolerant topology and fault-tolerant algorithm at 0.25 seconds, the phase B current recovers around 0.35 seconds, and the three-phase current returns to an approximately sinusoidal state. Maintain derating operation of the three-phase four-switch system. Figure 12 It can be seen that the switch S1 experiences an open-circuit fault at 0.2s. After judging the fault type, the topology is reconstructed for fault tolerance at 0.25s. Normal operation is maintained from 0 to 0.2s, and the electromagnetic torque is stable at around 13N*m. At 0.2s, the power switch S3 on phase B experiences an open-circuit fault. At this time, the electromagnetic torque pulsation is severe. The torque pulsation will be converted into periodic mechanical vibration, which will cause abnormal vibration of the motor body and transmission system, and will damage the load such as the power grid or the motor. After switching the fault-tolerant topology and fault-tolerant algorithm at 0.25s, the electromagnetic torque recovers to the stable state of normal operation at 0.35s. The stable value of the electromagnetic torque remains near the value of the electromagnetic torque during normal operation.

[0187] The two embodiments above demonstrate that the method proposed in this invention can complete open-circuit fault tolerance control for all cases of single-tube open circuit in the primary and secondary stages of the system, and each of the two levels of fault tolerance control uses only one modulation method.

[0188] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0189] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A fault-tolerant inverter based on topology reconfiguration, characterized in that, Includes DC-side voltage structure, three-phase bridge arms (A, B, and C phases), one redundant bridge arm, a set of topology switching circuits, and loads, wherein: (1) DC side voltage structure The DC-side voltage structure consists of capacitors C1 and C2 connected in series, with the midpoint of the two capacitors at point n. The input DC voltage is U. dc It is applied between the positive terminal of capacitor C1 and the negative terminal of capacitor C2; (2) Three-phase bridge arm of phase A, phase B and phase C The three-phase bridge arms (A, B, and C) consist of IGBT power switches S1-S6 and fuses F1-F6. IGBT power switches S1, S3, and S5 are the upper switches, and IGBT power switches S2, S4, and S6 are the lower switches. Fuse F1 is connected in series with IGBT power switches S1 and S4 to form phase A. Fuse F3 is connected in series with IGBT power switches S3 and S6 to form phase B. Fuse F5 is connected in series with IGBT power switches S1, S4, and F6 to form phase C. The C-phase bridge arm is composed of power switch S5, IGBT power switch S2, and fuse F2. The collectors of IGBT power switches S1, S3, and S5 are connected to the positive terminal of capacitor C1 through fuses F1, F3, and F5, respectively. The emitters of IGBT power switches S2, S4, and S6 are connected to the negative terminal of capacitor C2 through fuses F2, F4, and F6, respectively. The upper and lower tube connection points of the A, B, and C phase bridge arms are the midpoints a, b, and c of the corresponding bridge arms, respectively. The loads of phases A, B, and C are connected to the midpoints a, b, and c of the three-phase bridge arms, respectively. (3) One-phase redundant bridge arm One phase redundant bridge arm is controlled by relay K S Relay K X Connected in series with IGBT power switch S7, relay K S The common terminal is connected to the collector of the IGBT power switch S7, and the relay K X The common terminal is connected to the emitter of the IGBT power switch S7, and the relay K S Contact 1 is connected to the positive terminal of capacitor C1, and relay K... X Contact 1 is connected to the negative terminal of capacitor C2, and relay K S Contact 2 and relay K X Contact 2 is connected to the bidirectional thyristor TR A TR B TR C Connect to the midpoints a, b, and c of the three-phase bridge arms of phases A, B, and C, respectively; (4) A set of topology switching circuits A set of topology switching circuits consists of bidirectional thyristors TR AB TR AC and a relay K M Composition, bidirectional thyristor TR AB The bidirectional thyristor TR is connected between the midpoint a of phase A bridge arm and the midpoint b of phase B bridge arm. AC Relay K is connected between the midpoint a of phase A bridge arm and the midpoint c of phase C bridge arm. M Contact 1 is connected to the midpoint a of phase A bridge arm, contact 2 is connected to the midpoint n of capacitors C1 and C2, and relay K... M The common terminal is connected to the load of phase A.

2. The fault-tolerant inverter based on topology reconfiguration according to claim 1, characterized in that, IGBT power switch failures are classified into primary single-transistor failures and secondary single-transistor failures based on the order of occurrence. (1) Under normal operating conditions, relay K S Relay K remains at contact 1. X Relay K remains at contact 2. M With contact 1 maintained, the IGBT power switch S7 receives no drive signal and remains off, while the bidirectional thyristor TR... A TR B TR C TR AB TR AC All remain off, bidirectional thyristor TR A TR B TR C TR AB TR AC All connected pathways are in an open circuit state; (2) In the event of a primary single-tube fault, determine the corresponding primary fault-tolerant topology based on the fault location, and adjust the relay K in the redundant bridge arm. S Relay K X Contact position, and the conduction of the bidirectional thyristor TR A TR B TR C To perform topology switching, the fault-tolerant inverter based on topology reconfiguration remains in three-phase six-switch mode. When an open-circuit fault occurs in the IGBT power switch S1 of the upper arm of phase A, relay K... S Relay K remains at contact 1. X Relay K remains at contact 2. M Maintaining contact 1, bidirectional thyristor TR A On, bidirectional thyristor TR B TR C TR AB TR AC Keep it off; at this time, the upper end of the IGBT power switch S7 in the redundant bridge arm is connected to the input DC voltage U. dc The positive terminal of the IGBT power switch S7 is connected to the bidirectional thyristor TR. A Connect to the midpoint a of phase A bridge arm. At this time, the original upper bridge arm of phase A is replaced by the IGBT power switch S7 in the redundant bridge arm. When an open-circuit fault occurs in the IGBT power switch S4 of the lower arm of phase A, relay K... S Switch to contact 2, relay K X Switch to contact 1, relay K M Maintaining contact 1, bidirectional thyristor TR A On, bidirectional thyristor TR B TR C TR AB TR AC Keep it off. At this time, the upper end of the IGBT power switch S7 in the redundant bridge arm is connected to the bidirectional thyristor TR. A Connect to the midpoint a of phase A bridge arm, and connect the lower end of the IGBT power switch S7 to the input DC voltage U. dc The negative terminal of the original A-phase lower bridge arm is replaced by the IGBT power switch S7 in the redundant bridge arm. When the IGBT power switch S3 of the upper arm of phase B experiences an open-circuit fault, relay K... S Relay K remains at contact 1. X Relay K remains at contact 2. M Maintaining contact 1, bidirectional thyristor TR B On, bidirectional thyristor TR A TR C TR AB TR AC Keep it off; at this time, the upper end of the IGBT power switch S7 in the redundant bridge arm is connected to the input DC voltage U. dc The positive terminal of the IGBT power switch S7 is connected to the bidirectional thyristor TR. B Connect to the midpoint b of the B phase bridge arm. At this time, the original upper bridge arm of the B phase is replaced by the IGBT power switch S7 in the redundant bridge arm. When an open-circuit fault occurs in the IGBT power switch S6 of the lower arm of phase B, relay K... S Switch to contact 2, relay K X Switch to contact 1, relay K M Maintaining contact 1, bidirectional thyristor TR B On, bidirectional thyristor TR A TR C TR AB TR AC Keep it off. At this time, the upper end of the IGBT power switch S7 in the redundant bridge arm is connected to the bidirectional thyristor TR. B Connect to the midpoint b of phase B bridge arm, and connect the lower end of IGBT power switch S7 to the input DC voltage U. dc The negative terminal of the original B-phase lower bridge arm is replaced by the IGBT power switch S7 in the redundant bridge arm. When the IGBT power switch S5 of the upper arm of phase C experiences an open-circuit fault, relay K... S Relay K remains at contact 1. X Relay K remains at contact 2. M Maintaining contact 1, bidirectional thyristor TR C On, bidirectional thyristor TR A TR B TR AB TR AC Keep it off; at this time, the upper end of the IGBT power switch S7 in the redundant bridge arm is connected to the input DC voltage U. dc The positive terminal of the IGBT power switch S7 is connected to the bidirectional thyristor TR. C Connect to the midpoint c of the C-phase bridge arm. At this time, the original upper C-phase bridge arm is replaced by the IGBT power switch S7 in the redundant bridge arm. When the IGBT power switch S2 of the lower arm of phase C experiences an open-circuit fault, relay K... S Switch to contact 2, relay K X Switch to contact 1, relay K M Maintaining contact 1, bidirectional thyristor TR C On, bidirectional thyristor TR A TR B TR AB TR AC Keep it off. At this time, the upper end of the IGBT power switch S7 in the redundant bridge arm is connected to the bidirectional thyristor TR. C Connected to the midpoint c of phase C bridge arm, the lower end of IGBT power switch S7 is connected to the input DC voltage U. dc The negative terminal of the original C-phase lower bridge arm is replaced by the IGBT power switch S7 in the redundant bridge arm. (3) After fault tolerance is implemented in the event of a primary single-transistor fault, if a secondary single-transistor fault occurs, the corresponding secondary fault-tolerant topology is determined according to the fault location, and the relay K in the redundant bridge arm is determined. S K X and bidirectional thyristor TR A TR B TR C To maintain the fault-tolerant state of the primary single-tube circuit, the relay K in the topology switching circuit is adjusted. M Contact position and control of bidirectional thyristor TR AB TR AC To perform topology switching, the fault-tolerant inverter operating mode based on topology reconfiguration is switched to three-phase four-switch derating operation; When any IGBT power switch in phase A bridge arm experiences a secondary single-transistor fault, relay K... M Switching to contact 2, load phase A is connected via relay K. M Connected to the midpoint n of capacitors C1 and C2, the bidirectional thyristor TR AB TR AC Keep off. The two IGBT power switches of phase A bridge arm are turned off. At this time, the three-phase four-switch derating operation mode is controlled by phases B and C bridge arms. When any IGBT power switch in phase B bridge arm experiences a secondary single-transistor fault, relay K... M Switching to contact 2, load phase A is connected via relay K. M Connected to the midpoint n of capacitors C1 and C2, the bidirectional thyristor TR AB On, bidirectional thyristor TR AC Keep off, the two IGBT power switches of phase B bridge arm are turned off. At this time, the midpoint a of phase A bridge arm is connected to the midpoint b of phase B bridge arm. The midpoint a of phase A bridge arm is the midpoint of phase B bridge arm. At this time, the three-phase four-switch derating operation mode is controlled by phases A and C bridge arms. When any IGBT power switch in phase C bridge arm experiences a secondary single-transistor fault, relay K... M Switching to contact 2, load phase A is connected via relay K. M Connected to the midpoint n of capacitors C1 and C2, the bidirectional thyristor TR AC On, bidirectional thyristor TR AB When the phase C bridge arm is turned off, the two IGBT power switches are turned off. At this time, the midpoint a of the phase A bridge arm is connected to the midpoint c of the phase C bridge arm. The midpoint a of the phase A bridge arm is the midpoint of the phase C bridge arm. At this time, the three-phase four-switch derating operation mode is controlled by the phase A and B bridge arms.

3. A control method for a fault-tolerant inverter based on topology reconfiguration, characterized in that, Fault-tolerant control for the topology-reconfiguration-based fault-tolerant inverter according to any one of claims 1-2 includes the following steps: (a) Determine the SVPWM control under normal operating conditions Determine the switching state and basic voltage vector under normal operating conditions, divide the sector, determine the action time and action sequence of the basic voltage vector under normal operating conditions, and complete SVPWM control; (ii) Determining SVPWM control under primary single-transistor fault-tolerant operation. When a primary single-transistor fault occurs, adjust relay K in the redundant bridge arm according to the fault location of the IGBT power switch. S Relay K X Contact position, and the bidirectional thyristor TR that is connected. A TR B TR C To perform topology switching, the fault-tolerant inverter based on topology reconstruction operates in three-phase six-switch mode, that is, reconstructed to the corresponding primary fault-tolerant topology; by using the action time and action sequence of the basic voltage vector under normal operation, the effective IGBT power switching transistors used under primary single-transistor fault-tolerant operation are determined, and SVPWM control is completed. (III) Determining SVPWM control under fault-tolerant operation of secondary single transistor When a secondary single-tube fault occurs, relay K in the redundant bridge arm... S K X and bidirectional thyristor TR A TR B TR C Maintaining the fault-tolerant state after primary single-transistor failure, adjust relay K in the topology switching circuit according to the fault location of the IGBT power switch. M Contact position and control of bidirectional thyristor TR AB TR AC To perform topology switching, the fault-tolerant inverter operating mode based on topology reconstruction is switched to three-phase four-switch derating operation, that is, reconstructed to the corresponding secondary fault-tolerant topology; the effective phases under secondary single-transistor fault-tolerant operation are determined, the switching states and basic voltage vectors under secondary single-transistor fault-tolerant operation are determined, sector division is performed, the action time and action sequence of the basic voltage vectors under secondary single-transistor fault-tolerant operation are determined, and SVPWM control is completed.

4. The control method for a fault-tolerant inverter based on topology reconfiguration according to claim 3, characterized in that, (I) In determining the SVPWM control under normal operating conditions, the switching states and basic voltage vector under normal operating conditions are determined, sectors are divided, and the action time and sequence of the basic voltage vector under normal operating conditions are determined to complete the SVPWM control. The specific method is as follows: (1) Determine the switching state and basic voltage vector under normal operating conditions. In a three-phase bridge arm, each phase contains two switching states: 0 and 1. Under normal operating conditions, the "0" state indicates that the IGBT power switch of the upper bridge arm in a phase bridge arm is turned off and the IGBT power switch of the lower bridge arm is turned on. The "1" state indicates that the IGBT power switch of the upper bridge arm in a phase bridge arm is turned on and the IGBT power switch of the lower bridge arm is turned off. Define the switching function S x : ； Total output 2 3 =8 voltage state combinations, i.e. 8 switching states, corresponding to 8 basic voltage vectors: V0(000), V1(100), V2(110), V3(010), V4(011), V5(001), V6(101), and V7(111). The three numbers in parentheses represent the switching states of phase A, B, and C bridge arms, respectively. The first number represents the switching state of phase A bridge arm; the second number represents the switching state of phase B bridge arm; and the third number represents the switching state of phase C bridge arm. (2) Determine the sector division under normal operating conditions Define a function: ； ；C ； In the formula, , The voltage components of the reference voltage vector in the α and β phase stationary coordinate systems; Define symbolic functions: ； Define the sector number calculation value N: ； Determine the correspondence between the N value and the actual sector number to complete the sector division; when the calculated sector number N is 5, it corresponds to sector I; when the calculated sector number N is 4, it corresponds to sector II; when the calculated sector number N is 6, it corresponds to sector III; when the calculated sector number N is 2, it corresponds to sector IV; when the calculated sector number N is 3, it corresponds to sector V; when the calculated sector number N is 1, it corresponds to sector VI. The basic voltage vectors correspond to the following sectors: Sector I corresponds to basic voltage vectors V0(000), V1(100), V2(110), V7(111); Sector II corresponds to basic voltage vectors V0(000), V2(110), V3(010), V7(111); Sector III corresponds to basic voltage vectors V0(000), V3(010), V4(011), V7(111); Sector IV corresponds to basic voltage vectors V0(000), V4(011), V5(001), V7(111); Sector V corresponds to basic voltage vectors V0(000), V5(001), V6(101), V7(111); Sector VI corresponds to basic voltage vectors V0(000), V6(101), V1(100), V7(111). (3) Determine the action time and action sequence of the basic voltage vector under normal operating conditions to complete SVPWM control; Define the intermediate variable as: ； ； ； In the formula, U dc For the input DC voltage, T s For the switching period, T1, T2, and T0 are defined as the durations of action of the two effective vectors and the total zero vector in the basic voltage vector of the synthesized reference vector within one period, respectively. In sector I, the two effective vectors are V1(100) and V2(110), where the duration of action of V1(100) is T1=-Z and the duration of action of V2(110) is T2=X. The durations of action of the zero vector V0(000) and the zero vector V7(111) are both... The order of action is V0(000), V1(100), V2(110), V7(111), V2(110), V1(100), V0(000); In sector II, the two effective vectors are V2(110) and V3(010), with the action time of V2(110) being T1=Z and the action time of V3(010) being T2=Y. The action times of the zero vector V0(000) and the zero vector V7(111) are both... The order of action is V0(000), V3(010), V2(110), V7(111), V2(110), V3(010), V0(000); In sector III, the two effective vectors are V3(010) and V4(011), with the action time of V3(010) being T1=X and the action time of V4(011) being T2=-Y. The action times of the zero vector V0(000) and the zero vector V7(111) are both... The order of action is V0(000), V3(010), V4(011), V7(111), V4(011), V3(010), V0(000); In sector IV, the two effective vectors are V4(011) and V5(001), with the action time of V4(011) being T1=-X and the action time of V5(001) being T2=Z. The action times of the zero vector V0(000) and the zero vector V7(111) are both... The order of action is V0(000), V5(001), V4(011), V7(111), V4(011), V5(001), V0(000); In sector V, the two effective vectors are V5(001) and V6(101), with the action time of V5(001) being T1=-Y and the action time of V6(101) being T2=-Z. The action times of the zero vectors V0(000) and V7(111) are both... The order of action is V0(000), V5(001), V6(101), V7(111), V6(101), V5(001), V0(000); In sector VI, the two effective vectors are V6(101) and V1(100), with the action time of V6(101) being T1=Y and the action time of V1(100) being T2=-X. The action times of the zero vectors V0(000) and V7(111) are both... The order of action is V0(000), V1(100), V6(101), V7(111), V6(101), V1(100), V0(000); Based on the action time and sequence of the basic voltage vector, the conduction time of the IGBT power switch in the three-phase bridge arm is determined, and a PWM signal is generated and input to the gate of the IGBT power switch in the three-phase bridge arm to control the on and off of the IGBT power switch, thus completing the control of the fault-tolerant inverter based on topology reconfiguration under normal operating conditions.

5. The control method for a fault-tolerant inverter based on topology reconfiguration according to claim 4, characterized in that, (II) Determining the SVPWM control under fault-tolerant operation state of the primary single transistor: When a primary single transistor fault occurs in the SVPWM control under fault-tolerant operation state, the relay K in the redundant bridge arm is adjusted according to the fault location of the IGBT power switch. S Relay K X Contact position, and the bidirectional thyristor TR that is connected. A TR B TR C To perform topology switching, the fault-tolerant inverter based on topology reconfiguration maintains operation in three-phase six-switch mode, i.e., reconfigured to the corresponding primary fault-tolerant topology. Utilizing the duration and sequence of the basic voltage vector under normal operating conditions, the effective IGBT power switches for primary single-transistor fault-tolerant operation are determined, and SVPWM control is completed. The specific method is as follows: (1) Adjust relay K in the redundant bridge arm according to the fault location of the IGBT power switch. S Relay K X Contact position, and the bidirectional thyristor TR that is connected. A TR B TR C To perform topology switching, the fault-tolerant inverter based on topology reconfiguration operates in three-phase six-switch mode, that is, reconfigured to the corresponding primary fault-tolerant topology; When an open-circuit fault is diagnosed in the IGBT power switch S1 of the upper arm of phase A, the bidirectional thyristor TR... A When the control electrode signal input is high, the bidirectional thyristor TR... B TR C TR AB TR AC When the control electrode signal input is low, the bidirectional thyristor TR... A On, bidirectional thyristor TR B TR C TR AB TR AC Off, relay K S Relay K remains at contact 1. X Relay K remains at contact 2. M Maintain contact 1; so that the IGBT power switch S7 in the redundant bridge arm is reconstituted into the upper bridge arm of phase A; at this time, stop the signal input to the faulty phase IGBT power switch S1, and control the on / off of the faulty phase IGBT power switch S4 and IGBT power switch S7. When an open-circuit fault is diagnosed in the IGBT power switch S4 of the lower arm of phase A, the bidirectional thyristor TR... A When the control electrode signal input is high, the bidirectional thyristor TR... B TR C TR AB TR AC The control electrode signal input is in a low-level state; relay K S K X When a current signal is applied, relay K... S Switch to contact 2, relay K X Switch to contact 1, relay K M Maintain contact 1; so that the IGBT power switch S7 in the redundant bridge arm is reconstituted into the lower bridge arm of phase A; at this time, stop the signal input to the faulty phase IGBT power switch S4, and control the on / off of the faulty phase IGBT power switch S1 and IGBT power switch S7. When an open-circuit fault is diagnosed in the IGBT power switch S3 of the upper bridge arm of phase B, the bidirectional thyristor TR... B When the control electrode signal input is high, the bidirectional thyristor TR... A TR C TR AB TR AC The control electrode signal input is at a low level; at this time, the bidirectional thyristor TR B On, bidirectional thyristor TR A TR C TR AB TR AC Off, relay K S Relay K remains at contact 1. X Relay K remains at contact 2. M Maintain contact 1; so that the IGBT power switch S7 in the redundant bridge arm is reconstituted into the upper bridge arm of phase B; at this time, stop the signal input to the faulty phase IGBT power switch S3, and control the on / off of the faulty phase IGBT power switch S6 and IGBT power switch S7. When an open-circuit fault is diagnosed in the IGBT power switch S6 of the lower arm of phase B, the bidirectional thyristor TR... B When the control electrode signal input is high, the bidirectional thyristor TR... A TR C TR AB TR AC The control electrode signal input is at a low level; at this time, the bidirectional thyristor TR B On, bidirectional thyristor TR A TR C TR AB TR AC Off, relay K S K X When a current signal is applied, relay K... S Switch to contact 2, relay K X Switch to contact 1, relay K M Maintain contact 1; so that the IGBT power switch S7 in the redundant bridge arm is reconstituted into the lower bridge arm of phase B; at this time, stop the signal input to the faulty phase IGBT power switch S6, and control the on / off of the faulty phase IGBT power switch S3 and IGBT power switch S7. When an open-circuit fault is diagnosed in the IGBT power switch S5 of the upper arm of phase C, the bidirectional thyristor TR... C When the control electrode signal input is high, the bidirectional thyristor TR... A TR B TR AB TR AC The control electrode signal input is at a low level; at this time, the bidirectional thyristor TR C On, bidirectional thyristor TR A TR B TR AB TR AC Off, relay K S Relay K remains at contact 1. X Relay K remains at contact 2. M Maintain contact 1; so that the IGBT power switch S7 in the redundant bridge arm is reconstituted into the upper bridge arm of phase C; at this time, stop the signal input to the faulty phase IGBT power switch S5, and control the on / off of the faulty phase IGBT power switch S2 and IGBT power switch S7. When an open-circuit fault is diagnosed in the IGBT power switch S2 of the lower arm of phase C, the bidirectional thyristor TR... C When the control electrode signal input is high, the bidirectional thyristor TR... A TR B TR AB TR AC The control electrode signal input is at a low level; at this time, the bidirectional thyristor TR C On, bidirectional thyristor TR A TR B TR AB TR AC Off, relay K S K X When a current signal is applied, relay K... S Switch to contact 2, relay K X Switch to contact 1, relay K M Maintain contact 1; so that the IGBT power switch S7 in the redundant bridge arm is reconstituted into the lower bridge arm of phase C; at this time, stop the signal input to the faulty phase IGBT power switch S2, and control the on / off of the faulty phase IGBT power switch S5 and IGBT power switch S7. (2) By utilizing the action time and action sequence of the basic voltage vector under normal operating conditions, determine the IGBT power switching transistors that are effectively used under primary single-transistor fault-tolerant operating conditions, and complete SVPWM control; When an open-circuit fault occurs in the IGBT power switch S1 of the upper arm of phase A, after fault tolerance, the IGBT power switches that can be effectively used in the primary single-tube fault tolerance operation state are: IGBT power switches S7, S2, S3, S4, S5, and S6. When an open-circuit fault occurs in the IGBT power switch S4 of the lower arm of phase A, after fault tolerance, the IGBT power switches that are effectively used in the primary single-tube fault-tolerant operation state are: IGBT power switches S1, S2, S3, S7, S5, and S6. When an open-circuit fault occurs in the IGBT power switch S3 of the upper arm of phase B, after fault tolerance, the IGBT power switches that can be effectively used in the primary single-tube fault tolerance operation state are: IGBT power switches S1, S2, S7, S4, S5, and S6. When an open-circuit fault occurs in the IGBT power switch S6 of the lower arm of phase B, after fault tolerance, the IGBT power switches that are effectively used in the primary single-tube fault-tolerant operation state are: IGBT power switches S1, S2, S3, S4, S5, and S7. When an open-circuit fault occurs in the IGBT power switch S5 of the upper arm of phase C, after fault tolerance, the IGBT power switches that can be effectively used in the primary single-tube fault tolerance operation state are: IGBT power switches S1, S2, S3, S4, S7, and S6. When an open-circuit fault occurs in the IGBT power switch S2 of the lower arm of phase C, after fault tolerance, the IGBT power switches that can be effectively used in the primary single-tube fault-tolerant operation state are: IGBT power switches S1, S7, S3, S4, S5, and S6. Based on the action time and sequence of the basic voltage vector under normal operating conditions, the conduction time of the effectively used IGBT power switches is determined, and a PWM signal is generated and input to the gate of the effectively used IGBT power switches to control the on / off state of the effectively used IGBT power switches, thus completing the control of the fault-tolerant inverter based on topology reconfiguration under the fault-tolerant operation state of the primary single-tube fault.

6. The control method for a fault-tolerant inverter based on topology reconfiguration according to claim 5, characterized in that, (III) In the SVPWM control under secondary single-transistor fault-tolerant operation, when a secondary single-transistor fault occurs, the relay K in the redundant bridge arm... S K X and bidirectional thyristor TR A TR B TR C Maintaining the fault-tolerant state after primary single-transistor failure, adjust relay K in the topology switching circuit according to the fault location of the IGBT power switch. M Contact position and control of bidirectional thyristor TR AB TR AC To perform topology switching, the fault-tolerant inverter operating mode based on topology reconstruction is switched to three-phase four-switch derating operation, i.e., reconstructed to the corresponding secondary fault-tolerant topology; the effectively used phases under secondary single-transistor fault-tolerant operation are determined, as are the switching states and basic voltage vectors under secondary single-transistor fault-tolerant operation. Sector division is performed, and the action time and sequence of the basic voltage vectors under secondary single-transistor fault-tolerant operation are determined to complete SVPWM control, wherein: When a secondary single-tube fault occurs, relay K in the redundant bridge arm... S K X and bidirectional thyristor TR A TR B TR C Maintaining the fault-tolerant state after primary single-transistor failure, adjust relay K in the topology switching circuit according to the fault location of the IGBT power switch. M Contact position and control of bidirectional thyristor TR AB TR AC To perform topology switching, the fault-tolerant inverter operating mode based on topology reconfiguration is switched to three-phase four-switch derating operation, that is, reconfigured to the corresponding secondary fault-tolerant topology. The specific method is as follows: When an open-circuit fault is diagnosed in the upper or lower IGBT power switch connected to the A-phase load, the bidirectional thyristor TR... AB TR AC When the control electrode signal input is low, the bidirectional thyristor TR... AB TR AC Keep off; Relay K M When a current signal is applied, relay K... M The contact switches to contact 2, allowing the load of phase A to pass through relay K. M Connect the load to the midpoint n of capacitors C1 and C2, connect the load of phase B to the midpoint b of phase B bridge arm, and connect the load of phase C to the midpoint c of phase C bridge arm. When an open-circuit fault is diagnosed in the upper arm IGBT power switch or the lower arm IGBT power switch connected to the B-phase load, the bidirectional thyristor TR... AB When the control electrode signal input is high, TR AC When the control electrode signal input is low, the bidirectional thyristor TR... AB On, bidirectional thyristor TR AC Off; Relay K M When a current signal is applied, relay K... M The contact switches to contact 2, allowing the load of phase A to pass through relay K. M Connected to the midpoint n of capacitors C1 and C2, the B-phase load is connected through the bidirectional thyristor TR. AB Connect the load to the midpoint a of phase A bridge arm, and connect the load to the midpoint c of phase C bridge arm; When an open-circuit fault is diagnosed in the upper arm IGBT power switch or the lower arm IGBT power switch connected to the C-phase load, TR AB When the control electrode signal input is low, TR AC When the control electrode signal input is high, the bidirectional thyristor TR... AB Turn off, bidirectional thyristor TR AC On; Relay K M When a current signal is applied, relay K... M The contact switches to contact 2, allowing the load of phase A to pass through relay K. M The load of phase B is connected to the midpoint n of capacitors C1 and C2, and the load of phase C is connected to the midpoint b of phase B bridge arm. The load of phase C is connected through the bidirectional thyristor TR. AC Connect to the midpoint a of phase A bridge arm.

7. The control method for a fault-tolerant inverter based on topology reconfiguration according to claim 6, characterized in that, (III) In the SVPWM control under secondary single-transistor fault-tolerant operation, when a secondary single-transistor fault occurs, the relay K in the redundant bridge arm... S K X and bidirectional thyristor TR A TR B TR C Maintaining the fault-tolerant state after primary single-transistor failure, adjust relay K in the topology switching circuit according to the fault location of the IGBT power switch. M Contact position and control of bidirectional thyristor TR AB TR AC To perform topology switching, the fault-tolerant inverter operating mode based on topology reconstruction is switched to three-phase four-switch derating operation, i.e., reconstructed to the corresponding secondary fault-tolerant topology; the effectively used phases under secondary single-transistor fault-tolerant operation are determined, as are the switching states and basic voltage vectors under secondary single-transistor fault-tolerant operation. Sector division is performed, and the action time and sequence of the basic voltage vectors under secondary single-transistor fault-tolerant operation are determined to complete SVPWM control, wherein: Determine the effective phases under the fault-tolerant operation state of the secondary single transistor, determine the switching state and basic voltage vector under the fault-tolerant operation state of the secondary single transistor, divide the sector, determine the action time and action sequence of the basic voltage vector under the fault-tolerant operation state of the secondary single transistor, and complete SVPWM control; (a) Determine the effective phases under fault-tolerant operation of the secondary single-tube, specifically by: When a secondary single-tube fault occurs in the IGBT power switch of the upper or lower bridge arm connected to the load of phase A, after fault tolerance, the load of phase B is connected to the midpoint b of the phase B bridge arm, and the load of phase C is connected to the midpoint c of the phase C bridge arm. Under the fault-tolerant operation state of secondary single-tube fault, the effective phases are phase B and phase C bridge arms. When a secondary single-tube fault occurs in the IGBT power switch of the upper or lower bridge arm connected to the load of phase B, after fault tolerance, the load of phase B is connected to the midpoint a of the bridge arm of phase A, and the load of phase C is connected to the midpoint c of the bridge arm of phase C. Under the fault tolerance operation state of secondary single-tube fault, the effective phases are: bridge arms of phases A and C. When a secondary single-tube fault occurs in the IGBT power switch of the upper or lower bridge arm connected to the C-phase load, after fault tolerance, the B-phase load is connected to the midpoint b of the B-phase bridge arm, and the C-phase load is connected to the midpoint a of the A-phase bridge arm. Under the fault-tolerant operation state of the secondary single-tube fault, the effective phases are: the A and B phase bridge arms. (b) Determine the switching state and basic voltage vector under the fault-tolerant operation state of the secondary single-transistor; after switching the secondary fault-tolerant topology, the three-phase bridge arm is always connected to the loads of phases B and C, and the load of phase A is always connected to the midpoint n of the capacitor. Only the bridge arm connected to the loads of phases B and C needs to be controlled, with a total output of 2. 2 =4 voltage state combinations, i.e. 4 switching states, corresponding to 4 basic voltage vectors, V1(00), V2(10), V3(11), V4(01); The two numbers 0 and 1 in the parentheses of the switching function represent the switching states of the bridge arms connected to the B and C phase loads, respectively. The first number represents the switching state of the bridge arm connected to the B phase load. Switching state "0" means that the upper bridge arm IGBT power switch connected to the B phase load is off and the lower bridge arm IGBT power switch connected to the B phase load is on. Switching state "1" means that the upper bridge arm IGBT power switch connected to the B phase load is on and the lower bridge arm IGBT power switch connected to the B phase load is off. The second number represents the switching state of the bridge arm connected to the C phase load. Switching state "0" means that the upper bridge arm IGBT power switch connected to the C phase load is off and the lower bridge arm IGBT power switch connected to the C phase load is on. Switching state "1" means that the upper bridge arm IGBT power switch connected to the C phase load is on and the lower bridge arm IGBT power switch connected to the C phase load is off. (c) Determine the sector division under the fault-tolerant operation state of the secondary single-tube fault; Define a function: ； ； Determine the correspondence between the A1 value, B1 value and the actual sector number to complete the sector division; when the A1 value is greater than 0 and the B1 value is greater than 0, it corresponds to sector I; when the A1 value is less than 0 and the B1 value is greater than 0, it corresponds to sector II; when the A1 value is less than 0 and the B1 value is less than 0, it corresponds to sector III; when the A1 value is greater than 0 and the B1 value is less than 0, it corresponds to sector IV. The basic voltage vectors correspond to the sectors as follows: the basic voltage vectors corresponding to sector I are: V1(00), V2(10), the basic voltage vectors corresponding to sector II are: V2(10), V3(11), the basic voltage vectors corresponding to sector III are: V3(11), V4(01), and the basic voltage vectors corresponding to sector IV are: V4(01), V1(00). (d) Determine the duration and sequence of action of the basic voltage vector in the fault-tolerant operation state of the secondary single-transistor; Define intermediate variable T x T y T z T represents the duration of action of the two effective vectors and the total zero vector within the fundamental voltage vector of the synthesized reference vector, respectively, during one period. s The time for one cycle: ； ； ； In sector I, the two effective vectors are V1(00) and V2(10), and the zero vector is synthesized from V1(00) and V3(11). The duration of action of V1(00) is T1 = T x +T z / 2, the duration of action of V2(10) is T2=T y The duration of action of V3(11) is T3=T z / 2; The order of action is V1(00), V2(10), V3(11), V2(10), V1(00); In sector II, the two effective vectors are V2(10) and V3(11), and the zero vector is synthesized from V1(00) and V3(11), where the duration of action of V1(00) is T1=T z / 2, the duration of action of V2(10) is T2=T x The duration of action of V3(11) is T3=T y +T z / 2; The order of action is V1(00), V2(10), V3(11), V2(10), V1(00); In sector III, the two effective vectors are V3(11) and V4(01), and the zero vector is synthesized from V1(00) and V3(11), where the duration of action of V1(00) is T1=T z / 2, the duration of V4(01) is T2=T y The duration of action of V3(11) is T3=T x +T z / 2; The order of action is V1(00), V4(01), V3(11), V4(01), V1(00); In sector IV, the two effective vectors are V4(01) and V1(00), and the zero vector is synthesized from V1(00) and V3(11). The duration of action of V1(00) is T1 = T y +T z / 2, the duration of V4(01) is T2=T x The duration of action of V3(11) is T3=T z / 2; The order of action is V1(00), V4(01), V3(11), V4(01), V1(00); (e) Complete SVPWM control; Based on the action time and sequence of the basic voltage vector under the fault-tolerant operation state of the secondary single-transistor fault, the conduction time of the IGBT power switch in the effectively used phase under the fault-tolerant operation state of the secondary single-transistor fault is determined. A PWM signal is generated and input to the gate of the IGBT power switch in the effectively used phase under the fault-tolerant operation state of the secondary single-transistor fault, controlling the on and off of the IGBT power switch in the effectively used phase under the fault-tolerant operation state of the secondary single-transistor fault, thus completing the control of the fault-tolerant inverter based on topology reconfiguration under the fault-tolerant operation state of the secondary single-transistor fault.

8. A control system for a fault-tolerant inverter based on topology reconfiguration, characterized in that, The control method for a fault-tolerant inverter based on topology reconfiguration as described in any one of claims 3-7 is implemented to realize the control of the fault-tolerant inverter based on topology reconfiguration. The control is divided into three modules, which respectively execute SVPWM control under normal operation, SVPWM control under primary single-tube fault-tolerant operation, and SVPWM control under secondary single-tube fault-tolerant operation.

9. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, it implements the control method for a fault-tolerant inverter based on topology reconfiguration as described in any one of claims 3-7, thereby realizing the control of the fault-tolerant inverter based on topology reconfiguration.

10. A computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, it implements the control method for a fault-tolerant inverter based on topology reconfiguration as described in any one of claims 3-7, thereby realizing fault-tolerant control of the fault-tolerant inverter based on topology reconfiguration.

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