Global dynamic self-biased low-noise phase-locked loop circuit and electronic equipment

Abstract

The invention discloses a global dynamic self-biased low-noise phase-locked loop circuit and electronic equipment. The global dynamic self-biased low-noise phase-locked loop circuit comprises a phase frequency detector, a charge pump, a current-to-voltage module, a comparison operational amplifier, a bias current mirror module, a voltage-to-current module, a current control oscillator, a feedback frequency dividing circuit and a low dropout regulator circuit, and the phase frequency detector, the charge pump, the current-to-voltage module, the comparison operational amplifier, the bias current mirror module, the voltage-to-current module and the current-controlled oscillator are connected in sequence so as to generate an output clock through the current-controlled oscillator. The invention aims to solve the problem of serious phase noise of a traditional phase-locked loop circuit in a high-speed and high-precision application scene, especially the problem of current mismatch of a charge pump, so that the phase-locked loop circuit bias has the characteristics of low noise and high speed.

Description

Technical Field

[0001] The present invention relates to a phase-locked loop circuit in an electronic circuit, and in particular to a global dynamic self-biased low-noise phase-locked loop circuit and electronic equipment. Background Art

[0002] Phase-locked loop (PLL) circuits are widely used in communication systems. The circuit structure of traditional PLL circuits is as follows: Figure 1 As shown, the PLL circuit includes a phase-frequency detector (PFD), a charge pump (CP), a voltage-to-current converter (V2I), a voltage-controlled oscillator (VCO) or a current-controlled oscillator (CCO), and a feedback divider (FB-Div). In high-speed, high-precision applications, traditional phase-locked loop (PLL) circuits suffer from severe phase noise, particularly current mismatch in the charge pump. This limits the application of PLL circuits in high-speed, high-precision circuits. Summary of the Invention

[0003] The technical problem to be solved by the present invention is as follows: In response to the above-mentioned problems of the prior art, a global dynamic self-biased low-noise phase-locked loop circuit and electronic equipment are provided. The present invention aims to solve the serious phase noise of traditional phase-locked loop circuits in high-speed and high-precision application scenarios, especially the current mismatch of the charge pump, so that the phase-locked loop circuit bias has the characteristics of low noise and high speed.

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is: A global dynamic self-biased low-noise phase-locked loop circuit includes a phase frequency detector, a charge pump cp, a current-to-voltage module I2V, a comparison operational amplifier A1, a bias current mirror module bias, a voltage-to-current module V2I, a current-controlled oscillator CCO, a feedback frequency division circuit, and a low-dropout linear regulator circuit LDO. The phase frequency detector, the charge pump cp, the current-to-voltage module I2V, the comparison operational amplifier A1, the bias current mirror module bias, the voltage-to-current module V2I, and the current-controlled oscillator CCO are sequentially connected to generate an output through the current-controlled oscillator CCO. The output clock Clk_out is output, and the input end of the feedback frequency divider circuit is connected to the output end of the current controlled oscillator CCO to divide the output clock Clk_out to generate the feedback clock Fb_clk required by the phase frequency detector. The bias voltage Vpsf of the charge pump cp, the current-to-voltage module I2V, the bias current mirror module bias, and the voltage-to-current module V2I all come from the low-dropout linear regulator circuit LDO, and the reference voltage Vreg of the low-dropout linear regulator circuit LDO is the same as the reference voltage Vreg of the comparison operational amplifier A1 to form a self-bias loop.

[0005] Optionally, the bias current mirror module bias includes pmos tubes Mp1-Mp10 and nmos tubes Mn1-Mn7, pmos tube Mp1 and nmos tube Mn1 are arranged in series between the bias voltage Vpsf and the ground, pmos tube Mp2, pmos tube Mp3, and nmos tube Mn2 are arranged in series between the bias voltage Vpsf and the ground, the gate of pmos tube Mp2 is connected to the frequency selection signal Freq_sel, the gate of pmos tube Mp1 is connected to the amplified signal Vbias output by the comparison operational amplifier A1, the gates of nmos tubes Mn1 and Mn2 are connected to form a current mirror to generate a bias current Vb and output it to the current-to-voltage module I2V; pmos tube Mp4 and pmos tube Mp7 are connected in series and one end is connected to the bias voltage Vpsf and the other end outputs the bias current Icp1 to the charge pump cp, pmos tubes Mp5 and pmos The transistor Mp5 is connected in series with one end connected to the bias voltage Vpsf and the other end outputting the bias current Icp2 to the charge pump cp. The pmos transistor Mp6 and the nmos transistor Mn3 are arranged in series between the bias voltage Vpsf and ground. The pmos transistor Mp9 and the nmos transistor Mn4 are arranged in series between the bias voltage Vpsf and ground. The gates of the nmos transistors Mn3 and Mn4 are connected to form a current mirror to generate a control signal to control the gate of the pmos transistor Mp10. The source of the pmos transistor Mp10 is connected to the bias voltage Vpsf, and the drain generates a bias current icas through multiple parallel units and outputs it to the voltage-to-current module V2I; the parallel units include nmos transistors Mn5, Mn6 and Mn7. The drain of the pmos transistor Mp10 is grounded in sequence through one or more groups of nmos transistors Mn5, Mn6 and Mn7, and the gate of the nmos transistor Mn7 is connected to the power supply voltage Vp_cp.

[0006] Optionally, the circuit portion that generates the bias voltage Vpsf in the low-dropout linear regulator circuit LDO includes an nmos tube Mn8, pmos tubes Mp11-Mp12, an operational amplifier A4, and multiple nmos tubes connected in series, the pmos tube Mp11 and the nmos tube Mn8 are arranged in series between the voltage Vph and ground, the gate of the nmos tube Mn8 is connected to the output voltage Vreg of the pmos tube Mp6 in the bias current mirror module bias, the drain of the pmos tube Mp11 is connected to the gate of the pmos tube Mp12, the pmos tube Mp12 and the multiple nmos tubes connected in series are arranged in series between the voltage Vph and ground, and the drain of the pmos tube Mp12 is connected to the input end of the operational amplifier A4 to output the bias voltage Vpsf through the output end of the operational amplifier A4.

[0007] Optionally, the circuit part that generates the power supply voltage Vp_cp in the low-dropout linear regulator circuit LDO includes a capacitor, an operational amplifier A5 and multiple pmos tubes connected in series. The multiple pmos tubes and the capacitor are connected in series and arranged in series between the voltage Vph and the ground, and the intermediate node between the capacitor and the multiple pmos tubes connected in series is connected to the input end of the operational amplifier A5 to output the power supply voltage Vp_cp through the output end of the operational amplifier A5.

[0008] Optionally, the charge pump cp includes operational amplifiers A2-A3, pmos tubes Mp13-Mp20 and nmos tubes Mn9-Mn16. The input signals of the charge pump cp are the increase signal UP, the inverted increase signal UPb, the decrease signal DN, the inverted decrease signal DN generated after the frequency and phase detection of the phase frequency detector PFD, the reference voltage signal Vref generated by the current-to-voltage module I2V, the bias voltage signal Vb generated after the bias current mirror module bias, and a pair of opposite power-on signals Pon and ponb; the output signal of the charge pump cp includes the control voltage signal Vctr l and Vint, the control voltage signal Vctrl is fed back to the voltage conversion current module V2I to control its pull-down network, which is also the input end of the comparison operational amplifier A1; the control voltage signal Vint is fed back to the gate of the nmos tube Mn20 of the current conversion voltage module I2V to control the generation of the control voltage signal Vctrl; the pull-up network that generates the control voltage signals Vctrl and Vint in the charge pump cp is controlled by the pmos tube Mp13 and the pmos tube Mp17 respectively; the pull-down network that generates the control voltage signal Vctrl and the control voltage signal Vint is controlled by the nmos tube Mn12 and nmos tube Mn16 control, increase signal UP input into the gate of nmos tube Mn10 and pmos tube Mp19, inverted increase signal UPb input into the gate of nmos tube Mn9 and pmos tube Mp20, decrease signal DN input into the gate of pmos tube Mp15 and nmos tube Mn14, inverted decrease signal DN input into the gate of nmos tube Mn13 and pmos tube Mp16, reference voltage signal Vref input into the gate of nmos tube Mn11 and Mn15, control the pull-down network of charge pump cp; bias voltage signal Vb input into pmos tube M The gates of p14 and Mp18 control the pull-up network of the charge pump cp; an operational amplifier A3 is clamped at the control terminal Vctrl_dump between the control voltage signal Vctrl and the drains of the pmos tube Mp15 and the nmos tube Mn9. At the same time, an identical operational amplifier A2 is also clamped at the control terminal Vint_dump between the control voltage signal Vint and the drains of the pmos tube Mp20 and the nmos tube Mn14. There are a total of 24 groups of charge pumps cp that generate the control voltage signal Vctrl, and a total of 8 groups of charge pumps cp that generate the control voltage signal Vint.

[0009] Optionally, the current-to-voltage module I2V includes pmos tubes Mp21-Mp26 and nmos tubes Mn17-Mn25, the input signal is a bias voltage signal Vb generated after the bias current mirror module bias is biased, a pair of opposite power-on signals Pon and ponb, and a control signal Pon_stop, and the output signal is a control voltage signal Vctrl and a reference voltage signal Vref; the reference voltage signal Vref is fed back to the charge pump cp to control the pull-down network of the charge pump cp; the control voltage signal Vctrl is fed back to the voltage conversion current module V2I to control its pull-down network, and is also the input end of the comparison operational amplifier A1; the power-on signal Ponb is connected to the gates of the pmos tubes Mp24 and Mp21, the power-on signal Pon is connected to the gates of the nmos tubes Mn17-Mn18, Mn21-Mn22, Mn23-Mn25, and the control signal Pon_stop is connected to the gates of the pmos tubes Mp23 and Mp26.

[0010] Optionally, the voltage-to-current module V2I includes a pmos tube Mp27 and nmos tubes Mn26-Mn28, the input signals are the amplified signal Vbias output by the comparison operational amplifier A1, the bias signal icas generated after the bias current mirror module bias is biased, and the control voltage signal Vctrl jointly adjusted and generated by the current-to-voltage module I2V and the CP module. The output signal is the current-controlled oscillator CCO input signal ivco, which controls the oscillation frequency of the current-controlled oscillator CCO; the amplified signal Vbias is connected to the gate of the pmos tube Mp27 to control the pull-up network that generates the input signal ivco of the current-controlled oscillator CCO, and the bias signal icas and the control voltage signal Vctrl are respectively connected to the gates of the nmos tubes Mn26 and Mn27 to jointly control the pull-down network that generates the input signal ivco of the current-controlled oscillator CCO.

[0011] Optionally, the output end of the comparison operational amplifier A1 is further grounded via a MOS capacitor X501.

[0012] In addition, the present invention also provides an electronic device, including a device body and a circuit module arranged in the device body, wherein the circuit module includes the global dynamic self-bias low-noise phase-locked loop circuit.

[0013] Compared with the prior art, the present invention can mainly achieve the following beneficial effects: the present invention includes a phase frequency detector, a charge pump cp, a current-to-voltage module I2V, a comparison operational amplifier A1, a bias current mirror module bias, a voltage-conversion current module V2I, a current-controlled oscillator CCO, a feedback frequency division circuit, and a low-dropout linear regulator circuit LDO. The phase frequency detector, the charge pump cp, the current-to-voltage module I2V, the comparison operational amplifier A1, the bias current mirror module bias, the voltage-conversion current module V2I, and the current-controlled oscillator CCO are sequentially connected to generate an output clock Clk_out through the current-controlled oscillator CCO, and the global dynamic self-bias low-noise The bias voltages for all modules in the acoustic phase-locked loop circuit are provided by an internal low-dropout linear regulator circuit (LDO). At the same time, the reference current for the LDO is provided by the loop's comparator operational amplifier (A1), forming a self-bias loop. The self-biased modules in the self-bias loop include the comparator operational amplifier (A1), the current-to-voltage module (I2V), the voltage-to-current module (V2I), the charge pump (CP), the low-dropout linear regulator circuit (LDO), and the bias current mirror module (BIAS). This solves the severe phase noise issues of traditional phase-locked loop circuits in high-speed and high-precision applications, particularly the current mismatch of the charge pump. This ensures low-noise and high-speed biasing of the phase-locked loop circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 Schematic diagram of the circuit structure of a traditional phase-locked loop circuit.

[0015] Figure 2 Schematic diagram of the circuit framework structure of the phase-locked loop circuit in an embodiment of the present invention.

[0016] Figure 3 2 is a schematic diagram of the circuit principle of the phase-locked loop circuit in an embodiment of the present invention.

[0017] Figure 4 1 is a circuit schematic diagram of two parts of a low-dropout linear regulator circuit LDO in an embodiment of the present invention, wherein (a) is a circuit part for generating a bias voltage Vpsf, and (b) is a circuit part for generating a power supply voltage Vp_cp.

[0018] Figure 5 FIG. 4 is a schematic diagram of a feedback loop of a charge pump cp according to an embodiment of the present invention. DETAILED DESCRIPTION

[0019] In order to enable those skilled in the art to better understand the technical solution of the present invention, the technical solution of the present invention will be further described in detail below with reference to the accompanying drawings in the embodiments of the present invention.

[0020] like Figure 2 and Figure 3As shown, the global dynamic self-biased low-noise phase-locked loop circuit of this embodiment includes a phase frequency detector, a charge pump cp, a current-to-voltage module I2V, a comparison operational amplifier A1, a bias current mirror module bias, a voltage-to-current module V2I, a current-controlled oscillator CCO, a feedback frequency division circuit, and a low-dropout linear regulator circuit LDO. The phase frequency detector, the charge pump cp, the current-to-voltage module I2V, the comparison operational amplifier A1, the bias current mirror module bias, the voltage-to-current module V2I, and the current-controlled oscillator CCO are sequentially connected to generate a current through the current-controlled oscillator CCO. The output clock Clk_out is generated. The input end of the feedback frequency divider circuit is connected to the output end of the current controlled oscillator CCO to divide the output clock Clk_out to generate the feedback clock Fb_clk required by the phase frequency detector. The bias voltage Vpsf of the charge pump cp, the current-to-voltage module I2V, the bias current mirror module bias, and the voltage-to-current module V2I all come from the low-dropout linear regulator circuit LDO, and the reference voltage Vreg of the low-dropout linear regulator circuit LDO is the same as the reference voltage Vreg of the comparison operational amplifier A1 to form a self-bias loop. Among them, the low-dropout linear regulator circuit LDO is used to provide the voltage required by each module; the charge pump cp is used to convert the phase information of the frequency and phase detector into current; the current-to-voltage module I2V is used to convert the current output by the charge pump cp into a voltage value; the comparison operational amplifier module is used to output the voltage difference between the control voltage signal Vtrl and the reference voltage signal Vref of the current-to-voltage module I2V to the bias current mirror module bias through the operational amplifier; the bias current mirror module bias is used to convert the operational amplifier output voltage value into the dynamic bias current required globally; the voltage-to-current module V2I is used to convert the voltage value generated by the bias current mirror module bias into a current value to drive the current-controlled oscillator CCO, and generate the required clock signal through the current-controlled oscillator CCO.

[0021] After the bias current mirror module is biased by the comparison operational amplifier A1, it generates a reference current, which is then mirrored through the transistor to generate the bias current of the unity gain amplifier in the charge pump CP, biasing the two CP modules CP1 and CP2 in the charge pump CP respectively. The two modules CP1 and CP2 refer to a X24 and a X8 unit that generate the control voltage signals Vctrl and Vint, respectively, where X24 and X8 represent the number of groups of CP modules CP1 and CP2. Figure 3As shown, the bias current mirror module bias in this embodiment includes pmos transistors Mp1-Mp10 and nmos transistors Mn1-Mn7, the pmos transistors Mp1 and the nmos transistor Mn1 are arranged in series between the bias voltage Vpsf and the ground, the pmos transistors Mp2, the pmos transistors Mp3, and the nmos transistors Mn2 are arranged in series between the bias voltage Vpsf and the ground, the gate of the pmos transistor Mp2 is connected to the frequency selection signal Freq_sel, the gate of the pmos transistor Mp1 is connected to the amplified signal Vbias output by the comparison operational amplifier A1, the gates of the nmos transistors Mn1 and Mn2 are connected to form a current mirror to generate a bias current Vb and output it to the current-to-voltage module I2V; the pmos transistors Mp4 and the pmos transistors Mp7 are connected in series with one end connected to the bias voltage Vpsf and the other end outputting the bias current Icp1 to the charge pump cp, the pmos transistors Mp5 and pmos transistors Mp6 are connected in series with one end connected to the bias voltage Vpsf and the other end outputting the bias current Icp1 to the charge pump cp. The pmos transistor Mp5 is connected in series, with one end connected to the bias voltage Vpsf and the other end outputting a bias current Icp2 to the charge pump CP. The pmos transistor Mp6 and the nmos transistor Mn3 are arranged in series between the bias voltage Vpsf and ground. The pmos transistor Mp9 and the nmos transistor Mn4 are arranged in series between the bias voltage Vpsf and ground. The gates of the nmos transistors Mn3 and Mn4 are connected to form a current mirror to generate a control signal to control the gate of the pmos transistor Mp10. The source of the pmos transistor Mp10 is connected to the bias voltage Vpsf, and the drain generates a bias current icas through multiple parallel units and outputs it to the voltage-to-current conversion module V2I; the parallel units include nmos transistors Mn5, Mn6, and Mn7. The drain of the pmos transistor Mp10 is grounded in sequence through one or more groups of nmos transistors Mn5, Mn6, and Mn7. The gate of the nmos transistor Mn7 is connected to the power supply voltage Vp_cp.

[0022] The low-dropout linear regulator circuit LDO in this embodiment includes two circuit parts: a circuit part for generating a bias voltage Vpsf and a circuit part for generating a power supply voltage Vp_cp, which are used to provide the voltage required by each module and respectively control the comparison operational amplifier A1, the current-to-voltage module I2V, the voltage-to-current module V2I, the bias current mirror module bias, and the charge pump cp. Figure 4As shown in (a), the circuit portion that generates the bias voltage Vpsf in the low-dropout linear regulator circuit LDO includes an nmos transistor Mn8, pmos transistors Mp11-Mp12, an operational amplifier A4, and multiple nmos transistors connected in series. The pmos transistor Mp11 and the nmos transistor Mn8 are arranged in series between the voltage Vph and ground. The gate of the nmos transistor Mn8 is connected to the output voltage Vreg of the pmos transistor Mp6 in the bias current mirror module bias. The drain of the pmos transistor Mp11 is connected to the gate of the pmos transistor Mp12. The pmos transistor Mp12 and the multiple series-connected nmos transistors are arranged in series between the voltage Vph and ground, and the drain of the pmos transistor Mp12 is connected to the input terminal of the operational amplifier A4 to output the bias voltage Vpsf through the output terminal of the operational amplifier A4. Figure 4 As shown in (b), the circuit portion for generating the power supply voltage Vp_cp in the low-dropout linear regulator circuit LDO includes a capacitor, an operational amplifier A5, and a plurality of pmos transistors connected in series. The plurality of pmos transistors connected in series and the capacitor are connected in series and arranged in series between the voltage Vph and the ground, and an intermediate node between the capacitor and the plurality of pmos transistors connected in series is connected to the input end of the operational amplifier A5 so as to output the power supply voltage Vp_cp through the output end of the operational amplifier A5.

[0023] The charge pump cp includes two matched current source structures, wherein the current source structures utilize two unity-gain operational amplifiers to convert the frequency and phase discrimination information of the increase signal UP and the decrease signal DN into current information and inject it into the current-to-voltage module I2V.

[0024] The charge pump cp with two pairs of transistors of matching sizes controls the current-to-voltage module I2V while also sending the control voltage signal Vctrl to the voltage-to-current module V2I to control the current that the voltage-to-current module V2I injects into the current-controlled oscillator CCO. Figure 3 and Figure 5As shown, the charge pump cp in this embodiment includes operational amplifiers A2-A3, pmos transistors Mp13-Mp20 and nmos transistors Mn9-Mn16. The input signals of the charge pump cp are the increase signal UP, the inverted increase signal UPb, the decrease signal DN, the inverted decrease signal DN generated after the frequency and phase detection of the phase frequency detector PFD, the reference voltage signal Vref generated by the current-to-voltage module I2V, the bias voltage signal Vb generated after the bias current mirror module bias, and a pair of opposite power-on signals Pon and ponb; the output signal of the charge pump cp includes the control voltage signal Vc trl and Vint, the control voltage signal Vctrl is fed back to the voltage conversion current module V2I to control its pull-down network, which is also the input end of the comparison operational amplifier A1; the control voltage signal Vint is fed back to the gate of the nmos tube Mn20 of the current conversion voltage module I2V to control the generation of the control voltage signal Vctrl; the pull-up network that generates the control voltage signals Vctrl and Vint in the charge pump cp is controlled by the pmos tube Mp13 and the pmos tube Mp17 respectively; the pull-down network that generates the control voltage signal Vctrl and the control voltage signal Vint is controlled by the nmos tube The increase signal UP is input into the gate of the nmos tube Mn10 and the pmos tube Mp19, the inverted increase signal UPb is input into the gate of the nmos tube Mn9 and the pmos tube Mp20, the decrease signal DN is input into the gate of the pmos tube Mp15 and the nmos tube Mn14, the inverted decrease signal DN is input into the gate of the nmos tube Mn13 and the pmos tube Mp16, the reference voltage signal Vref is input into the gate of the nmos tube Mn11 and Mn15 to control the pull-down network of the charge pump cp; the bias voltage signal Vb is input into the pmos tube The gates of Mp14 and Mp18 control the pull-up network of the charge pump cp; an operational amplifier A3 is clamped at the control terminal Vctrl_dump between the control voltage signal Vctrl and the drains of the pmos transistor Mp15 and the nmos transistor Mn9. At the same time, an identical operational amplifier A2 is also clamped at the control terminal Vint_dump between the control voltage signal Vint and the drains of the pmos transistor Mp20 and the nmos transistor Mn14. There are a total of 24 groups of charge pumps cp that generate the control voltage signal Vctrl, and a total of 8 groups of charge pumps cp that generate the control voltage signal Vint.

[0025] The current-to-voltage module I2V is divided into two paths, which also ensures that the transistor sizes are matched with each other. One path generates a reference voltage signal Vref as the input reference voltage of the comparison operational amplifier A1, and the other path is controlled by the control voltage signals Vctrl and Vint generated by the charge pump cp. At the same time, the generated control voltage signal Vctrl is used as another input signal of the comparison operational amplifier A1. The comparison operational amplifier A1 compares the control voltage signal Vctrl and the reference voltage signal Vref, determines the difference between the control voltage signal Vctrl and the reference voltage signal Vref at this time, and then outputs it as the reference voltage Vbias of the bias current mirror module bias. Figure 3 and Figure 5 As shown, the current-to-voltage module I2V in this embodiment includes pmos tubes Mp21-Mp26 and nmos tubes Mn17-Mn25. The input signal is the bias voltage signal Vb generated after the bias current mirror module bias is biased, a pair of opposite power-on signals Pon and ponb, and a control signal Pon_stop. The output signals are the control voltage signal Vctrl and the reference voltage signal Vref; the reference voltage signal Vref is fed back to the charge pump cp to control the pull-down network of the charge pump cp; the control voltage signal Vctrl is fed back to the voltage-to-current module V2I to control its pull-down network, and is also the input end of the comparison operational amplifier A1; the power-on signal Ponb is connected to the gates of the pmos tubes Mp24 and Mp21, the power-on signal Pon is connected to the gates of the nmos tubes Mn17-Mn18, Mn21-Mn22, Mn23-Mn25, and the control signal Pon_stop is connected to the gates of the pmos tubes Mp23 and Mp26.

[0026] like Figure 3 and Figure 5 As shown, the voltage-to-current module V2I in this embodiment includes a pmos transistor MP27 and nmos transistors Mn26-Mn28. The input signals are the amplified signal Vbias output by the comparison operational amplifier A1, the bias signal icas generated after the bias current mirror module bias is biased, and the control voltage signal Vctrl jointly regulated and generated by the current-to-voltage module I2V and the charge pump cp. The output signal is the input signal ivco of the current controlled oscillator CCO, which controls the oscillation frequency of the current controlled oscillator CCO. The amplified signal Vbias is connected to the gate of the pmos transistor MP27 to control the pull-up network that generates the input signal ivco of the current controlled oscillator CCO. The bias signal icas and the control voltage signal Vctrl are connected to the gates of the nmos transistors Mn26 and Mn27, respectively, to jointly control the pull-down network that generates the input signal ivco of the current controlled oscillator CCO.

[0027] In this embodiment, the bias voltages of all modules in the global dynamic self-biased low-noise phase-locked loop circuit are provided by the internal low-dropout linear regulator circuit LDO. At the same time, the reference current of the low-dropout linear regulator circuit LDO is provided by the comparative operational amplifier A1 of the loop, forming a self-biased loop. The self-biased modules in the self-biased loop include the comparative operational amplifier A1, the current-to-voltage module I2V, the voltage-to-current module V2I, the charge pump cp, the low-dropout linear regulator circuit LDO, and the bias current mirror module bias, as shown in FIG. Figure 5 As shown, a feedback loop is formed from the charge pump cp output current (Icp) - comparison operational amplifier A1 (input: Vtrl voltage and Vref voltage, output: Vbias voltage) - bias current mirror module bias (output reference current Icp1, Icp2, Icas, reference voltage Vreg) - charge pump cp, and it also includes two feedback loops, as shown in FIG. Figure 5 As shown by the red and green bold lines in the figure. The bias current mirror module bias is as follows Figure 5The blue line loop in the circuit controls the overall current of the charge pump CP, forming a loop from charge pump CP to charge pump CP, controlling the bias current of the entire circuit and creating a global dynamic self-bias circuit structure. The output voltage of the comparative operational amplifier A1 not only biases the bias current mirror module in the phase-locked loop circuit, but also serves as the bias for the PMOS transistor in the voltage-to-current conversion module V2I. Simultaneously, the NMOS transistor in the voltage-to-current conversion module V2I is biased by the charge pump CP and the control voltage signal Vctrl generated by the current-to-voltage conversion module I2V, forming a loop. While ensuring that the transistor sizes of the two CP modules (CP1 and CP2) match, and that the upper and lower X4 units in the current-to-voltage conversion module I2V, which generate the control voltage signal Vctrl and the reference voltage signal Vref, respectively, also match, it is also necessary to ensure that the transistor sizes of the charge pump CP and the current-to-voltage conversion module I2V match. When the bias current mirror module mirrors the current to the voltage-to-current conversion module V2I, it is also necessary to ensure that the transistor sizes of the bias module and the voltage-to-current conversion module V2I match. All reference currents in the phase-locked loop circuit of this embodiment come from the bias current mirror module bias, and the reference voltage of the bias current mirror module bias comes from the output of the comparison operational amplifier A1, which determines the difference between the input control voltage signal Vctrl and the reference voltage signal Vref. Therefore, the entire circuit module forms a global dynamic self-bias structure. The characteristic of this structure is that when the phase-locked loop is working, when the charge pump cp makes a large adjustment, the current of the charge pump cp and the current-to-voltage module I2V will not produce a large mismatch. At the same time, the current of the bias loop is copied and used together with the current-to-voltage module I2V as the input current of the current-controlled oscillator CCO, which can adjust the frequency of the current-controlled oscillator CCO more quickly. Compared with the traditional bias structure, this circuit architecture has the characteristics of low noise and high speed.

[0028] like Figure 3 As shown, the output end of the comparison operational amplifier A1 in this embodiment is also grounded via a MOS capacitor X501.

[0029] In addition, this embodiment further provides an electronic device, including a device body and a circuit module disposed in the device body, wherein the circuit module includes the global dynamic self-biased low-noise phase-locked loop circuit described above in this embodiment.

[0030] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiment. All technical solutions based on the concept of the present invention are within the scope of protection of the present invention. It should be noted that for those skilled in the art, various improvements and modifications that do not depart from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A global dynamic self-bias low-noise phase-locked loop circuit, characterized in that: The system includes a phase frequency detector, a charge pump cp, a current-to-voltage module I2V, a comparison operational amplifier A1, a bias current mirror module bias, a voltage-to-current module V2I, a current-controlled oscillator CCO, a feedback frequency division circuit, and a low-dropout linear regulator circuit LDO. The phase frequency detector, the charge pump cp, the current-to-voltage module I2V, the comparison operational amplifier A1, the bias current mirror module bias, the voltage-to-current module V2I, and the current-controlled oscillator CCO are sequentially connected to generate an output clock Clk_ou through the current-controlled oscillator CCO. t, the input end of the feedback frequency divider circuit is connected to the output end of the current controlled oscillator CCO to divide the output clock Clk_out to generate the feedback clock Fb_clk required by the phase frequency detector. The bias voltage Vpsf of the charge pump cp, the current-to-voltage module I2V, the bias current mirror module bias, and the voltage-to-current module V2I all come from the low-dropout linear regulator circuit LDO, and the reference voltage Vreg of the low-dropout linear regulator circuit LDO is the same as the reference voltage Vreg of the comparison operational amplifier A1 to form a self-bias loop.

2. The global dynamic self-bias low-noise phase-locked loop circuit according to claim 1, characterized in that: The bias current mirror module bias includes pmos tubes Mp1-Mp10 and nmos tubes Mn1-Mn7, pmos tubes Mp1 and nmos tubes Mn1 are arranged in series between the bias voltage Vpsf and the ground, pmos tubes Mp2, pmos tubes Mp3, and nmos tubes Mn2 are arranged in series between the bias voltage Vpsf and the ground, the gate of pmos tube Mp2 is connected to the frequency selection signal Freq_sel, the gate of pmos tube Mp1 is connected to the amplified signal Vbias output by the comparison operational amplifier A1, the gates of nmos tubes Mn1 and Mn2 are connected to form a current mirror to generate a bias current Vb and output it to the current-to-voltage module I2V; pmos tubes Mp4 and pmos tubes Mp7 are connected in series with one end connected to the bias voltage Vpsf and the other end outputting the bias current Icp1 to the charge pump cp, pmos tubes Mp5 and pmos tubes M p5 is connected in series, one end of which is connected to the bias voltage Vpsf, and the other end outputs the bias current Icp2 to the charge pump cp. The pmos transistor Mp6 and the nmos transistor Mn3 are arranged in series between the bias voltage Vpsf and ground. The pmos transistor Mp9 and the nmos transistor Mn4 are arranged in series between the bias voltage Vpsf and ground. The gates of the nmos transistors Mn3 and Mn4 are connected to form a current mirror to generate a control signal to control the gate of the pmos transistor Mp10. The source of the pmos transistor Mp10 is connected to the bias voltage Vpsf, and the drain generates a bias current icas through multiple parallel units and outputs it to the voltage-to-current conversion module V2I; the parallel units include nmos transistors Mn5, Mn6 and Mn7. The drain of the pmos transistor Mp10 is grounded in sequence through one or more groups of nmos transistors Mn5, Mn6 and Mn7, and the gate of the nmos transistor Mn7 is connected to the power supply voltage Vp_cp.

3. The global dynamic self-bias low-noise phase-locked loop circuit according to claim 2, characterized in that: The circuit portion for generating the bias voltage Vpsf in the low-dropout linear regulator circuit LDO includes an nmos transistor Mn8, pmos transistors Mp11-Mp12, an operational amplifier A4, and multiple nmos transistors connected in series. The pmos transistor Mp11 and the nmos transistor Mn8 are arranged in series between the voltage Vph and ground. The gate of the nmos transistor Mn8 is connected to the output voltage Vreg of the pmos transistor Mp6 in the bias current mirror module bias. The drain of the pmos transistor Mp11 is connected to the gate of the pmos transistor Mp12. The pmos transistor Mp12 and the multiple nmos transistors connected in series are arranged in series between the voltage Vph and ground. The drain of the pmos transistor Mp12 is connected to the input end of the operational amplifier A4 to output the bias voltage Vpsf through the output end of the operational amplifier A4.

4. The global dynamic self-bias low-noise phase-locked loop circuit according to claim 3, characterized in that: The circuit portion for generating the power supply voltage Vp_cp in the low-dropout linear regulator circuit LDO includes a capacitor, an operational amplifier A5, and multiple pmos transistors connected in series. The multiple pmos transistors and the capacitor are connected in series and arranged in series between the voltage Vph and the ground. The intermediate node between the capacitor and the multiple pmos transistors in series is connected to the input end of the operational amplifier A5 to output the power supply voltage Vp_cp through the output end of the operational amplifier A5.

5. The global dynamic self-bias low-noise phase-locked loop circuit according to claim 1, characterized in that: The charge pump cp includes operational amplifiers A2-A3, pmos tubes Mp13-Mp20 and nmos tubes Mn9-Mn16. The input signals of the charge pump cp are the increase signal UP, the inverted increase signal UPb, the decrease signal DN, the inverted decrease signal DN generated by the phase frequency detector PFD after frequency and phase detection, the reference voltage signal Vref generated by the current-to-voltage module I2V, the bias voltage signal Vb generated after the bias current mirror module bias, and a pair of opposite power-on signals Pon and ponb; the output signals of the charge pump cp include the control voltage signal Vctrl and V int, the control voltage signal Vctrl is fed back to the voltage conversion current module V2I to control its pull-down network, which is also the input end of the comparison operational amplifier A1; the control voltage signal Vint is fed back to the gate of the nmos tube Mn20 of the current conversion voltage module I2V to control the generation of the control voltage signal Vctrl; the pull-up network that generates the control voltage signals Vctrl and Vint in the charge pump cp is controlled by the pmos tube Mp13 and the pmos tube Mp17 respectively; the pull-down network that generates the control voltage signal Vctrl and the control voltage signal Vint is controlled by the nmos tube Mn 12 and nmos tube Mn16 control, increase signal UP input into the gate of nmos tube Mn10 and pmos tube Mp19, inverted increase signal UPb input into the gate of nmos tube Mn9 and pmos tube Mp20, decrease signal DN input into the gate of pmos tube Mp15 and nmos tube Mn14, inverted decrease signal DN input into the gate of nmos tube Mn13 and pmos tube Mp16, reference voltage signal Vref input into the gate of nmos tube Mn11 and Mn15, control the pull-down network of charge pump cp; bias voltage signal Vb input into pmos tube Mp The gates of Mp14 and Mp18 control the pull-up network of the charge pump cp; an operational amplifier A3 is clamped at the control terminal Vctrl_dump between the control voltage signal Vctrl and the drains of the pmos transistors Mp15 and the nmos transistors Mn9, and an identical operational amplifier A2 is also clamped at the control terminal Vint_dump between the control voltage signal Vint and the drains of the pmos transistors Mp20 and the nmos transistors Mn14. There are a total of 24 groups of charge pumps cp that generate the control voltage signal Vctrl, and a total of 8 groups of charge pumps cp that generate the control voltage signal Vint.

6. The global dynamic self-bias low-noise phase-locked loop circuit according to claim 1, characterized in that: The current-to-voltage module I2V includes pmos tubes Mp21-Mp26 and nmos tubes Mn17-Mn25. The input signal is the bias voltage signal Vb generated after the bias current mirror module bias is biased, a pair of opposite power-on signals Pon and ponb, and a control signal Pon_stop. The output signals are the control voltage signal Vctrl and the reference voltage signal Vref; the reference voltage signal Vref is fed back to the charge pump cp to control the pull-down network of the charge pump cp; the control voltage signal Vctrl is fed back to the voltage-conversion current module V2I to control its pull-down network, and is also the input end of the comparison operational amplifier A1; the power-on signal Ponb is connected to the gates of the pmos tubes Mp24 and Mp21, the power-on signal Pon is connected to the gates of the nmos tubes Mn17-Mn18, Mn21-Mn22, Mn23-Mn25, and the control signal Pon_stop is connected to the gates of the pmos tubes Mp23 and Mp26.

7. The global dynamic self-bias low-noise phase-locked loop circuit according to claim 1, characterized in that: The voltage-to-current module V2I includes a pmos transistor Mp27 and nmos transistors Mn26-Mn28. Its input signals are the amplified signal Vbias output by the comparison operational amplifier A1, the bias signal icas generated after the bias current mirror module bias is biased, and the control voltage signal Vctrl jointly regulated and generated by the current-to-voltage module I2V and the CP module. The output signal is the current-controlled oscillator CCO input signal ivco, which controls the oscillation frequency of the current-controlled oscillator CCO. The amplified signal Vbias is connected to the gate of the pmos transistor Mp27 to control the pull-up network that generates the input signal ivco of the current-controlled oscillator CCO. The bias signal icas and the control voltage signal Vctrl are connected to the gates of the nmos transistors Mn26 and Mn27, respectively, to jointly control the pull-down network that generates the input signal ivco of the current-controlled oscillator CCO.

8. The global dynamic self-bias low-noise phase-locked loop circuit according to claim 1, characterized in that: The output end of the comparison operational amplifier A1 is also grounded via a MOS capacitor X501.

9. An electronic device comprising a device body and a circuit module disposed in the device body, characterized in that: The circuit module includes the global dynamic self-bias low-noise phase-locked loop circuit according to any one of claims 1 to 8.

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