Test data high-speed reliable acquisition equipment and control method

Abstract

According to the test data high-speed reliable acquisition equipment and the control method, through the design based on the USB cache, rapid and reliable data transmission can be achieved, potential safety hazards and bandwidth limitation in network transmission are avoided, and meanwhile the problem of compatibility of physical media and the problem of insufficient storage capacity are solved; through the built-in cache module, the storage efficiency and the transmission speed of data can be improved, stable data exchange can be ensured in various environments, the safety and the integrity of the data are ensured, and particularly, the data are ensured not to be lost or damaged easily in a severe environment.

Description

Technical Field

[0001] The present invention relates to the field of computers, and in particular to a high-speed and reliable test data acquisition device and a control method. Background Art

[0002] With the rapid development of information technology, data security and efficient transmission are becoming increasingly important across various fields, especially when it comes to collecting test data in harsh environments such as field operations and industrial control. In these challenging environments, test equipment often faces challenges such as extreme temperatures, vibration, humidity, and electromagnetic interference, placing higher demands on the storage and transmission of test data. Ruggedized laptops, due to their durability and high performance, are widely used in these fields.

[0003] However, in these extreme environments, traditional storage and transmission methods often face numerous challenges, including unstable data transmission speeds, susceptibility of devices to external interference, fragility of storage media, and data security. Ensuring the reliable transmission and storage of test data is particularly pressing when cross-device data exchange is required. While the USB interface is a common solution due to its high transmission speed and wide compatibility, its performance under high loads and harsh environments still has certain limitations. In particular, the transmission process is susceptible to interference from external factors, resulting in data loss or errors.

[0004] Therefore, how to provide a computer-specific data acquisition device is a problem that those skilled in the art urgently need to solve. Summary of the Invention

[0005] The present invention aims to provide a high-speed and reliable test data acquisition device and a control method that overcome the above problems or at least partially solve the above problems.

[0006] To achieve the above object, the technical solution of the present invention is specifically implemented as follows:

[0007] One aspect of the present invention provides a high-speed and reliable test data acquisition device, comprising:

[0008] Internal docking computer interface module, used to connect to the source computer and provide a physical interface for data transmission;

[0009] External USB interface module, used to connect to the target computer and transfer data via the USB interface;

[0010] Built-in cache module, used to store files or data temporarily during data transmission, using MLC storage granularity;

[0011] a control unit, configured to manage data read and write operations, including reading data from the source computer, writing data into the built-in cache module, and writing data from the built-in cache module into the target computer;

[0012] The USB switching module is used to switch the connection interface of the USB cache and switch the data transmission path between the source computer and the target computer.

[0013] Optionally, the high-speed and reliable test data acquisition device of the present invention further includes:

[0014] The data transmission management module is used to monitor status and handle errors during data transmission.

[0015] Optionally, the control unit manages data read and write operations in the following manner:

[0016] When the device is started, the control unit identifies and initializes the built-in cache module and sets the FAT32 format of the built-in cache module;

[0017] The control unit transmits the data to be transmitted in the source computer to the built-in cache module through the internal docking computer interface module, and the data is temporarily stored in a designated storage area of ​​the built-in cache module, wherein the built-in cache module adopts MLC storage particles for storage;

[0018] The control unit schedules the built-in cache module to read and write data according to the data transmission requirements;

[0019] When writing data into the target computer, the control unit adjusts the speed according to the read rate of the target computer interface and the writing capability of the built-in cache module.

[0020] Optionally, the control unit manages data read and write operations in the following manner:

[0021] The control unit receives data transmitted from the source computer to the built-in cache module and verifies the received data;

[0022] During data transmission, the control unit performs verification by checking the header information and the check code of the data packet;

[0023] The control unit determines whether the data are consistent based on the verification result. If they are consistent, the control unit allows the data to continue to be stored in the built-in cache module; if they are inconsistent, the control unit requests the data to be retransmitted.

[0024] The control unit performs a data consistency check again before writing the data into the target computer;

[0025] During the process of writing to the target computer, the control unit performs dynamic adjustments according to the data transmission situation, controls the data flow rate according to the writing speed of the target computer, and adopts a corresponding buffer management strategy.

[0026] Optionally, the control unit performs verification in the following manner: using a cyclic redundancy check algorithm for verification, and the verification formula is:

[0027]

[0028] Among them, D i is the i-th bit of the data packet, W i is the weight, CRC init is the initial check value, and N is the length of the data packet.

[0029] Optionally, the control unit manages data read and write operations in the following manner:

[0030] Before data transmission begins, the control unit selects a USB interface connection mode according to the connection status between the source computer and the target computer, and switches the USB cache interface between the source computer and the target computer through the USB switch;

[0031] When reading data from the source computer, the control unit connects the USB interface of the source computer to the built-in cache module through the USB switch, and the data is read from the source computer through the interface and stored in the built-in cache module;

[0032] When data needs to be written from the built-in cache module to the target computer, the control unit connects the USB interface of the target computer to the built-in cache module via the USB switch, and the data is written from the built-in cache module to the target computer via the interface;

[0033] The control unit dynamically adjusts the data transmission path by controlling the USB switch, monitors the status of the USB switch according to the progress of data transmission, and switches the interface when the switching conditions are met.

[0034] Optionally, the USB switch uses an ultra-high-speed analog switch chip CH482X, which supports the USB 3.1 Gen 2 interface, wherein the signal switching formula is:

[0035] Signal out =MUX(Signal in1 ,Signal in2 )

[0036] Among them, Signal in1and Signal in2 are two differential input signals, MUX(·) is the switching function of the analog switch, Signal out is the output signal.

[0037] Optionally, the control unit manages data read and write operations in the following manner:

[0038] After receiving the data read from the source computer, the control unit stores the data into the built-in cache module in a process that complies with the alignment requirements of the data blocks;

[0039] Before writing to the target computer, the control unit uses a flow control algorithm to adjust the data flow rate according to the difference between the USB interface transmission rate of the target computer and the write rate of the built-in cache module;

[0040] The control unit processes the data packets in segments, each data packet having a size of P bytes;

[0041] During the writing process, the control unit verifies the data using a write verification algorithm;

[0042] After each data packet is written to the target computer, the control unit verifies the consistency of the written data with the original data in the built-in cache module. If they are consistent, the control unit continues to write the next data packet; if they are inconsistent, the control unit retransmits the data packet.

[0043] After all the data are written into the target computer, the control unit performs an integrity check and confirms whether the data transmission is completed according to a write success flag.

[0044] Optionally, the verification formula of the write verification algorithm is:

[0045]

[0046] Among them, D i is the i-th byte in the written data packet, W i is the weight, k is the number of check bits, and N is the byte length of the data packet.

[0047] Another aspect of the present invention provides a method for high-speed and reliable acquisition and control of test data, which uses the above-mentioned high-speed and reliable acquisition device for test data to perform acquisition and control.

[0048] It can be seen that the high-speed and reliable test data acquisition equipment and control method provided by the present invention provide an efficient, safe and easy-to-use data acquisition equipment. Through the design based on USB cache, fast and reliable data transmission can be achieved, avoiding security risks and bandwidth limitations in network transmission, and solving the compatibility problems of physical media and insufficient storage capacity problems. Through the built-in cache module, the present invention can improve the storage efficiency and transmission speed of data, ensure stable data exchange in various environments, and ensure the security and integrity of data, especially in harsh environments, to ensure that data is not easily lost or damaged. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0050] Figure 1 A schematic diagram of the structure of a high-speed and reliable test data acquisition device provided by an embodiment of the present invention;

[0051] Figure 2 A flowchart of the configuration of a high-speed and reliable test data acquisition device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0052] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0053] Figure 1 The schematic diagram of the structure of the test data high-speed and reliable acquisition device provided by the embodiment of the present invention is shown in FIG. Figure 1 The embodiment of the present invention provides a high-speed and reliable test data acquisition device, comprising:

[0054] Internal docking computer interface module, used to connect to the source computer and provide a physical interface for data transmission;

[0055] External USB interface module, used to connect to the target computer and transfer data via the USB interface;

[0056] Built-in cache module, used to store files or data temporarily during data transmission, using MLC storage granularity;

[0057] A control unit, configured to manage data read and write operations, including reading data from a source computer, writing data into a built-in cache module, and writing data from the built-in cache module into a target computer;

[0058] The USB switch module is used to switch the connection interface of the USB cache and switch the data transmission path between the source computer and the target computer.

[0059] As an optional implementation of the embodiment of the present invention, the high-speed and reliable test data acquisition device further includes: a data transmission management module for performing status monitoring and error processing during the data transmission process.

[0060] Specifically, the internal docking computer interface module is used to connect and dock with a source computer or a target computer and provide a physical interface for data transmission. The interface is usually a USB interface for connecting to a computer.

[0061] An external USB interface module, used for connecting to a source computer and a target computer and transmitting data via a USB interface;

[0062] Built-in cache module, using FAT32 format, with 256GB storage space and MLC storage granularity, used to store data read from the source computer;

[0063] A control unit, configured to control the reading, writing, and management of data, including reading data from a source computer, writing data into a built-in cache module, and writing data from the built-in cache module into a target computer;

[0064] The USB switch module is used to switch the connection interface of the USB cache to realize the data collection function. Through the USB switch, the data transmission channel can be quickly switched between different computers.

[0065] When configuring, you can refer to Figure 2 The method shown is used to configure the equipment for high-speed and reliable data acquisition of test data:

[0066] S1, providing an internal docking computer interface for connecting to the source computer;

[0067] S2, providing an external USB interface for connecting to the target computer;

[0068] S3. Set up a built-in cache module with FAT32 format, 256GB storage space, and MLC storage granularity to store data read from the source computer;

[0069] S4. Configure a control unit to control data reading, writing and management

[0070] S5. Configuring a USB switch to switch the connection interface of the USB cache and switch the data transmission path between the source computer and the target computer;

[0071] S6. Read data from the source computer and store the data in the built-in cache module;

[0072] S7, writing the data in the cache module into the target computer;

[0073] S8. Manage data read and write operations through the control unit.

[0074] As an optional implementation of the embodiment of the present invention, the control unit manages the read and write operations of data in the following manner:

[0075] When the device starts, the control unit identifies and initializes the built-in cache module and sets the FAT32 format of the built-in cache module;

[0076] The control unit transmits the data to be transmitted from the source computer to the built-in cache module through the internal docking computer interface module. The data is temporarily stored in the designated storage area of ​​the built-in cache module, wherein the built-in cache module uses MLC storage particles for storage;

[0077] The control unit schedules the built-in cache module to read and write data according to the data transmission requirements;

[0078] When data is written into the target computer, the control unit adjusts the speed according to the read rate of the target computer interface and the write capability of the built-in cache module.

[0079] During specific implementation, the present invention performs the following operations:

[0080] When the device starts, the control unit identifies and initializes the built-in cache module and sets the FAT32 format of the built-in cache module;

[0081] The data to be transferred in the source computer is transferred to the built-in cache module via the USB interface, and the data is temporarily stored in the designated storage area of ​​the built-in cache module;

[0082] The MLC storage particles used in the built-in cache module have write durability;

[0083] The control unit dispatches the built-in cache module to read and write data according to the data transmission requirements, and no data loss occurs when writing to the target computer;

[0084] When data is written into the target computer, the control unit adjusts the speed according to the read rate of the target computer interface and the write capability of the built-in cache module.

[0085] As an optional implementation of the embodiment of the present invention, the control unit manages the read and write operations of data in the following manner:

[0086] The control unit receives data transmitted from the source computer to the built-in cache module and verifies the received data;

[0087] During data transmission, the control unit verifies the data by checking the header information and the check code of the data packet;

[0088] The control unit determines whether the data is consistent based on the verification result. If it is consistent, the data is allowed to continue to be stored in the built-in cache module; if it is inconsistent, a retransmission request is made for the data;

[0089] The control unit performs data consistency check again before writing to the target computer;

[0090] During the writing process to the target computer, the control unit makes dynamic adjustments according to the data transmission situation, controls the data flow rate according to the writing speed of the target computer, and adopts the corresponding buffer management strategy.

[0091] The control unit is verified in the following way: a cyclic redundancy check algorithm is used for verification, and the verification formula is:

[0092]

[0093] Among them, D i is the i-th bit of the data packet, W i is the weight, CRC init is the initial check value, and N is the length of the data packet.

[0094] During specific implementation, the present invention performs the following operations:

[0095] The control unit receives data transmitted from the source computer to the built-in cache module and verifies the received data using a cyclic redundancy check (CRC);

[0096] During data transmission, the control unit checks the packet header information and check code using a cyclic redundancy check algorithm. The check formula is:

[0097]

[0098] Among them, D i is the i-th bit of the data packet, W i is the weight, CRC init is the initial check value, N is the length of the data packet;

[0099] The control unit determines whether the data is consistent based on the verification result. If it is consistent, the data is allowed to continue to be stored in the built-in cache module; if it is inconsistent, a retransmission request is made for the data;

[0100] The control unit performs a data consistency check again before writing the data into the target computer;

[0101] During the process of writing to the target computer, the control unit makes dynamic adjustments according to the data transmission situation, controls the data flow rate according to the writing speed of the target computer, and adopts an appropriate buffer management strategy.

[0102] As an optional implementation of the embodiment of the present invention, the control unit manages the read and write operations of data in the following manner:

[0103] Before data transmission begins, the control unit selects a USB interface connection mode according to the connection status of the source computer and the target computer, and switches the USB cache interface between the source computer and the target computer through the USB switch;

[0104] When reading data from the source computer, the control unit connects the USB interface of the source computer to the built-in cache module through the USB switch, and the data is read from the source computer through the interface and stored in the built-in cache module;

[0105] When data needs to be written from the built-in cache module to the target computer, the control unit connects the USB interface of the target computer to the built-in cache module via the USB switch, and the data is written from the built-in cache module to the target computer via the interface;

[0106] The control unit dynamically adjusts the data transmission path by controlling the USB switch, monitors the status of the USB switch according to the progress of data transmission, and switches the interface when the switching conditions are met.

[0107] The USB switch uses the ultra-high-speed analog switch chip CH482X, which supports the USB3.1 Gen2 interface. The signal switching formula is:

[0108] Signal out =MUX(Signal in1 ,Signal in2 )

[0109] Among them, Signal in1 and Signal in2 are two differential input signals, MUX(·) is the switching function of the analog switch, Signal out is the output signal.

[0110] During specific implementation, the present invention performs the following operations:

[0111] Before data transmission begins, the control unit selects a suitable USB interface connection mode according to the connection status of the source computer and the target computer, and switches the USB cache interface between the source computer and the target computer through the USB switch;

[0112] When reading data from the source computer, the control unit connects the USB interface of the source computer to the built-in cache module through the USB switch, and the data is read from the source computer through the interface and stored in the cache module;

[0113] When data needs to be written from the built-in cache module to the target computer, the control unit connects the USB interface of the target computer to the built-in cache module via the USB switch, and the data is written from the built-in cache module to the target computer via the interface;

[0114] The USB switch uses the ultra-high-speed analog switch chip CH482X, which supports the USB3.1 Gen2 interface. The signal switching formula is:

[0115] Signal out =MUX(Signal i11 ,Signal in2 )

[0116] Among them, Signal in1 and Signal in2 are two differential input signals, MUX(·) is the switching function of the analog switch, Signal out is the output signal;

[0117] The control unit dynamically adjusts the data transmission path by controlling the USB switch, ensuring seamless connection and maintaining the continuity of data flow;

[0118] The control unit monitors the status of the switch according to the progress of data transmission and switches the interface when necessary.

[0119] As an optional implementation of the embodiment of the present invention, the control unit manages the read and write operations of data in the following manner:

[0120] After receiving the data read from the source computer, the control unit stores the data into the built-in cache module in a process that complies with the alignment requirements of the data blocks;

[0121] Before writing to the target computer, the control unit uses a flow control algorithm to adjust the data flow rate according to the difference between the USB interface transmission rate of the target computer and the write rate of the built-in cache module;

[0122] The control unit processes the data packets by segmenting them, and each data packet has a size of P bytes;

[0123] During the writing process, the control unit verifies the data using a write verification algorithm;

[0124] After each data packet is written to the target computer, the control unit verifies the consistency of the written data with the original data in the built-in cache module. If they are consistent, the writing of the next data packet will continue; if they are inconsistent, the data packet will be retransmitted;

[0125] After all the data is written to the target computer, the control unit performs an integrity check and confirms whether the data transfer is completed based on the write success flag.

[0126] Among them, the verification formula of the write verification algorithm is:

[0127]

[0128] Among them, D i is the i-th byte in the written data packet, W i is the weight, k is the number of check bits, and N is the byte length of the data packet.

[0129] During specific implementation, the present invention performs the following operations:

[0130] After receiving the data read from the source computer, the control unit stores the data in the built-in cache module. The data storage format is FAT32 and stored in the designated cache area. The storage process complies with the alignment requirements of the data blocks.

[0131] Before writing to the target computer, the control unit uses a flow control algorithm to adjust the data flow rate based on the difference between the USB interface transmission rate of the target computer and the write rate of the built-in cache module, so that the write rate does not exceed 100MB / s;

[0132] The control unit processes the data packets by segmenting them, and each data packet has a size of P bytes;

[0133] During the writing process, the control unit uses the write verification algorithm to verify the data. The verification formula used is:

[0134]

[0135] Among them, D i is the i-th byte in the written data packet, W i is the weight, k is the number of check bits, and N is the byte length of the data packet;

[0136] After each data packet is written to the target computer, the control unit verifies the consistency of the written data with the original data in the cache. If they are consistent, the writing of the next data packet will continue; if they are inconsistent, the data packet will be retransmitted;

[0137] After all the data is written to the target computer, the control unit performs a final integrity check and confirms whether the data transfer is complete based on the write success flag.

[0138] A specific embodiment of the present invention is provided below, but the present invention is not limited thereto:

[0139] In order to verify the feasibility of the present invention in practice, the present invention was applied to a large-scale field test process to address the computer data transmission requirements in this environment, especially the challenges in terms of test data security, transmission speed, and equipment compatibility. In this scenario, the computer equipment in the test center needs to quickly and accurately transmit a large amount of test data, involving multiple test equipment. Due to the complexity and interference of the communication network environment, traditional network transmission methods often face problems such as data leakage, slow speed, and incompatibility, which affect the smooth progress of the task.

[0140] In this scenario, the present invention is deployed between multiple test devices to achieve efficient and secure data transfer. The test device computer is connected to the target computer via a USB interface, while a built-in 256GB USB cache module is used to temporarily store and exchange test data. Test data is read from the test device computer, temporarily stored in the USB cache module, and then managed by the control unit and written to the target computer, ensuring data integrity and consistency.

[0141] To meet the demand for fast data transfer in experimental systems, the USB cache device of the present invention enables data transmission directly through the USB interface without relying on a network, avoiding communication interruptions caused by network failures or interference. Using a USB switch, the system can quickly switch data sources between different computers, improving the efficiency and security of data exchange.

[0142] According to field test records, when using traditional network transmission methods, the average test data transmission speed was 50MB / s, and the entire task took 2 hours and 30 minutes. In contrast, after using the USB cache device of the present invention, the test data transmission speed was increased to 200MB / s, and the total transmission time was shortened to 1 hour. The specific data table is as follows:

[0143] Table 1 Comparison of test data transmission methods

[0144]

[0145]

[0146] As shown in Table 1, the average speed of traditional test data transmission is 50MB / s, and the entire task takes 2 hours and 30 minutes. In contrast, using the USB caching device of the present invention increases the test data transmission speed to 200MB / s, and the total transmission time is shortened to 1 hour. Due to network interference or packet loss, traditional test data transmission may not be fully transmitted, resulting in inconsistent transmission content. USB caching technology eliminates packet loss during transmission, ensuring the integrity of test data. Traditional test data transmission is easily interrupted in unstable network conditions (such as signal interference, bandwidth fluctuations, etc.), resulting in test data loss or transmission failure. The USB caching transmission method of the present invention can maintain stable operation and avoid interruptions even in complex environments, such as those with severe electromagnetic interference. Traditional network transmission methods require complex configuration and adjustment between different systems, especially network protocol compatibility between different operating systems, which can cause connection problems. However, the USB caching transmission method of the present invention has a highly compatible USB interface, enabling plug-and-play operation and eliminating the need for complex configuration between systems. Traditional network transmission methods suffer from poor network transmission quality in complex environments (such as areas with strong electromagnetic interference) and are prone to data loss or delays. The USB cache transmission method of the present invention can transmit data stably and without delay in complex environments, demonstrating greater adaptability. Traditional network transmission methods require waiting for a stable network connection and take a long time to start. The USB cache transmission method of the present invention allows devices to be plug-and-play, requiring no network connection, and be immediately operational.

[0147] Comparisons show that the USB cache transmission method of the present invention significantly outperforms traditional network transmission methods in every respect. The technical solution of the present invention offers significant improvements in transmission rate, data integrity, system compatibility, and adaptability. In particular, its stability and rapid data transmission capabilities in harsh environments give the present invention significant advantages in practical applications, meeting the demands for greater efficiency and security.

[0148] Thus, the high-speed, reliable test data acquisition device provided by the embodiments of the present invention can effectively address the security, speed, and compatibility issues that exist in the prior art test data transmission process. By optimizing key steps in the data transmission process through the built-in USB buffer, data transmission speed and stability are significantly improved while ensuring data security.

[0149] The present invention has the following beneficial effects:

[0150] First, the introduction of the USB cache module effectively avoids interference, attacks, and data leaks that can occur with traditional network transmission. By replacing the physical medium and applying encryption, data can be transferred quickly, securely, and reliably between the source and destination computers, reducing potential risks associated with interference and network security vulnerabilities.

[0151] Secondly, the present invention addresses the bandwidth bottlenecks and storage capacity limitations of traditional storage media during transmission by integrating a 256GB USB cache module. Even with large amounts of data, the cache module provides ample storage space, ensuring efficient data storage and rapid access, thereby improving overall data exchange efficiency. Compared to traditional physical media, the USB cache module's efficient read and write speeds significantly reduce transmission latency, ensuring fast and accurate data transfer.

[0152] Finally, the use of a USB switch not only simplifies interface selection during data transmission but also improves device compatibility, enabling smooth operation across diverse systems and environments, avoiding the compatibility issues that traditional devices may encounter during cross-platform transmission. Overall, this invention enhances the adaptability and reliability of devices in complex environments while ensuring data transmission security. This significantly improves the efficiency and stability of experimental data transmission, meeting the demand for efficient and secure data transmission in the field and industrial control fields.

[0153] The present invention also provides a method for high-speed and reliable acquisition and control of test data, which uses the above-mentioned high-speed and reliable acquisition equipment for test data to perform acquisition and control.

[0154] Thus, the high-speed, reliable test data acquisition and control method provided by the embodiments of the present invention effectively addresses the security, speed, and compatibility issues that exist in the prior art test data transmission process. By optimizing key steps in the data transmission process through the built-in USB buffer, data transmission speed and stability are significantly improved while ensuring data security.

[0155] The above are merely embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should all be included within the scope of the claims of the present application.

Claims

1. A high-speed and reliable test data acquisition device, characterized in that: include: Internal docking computer interface module, used to connect to the source computer and provide a physical interface for data transmission; External USB interface module, used to connect to the target computer and transfer data via the USB interface; Built-in cache module, used to store files or data temporarily during data transmission, using MLC storage granularity; a control unit, configured to manage data read and write operations, including reading data from the source computer, writing data into the built-in cache module, and writing data from the built-in cache module into the target computer; The USB switching module is used to switch the connection interface of the USB cache and switch the data transmission path between the source computer and the target computer.

2. The high-speed and reliable test data acquisition device according to claim 1, characterized in that: Also includes: The data transmission management module is used to monitor status and handle errors during data transmission.

3. The high-speed and reliable test data acquisition device according to claim 2, characterized in that: The control unit manages the reading and writing of data in the following manner: When the device is started, the control unit identifies and initializes the built-in cache module and sets the FAT32 format of the built-in cache module; The control unit transmits the data to be transmitted in the source computer to the built-in cache module through the internal docking computer interface module, and the data is temporarily stored in a designated storage area of ​​the built-in cache module, wherein the built-in cache module adopts MLC storage particles for storage; The control unit schedules the built-in cache module to read and write data according to the data transmission requirements; When writing data into the target computer, the control unit adjusts the speed according to the read rate of the target computer interface and the writing capability of the built-in cache module.

4. The high-speed and reliable test data acquisition device according to claim 2, characterized in that: The control unit manages the reading and writing of data in the following manner: The control unit receives data transmitted from the source computer to the built-in cache module and verifies the received data; During data transmission, the control unit performs verification by checking the header information and the check code of the data packet; The control unit determines whether the data are consistent according to the verification result, and if they are consistent, allows the data to continue to be stored in the built-in cache module; If they are inconsistent, a retransmission request is made for the data; The control unit performs a data consistency check again before writing the data into the target computer; During the process of writing to the target computer, the control unit performs dynamic adjustments according to the data transmission situation, controls the data flow rate according to the writing speed of the target computer, and adopts a corresponding buffer management strategy.

5. The high-speed and reliable test data acquisition device according to claim 4, characterized in that: The control unit is verified in the following manner: a cyclic redundancy check algorithm is used for verification, and the verification formula is: Among them, D i is the i-th bit of the data packet, W i is the weight, CRC init is the initial check value, and N is the length of the data packet.

6. The high-speed and reliable test data acquisition device according to claim 2, characterized in that: The control unit manages the reading and writing of data in the following manner: Before data transmission begins, the control unit selects a USB interface connection mode according to the connection status between the source computer and the target computer, and switches the USB cache interface between the source computer and the target computer through the USB switch; When reading data from the source computer, the control unit connects the USB interface of the source computer to the built-in cache module through the USB switch, and the data is read from the source computer through the interface and stored in the built-in cache module; When data needs to be written from the built-in cache module to the target computer, the control unit connects the USB interface of the target computer to the built-in cache module via the USB switch, and the data is written from the built-in cache module to the target computer via the interface; The control unit dynamically adjusts the data transmission path by controlling the USB switch, monitors the status of the USB switch according to the progress of data transmission, and switches the interface when the switching conditions are met.

7. The high-speed and reliable test data acquisition device according to claim 6, characterized in that: The USB switch uses the ultra-high-speed analog switch chip CH482X, which supports the USB 3.1 Gen 2 interface. The signal switching formula is: Signal out =MUX(Signal in1 ,Signal in2 ) Among them, Signal in1 and Signal in2 are two differential input signals, MUX(·) is the switching function of the analog switch, Signal out is the output signal.

8. The high-speed and reliable test data acquisition device according to claim 2, characterized in that: The control unit manages the reading and writing of data in the following manner: After receiving the data read from the source computer, the control unit stores the data into the built-in cache module in a process that complies with the alignment requirements of the data blocks; Before writing to the target computer, the control unit uses a flow control algorithm to adjust the data flow rate according to the difference between the USB interface transmission rate of the target computer and the write rate of the built-in cache module; The control unit processes the data packets in segments, each data packet having a size of P bytes; During the writing process, the control unit verifies the data using a write verification algorithm; After each data packet is written to the target computer, the control unit verifies the consistency of the written data with the original data in the built-in cache module. If they are consistent, the control unit continues to write the next data packet; if they are inconsistent, the control unit retransmits the data packet. After all the data are written into the target computer, the control unit performs an integrity check and confirms whether the data transmission is completed according to a write success flag.

9. The high-speed and reliable test data acquisition device according to claim 8, characterized in that: The verification formula of the write verification algorithm is: Among them, D i is the i-th byte in the written data packet, W i is the weight, k is the number of check bits, and N is the byte length of the data packet.

10. A high-speed and reliable test data acquisition and control method, characterized in that: The high-speed and reliable test data acquisition device according to any one of claims 1 to 9 is used for acquisition control.

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