Electronic device performing quantization using multiplier and accumulator and control method thereof

Abstract

An electronic device is provided. The electronic device includes a processor including a memory, a multiplier, and an accumulator. The processor obtains multiplicand data according to a convolution operation between an activation value and a weight value by using the multiplier and the accumulator, and stores the multiplicand data in the memory, based on a first scaling factor for quantizing the activation value, a second scaling factor for quantizing the weight value, and a third scaling factor for quantizing the multiplicand data, obtaining multiplier data and a displacement factor, and storing the multiplier data and the displacement factor in the memory, and using the multiplier to obtain an integer quantizing the multiplicand data from a multiplication operation between the multiplicand data, the multiplier data, and the displacement factor stored in the memory.

Description

Technical Field

[0001] The present disclosure relates to an electronic device and a control method thereof, and more particularly, to an electronic device and a control method thereof that performs quantization by using a multiplier and an accumulator. Background Art

[0002] For conventional artificial intelligence models that perform quantization, there is a problem in that a multiplier dedicated to quantization must be used that can perform operations on relatively larger bits than multipliers used in multiplication processing (e.g., multipliers of multiplier-accumulator (MAC)).

[0003] A multiplier dedicated to quantization capable of performing large-bit operations has a problem of increasing the size of a processor (eg, a chip) included in an electronic device.

[0004] For example, in the case of a conventional electronic device, if a multiplication-accumulation operation (ie, 32 (2 5 ) convolution operation between 8-bit input feature maps and 8-bit weights), the multiplier of the multiplier-accumulator (MAC) needs to perform an 8-bit × 8-bit multiplication operation, and if the result of the accumulator performing the accumulation operation is 21 bits (8 bits + 8 bits + 5 bits), the multiplier dedicated to quantization needs to perform a 21-bit × 32-bit multiplication operation, so there is a problem that the multiplier dedicated to quantization requires a larger area than the multiplier of the multiplier-accumulator. Summary of the Invention

[0005] Technical Solution According to an embodiment of the present disclosure, an electronic device for achieving the above-mentioned purpose includes a memory and a processor including a multiplier and an accumulator, wherein the processor is configured to obtain multiplicand data according to a convolution operation between an activation value and a weight value by using the multiplier and the accumulator, and store the multiplicand data in the memory, and obtain multiplier data and a displacement factor based on a first scaling factor for quantizing the activation value, a second scaling factor for quantizing the weight value, and a third scaling factor for quantizing the multiplicand data, and store the multiplier data and the displacement factor in the memory, and obtain an integer of the quantized multiplicand data according to a multiplication operation between the multiplicand data, the multiplier data, and the displacement factor stored in the memory by using the multiplier.

[0006] According to an embodiment of the present disclosure, a control method for an electronic device including a multiplier, an accumulator and a memory includes: obtaining multiplicand data according to a convolution operation between an activation value and a weight value by using a multiplier and an accumulator, and storing the multiplicand data in a memory; obtaining multiplier data and a displacement factor based on a first scaling factor for quantizing the activation value, a second scaling factor for quantizing the weight value and a third scaling factor for quantizing the multiplicand data, and storing the multiplier data and the displacement factor in the memory; and obtaining an integer of the quantized multiplicand data according to a multiplication operation between the multiplicand data, the multiplier data and the displacement factor by using a multiplier.

[0007] In a computer-readable recording medium including a program for executing a control method for an electronic device including a multiplier, an accumulator, and a memory according to an embodiment of the present disclosure, the control method for the electronic device includes: obtaining multiplicand data according to a convolution operation between an activation value and a weight value by using a multiplier and an accumulator, and storing the multiplicand data in a memory, and obtaining multiplier data and a displacement factor based on a first scaling factor for quantizing the activation value, a second scaling factor for quantizing the weight value, and a third scaling factor for quantizing the multiplicand data, and storing the multiplier data and the displacement factor in the memory, and obtaining an integer of the quantized multiplicand data according to a multiplication operation between the multiplicand data, the multiplier data, and the displacement factor by using a multiplier. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a diagram for illustrating an electronic device that performs quantization according to a conventional technique; Figure 2 is a block diagram for illustrating a configuration of an electronic device according to an embodiment of the present disclosure; Figure 3 is a detailed block diagram for illustrating a configuration of an electronic device according to an embodiment of the present disclosure; Figure 4 is a diagram for illustrating multiplicand data and multiplier data according to an embodiment of the present disclosure; Figure 5 is a diagram for illustrating multiplicand data and multiplier data divided in units of digits corresponding to a first bit according to an embodiment of the present disclosure; Figure 6 is a diagram for illustrating a multiplication operation between multiplicand data and multiplier data according to an embodiment of the present disclosure; Figure 7 is a diagram for illustrating a plurality of combinations according to a multiplication operation according to an embodiment of the present disclosure; Figure 8 is a diagram for illustrating a plurality of groups for grouping a plurality of combinations according to an embodiment of the present disclosure; Figure 9 is a diagram for illustrating an accumulation operation among a plurality of groups according to an embodiment of the present disclosure; Figure 10 is a diagram for illustrating conditions for ending an operation according to an embodiment of the present disclosure; Figure 11 is a diagram for illustrating conditions for ending an operation according to an embodiment of the present disclosure; Figure 12 is a diagram for illustrating 24-bit multiplicand data and multiplier data according to an embodiment of the present disclosure; Figure 13 is a diagram for illustrating an operation order of each of a plurality of combinations of multiplication operations according to an embodiment of the present disclosure; Figure 14 is a diagram for illustrating an operation result of each of a plurality of combinations according to an embodiment of the present disclosure; Figure 15 is a diagram for illustrating an operation result according to information on the number of iterations according to an embodiment of the present disclosure; and Figure 16 is a diagram for illustrating a method of acquiring an integer of quantized multiplicand data according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0009] First, terms used in this specification will be briefly described, and then the present disclosure will be described in detail.

[0010] As the terms used in the embodiments of the present disclosure, taking into account the functions described in the present disclosure, general terms that are currently widely used are selected as much as possible. However, the terms may change according to the intentions of those skilled in the art working in the relevant field, previous court decisions, or the emergence of new technologies. In addition, in specific cases, there may be terms specified by the applicant himself, and in this case, the meaning of the terms will be described in detail in the relevant description of the present disclosure. Therefore, the terms used in the present disclosure should be defined based on the meaning of the terms and the overall content of the present disclosure, rather than just based on the names of the terms.

[0011] In addition, various modifications may be made to the embodiments of the present disclosure, and various types of embodiments may exist. Therefore, specific embodiments will be shown in the drawings, and the embodiments will be described in detail in the specific description. However, it should be noted that the various embodiments are not intended to limit the scope of the present disclosure to specific embodiments, but rather they should be interpreted as including all modifications, equivalents, or alternative forms of the embodiments included in the ideas and technical scope disclosed herein. At the same time, in the case where it is determined that a detailed explanation of the relevant known technology when describing the embodiments may unnecessarily confuse the main purpose of the present disclosure, the detailed explanation will be omitted.

[0012] In addition, terms such as "first," "second," etc. may be used to describe various components, but the components are not intended to be limited by the terms. These terms are only used to distinguish one component from another.

[0013] In addition, unless clearly defined differently in the context, singular expressions include plural expressions. In addition, in the present disclosure, terms such as "including" and "consisting of" should be interpreted as specifying the presence of the features, quantities, steps, operations, elements, components, or combinations thereof described in the specification, rather than excluding in advance the presence or possibility of adding one or more other features, quantities, steps, operations, elements, components, or combinations thereof.

[0014] In addition, in the present disclosure, a "module" or "component" performs at least one function or operation and can be implemented as hardware or software, or as a combination of hardware and software. In addition, in addition to the "module" or "part" that needs to be implemented as specific hardware, multiple "modules" or "components" can be integrated into at least one module and implemented as at least one processor (not shown).

[0015] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that a person skilled in the art can easily implement the present disclosure. However, it should be noted that the present disclosure can be implemented in various forms and is not limited to the embodiments described herein. In addition, in the accompanying drawings, parts not related to the explanation are omitted for clarity of explanation, and similar components are represented by similar reference numerals throughout the specification.

[0016] Figure 1 is a diagram for illustrating an electronic device that performs quantization according to a conventional technique.

[0017] Reference Figure 1 ,Traditional AI models perform quantization to reduce the amount of data to be processed and increase processing speed.

[0018] For example, in order to use an artificial intelligence model trained using a high-performance computer such as a server (or cloud server) in an electronic device (e.g., a user terminal device), the weight of the artificial intelligence model can be reduced by using a post-quantization method. For example, an integer-only quantization method is currently commonly used to compress the artificial intelligence model by using only integer values.

[0019] According to an embodiment, the user terminal device can output the result of performing multiplication, accumulation, and quantization artificial intelligence reasoning operations by using a lightweight artificial intelligence model.

[0020] However, conventional lightweight AI models for performing quantization have the problem of requiring the use of specialized quantization multipliers capable of performing relatively larger-bit operations than multipliers used in multiplication operations (e.g., multipliers of multiplier-accumulator (MAC) units). Furthermore, specialized quantization multipliers capable of performing large-bit operations have the problem of increasing the size of processors (e.g., chips) included in electronic devices.

[0021] For example, in the integer-only quantization method, input data in integer form is not dequantized into data in real form, but the result of performing an inference operation may be requantized into data in integer form and output.

[0022] For example, in the case of a conventional electronic device, if a multiplication-accumulation operation (ie, 32 (2 5 ) convolution operation between an 8-bit input feature map and an 8-bit weight), the multiplier of the multiplier-accumulator (MAC) can perform an 8-bit × 8-bit multiplication operation, and the result of the accumulation operation performed by the accumulator can be 21 bits (8 bits + 8 bits + 5 bits).

[0023] According to an embodiment, a conventional electronic device may perform a multiplication and accumulation operation (output of the accumulator = P sum The 21-bit result (P bits) is multiplied by the 32-bit value and the quantization of the value is shifted.

[0024] For example, an operation of multiplying 32-bit integer data by b / a (i.e., accumulator output (output) × b / a) can be replaced by an operation of multiplying 32-bit integer data by b×Ms and a shift operation (>>ms) (i.e., accumulator output (output) × (b×Ms)>>ms=quantized output (Q bits)).

[0025] Therefore, the multiplier dedicated to quantization according to the embodiment should perform a 21-bit×32-bit multiplication operation, and thus there is a problem that it requires a larger area than a multiplier of a multiplier-accumulator (MAC).

[0026] Hereinafter, a processor (eg, a neural processing unit (NPU)) according to various embodiments of the present disclosure will be explained, which performs quantization by using a multiplier-accumulator (MAC) without a multiplier dedicated to quantization requiring a relatively large area.

[0027] Figure 2 is a block diagram for illustrating a configuration of an electronic device according to an embodiment of the present disclosure.

[0028] Reference Figure 2 , the electronic device 100 may include a memory 110 and a processor 120 .

[0029] According to an embodiment, the memory 110 is a volatile storage medium and requires a power supply to maintain stored information (e.g., execution code and data). As an example, the memory 110 may be implemented as a random access memory (RAM). According to an embodiment, the memory 110 may be referred to as a cache memory, a buffer memory, etc., but hereinafter, for ease of explanation, it will be collectively referred to as the memory 110. Furthermore, the memory 110 is not limited to a volatile storage medium and may obviously be implemented as a non-volatile storage medium such as a non-volatile memory, a flash memory, a hard disk drive (HDD), or a solid-state drive (SSD).

[0030] According to an embodiment, the processor 120 controls the overall operation of the electronic device 100 .

[0031] According to an embodiment of the present disclosure, the processor 120 may be implemented as a digital signal processor (DSP), a microprocessor, and a timing controller (TCON) for processing digital signals. However, the present disclosure is not limited thereto, and the processor 120 may include one or more of a central processing unit (CPU), a microcontroller unit (MCU), a microprocessing unit (MPU), a controller, an application processor (AP) or a communication processor (CP), an ARM processor, and an artificial intelligence (AI) processor, or may be defined by these terms. In addition, the processor 120 may be implemented as a system on chip (SoC) or a large-scale integrated circuit (LSI) in which a processing algorithm is stored, or may be implemented in the form of a field programmable gate array (FPGA). The processor 120 may perform various functions by executing computer-executable instructions stored in the memory 110.

[0032] The processor 120 may include one or more of a central processing unit (CPU), a graphics processing unit (GPU), an accelerated processing unit (APU), an integrated many-core processor (MIC), a digital signal processor (DSP), a neural processing unit (NPU), a hardware accelerator, or a machine learning accelerator. The processor 120 may control one or a random combination of other components of the electronic device and perform operations related to communication or data processing. In addition, the processor 120 may execute one or more programs or instructions stored in the memory 110. For example, the processor 120 may execute the method according to an embodiment of the present disclosure by executing one or more instructions stored in the memory 110.

[0033] When the method according to an embodiment of the present disclosure includes multiple operations, the multiple operations may be performed by one processor or by multiple processors. For example, when a first operation, a second operation, and a third operation are performed by the method according to an embodiment, the first operation, the second operation, and the third operation may all be performed by the first processor, or the first operation and the second operation may be performed by the first processor (e.g., a general-purpose processor), and the third operation may be performed by the second processor (e.g., an artificial intelligence-specific processor).

[0034] The processor 120 may be implemented as a single-core processor including one core, or may be implemented as one or more multi-core processors including multiple cores (e.g., multiple cores of the same type or multiple cores of different types). In the case where the processor 120 is implemented as a multi-core processor, each of the multiple cores included in the multi-core processor may include an internal memory of the processor, such as a cache memory, an on-chip memory, etc., and a common cache shared by the multiple cores may be included in the multi-core processor. In addition, each of the multiple cores included in the multi-core processor (or some of the multiple cores) may independently read program instructions for implementing the method according to the embodiments of the present disclosure and execute the instructions, or multiple cores (or some of the cores) may be linked to each other and read program instructions for implementing the method according to the embodiments of the present disclosure and execute the instructions.

[0035] In the case where the method according to an embodiment of the present disclosure includes multiple operations, the multiple operations may be performed by one of the multiple cores included in the multi-core processor, or may be performed by multiple cores. For example, when the first operation, the second operation, and the third operation are performed by the method according to the embodiment, the first operation, the second operation, and the third operation may all be performed by the first core included in the multi-core processor, or the first operation and the second operation may be performed by the first core included in the multi-core processor, and the third operation may be performed by the second core included in the multi-core processor.

[0036] In the embodiments of the present disclosure, the processor may refer to a system on a chip (SoC) in which at least one processor and other electronic components are integrated, a single-core processor, a multi-core processor, or a core included in a single-core processor or a multi-core processor. In addition, here, the core may be implemented as a CPU, GPU, APU, MIC, DSP, NPU, hardware accelerator, or machine learning accelerator, etc., but the embodiments of the present disclosure are not limited thereto.

[0037] In addition, the artificial intelligence-related functions according to the present disclosure are operated by the processor 120 and the memory 110 of the electronic device 100. The processor 120 may include one or more processors. Here, the one or more processors may include at least one of a central processing unit (CPU), a graphics processing unit (GPU), or a neural processing unit (NPU), but are not limited to the aforementioned embodiments of the processor.

[0038] A CPU is a general-purpose processor capable of performing not only general-purpose operations but also artificial intelligence operations. It can efficiently execute complex programs using a multi-layer cache structure. The CPU is advantageous for serial processing methods, which systematically link the results of previous and next calculations through sequential calculations. While the CPU is designated as a general-purpose processor, the general-purpose processor is not limited to the aforementioned example.

[0039] A GPU is a processor for large-scale operations, such as floating-point operations for graphics processing, and can execute large-scale operations in parallel using a large number of integrated cores. In particular, a GPU can be advantageous over a CPU for parallel processing methods, such as convolution operations. Furthermore, a GPU can be used as a coprocessor to supplement the functions of a CPU. While the processor for large-scale operations is designated as the aforementioned GPU, the processor for large-scale operations is not limited to the aforementioned example.

[0040] An NPU is a processor dedicated to AI operations using artificial neural networks (ANNs), and it can implement each layer of an ANN as hardware (e.g., silicon). NPUs are designed to be specialized according to a company's needs, offering less flexibility than CPUs or GPUs, but can effectively handle the AI ​​operations a company requires. Furthermore, as a processor dedicated to AI operations, NPUs can be implemented in various forms, such as tensor processing units (TPUs), intelligence processing units (IPUs), and vision processing units (VPUs). While the AI ​​processor is designated as an NPU, the AI ​​processor is not limited to the aforementioned examples.

[0041] Furthermore, one or more processors may be implemented as a system on chip (SoC), which may include, in addition to one or more processors, a memory and a network interface such as a bus for data communication between the processor and the memory.

[0042] In the case where a system on a chip (SoC) included in the electronic device 100 includes multiple processors, the electronic device 100 can use some of the multiple processors to perform operations related to artificial intelligence (e.g., operations related to learning or reasoning of an artificial intelligence model). For example, the electronic device 100 can use at least one of the multiple processors, including a GPU, an NPU, a VPU, a TPU, or a hardware accelerator dedicated to artificial intelligence operations such as convolution operations and matrix product operations, to perform operations related to artificial intelligence. However, this is merely an example, and the electronic device 100 can obviously process operations related to artificial intelligence using a general-purpose processor such as a CPU.

[0043] In addition, the electronic device 100 can perform operations related to functions related to artificial intelligence by using multiple cores (e.g., dual cores, quad cores, etc.) included in one processor. Specifically, the electronic device 100 can perform artificial intelligence operations such as convolution operations, matrix product operations, etc. in parallel by using multiple cores included in the processor 120.

[0044] The one or more processors may perform control to process input data according to predefined operation rules or artificial intelligence models stored in the memory 110. The predefined operation rules or artificial intelligence models are characterized in that they are created through learning.

[0045] Here, creating by learning means creating predefined operation rules or an artificial intelligence model with desired characteristics by applying a learning algorithm to multiple training data. This learning can be performed in the device itself that performs artificial intelligence according to the present disclosure, or by a separate server / system.

[0046] The artificial intelligence model can be composed of multiple neural network layers. At least one layer has at least one weight value, and the operation of the layer is performed by the operation result of the previous layer and at least one defined operation. As examples of neural networks, there are convolutional neural networks (CNN), deep neural networks (DNN), recurrent neural networks (RNN), restricted Boltzmann machines (RBM), deep belief networks (DBN), bidirectional recurrent deep neural networks (BRDNN), deep Q networks, and transformers, but except for the specified cases, the neural networks in the present disclosure are not limited to the above examples.

[0047] A learning algorithm is a method for training a specific device (e.g., a robot) using a large amount of training data, thereby enabling the device to make decisions or predictions independently. Examples of learning algorithms include supervised learning, unsupervised learning, semi-supervised learning, and reinforcement learning. However, the learning algorithms described in this disclosure are not limited to these examples, except in specific cases.

[0048] The processor 120 according to an embodiment of the present disclosure may include a multiplier 121 and an accumulator 122 .

[0049] Reference Figure 3 , the processor 120 that performs quantization by using the multiplier 121 and the accumulator 122 will be explained.

[0050] Figure 3 is a detailed block diagram for illustrating a configuration of an electronic device according to an embodiment of the present disclosure.

[0051] Reference Figure 3 , the processor 120 may include a multiplier 121 and an accumulator (or adder) 122 of the MAC. Figure 3 In the figure, for the convenience of explanation, the data transmission direction is indicated by an arrow, and the number of bits of the transmitted data is shown below the arrow.

[0052] First, the processor 120 may store an N-bit activation value in a register (Reg) and an M-bit weight value in a register (Reg).

[0053] Then, the processor 120 may obtain P-bit multiplicand data according to a multiply-accumulate operation (ie, a convolution operation between the activation value and the weight value using the multiplier 121 and the accumulator 122 ).

[0054] The P-bit multiplicand data is expressed as the following formula.

[0055] First, the quantized activation value Iqnt (e.g., input feature map) and the quantized weight value Fqnt (e.g., filter) are input into the processor 120, and the relationship between the actual value (i.e., actual activation value i, actual weight value f) and the quantized value can be expressed as the following Formulas 1 and 2.

[0056] [Formula 1] I qnt [w][h]= (i[w][h]- ZeroPoint i ) × scale i i[w][h]= (I qnt [w][h]+ ZeroPoint i ) / scale i [Formula 2] F qnt [w][h]= (f[w][h]- ZeroPoint f ) × scale f f[w][h]= (F qnt[w][h]+ ZeroPoint f ) / scale f Then, the output value (e.g., output feature map) o[w][h] before quantization can be expressed as the following Formula 3.

[0057] [Formula 3]

[0058]

[0059] Here, if the input feature map, filter, and output feature map are assumed to be symmetric data for ease of explanation, then ZeroPoint i 、ZeroPoint f , and ZeroPoint o Each of can be 0.

[0060] Then, the output value is quantized, and the quantization can be expressed as the following Formula 4.

[0061] [Formula 4]

[0062]

[0063] Here, Oqnt[w][h] may be a quantized output value.

[0064] In addition, the processor 120 may replace the division operation with a multiplication operation and a shift operation as shown in the following Formula 5.

[0065] [Formula 5]

[0066]

[0067] Therefore, the quantized output value can be expressed as the following Formula 6.

[0068] [Formula 6]

[0069] In addition, if Figure 3 As shown in , the processor 120 may obtain a requantized output value by using a multiplier 121 and an accumulator 122 without using a multiplier dedicated for quantization after a convolution operation.

[0070] The requantized output value Oqnt[w][h] can be expressed as the following Formula 7.

[0071] [Formula 7]

[0072] Here, P sum Psum may be P-bit multiplicand data (ie, a result value of a convolution operation), Ms may be Ms-bit multiplier data, and a result value of a multiplication operation between Psum and Ms may be (P+Ms)-bit data.

[0073] In addition, refer to Figure 5 , the processor 120 may be based on a first scaling factor scale for quantizing the activation value i , the second scaling factor scale used to quantize the weight value f and a third scaling factor scale for quantizing the multiplicand data Psum o To obtain the multiplier data Ms and the shift factor 2 -ms .

[0074] Then, the processor 120 can calculate the quantization result according to the multiplicand data Psum, the multiplier data Ms and the shift factor 2 by using the multiplier 121 instead of the multiplier dedicated to quantization. -ms The multiplication operation between them is performed to obtain the integer of the quantized multiplicand data Psum as the output value.

[0075] Figure 4 is a diagram for illustrating multiplicand data and multiplier data according to an embodiment of the present disclosure.

[0076] Reference Figure 4 , the multiplicand data Psum can be P-bit data, and the multiplier data Ms can be Ms-bit data.

[0077] Furthermore, before the shift operation is performed, the result value Temp according to the multiplication operation between the multiplicand data Psum and the multiplier data Ms may be data of (P+Ms) bits.

[0078] Furthermore, the processor 120 according to an embodiment of the present disclosure performs a multiplication operation by using the multiplier 121 instead of a multiplier dedicated to quantization, and thus the multiplier 121 cannot perform a multiplication operation of P bits×Ms bits.

[0079] Hereinafter, a method in which the processor 120 obtains the result value Temp (i.e., an integer of the quantized multiplicand data Psum) according to the multiplication operation between the multiplicand data Psum and the multiplier data Ms by using the multiplier 121 will be explained, although the multiplier 121 does not perform a multiplication operation of P bits×Ms bits.

[0080] Figure 5 is a diagram for illustrating multiplicand data and multiplier data divided in units of a digit corresponding to a first bit according to an embodiment of the present disclosure.

[0081] Reference Figure 5 , the processor 120 according to an embodiment may divide the multiplicand data Psum into units of digits corresponding to the first bit and obtain at least one first parameter.

[0082] For example, the processor 120 may divide the P-bit multiplicand data Psum into units of digits corresponding to N bits and obtain a plurality of first parameters Psum0 to Psum3.

[0083] Here, Psum0 among the plurality of first parameters may include the AND 2 of the multiplicand data Psum. 0 ~2 n-1 In addition, Psum1 in the plurality of first parameters may include the AND 2 in the multiplicand data Psum. n to 2 2n-1 The corresponding digit.

[0084] Accordingly, Psumα in the plurality of first parameters may include the multiplicand data Psum and 2 α*n to 2 (α+1)*n-1 The corresponding digit.

[0085] Reference Figure 5 , the processor 120 according to an embodiment may divide the multiplier data Ms into units of digits corresponding to the first bit and obtain at least one second parameter.

[0086] For example, the processor 120 may divide the Ms-bit multiplier data Ms into units of digits corresponding to N bits and obtain a plurality of second parameters Ms0 to Ms3.

[0087] Here, Ms0 among the plurality of second parameters may include the multiplier data Ms and 2 0 to 2 n-1 In addition, Ms1 in the plurality of second parameters may include the multiplier data Ms and 2 n to 2 2n-1 The corresponding digit.

[0088] Accordingly, Msβ in the plurality of second parameters may include the multiplier data Ms and 2 β*n to 2 (β+1)*n-1 The corresponding digit.

[0089] Then, the processor 120 may identify a plurality of combinations according to the multiplication operation between the plurality of first parameters and the plurality of second parameters. Then, the processor 120 may group the plurality of combinations into units of the first digit and obtain a plurality of combinations.

[0090] First, refer to Figure 6A plurality of combinations according to multiplication operations between the plurality of first parameters and the plurality of second parameters are interpreted.

[0091] Figure 6 is a diagram for illustrating a multiplication operation between multiplicand data and multiplier data according to an embodiment of the present disclosure.

[0092] According to an embodiment, the multiplier 121 may perform an N-bit×M-bit multiplication operation.

[0093] As in Figure 5 As explained in , in the case where the P-bit multiplicand data Psum is divided by N bits (eg, 8 bits) as the multiplicand value of the multiplier 121 , the multiplicand data Psum can be expressed as in the following Formula 8.

[0094] [Formula 8] P sum = P sum3 × 2 3N + P sum2 × 2 2N + P sum1 × 2 N + P sum0 According to an embodiment, if the multiplier data Ms is M bits as a multiplier value of the multiplier 121, the multiplication operation between the multiplicand data Psum and the multiplier data Ms, that is, the quantized output value Oqnt of the multiplicand data Psum can be expressed as the following Formula 9.

[0095] [Formula 9] O qnt = ((M s P sum3 × 2 3N ) + (M s P sum2 × 2 2N ) + (M s P sum1 × 2 N ) + M s P sum0 ) × 2 -ms Each of the plurality of first parameters (ie, Psum#) is N bits, and the multiplier data Ms is M bits. Therefore, the processor 120 can obtain the operation result of Ms×Psum# by using the N-bit×M-bit multiplier 121, and calculate the result according to 2 -ms A shift operation is performed (ie, the operation result of the binary number is shifted left ms times) to obtain a quantized output value Oqnt.

[0096] According to an embodiment, the processor 120 may input Psum0 included in the multiplicand data Psum and the multiplier data Ms stored in the memory 110 into the multiplier 121. In addition, according to an embodiment, the processor 120 may obtain an operation result of Ms×Psum0 in the first iteration and store the result in the memory 110.

[0097] Then, the processor 120 can obtain (Ms×Psum1)×2 in the second iteration. N The operation result of is obtained (for example, by performing a multiplication operation of Ms×Psum1 using the multiplier 121 and then shifting right by N bits), and the result is stored in the memory 110.

[0098] Then, the processor 120 may obtain (Ms×Psum2)×2 in the third iteration. 2N The calculation result is stored in the memory 110.

[0099] Then, the processor 120 may obtain (Ms×Psum3)×2 in the fourth iteration. 3N The calculation result is stored in the memory 110.

[0100] According to an embodiment, the processor 120 may perform an accumulation operation on a plurality of operation results stored in the memory by using the accumulator 122, and then calculate the result according to 2 -ms A shift operation is performed to obtain a quantized output value Oqnt.

[0101] Furthermore, in the aforementioned embodiments, specific numerical values, specific times of iterations, etc. are merely examples for convenience of explanation, and the present disclosure is obviously not limited thereto.

[0102] Furthermore, according to an embodiment of the present disclosure, the number of iterations may be reduced under certain conditions (eg, overflow), and the bit width of the memory 110 may be reduced.

[0103] For example, since the requantized output value is Q-bit data, the maximum output value is 2 Q -1. In addition, due to the shift factor 2 used for quantization before the convolution operation -ms ms is set to a constant, so that the processor 120 can identify whether a specific condition, ie, overflow (output = maximum value), occurs in each iteration, thereby obtaining a quantized output value in the middle of the operation.

[0104] Furthermore, the processor 120 according to the embodiment does not store data according to lower bits to be discarded through a shift operation in the memory 110 at each iteration, and thus the size of data stored in the memory 110 can be reduced.

[0105] For convenience of explaining the above embodiment, it will be assumed that the multiplicand and the multiplier of the multiplier 121 have the same number of bits (eg, N=M in N bits×M bits).

[0106] For example, it can be assumed that the multiplier 121 can perform an 8-bit×8-bit multiplication operation, and the multiplicand data Psum is 32 bits, the multiplier data Ms is 32 bits, and the shift factor 2 -ms The case where ms is 64 bits. However, the specific numerical values ​​are only examples for ease of explanation, and the present disclosure is obviously not limited thereto. Moreover, it is obvious that the number of bits of the multiplicand and the multiplier may be different.

[0107] As in Figure 5 As explained in , when the multiplicand data Psum of P bits is divided by N bits (eg, 8 bits) as the multiplicand value of the multiplier 121 , it can be expressed as the following Formula 10.

[0108] [Formula 10] P sum = P sum3 × 2 3N + P sum2 × 2 2N + P sum1 × 2 N + P sum0 P sum = P sum3 × (2 8 ) 3 + P sum2 × (2 8 ) 2 + P sum1 × (2 8 ) 1 + P sum0 (Only when N=8 bits) Furthermore, when the Ms-bit multiplier data Ms is divided by M bits (for example, 8 bits) as a multiplier value of the multiplier 121 , it can be expressed as the following Formula 11.

[0109] [Formula 11] M s = M s3 × 2 3M + M s2 × 2 2M + M s1 × 2 M + M s0 M s = M s3 × (2 8 ) 3 + Ms2 × (2 8 ) 2 + M s1 × (2 8 ) + M s0 (Only when M=8 bits) According to an embodiment, the processor 120 may divide the multiplicand data Psum in units of digits corresponding to the first bit (eg, 8 bits) and obtain a plurality of first parameters Psum0 to Psum3 .

[0110] Furthermore, the processor 120 may divide the multiplier data Ms in units of digits corresponding to the first bit (eg, 8 bits) and obtain a plurality of second parameters Ms0 to Ms3 .

[0111] Then, the processor 120 may identify a plurality of combinations according to the multiplication operation between the plurality of first parameters and the plurality of second parameters, and group the plurality of identified combinations into units of the first digit, thereby obtaining a plurality of groups.

[0112] According to an embodiment, a result value Temp of the multiplication operation between the multiplicand data Psum and the multiplier data Ms may be expressed as the following Formula 12.

[0113] [Formula 12] Temp = P sum × M s = (P sum3 × (2 8 ) 3 + P sum2 × (2 8 ) 2 + P sum1 × (2 8 ) 1 + P sum0 ) × (M s3 × (2 8 ) 3 + M s2 ×(2 8 ) 2 + M s1 × (2 8 ) + M s0 ) = P sum3 M s3 × (2 8 ) 6 + (P sum2 M s3 + P sum3 M s2 ) × (2 8 )5 + (P sum1 M s3 + P sum2 M s2 + P sum3 M s1 )× (2 8 ) 4 + (P sum0 M s3 + P sum1 M s2 + P sum2 M s1 + P sum3 M s0 ) × (2 8 ) 3 + (P sum0 M s2 + P sum1 M s1 + P sum2 M s0 )× (2 8 ) 2 + (P sum0 M s1 + P sum1 M s0 ) × (2 8 ) + P sum0 M s0 = Temp6 × (2 8 ) 6 + (Temp50+ Temp51) × (2 8 ) 5 + (Temp40+ Temp41+ Temp42) ×(2 8 ) 4 + (Temp30+ Temp31+ Temp32+ Temp33) × (2 8 ) 3 + (Temp20+ Temp21+ Temp22) ×(2 8 ) 2 + (Temp10+ Temp11) × (2 8 ) + Temp0 = T7×(2 8 ) 7 + T6×(2 8 ) 6 + T5×(2 8 ) 5 + T4×(2 8 )4 + T3×(2 8 ) 3 + T2×(2 8 ) 2 + T1×(2 8 ) 1 + T0×(2 8 ).

[0114] Referring to formula 12, multiple combinations can be Psum3×Ms3×(2 8 ) 6 , Psum2×Ms3×(2 8 ) 5 , Psum3×Ms2×(2 8 ) 5 , Psum1×Ms3×(2 8 ) 4 , Psum2×Ms2×(2 8 ) 4 , Psum3×Ms1×(2 8 ) 4 , Psum0×Ms3×(2 8 ) 3 , Psum1×Ms2×(2 8 ) 3 , Psum2×Ms1×(2 8 ) 3 , Psum3×Ms0×(2 8 ) 3 , Psum0×Ms2×(2 8 ) 2 , Psum1×Ms1×(2 8 ) 2 , Psum2×Ms0×(2 8 ) 2 , Psum0×Ms1×2 8 , Psum1×Ms0×2 8 ,Psum0×Ms0.

[0115] The processor 120 according to an embodiment may group a plurality of combinations into units of the first digit (for example, 8 bits) and obtain a plurality of groups, and the plurality of groups may be as follows.

[0116] According to (2 8 ) 0 The first group (hereinafter referred to as T0) = (Psum0×Ms0(=Temp0)), According to (2 8 ) 1The second group (hereinafter referred to as T1) = (Psum0×Ms1(=Temp10), Psum1×Ms0(=Temp11)), According to (2 8 ) 2 The third group (hereinafter referred to as T2) = (Psum0×Ms2(=Temp20), Psum1×Ms1(=Temp21), Psum2×Ms0(=Temp22)), According to (2 8 ) 3 The fourth group (hereinafter referred to as T3) = (Psum0×Ms3(=Temp30), Psum1×Ms2(=Temp31), Psum2×Ms1(=Temp32), Psum3×Ms0(=Temp33)).

[0117] According to (2 8 ) 4 The fifth group (hereinafter referred to as T4) = (Psum1×Ms3(=Temp40), Psum2×Ms2(=Temp41), Psum3×Ms1(=Temp42)).

[0118] According to (2 8 ) 5 The sixth group (hereinafter referred to as T5) = (Psum2×Ms3(=Temp50), Psum3×Ms2(=Temp51)), According to (2 8 ) 6 The seventh group (hereinafter referred to as T6) = (P sum3 ×Ms3(=Temp6)).

[0119] Then, the processor 120 may obtain an intermediate operation value corresponding to a combination included in a group corresponding to the information about the number of iterations among the plurality of groups by using the multiplier 121 .

[0120] Will refer to Figure 7 Describe a detailed explanation of this aspect.

[0121] Figure 7 is a diagram for illustrating a plurality of combinations according to a multiplication operation according to an embodiment of the present disclosure.

[0122] Reference Figure 7 , a result value Temp of the multiplication operation between the multiplicand data Psum and the multiplier data Ms may be divided into a plurality of groups grouped into units of the first bit (eg, T0 to T6).

[0123] According to an embodiment, the first group T0 may include one combination (Psum0×Ms0 (=Temp0)).

[0124] According to another embodiment, the second group T1 may include two combinations (Psum0×Ms1(=Temp10), Psum1×Ms0(=Temp11)).

[0125] In addition, the processor 120 can obtain an intermediate operation value by performing a multiplication operation on each combination included in a specific group corresponding to the number of iterative operations among the multiple groups using the multiplier 121. Then, the processor 120 can obtain the sum of the intermediate operation values ​​as an operation value corresponding to the specific group by using the accumulator 122 and store the value in the memory 110.

[0126] According to an embodiment, if the number of iterative operations is the initial value (e.g., 0 times (iteration 0)), the processor 120 may obtain the operation result of the combination included in the first group T0, that is, Psum0×Ms0, as the intermediate operation value of the first group T0. In addition, since there is a combination included in the first group T0, the operation result of Psum0×Ms0 may be obtained as the operation value of the first group T0 and stored in the memory 110.

[0127] According to an embodiment, if the number of iterative operations is not the initial value, the processor 120 may obtain an intermediate operation value by performing a multiplication operation on each combination included in a specific group corresponding to the number of iterative operations among the multiple groups using the multiplier 121. Then, the processor 120 may obtain the sum of the operation value stored just before in the memory 110 and the intermediate operation value by using the accumulator 122 as the operation value of the specific group, and store the value in the memory 110.

[0128] Will refer to Figure 8 Describe a detailed explanation of this aspect.

[0129] <Iteration 0> First, if the number of iterative operations is the initial value, the processor 120 may obtain the operation results of Psum0×Ms0, which are the combinations included in the first group T1 among the plurality of groups, as the intermediate operation values ​​of the first group T0. Then, the processor 120 may obtain the sum of the obtained intermediate operation values ​​as the operation value of the first group T0.

[0130] In addition, the processor 120 may remove the digit corresponding to the first digit from the sum of the intermediate operation values ​​(eg, 2 0 to 2 7 ) (hereinafter referred to as the data according to the lower bit) 8 to 2 15) (hereinafter referred to as data according to the upper bits) as the operation value corresponding to the first group T0 is stored in the memory 110. Therefore, the processor 120 can store the data except the lower bits (ie, 2 0 to 2 N-1 ) other than the high-order data (ie, 2 N to 2 2N-1 ) is stored as the operation value corresponding to the group.

[0131] The processor 120 may then increase the number of iterations (eg, by one (iteration 1)).

[0132] <Iteration 1> Then, the processor 120 may obtain an intermediate operation value of each of Psum0×Ms1 and Psum1×Ms0 , which are combinations included in the second group T1 corresponding to the number of iterative operations among the plurality of groups, by using the multiplier 121 .

[0133] Then, the processor 120 may obtain the sum of the operation values ​​(ie, the operation values ​​corresponding to the first group T0 ) stored just before in the memory 110 and the intermediate operation values ​​of the second group T1 .

[0134] The processor 120 according to an embodiment may calculate the sum of the operation values ​​corresponding to the first group T0 and the intermediate operation values ​​of the second group T1 except for the digit corresponding to the first digit (for example, 2 0 to 2 7 ) (hereinafter, referred to as the data according to the lower bit) 8 to 2 15 ) is stored in the memory 110 as the operation value corresponding to the first group T0.

[0135] Then, the processor 120 may increase the number of iterations (eg, by two (iteration 2)).

[0136] Reference Figure 8 According to an embodiment, the processor 120 may perform a multiplication and accumulation operation of a combination sequentially included in each of the first to sixth groups T0 to T6 (or the seventh group T7 ) by using the multiplier 121 and the accumulator 122 .

[0137] Will refer to Figure 9 Describe a detailed explanation of this aspect.

[0138] Figure 9 is a diagram for illustrating accumulation operations in a plurality of groups according to an embodiment of the present disclosure.

[0139] exist Figure 9, for ease of explanation, a first group corresponding to the number of current iterative operations will be defined as T0, a sum of combined intermediate operation values ​​(e.g., a result of a multiplication operation using the multiplier 121) included in the first group (e.g., a result of an accumulation operation using the accumulator 122) will be defined as Temp0, data according to a low bit in Temp0 will be defined as out, and data according to a high bit in Temp0 will be defined as acc.

[0140] First, the processor 120 may obtain intermediate operation values ​​by performing a multiplication operation based on the combination included in the first group corresponding to the number of current iterative operations using the multiplier 121 , and obtain the sum of the intermediate operation values ​​by performing an accumulation operation using the accumulator 122 .

[0141] Then, the processor 120 may store the data acc according to upper bits except the data out according to lower bits in the sum of the intermediate operation values ​​in the memory 110 as the operation value corresponding to the first group T0 .

[0142] Then, the processor 120 may increase the number of iterative operations.

[0143] Then, the processor 120 may obtain intermediate operation values ​​by performing a multiplication operation based on the combination included in the second group T1 corresponding to the increased number of iterative operations using the multiplier 121 and obtain the sum (eg, Temp1) of the intermediate operation values ​​by performing an accumulation operation using the accumulator 122 .

[0144] Then, the processor 120 may obtain the sum (hereinafter referred to as SnC) of the operation value (eg, acc) immediately before stored in the memory 110 and the sum of the intermediate operation values ​​corresponding to the second group T1 (eg, Temp1 ) by using the accumulator 122 .

[0145] In addition, the processor 120 may be configured to generate a 10 ... -ms ms to identify whether to iterate (or end) the operation.

[0146] For example, if an iterative operation is identified (eg, ms ≥ the first digit N), the processor 120 may increase the number of iterative operations and set the SnC to the value of the lower bit data (eg, 2 0 to 2 7 ) is defined as out, and the data in the high bit (for example, 2 8 to 2 15 ) is defined as the operation value acc of this group.

[0147] As another example, if the end operation is recognized (eg, ms<first digit N), the processor 120 may recognize whether a specific condition (eg, overflow) occurs and output quantized multiplicand data Qout based on SnC and out.

[0148] Will refer to Figure 10 Describe a detailed explanation of this aspect.

[0149] Figure 10 is a diagram illustrating conditions for ending an operation according to an embodiment of the present disclosure.

[0150] Reference Figure 9 and Figure 10 , if the displacement factor 2 -ms If the number remaining after excluding the number of iterative operations (e.g., Iteration #) from the value corresponding to the first bit in ms is less than the value corresponding to the first bit (expressed as the following Formula 13), the processor 120 can obtain intermediate operation values ​​corresponding to the combinations included in a specific group (e.g., Temp1) corresponding to the number of iterative operations, and add these values ​​to the operation value (acc in Temp0) of the group corresponding to the number of iterative operations just before.

[0151] [Formula 13] ms-(Iteration #)×(N bits) <N Here, N represents the number corresponding to the first digit, and Iteration# represents the number of iteration operations.

[0152] Here, the sum of the intermediate operation value corresponding to the combination included in a specific group corresponding to the number of iterative operations (for example, Temp1) and the operation value (acc in Temp0) of the group corresponding to the number of iterative operations just before is defined as SnC.

[0153] Then, the processor 120 may output the quantized multiplicand data Qout based on SnC and data according to lower bits of a group corresponding to the number of times of the immediately previous iterative operation (acc in Temp0).

[0154] As an example, if SnC is (ms- (iteration #) Х (N)) to 2 2N If the value of the digit of is not 0, the processor 120 may recognize it as an overflow and output 2 as the overflow value. Q -1 (maximum value) is used as the quantized multiplicand data Qout. Then, the processor 120 may end the operation.

[0155] Figure 11 is a diagram for illustrating conditions for ending an operation according to an embodiment of the present disclosure.

[0156] As an example, if the displacement factor is 2 -ms If the remaining value after excluding the value corresponding to the first bit from the number of iterative operations (e.g., Iteration #) in ms is less than the value corresponding to the first bit, the processor 120 can obtain intermediate operation values ​​corresponding to the combinations included in a specific group (e.g., Temp1) corresponding to the number of iterative operations, and add these values ​​to the operation value of the group corresponding to the number of iterative operations just before (acc in Temp0).

[0157] Here, the sum of the intermediate operation value corresponding to the combination included in a specific group corresponding to the number of iterative operations (for example, Temp1) and the operation value (acc in Temp0) of the group corresponding to the number of iterative operations just before is defined as SnC.

[0158] If SnC is from 2 (ms- (iteration #)×(N)) to 2 2N If the value of the digit is 0, the processor 120 can recognize that it is not an overflow.

[0159] Then, the processor 120 may select the data according to the lower bit (out in Temp0) of the group corresponding to the number of iteration operations just before from 2 （ms-（iteration#）×（N）） to 2 N-1 And SnC from 2 0 to 2 (ms-(iteration #)×(N))-1+M-N The value corresponding to the digit of is output as the quantized multiplicand data Qout.

[0160] [Formula 14] Qout=[SnC[ms-1+MN:0,out[N-1:ms]], when Temp 2 ~ 6 = 0 Qout = 2 Q -1 (maximum value) when Temp 2 ~ 6 ≠ 0 Then, the processor 120 may terminate the operation.

[0161] For convenience of explanation, hereinafter, the multiplicand data Qout quantized by using the multiplier 121 and the accumulator 122 will be explained by assuming specific numerical values.

[0162] Figure 12 24 is a diagram for illustrating 24-bit multiplicand data and multiplier data according to an embodiment of the present disclosure.

[0163] For example, the multiplicand data Psum will be assumed to be 10000000 10 , the multiplier data Ms will be assumed to be 23413412 10, and the ms shift factor will be assumed to be 40.

[0164] According to the embodiment, the multiplicand data Psum is 10000000 10 =1001100010010110100000002, and the multiplier data Ms is 23413412 10 =1011001010100001010101001002.

[0165] According to an embodiment, the processor 120 may divide 1001100010010110100000002 into units of the first digit. For example, the multiplicand data Psum may be expressed as the following Formula 15.

[0166] [Formula 15] Psum = Psum0 × (2 8 ) 0 + Psum1 × (2 8 ) 1 + Psum2 × (2 8 ) 2 = 10000000 × (2 8 ) 0 + 10010110 × (2 8 ) 1 + 10011000 × (2 8 ) 2 According to an embodiment, the processor 120 may divide 1011001010100001010101001002 into units of the first digit. For example, the multiplier data Ms may be expressed as the following Formula 16.

[0167] [Formula 16] Ms = Ms0 × (2 8 ) 0 + Ms1 × (2 8 ) 1 + Ms2 × (2 8 ) 2 + Ms3 × (2 8 ) 3 = 10100100 ×(2 8 ) 0 + 1000010 × (2 8 ) 1 + 1100101 × (2 8 ) 2 + 1 × (2 8 ) 3 Then, the processor 120 may identify a plurality of combinations according to a multiplication operation between a plurality of first parameters ( Psum0 to Psum2 ) corresponding to the multiplicand data Psum and a plurality of second parameters ( Ms0 to Ms3 ) corresponding to the multiplier data Ms.

[0168] Then, the processor 120 may group the plurality of combinations into units of the first digit (eg, 8 bits) and obtain a plurality of groups.

[0169] In addition, the processor 120 may sequentially perform multiplication operations on a plurality of combinations by using the multiplier 121, and refer to Figure 13 Describe a detailed explanation of this aspect.

[0170] Figure 13 is a diagram for illustrating an operation order for each of a plurality of combinations of multiplication operations according to an embodiment of the present disclosure.

[0171] Reference Figure 13 If the number of iterative operations is an initial value (eg, iteration 0), the processor 120 may obtain a result value of Psum0×Ms0 (=Temp0) included in a first group among the plurality of groups by using the multiplier 121 .

[0172] Then, the processor 120 may increase the number of iterative operations, and according to the increased number of iterative operations (e.g., iteration 1), the processor 120 may sequentially obtain a result value of each of Psum0×Ms1 (=Temp10) and Psum1×Ms0 (=Temp11) included in the second group of the plurality of groups by using the multiplier 121.

[0173] Then, the processor 120 can increase the number of iterative operations, and according to the increased number of iterative operations (for example, iteration 2), the processor 120 can sequentially obtain the result value of each of Psum0×Ms2 (=Temp20), Psum1×Ms1 (=Temp21) and Psum2×Ms0 (=Temp22) included in the third group of the multiple groups by using the multiplier 121.

[0174] For ease of explanation, reference will be made to Figure 14 Interpret the result value corresponding to each of the multiple combinations.

[0175] Figure 14 2 is a diagram for illustrating an operation result of each of a plurality of combinations according to an embodiment of the present disclosure.

[0176] exist Figure 14 For ease of explanation, the result value is described in decimal.

[0177] Figure 15 is a diagram for illustrating an operation result according to information about the number of iterations according to an embodiment of the present disclosure.

[0178] Reference Figure 14 and Figure 15 , each of SnC, acc, and out obtained by using the multiplier 121 and the accumulator 122 according to the information on the number of iterations will be explained.

[0179] <Iteration 0> First, if the number of iteration operations is an initial value (eg, iteration 0), the processor 120 can obtain 20992 by using the multiplier 121. 10 =1010010000000002, which is a result value of Psum0×Ms0 (=Temp0) included in the first group among the plurality of groups.

[0180] Then, processor 120 may use accumulator 122 to sum the result values ​​of the multiplication operations for each combination included in the first group (hereinafter referred to as intermediate operation values), and define the data according to the lower bits of the sum of the intermediate operation values ​​as out, and define the data according to the upper bits as acc. For example, processor 120 may define 00000000, corresponding to the lower bits of 101001000000002, as out, and define 1010010 as acc. Then, processor 120 may increase the number of iterative operations.

[0181] <Iteration 1> Then, since the remaining value after excluding the number of iterative operations from the value corresponding to the first bit in the ms of the displacement factor is greater than or equal to the value corresponding to the first bit (40-1*8≥8, where 40 is ms, 1 is the number of iterative operations, and 8 is the value corresponding to the first bit), the processor 120 can perform iterative operations.

[0182] The processor 120 according to an embodiment may add a result value of the multiplication operation of each of the plurality of combinations (Psum0×Ms1 (=Temp10), Psum1×Ms0 (=Temp11)) included in the second group corresponding to the increased number of iteration operations (ie, Iteration 1) to the acc stored in the memory 110.

[0183] For example, the processor 120 may obtain Psum0×Ms1(=Temp10)=8448 10 =100001000000002 and Psum1×Ms0(=Temp11)=24600 10=1100000000110002, and add them to acc=10100102 stored in the memory 110.

[0184] Then, the processor 120 may obtain 33130 which is the sum of the sum of the intermediate operation result values ​​of the second group (Temp1) and the acc stored in the memory 110. 10 =10000001011010102 as SnC.

[0185] Then, the processor 120 may increase the number of iterative operations.

[0186] <Iteration 2> Then, since the remaining value after excluding the number of iterative operations from the value corresponding to the first bit in the ms of the displacement factor is greater than or equal to the value corresponding to the first bit (40-2*8≥8, where 40 is ms, 2 is the number of iterative operations, and 8 is the value corresponding to the first bit), the processor 120 can perform iterative operations.

[0187] The processor 120 according to an embodiment may define data according to upper bits except for data according to lower bits in the SnC stored in the memory 110 as acc.

[0188] For example, the processor 120 may be configured to have SnC=33130 10 =10000001011010102, exclude 1101010, and add 100000012=129 10 Defined as acc.

[0189] The processor 120 according to an embodiment may add a result value of the multiplication operation of each of the plurality of combinations (Psum0×Ms2 (=Temp20), Psum1×Ms1 (=Temp21), Psum2×Ms0 (=Temp22)) included in the third group corresponding to the increased number of iteration operations (i.e., Iteration 2) to the acc stored in the memory 110.

[0190] For example, the processor 120 may obtain Psum0×Ms2(=Temp20)=12928 10 =110010100000002、Psum1×Ms1(=Temp21)=9900 10 =100110101011002, and Psum2×Ms0(=Temp22)=24928 10 =1100001011000002 and add them to the acc stored in memory 110 = 100000012 = 129 10 Add.

[0191] Then, the processor 120 may obtain 47885 as the sum of the sum of the intermediate operation result values ​​of the third group (Temp2) and the acc stored in the memory 110. 10 =10111011000011012 as SnC.

[0192] Then, the processor 120 may increase the number of iterative operations.

[0193] <Iteration 3> Then, since the remaining value after excluding the number of iterative operations from the value corresponding to the first bit in the ms of the displacement factor is greater than or equal to the value corresponding to the first bit (40-3*8≥8, where 40 is ms, 3 is the number of iterative operations, and 8 is the value corresponding to the first bit), the processor 120 can perform iterative operations.

[0194] The processor 120 according to an embodiment may define data according to upper bits except for data according to lower bits in the SnC stored in the memory 110 as acc.

[0195] For example, the processor 120 may be configured to have SnC=47885 10 =10111011000011012, exclude 1101, and make 101110112=187 10 Defined as acc.

[0196] The processor 120 according to an embodiment may add a result value of the multiplication operation of each of the plurality of combinations (Psum0×Ms3 (=Temp30), Psum1×Ms2 (=Temp31), Psum2×Ms1 (=Temp32)) included in the fourth group corresponding to the increased number of iteration operations (i.e., Iteration 3) to the acc stored in the memory 110.

[0197] For example, the processor 120 may obtain Psum0×Ms3 (=Temp30)=128 10 =100000002, Psum1×Ms2 (=Temp31)=15150 10 =111011001011102 and Psum2×Ms1(=Temp32)=10032 10 =100111001100002 and add them to the acc stored in memory 110 = 101110112 = 187 10 Add.

[0198] Then, the processor 120 may obtain 25497 as the sum of the sum of the intermediate operation result values ​​of the fourth group (Temp3) and the acc stored in the memory 110. 10 =1100011100110012 as SnC.

[0199] Then, the processor 120 may increase the number of iterative operations.

[0200] <Iteration 4> Then, since the remaining value after excluding the number of iterative operations from the value corresponding to the first bit in the ms of the displacement factor is greater than or equal to the value corresponding to the first bit (40-4*8≥8, where 40 is ms, 4 is the number of iterative operations, and 8 is the value corresponding to the first bit), the processor 120 can perform iterative operations.

[0201] The processor 120 according to an embodiment may define data according to upper bits except for data according to lower bits in the SnC stored in the memory 110 as acc.

[0202] For example, the processor 120 may be configured to have SnC=25497 10 =1100011100110012, exclude 10011001, and make 11000112=99 10 Defined as acc.

[0203] The processor 120 according to an embodiment may add a result value of the multiplication operation of each of the plurality of combinations (Psum1×Ms3 (=Temp40), Psum2×Ms2 (=Temp41)) included in the fifth group corresponding to the increased number of iteration operations (ie, Iteration 4) to the acc stored in the memory 110.

[0204] For example, the processor 120 may obtain Psum1×Ms3 (=Temp40)=150 10 =100101102 and Psum2×Ms2(=Temp41)=15352 10 =111011111110002 and add them to the acc stored in memory 110 = 11000112 = 99 10 Add.

[0205] Then, the processor 120 may obtain 15601 which is the sum of the sum of the intermediate operation result values ​​of the fifth group (Temp4) and the acc stored in the memory 110. 10 =111100111100012 as SnC.

[0206] Then, the processor 120 may increase the number of iterative operations.

[0207] <Iteration 5> Then, since the remaining value after excluding the number of iterative operations from the value corresponding to the first bit in the shift factor ms is less than the value corresponding to the first bit (40-5*8<8, where 40 is ms, 5 is the number of iterative operations, and 8 is the value corresponding to the first bit), the processor 120 can identify whether to perform an iterative operation.

[0208] Since Psum2×Ms3 (=Temp50)=152 according to the result values ​​of the multiplication operation of the plurality of combinations included in the sixth group corresponding to the increased number of iteration operations (ie, Iteration 5) 10 = the high bit in 100110002 (i.e., 2 n to 2 2n -1 ) is 0, the processor 120 according to the embodiment can recognize that it is not an overflow. Therefore, the processor 120 can iterate the operation.

[0209] Then, the processor 120 may define data according to upper bits except for data according to lower bits in the SnC stored in the memory 110 as acc.

[0210] For example, the processor 120 may be configured to have SnC=15601 10 =111100111100012, exclude 11110001, and add 1111002=60 10 Defined as acc.

[0211] Then, the processor 120 may obtain 212 which is the sum of the sum of the intermediate operation result values ​​of the sixth group (Temp5) and the acc stored in the memory 110. 10 As SnC.

[0212] Then, the processor 120 may increase the number of iterative operations.

[0213] <Iteration 6> Then, since the remaining value after excluding the number of iterative operations from the value corresponding to the first bit in the ms of the displacement factor is less than 0 (40-6*8<0, where 40 is ms, 6 is the number of iterative operations, and 8 is the value corresponding to the first bit), the processor 120 can terminate the operation.

[0214] Then, the processor 120 may output SnC=212 stored in the memory 110 as the quantized multiplicand data Qout. For example, the processor 120 may output SnC=212 10 As Qout.

[0215] Referring to the above embodiment, since Psum×Ms×2 -ms =100000000×23413412×2 -40 ≒212.9437, the processor 120 may obtain the quantized multiplicand data Qout by using the multiplier 121 (eg, a multiplier that performs an 8-bit×8-bit multiplication operation) instead of a multiplier dedicated to quantization.

[0216] Figure 16 is a diagram for illustrating a method of acquiring an integer of quantized multiplicand data according to an embodiment of the present disclosure.

[0217] According to an embodiment, in step S1601 , the processor 120 may set each of the number of iterative operations, the shift factor ms, acc, and out to an initial value.

[0218] According to an embodiment, the processor 120 can obtain the multiplicand data Psum according to the convolution operation between the activation value and the weight value in step S1602, and sequentially operate each of the multiple groups according to the number of iterative operations in step S1603, and obtain Temp# corresponding to each of the multiple groups.

[0219] According to an embodiment, after the processor 120 obtains the operation value acc corresponding to the second group according to steps S1601 to S1603, if in steps S1605: Yes, S1606: No and S1609: No, the remaining value after excluding the value corresponding to the first bit in the shift factor by the number of iterative operations is greater than or equal to the value corresponding to the first bit, the processor 120 can obtain a third intermediate operation value corresponding to the combination included in the third group according to the number of iterative operations in multiple groups by using the multiplier 121, and obtain the remaining number of the sum of the second operation value and the third intermediate operation value stored in the memory 110 just before, excluding the number of digits corresponding to the first bit, as the third operation value corresponding to the third group, and after storing the third operation value in the memory 110 in step S1614, increase the number of iterative operations by increasing the number of iterative operations.

[0220] According to an embodiment, if in steps S1605: Yes, S1606: No, and S1609: Yes, the remaining value after excluding the value corresponding to the first bit in the shift factor by the increased number of iterative operations is less than the value corresponding to the first bit, the processor 120 may obtain a fourth intermediate operation value corresponding to a combination included in a fourth group according to the increased number of iterative operations, and in steps S1610: No and S1615, output the overflow value as an integer based on the number from the digit corresponding to the remaining number to the digit corresponding to the first bit in the sum of the third operation value and the fourth intermediate operation value stored just before in the memory 110.

[0221] If in step S1606: Yes, the remaining value after excluding the value corresponding to the first bit in the shift factor by the number of iterative operations is zero, the processor 120 according to the embodiment can obtain a fourth intermediate operation value corresponding to the combination included in the fourth group according to the increased number of iterative operations, and in steps S1607: Yes, S1608, S1603, S1604, S1605: No and S1616, output the number of the digit corresponding to the first bit in the sum of the third operation value and the fourth intermediate operation value just previously stored in the memory 110 as an integer.

[0222] If in step S1605: Yes, step S1606: No and step S1609: No, the remaining value after excluding the value corresponding to the first bit in the shift factor by the increased number of iterative operations is greater than or equal to the value corresponding to the first bit, then in step S1614, the processor 120 according to the embodiment can obtain a third intermediate operation value corresponding to the combination included in the third group according to the number of iterative operations in the multiple groups by using the multiplier 121.

[0223] In addition, if in step S1607: Yes, the remaining value after excluding the value of the digit corresponding to the first digit in the sum of the second operation value and the third intermediate operation value stored in the memory 110 just before is zero, then the processor 120 according to the embodiment can output the number of the digit corresponding to the first digit as an integer in steps S1608, S1604, S1605 and S1616.

[0224] In addition, according to Figure 16 Steps S1601 to S1616 of the flowchart shown in FIG. 16 can be expressed as the following pseudo code.

[0225]

Table 1

[0226] In a control method for an electronic device including a multiplier, an accumulator, and a memory according to an embodiment of the present disclosure, first, multiplicand data according to a convolution operation between an activation value and a weight value is obtained by using the multiplier and the accumulator, and the data is stored in the memory. Then, based on a first scaling factor for quantizing the activation value, a second scaling factor for quantizing the weight value, and a third scaling factor for quantizing the multiplicand data, multiplier data and a shift factor are obtained and stored in the memory.

[0227] Then, by using a multiplier, an integer of the quantized multiplicand data according to the multiplication operation among the multiplicand data, the multiplier data and the shift factor is obtained.

[0228] According to an embodiment, the step of obtaining an integer may include: dividing the multiplicand data into units of digits corresponding to the first digit and obtaining at least one first parameter, dividing the multiplier data into units of digits corresponding to the first digit and obtaining at least one second parameter, identifying multiple combinations based on a multiplication operation between the at least one first parameter and the at least one second parameter, grouping the identified multiple combinations into units of the first digit and obtaining multiple groups, obtaining a first intermediate operation value corresponding to a combination included in a first group according to the number of iterative operations among the multiple groups by using a multiplier, obtaining a sum of the first intermediate operation values ​​by using an accumulator, and obtaining a remaining value after excluding the value of the digit corresponding to the first digit from the sum of the first intermediate operation values ​​as a first operation value corresponding to the first group, and storing the value in a memory.

[0229] Here, the step of obtaining the first operation value may include: obtaining the first operation value based on the sum of the first intermediate operation values ​​based on the number of iterative operations corresponding to the initialized setting value, and obtaining the first operation value based on the sum of the operation value stored in the memory just before and the first intermediate operation value based on the number of iterative operations not corresponding to the initialized setting value.

[0230] The control method according to the embodiment may further include increasing the number of iterative operations by increasing the number of iterative operations after storing the first operation value in the memory.

[0231] Here, the step of obtaining an integer may include: obtaining a second intermediate operation value corresponding to a combination included in a second group of the plurality of groups according to the increased number of iterative operations by using a multiplier; obtaining the sum of the first intermediate operation value and the second intermediate operation value stored in the memory by using an accumulator; and obtaining the remaining value of the sum of the first intermediate operation value and the second intermediate operation value after excluding the value of the digit corresponding to the first digit as the second operation value corresponding to the second group. In addition, the step of increasing the number of iterative operations may include: increasing the number of iterative operations after storing the second operation value in the memory.

[0232] According to an embodiment, the step of obtaining an integer may include: obtaining a third intermediate operation value corresponding to a combination included in a third group according to the number of iterative operations among the plurality of groups by using a multiplier, based on the fact that a remaining value after excluding the value corresponding to the first digit in the shift factor by the number of iterative operations is greater than or equal to the value corresponding to the first digit, and obtaining a remaining value after excluding the value of the digit corresponding to the first digit from the sum of the second operation value and the third intermediate operation value stored immediately before in the memory as the third operation value corresponding to the third group. In addition, the step of increasing the number of iterations may include increasing the number of iterations by increasing the number of iterations after storing the third operation value in the memory.

[0233] Among them, the step of obtaining an integer may include: based on the fact that the remaining value after excluding the value corresponding to the first bit in the shift factor by the increased number of iterative operations is less than the value corresponding to the first bit, obtaining a fourth intermediate operation value corresponding to the combination included in the fourth group according to the increased number of iterative operations, and outputting the overflow value as an integer based on the values ​​from the digit corresponding to the remaining value to the digit corresponding to the first bit in the sum of the third operation value and the fourth intermediate operation value stored in the memory just before.

[0234] According to an embodiment, the step of obtaining an integer may include: based on the remaining value being zero after excluding the value corresponding to the first bit in the shift factor by the increased number of iterative operations, obtaining a fourth intermediate operation value corresponding to a combination included in a fourth group according to the increased number of iterative operations, and outputting the value of the digit corresponding to the first bit in the sum of the third operation value and the fourth intermediate operation value stored in the memory just before as an integer.

[0235] According to an embodiment, the step of obtaining an integer may include: based on the fact that a remaining value after excluding the value corresponding to the first bit in the shift factor by the increased number of iterative operations is greater than or equal to the value corresponding to the first bit, obtaining a third intermediate operation value corresponding to a combination included in a third group according to the number of iterative operations among the multiple groups by using a multiplier, and based on the fact that a remaining value after excluding the value of the digit corresponding to the first bit from the sum of the second operation value and the third intermediate operation value stored in the memory just before is zero, outputting the value of the digit corresponding to the first bit as an integer.

[0236] Furthermore, the methods according to the aforementioned various embodiments of the present disclosure may be implemented in the form of an application that can be installed on a conventional electronic device.

[0237] Furthermore, the methods according to the aforementioned various embodiments of the present disclosure may be implemented using only software upgrade or hardware upgrade for a conventional electronic device.

[0238] In addition, the aforementioned various embodiments of the present disclosure may also be executed by an embedded server provided on the electronic device or an external server of at least one of the electronic device or the display device.

[0239] In addition, according to an embodiment of the present disclosure, the various embodiments described above may be implemented as software including instructions stored in a machine-readable storage medium, which can be read by a machine (e.g., a computer). A machine refers to a device that calls instructions stored in a storage medium and can operate according to the called instructions, and the device may include an electronic device according to the embodiments disclosed herein. In the case where instructions are executed by a processor, the processor may perform functions corresponding to the instructions by itself or by using other components under its control. The instructions may include code generated or executed by a compiler or interpreter. The storage medium readable by the machine may be provided in the form of a non-transitory storage medium. Here, the term "non-transitory" only means that the storage medium does not include signals and is tangible, without indicating whether the data is stored semi-permanently or temporarily in the storage medium.

[0240] Furthermore, according to an embodiment of the present disclosure, the method according to the aforementioned various embodiments may be provided while being included in a computer program product. A computer program product refers to a product, and it may be traded between a seller and a buyer. The computer program product may be distributed in the form of a machine-readable storage medium (e.g., a compact disc read-only memory (CD-ROM)), or may be downloaded through an app store (e.g., PlayStore). TM In the case of online publishing, at least a portion of the computer program product may be at least temporarily stored in a storage medium (such as a memory of a manufacturer's server, an application store's server, and a relay server), or may be temporarily generated.

[0241] In addition, each of the components (e.g., modules or programs) according to the various embodiments described above may include a single object or multiple objects. Furthermore, among the corresponding subcomponents described above, some subcomponents may be omitted, or other subcomponents may be further included in various embodiments. Alternatively or additionally, some components (e.g., modules or programs) may be integrated into objects and perform the functions performed by each component prior to integration in the same or similar manner. Furthermore, the operations performed by the modules, programs, or other components according to various embodiments may be performed sequentially, in parallel, iteratively, or heuristically. Alternatively, at least some of the operations may be performed in a different order or omitted, or other operations may be added.

[0242] In addition, in the above, the preferred embodiments of the present disclosure have been shown and described, but the present disclosure is not limited to the aforementioned specific embodiments, and it is clear that various modifications can be made by those skilled in the art without departing from the main purpose of the present disclosure as claimed in the appended claims. In addition, it is intended that such modifications should not be interpreted independently of the technical ideas or prospects of the present disclosure.

Claims

1. An electronic device comprising: Memory; as well as processor, including multipliers and accumulators, Wherein, the processor is configured to: obtaining multiplicand data according to a convolution operation between an activation value and a weight value by using the multiplier and the accumulator, and storing the multiplicand data in the memory, obtaining multiplier data and a shift factor based on a first scaling factor for quantizing the activation value, a second scaling factor for quantizing the weight value, and a third scaling factor for quantizing the multiplicand data, and storing the multiplier data and the shift factor in the memory, and An integer quantizing the multiplicand data is obtained based on a multiplication operation among the multiplicand data stored in the memory, the multiplier data, and the shift factor by using the multiplier.

2. The electronic device according to claim 1, in, The processor is configured to: Dividing the multiplicand data into units of digits corresponding to the first bit and obtaining at least one first parameter, dividing the multiplier data into units of digits corresponding to the first bit, and obtaining at least one second parameter, identifying a plurality of combinations based on a multiplication operation between the at least one first parameter and the at least one second parameter, Grouping the identified multiple combinations into first-order units to obtain multiple groups, obtaining, by using the multiplier, a first intermediate operation value corresponding to a combination included in a first group according to the number of times of iterative operation among the plurality of groups, obtaining a sum of first intermediate operation values ​​by using the accumulator, and A remaining value of the sum of the first intermediate operation values ​​excluding the value of the digit corresponding to the first position is obtained as a first operation value corresponding to the first group, and the first operation value is stored in the memory.

3. The electronic device according to claim 2, in, The processor is configured to: Based on the number of iterative operations corresponding to the initialized setting value, obtaining a first operation value based on the sum of the first intermediate operation values; Based on the fact that the number of times of the iterative operation does not correspond to the initialized setting value, a first operation value is obtained based on the sum of the operation value stored immediately before in the memory and a first intermediate operation value.

4. The electronic device according to claim 2, in, The processor is configured to: The number of iterative operations is increased by increasing the number of iterative operations after storing the first operation value in the memory.

5. The electronic device according to claim 4, in, The processor is configured to: acquiring, by using the multiplier, a second intermediate operation value corresponding to a combination included in a second group according to an increased number of iterative operations among the plurality of groups, obtaining a sum of a first intermediate operation value and a second intermediate operation value stored in the memory by using the accumulator, Obtaining a remaining value after excluding the value of the digit corresponding to the first digit from the sum of the first intermediate operation value and the second intermediate operation value as a second operation value corresponding to the second group; After the second operation value is stored in the memory, the number of iteration operations is increased.

6. The electronic device according to claim 2, in, The processor is configured to: obtaining, by using the multiplier, a third intermediate operation value corresponding to a combination included in a third group according to the number of iterative operations among the plurality of groups, based on the remaining value after excluding the value corresponding to the first bit in the shift factor by the number of iterative operations is greater than or equal to the value corresponding to the first bit; Obtaining a remaining value after excluding the value of the digit corresponding to the first digit from the sum of the second operation value and the third intermediate operation value stored in the memory just before, as a third operation value corresponding to the third group; The number of iterative operations is increased by increasing the number of iterative operations after storing the third operation value in the memory.

7. The electronic device according to claim 6, in, The processor is configured to: obtaining a fourth intermediate operation value corresponding to a combination included in a fourth group according to the increased number of iterative operations based on a remaining value after excluding the value corresponding to the first bit in the shift factor by the increased number of iterative operations being smaller than the value corresponding to the first bit; An overflow value is output as the integer based on the values ​​from the digit corresponding to the remaining value to the digit corresponding to the first digit in the sum of the third operation value and the fourth intermediate operation value stored in the memory immediately before.

8. The electronic device according to claim 6, in, The processor is configured to: acquiring a fourth intermediate operation value corresponding to a combination included in a fourth group according to the increased number of iterative operations based on a remaining value being zero after excluding the value corresponding to the first bit in the shift factor by the increased number of iterative operations; The value of the digit corresponding to the first digit in the sum of the third operation value and the fourth intermediate operation value stored immediately before in the memory is output as the integer.

9. The electronic device according to claim 2, in, The processor is configured to: obtaining, by using the multiplier, a third intermediate operation value corresponding to a combination included in a third group according to the number of iterative operations among the plurality of groups, based on the remaining value after excluding the increased number of iterative operations from the value corresponding to the first bit in the shift factor being greater than or equal to the value corresponding to the first bit; Based on the fact that the remaining value after excluding the value of the digit corresponding to the first digit from the sum of the second operation value and the third intermediate operation value stored in the memory immediately before is zero, the value of the digit corresponding to the first digit is output as the integer.

10. A control method for an electronic device, the electronic device comprising a multiplier, an accumulator, and a memory, the method comprising: obtaining multiplicand data according to a convolution operation between an activation value and a weight value by using the multiplier and the accumulator, and storing the multiplicand data in the memory; obtaining multiplier data and a shift factor based on a first scaling factor for quantizing the activation value, a second scaling factor for quantizing the weight value, and a third scaling factor for quantizing the multiplicand data, and storing the multiplier data and the shift factor in the memory; as well as By using the multiplier, an integer quantizing the multiplicand data is obtained according to a multiplication operation among the multiplicand data, the multiplier data and the shift factor.

11. The control method according to claim 10, in, The steps of obtaining the integer include: Dividing the multiplicand data into units of digits corresponding to the first bit, and obtaining at least one first parameter; Dividing the multiplier data into units of digits corresponding to the first bit, and obtaining at least one second parameter; identifying a plurality of combinations based on a multiplication operation between the at least one first parameter and the at least one second parameter; Grouping the identified multiple combinations into first-order units to obtain multiple groups; obtaining, by using the multiplier, a first intermediate operation value corresponding to a combination included in a first group according to the number of iterative operations among the plurality of groups; obtaining a sum of first intermediate operation values ​​by using the accumulator; and A remaining value of the sum of the first intermediate operation values ​​excluding the value of the digit corresponding to the first position is obtained as a first operation value corresponding to the first group, and the first operation value is stored in the memory.

12. The control method according to claim 11, in, The step of obtaining a first operation value includes: Obtaining a first operation value based on the sum of the first intermediate operation values ​​according to the number of times of the iterative operation corresponding to the set value initialized; and Based on the fact that the number of iterative operations does not correspond to the initialized set value, a first operation value is acquired based on the sum of an operation value immediately before stored in the memory and a first intermediate operation value.

13. The control method according to claim 11, further comprising: The number of iterative operations is increased by increasing the number of iterative operations after storing the first operation value in the memory.

14. The control method according to claim 13, in, The steps of obtaining the integer include: obtaining, by using the multiplier, a second intermediate operation value corresponding to a combination included in a second group according to an increased number of iterative operations among the plurality of groups; obtaining a sum of a first intermediate operation value and a second intermediate operation value stored in the memory by using the accumulator; and Obtaining the remaining value after excluding the value of the digit corresponding to the first digit from the sum of the first intermediate operation value and the second intermediate operation value as the second operation value corresponding to the second group, The step of increasing the number of iterative operations includes: After the second operation value is stored in the memory, the number of iteration operations is increased.

15. The control method according to claim 11, in, The steps of obtaining the integer include: obtaining, by using the multiplier, a third intermediate operation value corresponding to a combination included in a third group according to the number of iterative operations among the plurality of groups, based on the remaining value after excluding the value corresponding to the first bit by the number of iterative operations in the shift factor being greater than or equal to the value corresponding to the first bit; and Obtaining a remaining value after excluding the value of the digit corresponding to the first digit from the sum of the second operation value and the third intermediate operation value stored just before in the memory as a third operation value corresponding to the third group, wherein the step of increasing the number of iterative operations includes: The number of iterative operations is increased by increasing the number of iterative operations after storing the third operation value in the memory.

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