PCIE device and operating method thereof

Abstract

The present invention provides a PCIE device and an operating method thereof. The PCIE device includes a bus channel, a PCIE control circuit, and an early response circuit. The PCIE control circuit receives a PCIE packet from a host and converts the PCIE packet into at least one AXI packet. The early response circuit is coupled between the PCIE control circuit and the bus channel. In response to an AXI packet sent by the PCIE control circuit including a write request to a core circuit, the early response circuit transmits the write request to the core circuit of the PCIE device via the bus channel. Before the core circuit feeds back a true response corresponding to the write request to the early response circuit, the early response circuit feeds back a dummy response corresponding to the write request to the PCIE control circuit, thereby triggering the PCIE control circuit to send the AXI packet corresponding to the next PCIE packet in advance.

Description

Technical Field

[0001] The present invention relates to an electronic device, and in particular to a PCIE (Peripheral Component Interconnect Express, or PCIe) device and an operating method thereof. Background Art

[0002] PCIe is a commonly used interface between computers and peripheral components. Depending on the application context, peripheral components include AI (Artificial Intelligence) cards or other peripheral components, while AI cards include GPU (Graphics Processing Unit) cards, GPGPU (General-Purpose GPU) cards, or other AI computing components. Peripheral components with a PCIe interface are called PCIe devices. The PCIe protocol is designed for system-level connectivity. The AMBA (Advanced Microcontroller Bus Architecture) protocol is widely used in ASIC (Application-Specific Integrated Circuit) design. For example, the AXI protocol is widely used for NoC (Network on Chip) connectivity. ASIC devices require a bridge to convert between the PCIe and AXI protocols. Implementing PCIe-AXI bridging functionality in PCIe devices is one of the many technical issues in the integrated circuit field. Summary of the Invention

[0003] The present invention is directed to a PCIE device and an operating method thereof, so as to realize a bridge connection between the PCIE protocol and the AXI (Advanced Extensible Interface) protocol.

[0004] In an embodiment of the present invention, the PCIE device includes a bus channel, a PCIE control circuit, and an early response circuit. The bus channel is coupled to the core circuit of the PCIE device. The PCIE control circuit receives a first PCIE packet from a host and converts the first PCIE packet into at least one first AXI packet. The early response circuit is coupled between the PCIE control circuit and the bus channel. In response to at least one first AXI packet sent by the PCIE control circuit including a write request to the core circuit, the early response circuit transmits the write request to the core circuit via the bus channel. Before the core circuit feeds back a true response corresponding to the write request to the early response circuit, the early response circuit feeds back a dummy response corresponding to the write request to the PCIE control circuit, thereby triggering the PCIE control circuit to send the AXI packet corresponding to the next PCIE packet in advance.

[0005] In an embodiment of the present invention, the operating method includes: receiving a first PCIE packet from a host by a PCIE control circuit of a PCIE device; converting the first PCIE packet into at least one first AXI packet by the PCIE control circuit; in response to the at least one first AXI packet sent by the PCIE control circuit including a write request to a core circuit, transmitting the write request to the core circuit through a bus channel of the PCIE device by an early response circuit; and before the core circuit feeds back a true response corresponding to the write request to the early response circuit, feeding back a dummy response corresponding to the write request to the PCIE control circuit by the early response circuit, thereby triggering the PCIE control circuit to send an AXI packet corresponding to the next PCIE packet in advance.

[0006] Based on the above, the early response circuit is placed between the PCIE control circuit and the bus channel. After the PCIE control circuit transmits the AXI packet (write request) corresponding to the current PCIE packet to the bus channel via the early response circuit, and before the bus channel returns the actual response for the current PCIE packet, the early response circuit first returns a dummy response to the current PCIE packet to the PCIE control circuit, triggering the PCIE control circuit to send the AXI packet corresponding to the next PCIE packet in advance. As a result, PCIE devices can improve system efficiency.

[0007] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic diagram of a circuit block of a PCIE device according to an embodiment of the present invention;

[0009] Figure 2 1 is a flow chart of an operating method of a PCIE device according to an embodiment of the present invention;

[0010] Figure 3 FIG. 1 is a circuit module diagram of a PCIE control circuit, an early response circuit, and a bus channel according to an embodiment of the present invention.

[0011] Explanation of Figure Numbers

[0012] 10: Host

[0013] 100: PCIE device

[0014] 110: PCIE control circuit

[0015] 111: PCIE controller

[0016] 112: Bridge

[0017] 112a: AXI write identifier buffer

[0018] 112b: AXI read identifier buffer

[0019] 120: Early response circuit

[0020] 121: Write controller

[0021] 122: Incomplete write buffer

[0022] 123: Read Controller

[0023] 124: pending read buffer

[0024] 125: Atomic Operation Controller

[0025] 126: Atomic Operation Buffer

[0026] 130: Bus channel

[0027] 140: Core Circuit

[0028] Addr: AXI write request address field

[0029] Ato_op: atomic operation information field

[0030] AXI_AR: Read address channel

[0031] AXI_AW: write address channel

[0032] AXI_B: Write response channel

[0033] AXI_ID: AXI write request identifier field

[0034] AXI_inf: AXI read request information field

[0035] AXI_R: Read data channel

[0036] AXI_W: write data channel

[0037] RD: ready field

[0038] BZ1: First busy bit field

[0039] BZ2: Second busy bit field

[0040] BZ3: Third busy bit field

[0041] W_cnt: First AXI write request quantity field

[0042] OSD_W: Second AXI write request quantity field

[0043] VF_ID1: First Virtual Function Identifier field

[0044] VF_ID2: Second virtual function identifier field DETAILED DESCRIPTION

[0045] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0046] The term "coupled (or connected)" as used throughout this specification (including the claims) may refer to any direct or indirect means of connection. For example, if a first device is described as being coupled (or connected) to a second device, this should be interpreted to mean that the first device may be directly connected to the second device, or the first device may be indirectly connected to the second device via another device or some other means of connection. Terms such as "first" and "second" throughout this specification (including the claims) are used to name components or to distinguish between different embodiments or scopes, and are not intended to limit the upper or lower limits on the number of components or the order of components. Whenever possible, components, members, and steps using the same reference numbers in the drawings and embodiments represent identical or similar parts. Components, members, and steps using the same reference numbers or the same terminology in different embodiments may refer to the relevant descriptions. It should be understood that features of the following embodiments may be combined. For example, features of the second embodiment may be implemented in combination with features of the first embodiment. Those skilled in the art can select appropriate feature combinations based on actual design requirements.

[0047] In the PCIe protocol, memory write (MemWr) operations are called posted requests, while memory read (MemRd) operations are called non-posted requests. Due to PCIe protocol limitations, a write operation cannot pass another posted request (MemWr), and a read operation cannot pass a posted operation (read operation is not allowed to pass posted operations). In the AXI protocol, multiple requests with different identifiers (IDs) can pass each other, thereby improving the efficiency of the ASIC bus channel. According to the PCIe protocol, a memory write operation cannot be issued until all previous memory write operations have completed to avoid the "write after write" (WAW) risk. In the AXI protocol, multiple memory modules can be connected to the bus channel, so different memory write operations can pass each other to improve efficiency. According to the PCIe protocol, a memory read operation cannot be issued until the previous memory write operation has completed to avoid the "read after write" (RAW) risk. In the AXI protocol, the "read after write" risk is solved through software and NoC, so the AXI protocol allows operations on different memory modules to override each other.

[0048] To bridge the gap between the PCIE and AXI protocols and improve system efficiency, the following embodiments describe a PCIE device with a PCIE-AXI bridge function. This PCIE device can convert between the PCIE and AXI protocols. Before a PCIE memory write operation on a bus channel completes, the PCIE device can generate a dummy response in advance, thereby preventing subsequent PCIE requests from being blocked. Because memory write operations request the system cache, HBM (High Bandwidth Memory) can take hundreds of cycles to complete. Due to pending memory writes on the AXI bus, subsequent memory reads may read data from the same address as the pre-written data, resulting in a "read-after-write" risk. Such reads should be blocked until the dependent memory write operation on the bus channel completes. Because the PCIE device processes multiple memory writes simultaneously, two memory writes may write to the same address. The PCIE device maintains the order of these memory writes to avoid the "write-after-write" risk. Some of these limitations can be addressed through NoC design, while others are addressed through the PCIE-AXI bridge function. The following embodiments will demonstrate a PCIE-AXI bridge design, where a PCIE device can convert between the PCIE protocol and the AXI protocol while complying with the rules of both the PCIE protocol and the AXI protocol.

[0049] Figure 1 FIG. 1 is a schematic diagram of a circuit module of a PCIE device 100 according to an embodiment of the present invention. Based on a request from a host 10 , the PCIE device 100 can provide resources (eg, memory space or other hardware resources) to the host 10 . Figure 1 The PCIE device 100 includes a PCIE control circuit 110, an early response circuit 120, a bus channel 130, and a core circuit 140. The bus channel 130 is coupled to the core circuit 140. Based on actual design and application, the core circuit 140 includes a system cache (such as an L2 cache), HBM, or other resource circuits.

[0050] Based on the host 10's request, the core circuit 140 provides the host 10 with resources (e.g., memory space, computing power, or other hardware resources) of the PCIE device 100 via the bus channel 130, the early response circuit 120, and the PCIE control circuit 110. This embodiment does not limit the specific implementation of the bus channel 130. For example, the bus channel 130 includes five channels defined by the AXI protocol: a read address channel AXI_AR, a read data channel AXI_R, a write address channel AXI_AW, a write data channel AXI_W, and a write response channel AXI_B. The read address channel AXI_AR and the read data channel AXI_R are used for read transactions, while the write address channel AXI_AW, the write data channel AXI_W, and the write response channel AXI_B are used for write transactions.

[0051] Figure 2 This is a flow chart of an operating method of a PCIE device according to an embodiment of the present invention. Figure 1 and Figure 2 In step S210, the PCIE control circuit 110 receives a PCIE packet from the host 10. In response to the PCIE packet sent by the host 10, the PCIE control circuit 110 converts the PCIE packet into at least one AXI packet (step S220). The early response circuit 120 is coupled between the PCIE control circuit 110 and the bus channel 130. The AXI packet pre-sent by the PCIE control circuit 110 to the bus channel 130 is transmitted to the early response circuit 120.

[0052] In step S230, in response to the AXI packet (first AXI packet) corresponding to the current PCIE packet (first PCIE packet) sent by the PCIE control circuit 110, which includes a write request to the core circuit 140, the early response circuit 120 transmits the write request to the core circuit 140 via the bus channel 130. Generally speaking, after completing the write request, the core circuit 140 feeds back a response (hereinafter referred to as a true response) to the early response circuit 120 via the bus channel 130. A true response (Real / Genuine / ValidResponse) is a response returned by the target (e.g., the core circuit 140 in the embodiment of the present invention) that carries the data or status information required by the request. Before the core circuit 140 feeds back the true response corresponding to the write request to the early response circuit 120, the early response circuit 120 feeds back a dummy response corresponding to the write request to the PCIE control circuit 110, triggering the PCIE control circuit 110 to send the AXI packet corresponding to the next PCIE packet to the early response circuit 120 in advance (step S240).

[0053] In summary, the early response circuit 120 is arranged between the PCIE control circuit 110 and the bus channel 130. After the PCIE control circuit 110 transmits the AXI packet (write request) corresponding to the current PCIE packet to the bus channel 130 via the early response circuit 120, and before the bus channel 130 returns the true response corresponding to the current PCIE packet (write request), the early response circuit 120 first returns a dummy response corresponding to the current PCIE packet (write request) to the PCIE control circuit 110, triggering the PCIE control circuit 110 to send the AXI packet corresponding to the next PCIE packet in advance. As a result, the PCIE device 100 can improve system efficiency.

[0054] Based on actual designs and applications, in some embodiments, the early acknowledgment circuit 120 includes an outstanding write buffer. In response to a write request issued by the PCIE control circuit 110, the early acknowledgment circuit 120 also records the identifier of the write request in the outstanding write buffer. In response to the PCIE control circuit 110 issuing at least one AXI packet (a second AXI packet) corresponding to another PCIE packet (a second PCIE packet) containing a read request to the core circuit 140, the early acknowledgment circuit 120 checks whether the read request address conflicts with the AXI write request address of any entry in the outstanding write buffer. If the read request address conflicts with the AXI write request address of any entry in the outstanding write buffer, the early acknowledgment circuit 120 waits for the write operation of the conflicting entry in the outstanding write buffer to complete before transmitting the read request to the core circuit 140 via the bus channel 130. In response to the read request address not conflicting with the AXI write request address of any entry in the outstanding write buffer, the early response circuit 120 transmits the read request to the core circuit 140 via the bus channel 130 in real time.

[0055] The data structure of the outstanding write buffer can be defined based on the actual design and application. For example, in some implementations, the outstanding write buffer includes a first busy bit field, a first virtual function identifier (VFID) field, an AXI write request identifier field, and an AXI write request address field. The early acknowledgement circuit 120 records the write request identifier in the AXI write request identifier field and the write request address in the AXI write request address field.

[0056] Based on actual designs and applications, in some embodiments, early acknowledgment circuit 120 also includes a pending read-ordered buffer. In response to a conflict between a read request address and an AXI write request address of any entry in the outstanding write buffer, early acknowledgment circuit 120 compares the read request address with the addresses of all entries in the outstanding write buffer to calculate how many entries in the outstanding write buffer have write operations with the same address as the read request, thereby obtaining the number of conflicting write requests corresponding to the read request. Early acknowledgment circuit 120 records the read request and the number of conflicting write requests in the pending read-ordered buffer.

[0057] The data structure of the pending read buffer can be defined based on the actual design and application. For example, in some implementations, the pending read buffer includes a second busy bit field, a ready bit field, a first AXI write request quantity field, and an AXI read request information field. Early acknowledgement circuit 120 records the read request in the AXI read request information field and the number of conflicting write requests in the first AXI write request quantity field.

[0058] In response to the core circuit 140 feeding back a true response corresponding to the write request to the early response circuit 120, the early response circuit 120 locates an incomplete write entry in the incomplete write buffer based on the identifier of the true response. The early response circuit 120 resets the busy bit field of the incomplete write entry. The early response circuit 120 queries the pending read order buffer based on the AXI write request address of the write request corresponding to the true response to locate the dependent entry corresponding to the AXI write request address in the pending read order buffer. The early response circuit 120 decrements the number of conflicting write requests in the first AXI write request number field of the corresponding entry in the pending read order buffer. In response to the number of conflicting write requests in the first AXI write request number field of the corresponding entry being decremented to an initial value (e.g., a value of 0), the early response circuit 120 sets the ready bit field of the corresponding entry to a ready state (e.g., a logical value of 1), indicating that all write operations dependent on the corresponding entry have completed. In response to the ready bit field of the relevant entry being set to the ready state, the early response circuit 120 transmits the read request corresponding to the relevant entry to the core circuit 140 via the bus channel 130 .

[0059] In response to the PCIE control circuit 110 issuing at least one AXI packet (a second AXI packet) corresponding to another PCIE packet (a second PCIE packet) including an atomic operation (AtomicOp) request to the core circuit 140, the early response circuit 120 checks whether there are any outstanding write requests in the outstanding write buffer. If there are any outstanding write requests in the outstanding write buffer, the early response circuit 120 waits for the outstanding write requests in the outstanding write buffer to complete before transmitting the atomic operation request to the core circuit 140 via the bus channel 130. If there are no outstanding write operations in the outstanding write buffer, the early response circuit 120 immediately transmits the atomic operation request to the core circuit 140 via the bus channel 130.

[0060] Figure 3 FIG. 1 is a circuit module diagram of a PCIE control circuit, an early response circuit, and a bus channel according to an embodiment of the present invention. Figure 3 The PCIE control circuit 110, early response circuit 120 and bus channel 130 shown can be used as Figure 1The PCIE control circuit 110 , the early response circuit 120 , and the bus channel 130 are shown as one of many implementation examples. Figure 3 The host 10, PCIE device 100, PCIE control circuit 110, early response circuit 120, bus channel 130 and core circuit 140 shown in FIG. Figure 1 In the Figure 3 In the illustrated embodiment, the PCIE control circuit 110 includes a PCIE controller 111 and a bridge 112. The early response circuit 120 includes a write controller 121, an uncompleted write buffer 122, a read controller 123, a pending read order buffer 124, an atomic operation controller 125, and an atomic operation buffer 126. The bus channel 130 includes a write address channel AXI_AW, a write data channel AXI_W, a write response channel AXI_B, a read address channel AXI_AR, and a read data channel AXI_R. The write address channel AXI_AW, the write data channel AXI_W, and the write response channel AXI_B are used for write transfer transactions, while the read address channel AXI_AR and the read data channel AXI_R are used for read transfer transactions.

[0061] Depending on the design, in some embodiments, at least one of the PCIE control circuit 110, PCIE controller 111, bridge 112, early response circuit 120, write controller 121, read controller 123, atomic operation controller 125, and core circuit 140 may be implemented as a hardware circuit. In other embodiments, at least one of the PCIE control circuit 110, PCIE controller 111, bridge 112, early response circuit 120, write controller 121, read controller 123, atomic operation controller 125, and core circuit 140 may be implemented as a combination of hardware, firmware, or software (i.e., a program).

[0062] In hardware terms, at least one of the PCIE control circuit 110, PCIE controller 111, bridge 112, early response circuit 120, write controller 121, read controller 123, atomic operation controller 125, and core circuit 140 may be implemented as a logic circuit on an integrated circuit. For example, the functions of at least one of the PCIE control circuit 110, PCIE controller 111, bridge 112, early response circuit 120, write controller 121, read controller 123, atomic operation controller 125, and core circuit 140 may be implemented as various logic blocks, modules, and circuits in at least one hardware controller, microcontroller, hardware processor, microprocessor, ASIC, DSP (digital signal processor), FPGA (field programmable gate array), CPU (central processing unit), or other processing unit. The related functions of at least one of the PCIE control circuit 110, PCIE controller 111, bridge 112, early response circuit 120, write controller 121, read controller 123, atomic operation controller 125 and core circuit 140 can be implemented as hardware circuits using hardware description languages ​​(such as Verilog HDL or VHDL) or other suitable programming languages, such as various logic blocks, modules and circuits in an integrated circuit.

[0063] In software or firmware form, the functions associated with at least one of the PCIE control circuit 110, PCIE controller 111, bridge 112, early response circuit 120, write controller 121, read controller 123, atomic operation controller 125, and core circuit 140 can be implemented as programming codes. For example, at least one of the PCIE control circuit 110, PCIE controller 111, bridge 112, early response circuit 120, write controller 121, read controller 123, atomic operation controller 125, and core circuit 140 can be implemented using a common programming language (e.g., C, C++, or assembly language) or other suitable programming language. The programming codes can be recorded / stored in a "non-transitory machine-readable storage medium." In some embodiments, the non-transitory machine-readable storage medium includes, for example, a semiconductor memory or a storage device. An electronic device (such as a computer, a CPU, a hardware controller, a microcontroller, a hardware processor or a microprocessor) can read and execute the programming code from the non-transitory machine-readable storage medium, thereby realizing the relevant functions of at least one of the PCIE control circuit 110, the PCIE controller 111, the bridge 112, the early response circuit 120, the write controller 121, the read controller 123, the atomic operation controller 125 and the core circuit 140.

[0064] exist Figure 3 In the illustrated embodiment, the PCIE controller 111 converts a PCIE packet received from the host 10 into a PCIE Transaction Layer Packet (TLP). Based on actual design and application, the PCIE controller 111 may include a known PCIE controller or other PCIE controllers. The bridge 112 is coupled to the PCIE controller 111 to receive the PCIE Transaction Layer Packet. The bridge 112 converts the PCIE Transaction Layer Packet into an AXI packet and transmits it to the early response circuit 120. Based on actual design and application, the bridge 112 may include a known bridge or other bridges. In response to the early response circuit 120 feeding back a dummy response corresponding to the AXI packet to the bridge 112, the bridge 112 sends the next AXI packet to the early response circuit 120 in real time. The following describes the workflow of a PCIE memory write operation.

[0065] The PCIE device 100 receives PCIE requests from a host 10 (e.g., a computer, a PCIE switch, or other host device). The PCIE controller 111 converts the received PCIE packets into PCIE transaction layer packets and transmits the transaction layer packets to the bridge 112. The bridge 112 converts the PCIE transaction layer packets into AXI packets, such as AXI read packets and AXI write packets.

[0066] For PCIE write operations, bridge 112 splits a PCIE write request (PCIE packet) into multiple AXI write requests. Multiple AXI write requests corresponding to the same PCIE write request can have different AXI identifiers (IDs) to align their order on bus channel 130 for improved efficiency. Bridge 112 checks AXI write identifier buffer 112a to assign AXI write identifiers to the AXI write requests and transmits the AXI write packets to write controller 121.

[0067] The write controller 121 is coupled to the PCIE control circuit 110 and the bus channel 130. In response to a write request issued by the PCIE control circuit 110, the write controller 121 transmits the write request to the write address channel AXI_AW and the write data channel AXI_W. The write request is then transmitted to the core circuit 140 via the bus channel 130. For each AXI write request sent, when the last of the multiple AXI write requests corresponding to the current PCIE write request (PCIE packet) is forwarded to the write data channel AXI_W, the write controller 121 performs two actions. First, the write controller 121 immediately transmits a dummy response from the write controller 121 to the bridge 112, even though the actual response has not yet been transmitted back to the write controller 121 via the write response channel AXI_B. The write controller 121 feeds the dummy response back to the PCIE control circuit 110 before the core circuit 140 feeds the actual response back to the early response circuit 120. In addition, the write controller 121 records the AXI write request identifier in the outstanding write buffer 122. A dummy response is a response that does not involve actual data transmission and is only used to meet protocol timing or process requirements.

[0068] The unfinished write buffer 122 is coupled to the write controller 121. In response to the write request sent by the PCIE control circuit 110, the write controller 121 also records the identifier of the write request in the unfinished write buffer 122. Figure 3In the illustrated embodiment, each entry in the outstanding write buffer 122 includes a first busy bit field BZ1, a first virtual function identifier field VF_ID1, an AXI write request identifier field AXI_ID, and an AXI write request address field Addr. The first busy bit field BZ1 indicates whether the entry is occupied. The first virtual function identifier field VF_ID1 records the virtual function (VF) identifier from the PCIE request. The AXI write request identifier field AXI_ID records the transmitted AXI write request identifier. The AXI write request address field Addr records the AXI write request address. The write controller 121 records the write request identifier in the AXI write request identifier field AXI_ID and the write controller 121 records the write request address in the AXI write request address field Addr.

[0069] For PCIE read operations, bridge 112 splits a PCIE read request (PCIE packet) into multiple AXI read requests. Multiple AXI read packets corresponding to the same PCIE read request should have the same AXI read identifier. Bridge 112 checks AXI read identifier buffer 112b to assign an AXI read identifier to the AXI read request and transmits the AXI read packet to read controller 123. Read controller 123 is coupled to write controller 121, outstanding write buffer 122, PCIE control circuit 110, and bus channel 130. In response to PCIE control circuit 110 issuing an AXI packet corresponding to the next PCIE packet containing a read request for core circuit 140, read controller 123 checks whether the read request address of the read request conflicts with the AXI write request address of any entry in outstanding write buffer 122. In response to a conflict between the read request address and the AXI write request address of any entry in the outstanding write buffer 122, the read controller 123 waits for the write operation of the conflicting entry in the outstanding write buffer 122 to complete before transmitting the read request to the core circuit 140 via the bus channel 130. In response to a conflict between the read request address and the AXI write request address of any entry in the outstanding write buffer 122, the read controller 123 transmits the read request to the core circuit 140 via the bus channel 130 in real time.

[0070] The pending read order buffer 124 is coupled to the read controller 123. In response to a conflict between the read request address and the AXI write request address of any entry in the uncompleted write buffer 122, the read controller 123 compares the read request address with the addresses of all entries in the uncompleted write buffer 122 to calculate how many entries have write operation addresses that are the same as the read request address, thereby obtaining the number of conflicting write requests corresponding to the read request. The read controller 123 records the read request and the corresponding number of conflicting write requests in the pending read order buffer 124. Figure 3 In the illustrated embodiment, the pending read order buffer 124 includes a second busy bit field BZ2, a ready bit field RD, a first AXI write request quantity field W_cnt, and an AXI read request information field AXI_inf. The second busy bit field BZ2 indicates whether this entry is busy. The ready bit field RD indicates whether all AXI write requests in the outstanding write buffer 122 that the AXI read request depends on have been returned. The first AXI write request quantity field W_cnt records the number of AXI write requests in the outstanding write buffer 122 that the AXI read request in the pending read order buffer 124 depends on. The AXI read request information field AXI_inf records useful AXI read request information. This information in the AXI read request information field AXI_inf is used when a read request is transmitted to the read address channel AXI_AR. The read controller 123 records the read request in the AXI read request information field AXI_inf and the number of conflicting write requests in the first AXI write request quantity field W_cnt.

[0071] Read controller 123 arbitrates requests from pending read buffer 124 and requests from bridge 112. Read controller 123 first checks whether the oldest entry in pending read buffer 124 has its ready bit field RD set to ready (e.g., logic 1). If the ready bit field RD is set to ready, indicating that all dependent AXI write operations for the entry have completed, read controller 123 grants the entry and transmits the corresponding read request to read address channel AXI_AR. Read controller 123 blocks requests from bridge 112 during this cycle. Otherwise, read controller 123 accepts the AXI read request from bridge 112.

[0072] When read controller 123 receives an AXI read request from bridge 112, it checks the outstanding write request address recorded in outstanding write buffer 122 at the 4KB level. If the outstanding AXI write request in outstanding write buffer 122 matches the 4KB address of the received read request, this indicates that the packet may be at risk of a "read-after-write" error. These received read requests should wait until the conflicting write operations in outstanding write buffer 122 complete before being forwarded to read address channel AXI_AR. If there are no 4KB-level conflicts, this indicates that these AXI read requests from the PCIE read request have no dependent write operations in outstanding write buffer 122. These AXI read requests can be directly forwarded to read address channel AXI_AR.

[0073] For AXI read operations with write conflicts at the 4KB level, the AXI read address is compared with the addresses of all entries in the outstanding write buffer 122 at the 512B level to calculate how many entries will be written to the same address as the AXI read request. This AXI read request and the number of entries are then recorded in the AXI read request information field AXI_inf and the first AXI write request number field W_cnt in the pending read order buffer 124.

[0074] When core circuit 140 completes an AXI write operation, its response is transmitted back to write controller 121 via write response channel AXI_B. In response to core circuit 140 feeding back a true response corresponding to the write request to write controller 121, write controller 121 locates the incomplete write entry in outstanding write buffer 122 based on the identifier of the true response. For example, write controller 121 locates the incomplete write entry by comparing the AXI write request identifier field AXI_ID in outstanding write buffer 122. Write controller 121 then resets the first busy bit field BZ1 of the incomplete write entry in the outstanding write buffer 122 to release the corresponding entry. Write controller 121 transmits the address of the found write entry (the AXI write request address of the write request corresponding to the true response) to read controller 123.

[0075] When the read controller 123 receives the address of the AXI write packet (AXI write request address) returned by the write controller 121, the read controller 123 queries the pending read order buffer 124 based on the address of the AXI write packet returned by the write controller 121 to locate the entry in the pending read order buffer 124 corresponding to the AXI write request address (the address of the AXI write packet returned by the write controller 121). The read controller 123 decrements the number of conflicting write requests in the first AXI write request number field W_cnt of the entry corresponding to the AXI write request address in the pending read order buffer 124. In response to the number of conflicting write requests in the first AXI write request number field W_cnt of the entry corresponding to the AXI write request address being decremented to an initial value (e.g., a value of 0), the read controller 123 sets the ready bit field RD of the entry corresponding to the AXI write request address to a ready state (e.g., a logical value of 1), indicating that all write operations dependent on the entry corresponding to the AXI write request address have completed. In response to the ready bit field RD of the entry corresponding to the AXI write request address being set to the ready state, the read controller 123 transmits the read request corresponding to the entry corresponding to the AXI write request address to the core circuit 140 via the bus channel 130 .

[0076] For example, the read controller 123 compares the AXI write request address with the address of each entry in the pending read order buffer 124. If the address of a related entry in the pending read order buffer 124 matches the AXI write request address, the number of conflicting write requests in the first AXI write request quantity field W_cnt of the related entry is decremented. After this decrement, if the number of conflicting write requests in the first AXI write request quantity field W_cnt is 0, the read controller 123 sets the ready bit field RD of the related entry to 1, indicating that all AXI write operations that the related entry depends on have completed and the "read after write" risk has been eliminated. In response to the ready bit field RD of the related entry being set to 1, the read controller 123 transmits the read request corresponding to the related entry to the core circuit 140 via the read address channel AXI_AR.

[0077] The PCIE protocol supports atomic operations. Atomic operations are a high-level synchronization mechanism. They are particularly useful when multiple transmitters or receivers need to synchronize in a non-blocking manner. Atomic operations require that all prior memory write operations have completed before executing the atomic operation. Figure 3 The outstanding write buffer 122 shown can store a large number of unfinished write requests, and the atomic operation controller 125 can record all previously uncompleted AXI write operations from memory write operations in the atomic operation buffer 126 and wait for these write operations to be completed before issuing atomic operation requests. Figure 3 In the illustrated embodiment, the atomic operation buffer 126 includes a third busy bit field BZ3, a second virtual function identifier field VF_ID2, an atomic operation information field Ato_op, and a second AXI write request number field OSD_W. The third busy bit field BZ3 indicates whether the entry is occupied and in use. The second virtual function identifier field VF_ID2 records the identifier of the virtual function on which the atomic operation depends. The atomic operation information field Ato_op records information about the atomic operation. The second AXI write request number field OSD_W records the number of outstanding write operations on which the atomic operation depends.

[0078] The atomic operation controller 125 is coupled to the PCIE control circuit 110, the outstanding write buffer 122, and the bus channel 130. The operation of the atomic operation controller 125 is described as follows. The bridge 112 transmits an atomic operation request to the atomic operation controller 125. In response to the PCIE control circuit 110 issuing at least one AXI packet (a second AXI packet) corresponding to another PCIE packet (a second PCIE packet) including an atomic operation request to the core circuit 140, the atomic operation controller 125 checks whether the outstanding write buffer 122 contains any outstanding write requests. If any outstanding write requests are found in the outstanding write buffer 122, the atomic operation controller 125 waits until the outstanding write requests in the outstanding write buffer 122 are completed before transmitting the atomic operation request to the core circuit 140 via the bus channel 130. If no outstanding write operations are found in the outstanding write buffer 122, the atomic operation controller 125 immediately transmits the atomic operation request to the core circuit 140 via the bus channel 130.

[0079] For example, if there are no outstanding write operations in the outstanding write buffer 122, the atomic operation controller 125 may transmit an atomic operation request to the bus channel 130 for atomic operation execution. If there are any outstanding write operations in the outstanding write buffer 122, the received atomic operation request must wait for these outstanding write operations to complete before being transmitted to the bus channel 130 for execution. Because the AXI identifiers of the write requests are different, the requests may be completed out of order.

[0080] We use the program code in Table 1 below to illustrate how to record the unfinished write operations to be waited for and how to check whether the unfinished write operations have been completed. In the program code shown in Table 1, the first line of program code atomic_osd_wr_d represents the unfinished write operations that this atomic operation request needs to wait for. Assuming that there are M entries in the unfinished write buffer 122, this atomic_osd_wr_d has M bits, each bit representing whether the atomic operation request should wait for the corresponding unfinished write operation. The second line of program code atomic_osd_wr_q represents the atomic_osd_wr_d of the previous cycle. The third line of program code osd_wr_busy represents the busy signal corresponding to the M entries in the unfinished write buffer 122, indicating which unfinished write operations this atomic operation request needs to wait for. The fourth line of program code atomic_osd_wr_d = osd_wr_busy indicates that when the atomic operation request arrives, the current unfinished write operation recorded in atomic_osd_wr_d.

[0081] Table 1: Program code

[0082]

[0083] The fifth line of program code is atomic_osd_wr_d = atomic_osd_wr_q&(~(osd_wr_busy_q&(~osd_wr_busy_d))), where (osd_wr_busy_q&(~osd_wr_busy_d)) indicates that the incomplete write operation was busy in the previous cycle (osd_wr_busy_q==1) and became idle in the current cycle (~osd_wr_busy_d). The bit corresponding to this operation is 1. The program code (~(osd_wr_busy_q&(~osd_wr_busy_d))) indicates that the bit of (osd_wr_busy_q&(~osd_wr_busy_d)) is inverted. If the incomplete write operation is completed in the current cycle, the bit is 0, otherwise it is 1. The program code atomic_osd_wr_q&(~(osd_wr_busy_q&(~osd_wr_busy_d))) indicates that the record is cleared using the result of (~(osd_wr_busy_q&(~osd_wr_busy_d)))). If the M bits in the equation are all 0, it means that the unfinished write operations in this atomic operation request have been completed, and this atomic operation request can be issued. When atomic_osd_wr_d is all 0, it means that all the unfinished write operations that this atomic operation request depends on have been completed. At this time, this atomic operation request can be sent to the bus channel 130.

[0084] In the PCIE protocol, a memory write operation cannot overtake another. To achieve higher efficiency, after the write controller 121 transmits the AXI packet corresponding to a memory write request to the bus channel 130, it immediately returns a "Completion without Data (Cpl)" or "Completion with Data (CplD)" response to the bridge 112, rather than waiting for a true response (returned via the write response channel AXI_B) from the target core circuitry 140 (e.g., L2 cache, HBM, etc.). This allows multiple memory write requests to be in progress (on-the-fly, not yet reaching the target memory). For two memory write requests, the first memory write request MemWr_1 and the second memory write request MemWr_2, the PCIE device 100 maintains the order of the memory write requests. If the target addresses of the first memory write request MemWr_1 and the second memory write request MemWr_2 are different, there is no risk of a "write-behind-the-write" error. Therefore, the order of the two memory write requests can be changed without affecting the final result. If the first memory write request MemWr_1 and the second memory write request MemWr_2 have the same target address, the order of the two memory write requests cannot be changed, otherwise the final memory result will be changed. The order of the first memory write request MemWr_1 and the second memory write request MemWr_2 is maintained by the PCIE controller 111 and the bridge 112 before being transmitted to the core circuit 140. The PCIE device 100 maintains the order of requests sent to the same address on the bus channel 130.

[0085] To address the "read-after-write" risk, a read operation must wait for a write operation to complete, otherwise outdated data will be read. In the PCIE device 100, the early acknowledgment circuit 120 checks for the "read-after-write" risk upon receiving an AXI request packet from the bridge 112 and pushes the read operation to the pending read order buffer 124. The early acknowledgment circuit 120 issues the pending AXI read operation only after all dependent memory write operations have completed. This mitigates the "read-after-write" risk.

[0086] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A PCIE device, characterized in that: include: A bus channel coupled to the core circuit of the PCIE device; The PCIE control circuit receives a first PCIE packet from a host and converts the first PCIE packet into at least one first AXI packet; as well as An early response circuit is coupled between the PCIE control circuit and the bus channel, wherein In response to the at least one first AXI packet sent by the PCIE control circuit including a write request to the core circuit, the early response circuit transmits the write request to the core circuit through the bus channel, and before the core circuit feeds back a true response corresponding to the write request to the early response circuit, the early response circuit feeds back a dummy response corresponding to the write request to the PCIE control circuit, so as to trigger the PCIE control circuit to send an AXI packet corresponding to the next PCIE packet in advance; The true response refers to a response returned by the target and carrying the data or status information required by the request, and the dummy response refers to a response without actual data transmission and only used to meet the protocol timing or process requirements.

2. The PCIE device according to claim 1, wherein: The PCIE control circuit includes: The PCIE controller converts the received first PCIE packet into a first PCIE transaction layer packet; and a bridge coupled to the PCIE controller to receive the first PCIE transaction layer packet, wherein the bridge converts the first PCIE transaction layer packet into the first AXI packet to the early response circuit, and In response to the early response circuit feeding back the dummy response corresponding to the first AXI packet to the bridge, the bridge sends the next AXI packet to the early response circuit in real time.

3. The PCIE device according to claim 1, wherein: The early response circuit includes: Outstanding write buffer, where In response to the write request sent by the PCIE control circuit, the early response circuit further records an identifier of the write request in the uncompleted write buffer; In response to the PCIE control circuit sending at least one second AXI packet corresponding to the second PCIE packet including a read request for the core circuit, the early response circuit checks whether a read request address of the read request conflicts with an AXI write request address of any entry in the outstanding write buffer; In response to a conflict between the read request address and the AXI write request address of any entry in the outstanding write buffer, the early response circuit waits for a write operation of the conflicting entry in the outstanding write buffer to complete before transmitting the read request to the core circuit via the bus channel; and In response to the read request address not conflicting with the AXI write request address of any entry in the outstanding write buffer, the early response circuit transmits the read request to the core circuit via the bus channel in real time.

4. The PCIE device according to claim 3, wherein: The unfinished write buffer includes a first busy bit field, an AXI write request identifier field, and an AXI write request address field. The early response circuit records the identifier of the write request in the AXI write request identifier field, and the early response circuit records the address of the write request in the AXI write request address field.

5. The PCIE device according to claim 4, wherein: The early response circuit further includes: Pending read order buffer, where In response to a conflict between the read request address and the AXI write request address of any entry in the outstanding write buffer, the early response circuit compares the read request address with the addresses of all entries in the outstanding write buffer to calculate how many entries have write operation addresses that are the same as the read request address, thereby obtaining a number of conflicting write requests corresponding to the read request; and The early response circuit records the read request and the number of conflicting write requests in the to-be-processed read order buffer.

6. The PCIE device according to claim 5, wherein: The pending read order buffer includes a ready bit field, a first AXI write request quantity field and an AXI read request information field. The early response circuit records the read request in the AXI read request information field, and the early response circuit records the number of conflicting write requests in the first AXI write request quantity field.

7. The PCIE device according to claim 6, wherein: In response to the core circuit feeding back the true response corresponding to the write request to the early response circuit, the early response circuit finds the incomplete write entry in the incomplete write buffer based on the identifier of the true response; The early response circuit resets the first busy bit field of the incomplete write entry; The early response circuit queries the pending read order buffer based on the AXI write request address of the write request corresponding to the true response to find a related entry corresponding to the AXI write request address in the pending read order buffer; as well as The early acknowledgement circuit reduces the number of conflicting write requests in the first AXI write request number field of the relevant entry in the pending read order buffer.

8. The PCIE device according to claim 7, wherein: In response to the conflicting write request number of the first AXI write request number field of the relevant entry being reduced to an initial value, the early response circuit sets the ready bit field of the relevant entry to a ready state, indicating that all write operations that the relevant entry depends on have been completed.

9. The PCIE device according to claim 8, wherein: In response to the ready bit field of the relevant entry being set to the ready state, the early response circuit transmits the read request corresponding to the relevant entry to the core circuit through the bus channel.

10. The PCIE device according to claim 1, wherein: The early response circuit includes: Outstanding write buffer, where In response to the write request sent by the PCIE control circuit, the early response circuit further records an identifier of the write request in the uncompleted write buffer; In response to the PCIE control circuit sending at least one second AXI packet corresponding to the second PCIE packet including an atomic operation request for the core circuit, the early response circuit checks whether there is any outstanding write request in the outstanding write buffer; In response to any incomplete write request in the incomplete write buffer, the early response circuit waits for the incomplete write request in the incomplete write buffer to be completed before transmitting the atomic operation request to the core circuit through the bus channel; and In response to there being no uncompleted write operation in the uncompleted write buffer, the early response circuit transmits the atomic operation request to the core circuit via the bus channel in real time.

11. The PCIE device according to claim 1, wherein: The early response circuit includes: A write controller is coupled to the PCIE control circuit and the bus channel, wherein In response to the write request issued by the PCIE control circuit, the write controller transmits the write request to the core circuit through the bus channel, and before the core circuit feeds back the true response to the early response circuit, the write controller feeds back the dummy response to the PCIE control circuit.

12. The PCIE device according to claim 11, wherein: The early response circuit further includes: an unfinished write buffer coupled to the write controller; and A read controller is coupled to the write controller, the unfinished write buffer, the PCIE control circuit and the bus channel, wherein In response to the write request sent by the PCIE control circuit, the write controller further records an identifier of the write request into the uncompleted write buffer; In response to the PCIE control circuit sending at least one second AXI packet corresponding to the second PCIE packet including a read request for the core circuit, the read controller checks whether a read request address of the read request conflicts with an AXI write request address of any entry in the outstanding write buffer; In response to a conflict between the read request address and the AXI write request address of any entry in the outstanding write buffer, the read controller waits for a write operation of the conflicting entry in the outstanding write buffer to complete before transmitting the read request to the core circuit via the bus channel; and In response to the read request address not conflicting with the AXI write request address of any entry in the outstanding write buffer, the read controller transmits the read request to the core circuit via the bus channel in real time.

13. The PCIE device according to claim 12, wherein: The unfinished write buffer includes a first busy bit field, an AXI write request identifier field, and an AXI write request address field. The write controller records the identifier of the write request in the AXI write request identifier field, and the write controller records the address of the write request in the AXI write request address field.

14. The PCIE device according to claim 13, wherein: The early response circuit further includes: A read order buffer to be processed is coupled to the read controller, wherein In response to a conflict between the read request address and the AXI write request address of any entry in the outstanding write buffer, the read controller compares the read request address with addresses of all entries in the outstanding write buffer to calculate how many entries have write operation addresses that are the same as the read request address, thereby obtaining a number of conflicting write requests corresponding to the read request; and The read controller records the read request and the number of conflicting write requests in the to-be-processed read order buffer.

15. The PCIE device according to claim 14, wherein: The pending read order buffer includes a ready bit field, a first AXI write request quantity field, and an AXI read request information field. The read controller records the read request in the AXI read request information field, and the read controller records the number of conflicting write requests in the first AXI write request quantity field.

16. The PCIE device according to claim 15, wherein: In response to the core circuit feeding back the true response corresponding to the write request to the write controller, the write controller finds the incomplete write entry in the incomplete write buffer based on the identifier of the true response; The write controller resets the first busy bit field of the incomplete write entry; The write controller transmits the AXI write request address of the write request corresponding to the true response to the read controller; The read controller queries the pending read order buffer based on the AXI write request address to find a related entry corresponding to the AXI write request address in the pending read order buffer; and The read controller reduces the number of conflicting write requests in the first AXI write request number field of the relevant entry in the pending read order buffer.

17. The PCIE device according to claim 16, wherein: In response to the conflicting write request number of the first AXI write request number field of the relevant entry being reduced to an initial value, the read controller sets the ready bit field of the relevant entry to a ready state, indicating that all write operations that the relevant entry depends on have been completed.

18. The PCIE device according to claim 17, wherein: In response to the ready bit field of the relevant entry being set to the ready state, the read controller transmits a read request corresponding to the relevant entry to the core circuit through the bus channel.

19. The PCIE device according to claim 11, wherein: The early response circuit further includes: an unfinished write buffer coupled to the write controller; and An atomic operation controller is coupled to the unfinished write buffer, the PCIE control circuit and the bus channel, wherein In response to the write request sent by the PCIE control circuit, the write controller further records an identifier of the write request into the uncompleted write buffer; In response to the PCIE control circuit sending at least one second AXI packet corresponding to the second PCIE packet including an atomic operation request for the core circuit, the atomic operation controller checks whether there is any outstanding write request in the outstanding write buffer; In response to any incomplete write request in the incomplete write buffer, the atomic operation controller waits for the incomplete write request in the incomplete write buffer to be completed before transmitting the atomic operation request to the core circuit via the bus channel; and In response to there being no uncompleted write operation in the uncompleted write buffer, the atomic operation controller transmits the atomic operation request to the core circuit via the bus channel in real time.

20. A method for operating a PCIE device, characterized in that: include: The PCIE control circuit of the PCIE device receives a first PCIE packet from a host; The PCIE control circuit converts the first PCIE packet into at least one first AXI packet, wherein the early response circuit of the PCIE device is coupled between the PCIE control circuit and a bus channel of the PCIE device, and the bus channel is coupled to the core circuit of the PCIE device; In response to the at least one first AXI packet sent by the PCIE control circuit including a write request to the core circuit, the early response circuit transmits the write request to the core circuit through the bus channel; as well as Before the core circuit feeds back the true response corresponding to the write request to the early response circuit, the early response circuit feeds back the dummy response corresponding to the write request to the PCIE control circuit to trigger the PCIE control circuit to send an AXI packet corresponding to the next PCIE packet in advance; The true response refers to a response returned by the target and carrying the data or status information required by the request, and the dummy response refers to a response without actual data transmission and only used to meet the protocol timing or process requirements.

21. The operating method according to claim 20, characterized in that: Also includes: The PCIE controller of the PCIE control circuit converts the received first PCIE packet into a first PCIE transaction layer packet, wherein the bridge of the PCIE control circuit is coupled to the PCIE controller to receive the first PCIE transaction layer packet; The bridge converts the first PCIE transaction layer packet into the first AXI packet and sends it to the early response circuit; as well as In response to the early response circuit feeding back the dummy response corresponding to the first AXI packet to the bridge, the bridge sends the next AXI packet to the early response circuit in real time.

22. The operating method according to claim 20, characterized in that: Also includes: In response to the write request sent by the PCIE control circuit, the early response circuit records the identifier of the write request in an uncompleted write buffer of the early response circuit; In response to the PCIE control circuit sending at least one second AXI packet corresponding to the second PCIE packet including a read request for the core circuit, the early response circuit checks whether a read request address of the read request conflicts with an AXI write request address of any entry in the uncompleted write buffer; In response to a conflict between the read request address and the AXI write request address of any entry in the outstanding write buffer, the early response circuit waits for a write operation of the conflicting entry in the outstanding write buffer to complete before transmitting the read request to the core circuit via the bus channel; as well as In response to the read request address not conflicting with the AXI write request address of any entry in the incomplete write buffer, the early response circuit transmits the read request to the core circuit via the bus channel in real time.

23. The operating method according to claim 22, characterized in that: The outstanding write buffer includes a first busy bit field, an AXI write request identifier field, and an AXI write request address field, and the operating method further includes: The early response circuit records the identifier of the write request into the AXI write request identifier field; and The early response circuit records the address of the write request into the AXI write request address field.

24. The operating method according to claim 23, characterized in that: Also includes: In response to a conflict between the read request address and the AXI write request address of any entry in the outstanding write buffer, the early response circuit compares the read request address with addresses of all entries in the outstanding write buffer to calculate how many entries have write operation addresses that are the same as the read request address, thereby obtaining a number of conflicting write requests corresponding to the read request; as well as The early response circuit records the number of the read request and the conflicting write request in a to-be-processed read sequence buffer of the early response circuit.

25. The operating method according to claim 24, characterized in that: The to-be-processed read order buffer includes a ready bit field, a first AXI write request quantity field, and an AXI read request information field. The operation method further includes: The early response circuit records the read request into the AXI read request information field; and The early response circuit records the number of conflicting write requests into the first AXI write request number field.

26. The operating method according to claim 25, characterized in that: Also includes: In response to the core circuit feeding back the true response corresponding to the write request to the early response circuit, the early response circuit finds the incomplete write entry in the incomplete write buffer based on the identifier of the true response; resetting, by the early response circuit, the first busy bit field of the incomplete write entry; The early response circuit queries the pending read order buffer based on the AXI write request address of the write request corresponding to the true response to find a related entry corresponding to the AXI write request address in the pending read order buffer; as well as The early response circuit reduces the number of conflicting write requests in the first AXI write request number field of the relevant entry in the pending read order buffer.

27. The operating method according to claim 26, characterized in that: Also includes: In response to the conflicting write request number of the first AXI write request number field of the relevant entry being reduced to an initial value, the early response circuit sets the ready bit field of the relevant entry to a ready state, indicating that all write operations that the relevant entry depends on have been completed.

28. The operating method according to claim 27, characterized in that: The operation method further includes: In response to the ready bit field of the relevant entry being set to the ready state, the early response circuit transmits the read request corresponding to the relevant entry to the core circuit via the bus channel.

29. The operating method according to claim 20, characterized in that: Also includes: In response to the write request sent by the PCIE control circuit, the early response circuit records the identifier of the write request in an uncompleted write buffer of the early response circuit; In response to the PCIE control circuit sending at least one second AXI packet corresponding to the second PCIE packet including an atomic operation request for the core circuit, the early response circuit checks whether there is any uncompleted write request in the uncompleted write buffer; In response to any uncompleted write request in the uncompleted write buffer, the early response circuit waits for the uncompleted write request in the uncompleted write buffer to be completed before transmitting the atomic operation request to the core circuit through the bus channel; as well as In response to there being no uncompleted write operation in the uncompleted write buffer, the early response circuit transmits the atomic operation request to the core circuit via the bus channel in real time.

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