Time sequence path analysis method and system

Abstract

According to the time sequence path analysis method and system provided by the invention, the time sequence allowance of each time sequence source point is calculated, the path analysis is carried out from the time sequence source point with the minimum time sequence allowance to find out the key paths, and when the number of the key paths reaches the number required by a user, the analysis is stopped, so that the analysis of a lot of useless paths is reduced, and the user experience is improved. The analysis time is saved, when the number of the paths meets the requirement, the paths are critical paths, compared with the prior art that all the paths need to be analyzed to find out the critical paths, the analysis time is greatly shortened, and the effect is very obvious especially when the number of devices is large.

Description

Technical Field

[0001] The present invention belongs to the field of FPGA technology, and in particular relates to a timing path analysis method and system. Background Art

[0002] When using FPGAs, EDA (Electronic Design Automation) software is an indispensable component. Timing analysis is particularly important, verifying whether the designed circuit meets design requirements. Static Timing Analysis (STA) is commonly referred to as timing analysis. Full-path timing analysis can display all critical paths from input points to registers, registers to registers, and registers to outputs to the customer. This plays a crucial role in helping customers design effective circuits.

[0003] When performing STA, the circuit is first abstracted into a diagrammatic topology and the components within it are abstracted. The entire circuit is represented by a netlist, with each component abstracted into a unit, and information such as ports, pins, and registers within the unit abstracted into points. The goal of timing analysis is to identify hidden timing issues and, based on the timing analysis results, optimize the logic or constraints to achieve timing closure. Finding a valid path within these timing netlists, which consist of tens of millions or even hundreds of millions of points, is extremely complex, requiring trillions of calculations. A method is needed to reduce the number of calculations while still achieving the desired goal.

[0004] A timing netlist is a directed graph with connections and delays, created based on the user design and timing model. The source of a timing path must be a register output port, and the destination must be a register input port. Based on this characteristic, the source and destination points of all timing paths are recorded.

[0005] In digital circuits, the critical path typically refers to the longest path in the timing sequence, the path that determines the circuit's maximum operating speed. For FPGAs, this may involve factors such as routing delays between logic blocks, combinatorial logic delays, and clock skew. Timing slack (S) is used as a criterion for determining a critical path; the smaller the timing slack, the more critical the path. Timing slack = Required duration (r) - Arrival duration (A).

[0006] Existing timing path analysis analyzes all timing sources to identify the most critical paths, with detailed path information for each path. However, timing reports only save critical paths, resulting in significant time wasted generating useless timing paths.

[0007] There are two main types of paths in the timing report: those with timing margin information and those without. Timing paths with timing margin include simultaneous clock paths, cross-clock paths, and asynchronous clock paths. Clock paths without timing margin include user-ignored paths and unconstrained paths. Summary of the Invention

[0008] The present invention mainly solves the problem of how to quickly find a valid path in a timing netlist, and provides a timing path analysis method and system.

[0009] In order to solve the above technical problems, the technical solutions adopted are: A timing path analysis method includes the following steps: Step 1: Create a timing netlist based on the timing model and user netlist information. The timing netlist includes timing points and directed timing edges. Timing points are used to represent devices, and directed timing edges are used to represent device connection relationships and signal directions. Step 2: Calculate the timing margin of each timing source point and sort the timing sources from small to large according to the timing margin of each timing source point; Step 3: Analyze the timing path from the timing source point with the minimum timing margin along the fan-out point direction to find the critical path; Step 4: When the number of critical paths reaches the number required by the user, stop the analysis and generate a timing report.

[0010] Furthermore, the method to create a timing netlist is: Step 1.1: Obtain the connection relationship between the device's internal input port and output port based on the timing model and create the connection within the device; Step 1.2: Obtain the connections between devices based on the user netlist and create the connection relationship between the devices to obtain the timing netlist. When creating, if the device has a register, use the output port of the register as the source point of the timing path and the input port of the register as the target point of the timing path.

[0011] Furthermore, the calculation method of the timing margin of each timing source point is: Step 2.1: Layer the timing points in the timing netlist. All source points are in the first layer. The fan-out point level is the current level plus 1. The fan-out point is used as the current timing point. The level of the fan-out point of the current timing point is plus 1 based on the level of the current timing point. This is repeated in this way, so that each timing point has level information. For a fan-out timing point that is a timing point of multiple different levels, the level of the fan-out timing point is saved as the maximum level of its predecessor point plus 1. Step 2.2: Classify the time series points according to the hierarchical information, put the time series points of the same level into the same container, and sort the containers according to the hierarchical information; Step 2.3: Calculate the arrival time of the timing point: Traverse all containers in ascending order from the smallest level. When traversing each container, it is necessary to traverse each time point in the container and calculate the arrival time of each time point. The arrival time of each time point is the arrival time of the current time point plus the signal delay. The arrival time of all time points in the first-level container is 0. After traversing all time points in each container, continue to traverse the next container. Step 2.4: Calculate the required time for the timing point: Traverse all containers from largest to smallest hierarchically. When traversing each container, traverse each timing point in the container and calculate the required time for each timing point. If the current timing point is the timing target point, obtain the required time based on the target register. Otherwise, subtract the signal delay from the required time of the fan-out point of the current timing point as the required time for the current timing point. After traversing all timing points in each container, continue traversing the next container. Step 2.5: After all containers are traversed, subtract the arrival time from the required time of each timing source to obtain the timing margin of each timing source.

[0012] Furthermore, starting from the timing source point with the minimum timing margin and analyzing the timing path along the fan-out point, the method to find the critical path is: Step 3.1: Sort the timing margins of each timing source point from small to large; Step 3.2: Starting from the source point with the smallest timing margin, create a timing subnet for the source point. The timing subnet is to use the fan-out point of the current source point as the connection timing point of the current source point, then use the fan-out point as the current point, find the fan-out point of the current point as the connection timing point of the current point, and repeat this step until the current point has no fan-out point. The timing subnet of the current source point is obtained. When the fan-out point is the target point of the timing path, it is recorded in the target point list; Step 3.3: Create predecessor point, delay and transition state information for the timing point in the timing subnet; Step 3.4: Get the target points from the target point list, pass through the predecessor points of each target point, and then use the predecessor points as the current point. Then, push forward through the predecessor points of the current point to obtain the timing points of a timing path between each target point and the timing source point. Step 3.5: Obtain the driving clock based on the source and destination points of each timing path. Calculate the clock period based on the driving clock as the required time, and use the delay at the destination point as the arrival time to calculate the timing margin of each timing path. Step 3.6: Compare the timing margins of multiple timing paths starting from a source point and select the path with the smallest timing margin as the critical path of the current source point.

[0013] Furthermore, when creating a timing subnet for each timing source point, the hierarchical information of each timing point in the subnet is the same as the hierarchical information in the timing netlist.

[0014] Furthermore, a method for creating predecessor point, delay and transition state information for a timing point in the timing subnet is: Step 3.3.1: Generate the delay information of the timing source point. The delay information of the timing source point includes rising edge delay and falling edge delay; Step 3.3.2: Create delay information for the fan-out point of the timing source point. The predecessor point of the fan-out point is the timing source point, and the delay of the fan-out point is the fan-out delay of the timing source point. Step 3.3.3: Traverse the timing subnet, starting from the second-layer timing point of the timing subnet. Based on the delay information of the current timing point, find the fan-out point of the current timing point in the timing subnet. The predecessor point of the fan-out point is the current timing point, and the delay information of the fan-out point is the timing delay of the current timing point plus the fan-out delay of the current timing point. Step 3.3.4: Traverse the timing points in the timing subnet hierarchy in sequence. After the traversal is completed, each timing point has predecessor point and delay information.

[0015] Furthermore, the fan-out delay at the current timing point needs to determine the rising edge delay or the falling edge delay of the fan-out signal according to the transition state of the current timing point and the transition state of the fan-out signal.

[0016] Furthermore, when generating a timing report, the device and port names used in the timing path are obtained, and device name and port hash tables are created respectively. The timing path stores the hash values ​​corresponding to the device names and port names. When displaying the timing path, the device name and port are searched in the hash table based on the hash value, and the path information is displayed in the timing report.

[0017] The present invention also provides a timing path analysis system, which is implemented using the steps of a timing path analysis method.

[0018] By adopting the above technical solution, the present invention has the following beneficial effects: The present invention provides a timing path analysis method and system. By calculating the timing margin of each timing source point, the system analyzes the path starting from the source point with the smallest timing margin to identify the critical path. Analysis stops when the number of critical paths reaches the user's required number, thereby reducing the analysis of many useless paths and saving analysis time. Furthermore, when the required number of paths is reached, these paths are identified as critical paths. Compared to the existing method, which requires analyzing all paths to identify the critical path, analysis time is significantly shortened, especially when the number of devices is large. For example, using a 10 million-gate circuit, the traditional analysis method takes 540 seconds, while the method of the present invention reduces the time to 32 seconds. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a flow chart of the system of the present invention; Figure 2 Express intent for the time series network; Figure 3 Calculate the arrival time flow chart for each timing point; Figure 4 A time calculation flow chart is required for each timing point. DETAILED DESCRIPTION

[0020] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0021] Figures 1 to 4 A specific embodiment of a timing path analysis method of the present invention is shown. Figure 1 As shown, the following steps are included: Step 1: Create a timing netlist based on the timing model and user netlist information. The timing netlist includes timing points and directed timing edges. Timing points are used to represent devices, and directed timing edges are used to represent device connection relationships and signal directions.

[0022] In this embodiment, the method for creating a timing netlist is: Step 1.1: Based on the timing model, obtain the internal connections between the device's input and output ports and create internal connections. The timing model stores basic device information, including port names and types, internal port connections, input port connections to output ports, and internal connection delays. Loading the timing model will reveal the internal device connections.

[0023] Step 1.2: Obtain the connections between devices based on the user netlist and create the connection relationship between devices to obtain the timing netlist. When creating, if the device has a register, use the output port of the register as the source point of the timing path, and the input port of the register as the target point of the timing path. The user netlist is a description of the connection relationship generated based on the user code. Load the user netlist to obtain the connection relationship between devices. Figure 2 The timing netlist shown shows the connection relationship between the three devices and the connection relationship within the device.

[0024] Step 2: Calculate the timing margin of each timing source point and sort the timing sources from small to large according to the timing margin of each timing source point.

[0025] A complete timing path is composed of multiple signals, and a signal may also be part of multiple paths. During the layout and routing stage, it is impossible to determine which information belongs to a timing path, and it is impossible to confirm which signals are critical path signals. In this embodiment, based on the characteristics of the timing path, the timing margin of the information on a path is consistent. The arrival time can be pushed back from the source point of the timing path, and the arrival time of each timing point can be recorded. The required time can be pushed forward from the target point of the timing path, and the required time of each point can be recorded. Then, based on the arrival time and required time of each timing point, the timing margin of each timing point can be calculated, and the timing margin of the timing source point can be known.

[0026] In this embodiment, the calculation method of the timing margin of each timing source point is: Step 2.1: Layer the timing points in the timing netlist. All source points are in the first layer. The fan-out point level is the current level plus 1. The fan-out point is used as the current timing point, and the fan-out level of the current timing point is increased by 1 based on the current timing point level. This is repeated in this manner, ensuring that each timing point has level information. For a fan-out timing point that is a timing point of multiple different levels, the level of the fan-out timing point is saved as the level corresponding to the timing point with the highest level as its predecessor, plus 1. Since calculating the timing slack is a process of calculating delay from front to back and back to front, to facilitate the forward and backward push process, this embodiment layers and containers the timing points in the timing netlist for easier calculation.

[0027] Step 2.2: Classify the time series points according to the hierarchical information, put the time series points of the same level into the same container, and sort the containers according to the hierarchical information.

[0028] Step 2.3: Calculate the arrival time of the timing point, such as Figure 3As shown, all containers are traversed in ascending order from the smallest level to the largest. When traversing each container, it is necessary to traverse each time point in the container and calculate the arrival time of each time point. The arrival time of each time point is the arrival time of the current time point plus the signal delay. The arrival time of all time points in the first-level container is 0. After all time points in each container are traversed, continue to traverse the next container.

[0029] Step 2.4: Calculate the required time of the timing point, such as Figure 4 As shown, all containers are traversed from large to small hierarchically. When traversing each container, each timing point in the container is traversed and the required time of each timing point is calculated. If the current timing point is the timing target point, the required time is obtained according to the target register. Otherwise, the required time of the fan-out point of the current timing point minus the signal delay is used as the required time of the current timing point. After all timing points in each container are traversed, the next container is traversed.

[0030] The required time generally refers to the time it takes for the target register to receive data within the required time. This is typically the clock cycle plus the target register clock path delay. This can be equated to the register input port, i.e., the target point in the timing path. Because the length of the timing path varies, the timing target points vary by layer. Timing target points may be encountered while traversing each container layer, and the required time for each target point must be calculated. The required time for other points in the timing path is the required time of the fan-out point minus the signal delay.

[0031] Step 2.5: After all containers are traversed, subtract the arrival time from the required time of each timing source to obtain the timing margin of each timing source.

[0032] In this embodiment, after the timing margin of each timing source point is obtained, all the timing source points are sorted from small to large, and the sorted timing path source points are saved in a designated file.

[0033] Step 3: Analyze the timing path from the timing source point with the minimum timing margin along the fan-out point direction to find the critical path.

[0034] When analyzing the timing path, the goal is to find the critical path among all timing paths. The analysis starts from the source point with the smallest timing margin because the timing margin is the standard for measuring whether the circuit has timing violations. The smaller the timing margin, the more critical the path. The timing margins of the timing points on the critical path are the same, so by finding the timing source point with the smallest timing margin, the critical path can be found.

[0035] The analysis process of a timing path: There may be a lot of timing paths from the source point to the target point. Timing analysis is to find a path with the longest delay as the timing path. When the path with the longest delay meets the timing requirements, the other paths will definitely meet the timing requirements. Therefore, this embodiment pushes back from the source point layer by layer according to the hierarchy of the netlist, so that each timing point can obtain the predecessor point and delay information. When traversing to the target point, the information of all complete timing paths can be obtained. However, since the timing netlist is very large, there will be a lot of useless information when traversing the netlist hierarchy, which wastes a lot of time. In order to solve this problem, this embodiment sorts the timing margins of the timing source points, starts analyzing one by one from the timing source point with the smallest timing margin, and when the number of timing paths meets the user's requirements, no further analysis is performed, thereby saving analysis time.

[0036] In this embodiment, the method for analyzing the timing path from the timing source point with the minimum timing margin along the fan-out point direction to find the critical path is: Step 3.1: Sort the timing margins of each timing source point from small to large; Step 3.2: Starting from the source point with the smallest timing margin, create a timing subnet for the source point. The timing subnet refers to using the fan-out point of the current source point as the connection timing point of the current source point, then using the fan-out point as the current point, finding the fan-out point of the current point as the connection timing point of the current point, and repeating this step until the current point has no fan-out point. The timing subnet of the current source point is obtained. When the fan-out point is the target point of the timing path, it is recorded in the target point list.

[0037] In this embodiment, a separate timing subnet is created for each timing source point, so that each timing source point only performs path analysis in its own subnet. There is no need to perform traversal analysis on all points at each level in the timing netlist, which avoids useless traversal and saves analysis time.

[0038] When creating a timing subnet for each timing source, the hierarchical information of each timing point in the subnet is the same as that in the timing netlist. Although a timing subnet is created, the hierarchy of the timing subnet in the timing netlist remains the same. However, the timing points related to the timing source are extracted to form the timing subnet. Timing points unrelated to the timing source do not need to be traversed and analyzed, saving analysis time.

[0039] Step 3.3: Create predecessor point, delay and transition status information for the timing point in the timing subnet.

[0040] In this embodiment, the method for creating the predecessor point, delay and transition state information for the timing point in the timing subnet is: Step 3.3.1: Generate the delay information of the timing source point. The delay information of the timing source point includes rising edge delay and falling edge delay; Step 3.3.2: Create delay information for the fan-out point of the timing source point. The predecessor point of the fan-out point is the timing source point, and the delay of the fan-out point is the fan-out delay of the timing source point. Step 3.3.3: Traverse the timing subnet, starting from the second-layer timing point of the timing subnet. Based on the delay information of the current timing point, find the fanout point of the current timing point in the timing subnet. The predecessor of this fanout point is the current timing point, and the delay information of this fanout point is the timing delay of the current timing point plus the fanout delay of the current timing point. As shown in Tables 1 and 2, the fanout delay of the current timing point needs to be calculated based on whether the current timing source point is on the rising or falling edge, the transition state of the current timing point, and the transition state of the fanout signal.

[0041] Table 1 Timing source rising edge delay to obtain delay status

[0042] Table 2 Timing source falling edge delay to obtain the lower delay state

[0043] Step 3.3.4: Traverse the timing points in the timing subnet hierarchy in sequence. After the traversal is completed, each timing point has predecessor point and delay information. Step 3.4: Get the target points from the target point list respectively, pass through the predecessor points of each target point, and then use the predecessor points as the current point. Then, push forward through the predecessor points of the current point to obtain the timing points of a timing path between each target point and the timing source point.

[0044] Step 3.5: Obtain the driving clock based on the source and destination points of each timing path. Calculate the clock period based on the driving clock as the required time, and use the delay at the destination point as the arrival time to calculate the timing margin of each timing path. Step 3.6: Compare the timing margins of multiple timing paths starting from a source point and select the path with the smallest timing margin as the critical path of the current source point.

[0045] Step 4: When the number of critical paths reaches the number required by the user, stop the analysis and generate a timing report.

[0046] In this embodiment, when generating a timing report, the device and port names used in the timing path are retrieved, and device name and port hash tables are created, respectively. The timing path stores the hash values ​​corresponding to the device and port names. When displaying the timing path, the device name and port are searched in the hash table based on the hash values, and the resulting path information is displayed in the timing report. Existing timing paths store the serial numbers of the timing points. The timing report displays information such as the device names, types, and input and output ports that the timing path passes through. This information is retrieved from the timing netlist based on the serial numbers of the timing points. A single device may exist in multiple timing paths. If this device information were stored in each path, data redundancy would result and storage space would be wasted. By storing the hash values ​​corresponding to the device and port names in the timing path, storage space can be reduced and data redundancy can be avoided.

[0047] The present invention also provides a timing path analysis system, which is implemented using the steps of a timing path analysis method.

[0048] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A timing path analysis method, characterized in that: The following steps are involved: Step 1: Create a timing netlist based on the timing model and user netlist information. The timing netlist includes timing points and directed timing edges. Timing points are used to represent devices, and directed timing edges are used to represent device connection relationships and signal directions. Step 2: Calculate the timing margin of each timing source point and sort the timing sources from small to large according to the timing margin of each timing source point; Step 3: Analyze the timing path from the timing source point with the minimum timing margin along the fan-out point direction to find the critical path; Step 4: When the number of critical paths reaches the number required by the user, stop the analysis and generate a timing report.

2. A timing path analysis method according to claim 1, characterized in that: The method to create a timing netlist is: Step 1.1: Obtain the connection relationship between the device's internal input port and output port based on the timing model and create the connection within the device; Step 1.2: Obtain the connections between devices based on the user netlist and create the connection relationship between the devices to obtain the timing netlist. When creating, if the device has a register, use the output port of the register as the source point of the timing path and the input port of the register as the target point of the timing path.

3. The timing path analysis method according to claim 2, wherein: The calculation method of the timing margin of each timing source point is: Step 2.1: Layer the timing points in the timing netlist. All source points are in the first layer. The fan-out point level is the current level plus 1. The fan-out point is used as the current timing point. The level of the fan-out point of the current timing point is plus 1 based on the level of the current timing point. This is repeated in this way, so that each timing point has level information. For a fan-out timing point that is a timing point of multiple different levels, the level of the fan-out timing point is saved as the maximum level of its predecessor point plus 1. Step 2.2: Classify the time series points according to the hierarchical information, put the time series points of the same level into the same container, and sort the containers according to the hierarchical information; Step 2.3: Calculate the arrival time of the timing point: Traverse all containers in ascending order from the smallest level. When traversing each container, it is necessary to traverse each time point in the container and calculate the arrival time of each time point. The arrival time of each time point is the arrival time of the current time point plus the signal delay. The arrival time of all time points in the first-level container is 0. After traversing all time points in each container, continue to traverse the next container. Step 2.4: Calculate the required time for the timing point: Traverse all containers from largest to smallest hierarchically. When traversing each container, traverse each timing point in the container and calculate the required time for each timing point. If the current timing point is the timing target point, obtain the required time based on the target register. Otherwise, subtract the signal delay from the required time of the fan-out point of the current timing point as the required time for the current timing point. After traversing all timing points in each container, continue traversing the next container. Step 2.5: After all containers are traversed, subtract the arrival time from the required time of each timing source to obtain the timing margin of each timing source.

4. A timing path analysis method according to claim 3, characterized in that: Starting from the timing source point with the minimum timing margin and analyzing the timing path along the fan-out point direction, the method to find the critical path is: Step 3.1: Sort the timing margins of each timing source point from small to large; Step 3.2: Starting from the source point with the smallest timing margin, create a timing subnet for the source point. The timing subnet is to use the fan-out point of the current source point as the connection timing point of the current source point, then use the fan-out point as the current point, find the fan-out point of the current point as the connection timing point of the current point, and repeat this step until the current point has no fan-out point. The timing subnet of the current source point is obtained. When the fan-out point is the target point of the timing path, it is recorded in the target point list; Step 3.3: Create predecessor point, delay and transition state information for the timing point in the timing subnet; Step 3.4: Get the target points from the target point list, pass through the predecessor points of each target point, and then use the predecessor points as the current point. Then, push forward through the predecessor points of the current point to obtain the timing points of a timing path between each target point and the timing source point. Step 3.5: Obtain the driving clock based on the source and destination points of each timing path. Calculate the clock period based on the driving clock as the required time, and use the delay at the destination point as the arrival time to calculate the timing margin of each timing path. Step 3.6: Compare the timing margins of multiple timing paths starting from a source point and select the path with the smallest timing margin as the critical path of the current source point.

5. A timing path analysis method according to claim 4, characterized in that: When creating a timing subnet for each timing source point, the hierarchical information of each timing point in the subnet is the same as the hierarchical information in the timing netlist.

6. A timing path analysis method according to claim 5, characterized in that: The method for creating predecessor point, delay and transition state information for the timing point in the timing subnet is: Step 3.3.1: Generate the delay information of the timing source point. The delay information of the timing source point includes rising edge delay and falling edge delay; Step 3.3.2: Create delay information for the fan-out point of the timing source point. The predecessor point of the fan-out point is the timing source point, and the delay of the fan-out point is the fan-out delay of the timing source point. Step 3.3.3: Traverse the timing subnet, starting from the second-layer timing point of the timing subnet. Based on the delay information of the current timing point, find the fan-out point of the current timing point in the timing subnet. The predecessor point of the fan-out point is the current timing point, and the delay information of the fan-out point is the timing delay of the current timing point plus the fan-out delay of the current timing point. Step 3.3.4: Traverse the timing points in the timing subnet hierarchy in sequence. After the traversal is completed, each timing point has predecessor point and delay information.

7. A timing path analysis method according to claim 6, characterized in that: The fan-out delay at the current timing point needs to take the rising edge delay or falling edge delay of the fan-out signal according to whether the current timing source point is at the rising edge or falling edge, the transition state of the current timing point, and the transition state of the fan-out signal.

8. The timing path analysis method according to claim 7, characterized in that: When generating a timing report, the device and port names used in the timing path are obtained, and device name and port hash tables are created respectively. The timing path stores the hash values ​​corresponding to the device names and port names. When displaying the timing path, the device name and port are searched in the hash table based on the hash values, and the path information is displayed in the timing report.

9. A timing path analysis system, characterized in that: The method is implemented by using each step of a timing path analysis method according to any one of claims 1 to 8.

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