Display module and display device

Abstract

The embodiment of the invention provides a display module and a display device. The display module comprises a display panel, a first chip and a capacitor to be tested. The first end of the to-be-tested capacitor is electrically connected with the first chip, and the second end of the to-be-tested capacitor is grounded. The display module comprises a test circuit and a processing circuit. The input end of the test circuit is electrically connected with the first end of the capacitor to be tested. The processing circuit is electrically connected with the output end of the test circuit. The display module comprises a first state, and based on the first state of the display module, the test circuit tests the to-be-tested capacitor. The processing circuit determines whether the to-be-tested capacitor is abnormal based on the test result of the test circuit. According to the display module provided by the embodiment of the invention, automatic detection of abnormal connection of the filter capacitor is realized, abnormal connection of the filter capacitor in the display module is found in time, and the quality of a product is finally ensured.

Description

Technical Field

[0001] The present application relates to the field of display, and in particular to a display module and a display device. Background Art

[0002] In some chips of display modules, in order to improve the stability of the chip's operating performance, it is necessary to design a filter capacitor on the corresponding chip pin. For example, in a power chip, in order to improve the stability of the power supply voltage, it is necessary to design a filter capacitor on the corresponding power supply pin. Filter capacitors are generally designed as chip capacitors. However, due to limitations in the production process, the SMT (Surface Mounted Technology) effect is poor, resulting in the filter capacitor falling off or the capacitance value of the filter capacitor differing significantly from the preset value. In related technologies, after the filter capacitor falls off or the capacitance value of the filter capacitor changes significantly, its abnormality cannot be detected in time, resulting in unstable chip performance and ultimately affecting the display effect.

[0003] In related technologies, in order to improve product yield, filter capacitors are mostly tested manually and subjectively. However, manual and subjective testing carries the risk of missed detection, which ultimately leads to product quality problems. Summary of the Invention

[0004] In view of this, the embodiments of the present application provide a display module and a display device, which aim to realize automatic detection of abnormal connection of filter capacitors, timely discover abnormal connection of filter capacitors in the display module, and ultimately ensure product quality.

[0005] A display module includes a display panel, a first chip, and a capacitor to be tested. The first end of the capacitor to be tested is electrically connected to the first chip, and the second end of the capacitor to be tested is grounded. The display module includes a test circuit and a processing circuit. The input end of the test circuit is electrically connected to the first end of the capacitor to be tested. The processing circuit is electrically connected to the output end of the test circuit. The display module includes a first state. Based on the display module being in the first state, the test circuit tests the capacitor to be tested. The processing circuit determines whether there is an abnormality in the capacitor to be tested based on the test results of the test circuit.

[0006] In a possible implementation of the first aspect, the first chip is a touch control chip, a power chip, or a display driver chip, and the test circuit and the processing circuit are integrated inside the touch control chip.

[0007] In a possible implementation of the first aspect, the test circuit reuses a capacitance detection circuit of the touch electrodes inside the touch chip, and the processing circuit reuses a capacitance detection processing circuit of the touch electrodes inside the touch chip.

[0008] In a possible implementation of the first aspect, the first chip is a touch control chip, a power chip, or a display driver chip, and the test circuit is located outside the touch control chip.

[0009] In a possible implementation manner of the first aspect, the display panel includes a non-display area, and the test circuit is integrated into the display panel and located in the non-display area.

[0010] In one possible implementation of the first aspect, a test circuit includes a detection switch module, a reset module, and a capacitance sampling module. The detection switch module is electrically connected to the reset module. The detection switch module is configured to control the on / off state of the test circuit. The reset module is electrically connected to the capacitance sampling module. The reset module is configured to perform high-level and low-level resets on an input terminal of the test circuit, thereby forming an alternating high- and low-level voltage signal at the input terminal of the test circuit. The capacitance sampling module is configured to sample capacitance values.

[0011] In a possible implementation of the first aspect, the reset module includes: a first reset switch and a second reset switch, the first end of the first reset switch receives a first reset signal, the second end of the first reset switch is electrically connected to the first end of the capacitor to be measured through the detection switch module, the first end of the second reset switch receives a second reset signal, and the second end of the second reset switch is electrically connected to the first end of the capacitor to be measured through the detection switch module.

[0012] In one possible implementation of the first aspect, the capacitance sampling module includes: a sample-and-hold control switch, a first voltage-stabilizing capacitor, and a sampling control switch. A first end of the sample-and-hold control switch is electrically connected to the detection switch module, a second end of the sample-and-hold control switch is electrically connected to the first end of the first voltage-stabilizing capacitor, and a second end of the first voltage-stabilizing capacitor is grounded. A second end of the sample-and-hold control switch is electrically connected to the first end of the sampling control switch, and the second end of the sampling control switch is electrically connected to the processing circuit.

[0013] In a possible implementation of the first aspect, the capacitance sampling module includes: a signal input switch, a first operational amplifier, a first level write switch, a second level write switch, a sampling and holding control switch, a first voltage-stabilizing capacitor, and a sampling control switch. The first end of the signal input switch is electrically connected to the detection switch module, and the second end of the signal input switch is electrically connected to the first input end of the first operational amplifier. The first end of the first level write switch is used to receive a first level signal, and the second end of the first level write switch is electrically connected to the second input end of the operational amplifier. The first end of the second level write switch is used to receive a second level signal, and the second end of the second level write switch is electrically connected to the second input end of the operational amplifier. The first end of the sampling and holding control switch is electrically connected to the output end of the operational amplifier, and the second end of the sampling and holding control switch is electrically connected to the first end of the first voltage-stabilizing capacitor, and the second end of the first voltage-stabilizing capacitor is grounded. The second end of the sampling and holding control switch is electrically connected to the first end of the sampling control switch, and the second end of the sampling control switch is electrically connected to the processing circuit.

[0014] In a possible implementation of the first aspect, the capacitance sampling module further includes: a first capacitor, a second capacitor, and a third reset switch. The first capacitor is electrically connected to the first input terminal of the operational amplifier. The second capacitor is electrically connected between the first input terminal and the output terminal of the operational amplifier. The third reset switch is electrically connected between the first input terminal and the output terminal of the operational amplifier.

[0015] In a possible implementation of the first aspect, the processing circuit determining whether the capacitor to be tested has an abnormality based on a test result of the test circuit includes: Based on the test result being outside the preset capacitance value reference range, the processing circuit determines that an abnormality exists in the capacitor to be tested.

[0016] In a possible implementation of the first aspect, the preset capacitance value reference range is [c (1-m%), c (1+m%)], where c is the reference capacitance value and m is the fluctuation range.

[0017] In one possible implementation of the first aspect, the test circuit includes at least two capacitors to be tested. The test circuit also includes a switch selection module electrically connected to the detection switch module. The switch selection module includes at least two selection switches, each of which is electrically connected to the capacitors to be tested in a one-to-one correspondence.

[0018] An embodiment of the present application further provides a display device, comprising the display module provided in the first aspect.

[0019] In the display module provided by the embodiment of the present application, when the display module is in the first state, the test circuit is activated to detect the capacitor to be tested and transmit the test result to the processing circuit. The processing circuit then determines whether the capacitor to be tested is abnormal based on the test result. This achieves automatic detection of the capacitor to be tested, thereby ensuring the stability of the power supply output signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0021] Figure 1 A schematic structural diagram of a display module provided in an embodiment of the present application; Figure 2 A schematic structural diagram of a display module provided in an embodiment of the present application; Figure 3 A schematic structural diagram of a display module provided in an embodiment of the present application; Figure 4 A schematic diagram of the principles of a test circuit and a processing circuit provided in an embodiment of the present application; Figure 5a A schematic diagram of a test circuit provided in an embodiment of the present application; Figure 5b A schematic diagram of a test circuit provided in an embodiment of the present application; Figure 6 A schematic diagram of the principles of a test circuit and a processing circuit provided in an embodiment of the present application; Figure 7 A schematic diagram of a test circuit provided in an embodiment of the present application; Figure 8 A schematic diagram of a test circuit provided in an embodiment of the present application; Figure 9 A method provided in the embodiment of the present application Figure 8 Corresponding control timing diagram; Figure 10a A schematic diagram of a test circuit provided in an embodiment of the present application; Figure 10b A schematic diagram of a test circuit provided in an embodiment of the present application; Figure 10c A schematic diagram of a test circuit provided in an embodiment of the present application.

[0022] Label Description 100. Display module; 101. Capacitor to be measured; 102. Flexible circuit board; 110. Display panel; 120. First chip; 101. Capacitor to be measured; 130. Test circuit; 131. Detection switch module; 132. Reset module; 133. Capacitor sampling module; 134. Switch selection module; 140. Processing circuit; 141. ADC; 142. Determination module. DETAILED DESCRIPTION

[0023] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0024] It should be clear that the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0025] The terms used in the embodiments of the present application are for the purpose of describing specific embodiments only and are not intended to limit the present application. The singular forms "a", "an", "the" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise.

[0026] It should be understood that the term "and / or" as used herein simply describes a relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A alone, A and B together, or B alone. Furthermore, the character " / " in this document generally indicates an "or" relationship between the associated objects.

[0027] Combine Figures 1 to 3 A display module 100 includes a display panel 110, a first chip 120, and a capacitor to be tested 101. The capacitor to be tested 101 is a filter capacitor, and is generally electrically connected to the power output terminal of the first chip 120. The display module 100 also includes a flexible circuit board 102. Figure 1 As shown, in a possible implementation, the capacitor to be measured 101 and the first chip 120 are located on the flexible circuit board 102 .

[0028] In one possible implementation, the first chip 120 can be a power chip, a touch chip or a display driver chip; wherein, when the first chip 120 is a display driver chip, the first chip 120 can be located on the flexible circuit board 102 or on the display panel 110. Specifically, the first end of the capacitor to be measured 101 is electrically connected to the first chip 120, and the second end of the capacitor to be measured 101 is grounded, that is, the first end of the capacitor to be measured 101 is a non-grounded end. For example, the first end of the capacitor to be measured 101 is electrically connected to the voltage output port of the first chip 120. Taking the first chip 120 as an example of a power chip, the power output end of the power chip includes: AVDD, DVDD, etc., then the capacitor to be measured 101 can be a filter capacitor electrically connected to the AVDD port of the power chip, or the capacitor to be measured 101 can also be a filter capacitor electrically connected to the DVDD port of the power chip. When the first chip 120 is a touch control chip or a display driver chip, a power module is integrated into the first chip 120, and the capacitor 101 to be tested can be a filter capacitor electrically connected to the power output terminal of the power module of the first chip 120. The capacitance of the capacitor 101 to be tested plays an important role in the stability of the power signal. Therefore, it is necessary to detect whether the capacitance of the capacitor 101 to be tested is within a reasonable range.

[0029] like Figures 1 to 3 As shown, the display module 100 includes a test circuit 130 and a processing circuit 140. The test circuit 130 is used to sample capacitance to facilitate testing of the capacitor 101 to be tested, and ultimately, the processing circuit 140 determines whether the capacitance value of the capacitor 101 to be tested is abnormal based on the test results of the test circuit 130. The processing circuit 140 is used to process and calculate the test results of the test circuit 130 to obtain the capacitance value at the sampling point, and then determine whether the capacitance value of the capacitor 101 to be tested is abnormal based on the capacitance value at the sampling point.

[0030] In one possible implementation, the input terminal of the test circuit 130 is electrically connected to the first terminal of the capacitor to be tested 101. The input terminal of the processing circuit 140 is electrically connected to the output terminal of the test circuit 130. The input terminal of the test circuit 130 is electrically connected to the non-ground terminal of the capacitor to be tested 101, which can detect the capacitance value of the capacitor to be tested 101; and can also detect the voltage drop of the capacitor to be tested 101 to ground, thereby facilitating the determination of whether there is a cold solder joint problem between the capacitor to be tested 101 and the first chip 120. The processing circuit 140 receives and processes the test results of the test circuit 130.

[0031] In one possible implementation, the input terminal of the test circuit 130 is electrically connected to the first pin of the first chip 120, and the first pin of the first chip 120 is electrically connected to the first end of the capacitor under test 101. The electrical connection between the input terminal of the test circuit 130 and the first pin of the first chip 120 can more directly determine whether there is a cold solder joint problem between the capacitor under test 101 and the first pin.

[0032] The display module 100 has a first state. When the display module 100 is in the first state, the test circuit 130 tests the capacitor 101. The processing circuit 140 determines whether the capacitor 101 is abnormal based on the test result of the test circuit 130.

[0033] The first state may be a detection state. When the display module 100 is in the first state, detection of the capacitor to be tested 101 is initiated. Specifically, the test circuit 130 may be activated to test the capacitor to be tested 101. The processing circuit 140 may process the test results of the test circuit 130 to obtain a capacitance value at a capacitance sampling point, and determine whether the capacitance value is within a preset range to determine whether the capacitor to be tested 101 is abnormal.

[0034] In the display module 100 provided in the embodiment of the present application, when in the first state, the test circuit 130 is activated to detect the capacitor 101 to be tested, and the test result is transmitted to the processing circuit 140. The processing circuit 140 processes and calculates the test result to obtain the capacitance value of the sampling point in the test circuit 130, and determines whether the capacitor 101 to be tested has an abnormality based on the capacitance value of the sampling point. This achieves automatic detection of the capacitor 101 to be tested, thereby ensuring the stability of the power supply output signal.

[0035] In one embodiment of the present application, the first chip 120 is a touch chip, a power chip or a display driver chip. The test circuit 130 and the processing circuit 140 are integrated into the touch chip. Figure 1 As shown, when the first chip 120 is a touch chip, the testing circuit 130 and the processing circuit 140 are integrated into the first chip 120 .

[0036] The test circuit 130 and the processing circuit 140 are integrated within the touch chip, which means that the capacitance measurement module within the touch chip can be reused to detect and process the capacitor to be measured 101. In one possible implementation, the touch chip includes a touch detection module, and the test circuit 130 and the processing circuit 140 are integrated within the touch detection module. Therefore, in this implementation, the touch detection module within the touch chip can be reused to test and process the capacitor to be measured 101, thereby reducing the need to modify the display module 100 and achieving automatic detection of the capacitor to be measured 101.

[0037] In one possible implementation, the touch detection module of the touch chip is used to perform touch detection to determine the location where the touch occurs. The touch detection module of the touch chip includes a capacitance detection circuit for the touch electrode and a capacitance detection processing circuit 140 for the touch electrode. The capacitance detection circuit for the touch electrode is used to detect the capacitance value of the touch electrode, and the capacitance detection processing circuit 140 for the touch electrode is used to process the detection result of the touch electrode detection circuit. The capacitance detection circuit for the touch electrode can detect the capacitance of the touch electrode, and the capacitance detection processing circuit 140 for the touch electrode can detect the specific capacitance value of the touch electrode and whether the capacitance value reaches the touch threshold. When the touch threshold is reached, it is determined that a touch occurs, and a touch point is reported to obtain the specific coordinates or position information of the touch position, so that the display module 100 can respond to the touch operation.

[0038] The test circuit 130 reuses the capacitance detection circuit for the touch electrodes within the touch chip, and the processing circuit 140 reuses the capacitance detection processing circuit 140 for the touch electrodes within the touch chip. Reusing the internal circuitry of the touch chip for the test circuit 130 and the processing circuit 140 can reduce the need for modifications to the display module 100, thereby reducing costs.

[0039] like Figure 2 or Figure 3 As shown, in one embodiment of the present application, the first chip 120 is a touch chip, a power chip or a display driver chip, and the test circuit 130 is located outside the touch chip.

[0040] In the embodiment of the present application, the test circuit 130 and the processing circuit 140 are located outside the touch chip, which means that the test circuit 130 and the processing circuit 140 do not need to reuse the touch detection module inside the touch chip. As a result, the touch chip does not need to additionally bear the capacitance detection and processing functions of the capacitor to be tested 101, thereby reducing the operating pressure and complexity of the touch chip.

[0041] like Figure 2 or Figure 3 As shown, in one embodiment of the present application, the display panel 110 includes a non-display area, and the test circuit 130 is integrated into the display panel 110 and located in the non-display area.

[0042] In one possible implementation, the display panel 110 includes a TFT array, and the test circuit 130 is integrated into the TFT array. The test circuit 130 is connected to the capacitor 101 under test via pins, thereby achieving electrical connection between the two. In other words, the test circuit 130 and the TFT array are manufactured using the same process, thereby alleviating the increased space occupied by the test circuit 130 when it is mounted externally to the display panel 110.

[0043] like Figure 2As shown, in one possible implementation, processing circuit 140 is integrated into first chip 120, and processing circuit 140 is electrically connected to test circuit 130 via pin bonding. Integrating the complex circuit structure of processing circuit 140 into first chip 120 can help reduce production costs during the development and manufacturing stages of display panel 110. Furthermore, integrating processing circuit 140 into first chip 120 facilitates functional integration.

[0044] like Figure 3 As shown, in one possible implementation, processing circuit 140 is integrated into a second chip. That is, processing circuit 140 is located outside of first chip 120. For example, processing circuit 140 is integrated into a single chip (i.e., the second chip). Integrating processing circuit 140 into a single chip facilitates future maintenance, avoiding the need to replace the entire first chip 120 due to a failure in processing circuit 140. Therefore, integrating processing circuit 140 into a single chip helps reduce future maintenance costs.

[0045] like Figure 4 As shown, in one possible implementation, the test circuit 130 includes: a detection switch module 131, a reset module 132, and a capacitance sampling module 133. The detection switch module 131 is electrically connected to the reset module 132. The detection switch module 131 is used to control the on / off state of the test circuit 130. The reset module 132 is electrically connected to the capacitance sampling module 133. The reset module 132 is used to reset the input end of the test circuit 130 to a high level and a low level, thereby forming a voltage signal alternating between high and low levels at the input end of the test circuit 130. The capacitance sampling module 133 is used to sample the capacitance value.

[0046] like Figure 5a and Figure 5b As shown, the detection switch module 131 includes at least a first transistor T1 switch. When the first transistor T1 switch is in the on state, the connection line between the detection circuit and the capacitor to be measured 101 is connected, and the detection circuit detects the capacitor to be measured 101. The reset module 132 periodically resets the input end of the test module to a high level and a low level, so that the input end of the test circuit 130 forms a high-low level alternating voltage signal, and the high-low level alternating voltage signal can realize the charging and discharging of the capacitor to be measured 101. The capacitance sampling module 133 is used to sample the analog signal of the sampling point that can be used to represent the capacitance value.

[0047] like Figure 6As shown, in one possible implementation, the processing circuit 140 includes an ADC (Analog to Digital Converter) and a determination module. The ADC is used to convert the analog signal collected by the capacitance sampling module 133 into a digital signal, so that the determination module can determine whether the capacitance value of the sampling point is abnormal based on the digital signal.

[0048] like Figure 5a As shown, in one possible implementation, the reset module 132 includes: a first reset switch T2 and a second reset switch T3, the first end of the first reset switch T2 receives a first reset signal, the second end of the first reset switch T2 is electrically connected to the first end of the capacitor to be measured 101 through the detection switch module 131, the first end of the second reset switch T3 receives a second reset signal, and the second end of the second reset switch T3 is electrically connected to the first end of the capacitor to be measured 101 through the detection switch module 131.

[0049] In this implementation, one of the first reset signal and the second reset signal is a high-level signal and the other is a low-level signal; for example, the first reset signal is a high-level signal and the second reset signal is a low-level signal. When the first reset switch T2 is in the on state, the first reset signal is written to the first end of the capacitor under test 101, and when the second reset switch T3 is in the on state, the second reset signal is written to the first end of the capacitor under test 101.

[0050] like Figure 5b As shown, in one possible implementation, reset module 132 further includes a master reset switch T4 electrically connected between detection switch module 131 and first reset switch T2 (or second reset switch T3). Master reset switch T4 controls the input of a reset signal to the test circuit 130.

[0051] like Figure 5a or Figure 5b As shown, in one possible implementation, the capacitance sampling module 133 includes a sampling and holding control switch T5, a first voltage-stabilizing capacitor CH1, and a sampling control switch T6. A first end of the sampling and holding control switch T5 is electrically connected to the detection switch module 131, a second end of the sampling and holding control switch T5 is electrically connected to a first end of the first voltage-stabilizing capacitor CH1, and a second end of the first voltage-stabilizing capacitor CH1 is grounded. A second end of the sampling and holding control switch T5 is electrically connected to a first end of the sampling control switch T6, and a second end of the sampling control switch T6 is electrically connected to the processing circuit 140.

[0052] When the sample-and-hold control switch T5 is on, the sampling point can capture a real-time signal; when it is off, the sampling point can capture a held signal. The first voltage-stabilizing capacitor CH1 provides a stable analog signal for the sampling point, reducing ripple at the sampling point. When the sampling control switch T6 is on, the analog signal at the sampling point can be transmitted to the processing circuit 140, for example, to an ADC.

[0053] like Figure 7 As shown, in one possible implementation, the capacitance sampling module 133 includes: a signal input switch T7, a first operational amplifier A1, a first level write switch T8, a second level write switch T9, a sampling and holding control switch T5, a first voltage-stabilizing capacitor CH1, and a sampling control switch T6. The first end of the signal input switch T7 is electrically connected to the detection switch module 131, and the second end of the signal input switch T7 is electrically connected to the first input end of the first operational amplifier A1. The first end of the first level write switch T8 is used to receive a first-level signal, and the second end of the first level write switch T8 is electrically connected to the second input end of the operational amplifier. The first end of the second level write switch T9 is used to receive a second-level signal, and the second end of the second level write switch T9 is electrically connected to the second input end of the operational amplifier. The first end of the sampling and holding control switch T5 is electrically connected to the output end of the operational amplifier, and the second end of the sampling and holding control switch T5 is electrically connected to the first end of the first voltage-stabilizing capacitor CH1. The second end of the first voltage-stabilizing capacitor CH1 is grounded. A second end of the sample and hold control switch T5 is electrically connected to a first end of the sample control switch T6 , and a second end of the sample control switch T6 is electrically connected to the processing circuit 140 .

[0054] Signal input switch T7 is used to control whether the first input terminal of first operational amplifier A1 can receive an input signal. When signal input switch T7 is in the on state, the first input terminal of first operational amplifier A1 can receive an input signal. When signal input switch T7 is in the off state, the first input terminal of first operational amplifier A1 cannot receive an input signal. First level write switch T8 is used to control the writing of a first level signal to the second input terminal of first operational amplifier A1: when first level write switch T8 is in the on state, the first level signal is written to the second input terminal of first operational amplifier A1. Second level write switch T9 is used to control the writing of a second level signal to the second input terminal of first operational amplifier A1: when second level write switch T9 is in the on state, the second level signal is written to the second input terminal of first operational amplifier A1.

[0055] When the sample-and-hold control switch T5 is on, the sampling point can capture a real-time signal; when it is off, the sampling point can capture a held signal. The first voltage-stabilizing capacitor CH1 provides a stable analog signal for the sampling point, reducing ripple at the sampling point. When the sampling control switch T6 is on, the analog signal at the sampling point can be transmitted to the processing circuit 140, for example, to an ADC.

[0056] The first operational amplifier A1 has an electrical isolation function, isolating the sampling point from the input end of the test circuit 130 , thereby reducing the ripple of the sampling point and improving the stability of the signal at the sampling point.

[0057] like Figure 8 As shown, in one possible implementation, the capacitance sampling module 133 further includes: a first capacitor C01, a second capacitor C02, and a third reset switch T10. The first capacitor C01 is electrically connected to the first input terminal of the operational amplifier A1. The second capacitor C02 is electrically connected between the first input terminal and the output terminal of the operational amplifier A1. The third reset switch T10 is electrically connected between the first input terminal and the output terminal of the operational amplifier.

[0058] In this implementation, the first capacitor C01 and the second capacitor C02 function as filtering and voltage stabilization, and the third reset switch T10 enables the output end of the first operational amplifier A1 to follow the first input end thereof.

[0059] Taking this implementation as an example, the control sequence is as follows Figure 9 As shown, SWTP is the driving signal of the first transistor T1, RST is the driving signal of the main reset switch T4 and the third reset switch T10; TVCH is the driving signal of the first reset switch T2; TVCL is the driving signal of the second reset switch T3; DUMP is the driving signal of the signal input switch T7; X_TCVH is the driving signal of the first level write switch T8; X_TVCL is the driving signal of the second level write switch T9; S / H(0) is the driving signal of the sample and hold control switch T5. The detection process and principle of the capacitor 101 to be tested include: During the t0 period, the first transistor T1 is in the off state, and the test circuit 130 does not test the capacitor 101 under test. During the t1 to t4 periods, the first transistor T1 is in the on state, and the test circuit 130 tests the capacitor 101 under test. During the t1 period, the second reset switch T3 and the main reset switch T4 are in the on state, and a second reset signal (e.g., a low level) is written to the first end of the capacitor under test (i.e., the input end of the test circuit). During the t2 period, the sample-and-hold switch T5, the signal input switch T7, and the second level writing switch T9 are turned on, and a second level signal (e.g., a low level) is written to the second input end of the first operational amplifier. At the same time, the voltage signal at the second end of the capacitor 101 under test is written to the first input end of the first operational amplifier. During the t3 period, the first reset switch T2 and the main reset switch T4 are in the on state, and a first reset signal (e.g., a high level) is written to the first end of the capacitor under test. The voltage at the output end of the first operational amplifier follows the voltage at the first input end, and the voltage signal at the sampling point is a low level signal. During period t4, the sample-and-hold switch T5, signal input switch T7, and first-level write switch T8 are turned on, and a first-level signal (e.g., a high level) is written to the second input terminal of the first operational amplifier. Simultaneously, the voltage signal at the second terminal of the capacitor under test 101 is written to the first input terminal of the first operational amplifier. During the next period t1, the voltage at the output terminal of the first operational amplifier follows the voltage at the first input terminal. At this point, the voltage signal at the sampling point is a high-level signal.

[0060] Therefore, the reset switch module can periodically generate high and low level square wave signals at the input end of the test circuit, thereby facilitating sampling at the sampling point and facilitating subsequent ADC calculation of the capacitance value at the sampling point.

[0061] In one embodiment of the present application, the processing circuit 140 determines whether the capacitor to be tested 101 has an abnormality based on the test result of the test circuit 130, including: based on the test result being outside the preset capacitance value reference range, the processing circuit 140 determines that the capacitor to be tested 101 has an abnormality.

[0062] In this embodiment, the data obtained after the acquisition signal received by the processing circuit 140 is converted by ADC is M. The processing circuit 140 determines whether the value of M is within a preset capacitance value reference range. If the value of M is within the preset capacitance value reference range, the capacitor 101 to be tested is determined to be normal; if the value of M is not within the preset capacitance value reference range, that is, the value of M is outside the preset capacitance value reference range, the capacitor 101 to be tested is determined to be abnormal.

[0063] The abnormality of the capacitor 101 under test includes: abnormal capacitance of the capacitor 101 under test, and / or a problem with the voltage drop of the capacitor 101 under test to ground (ie, a problem with a poor solder joint at the pins of the capacitor 101 under test).

[0064] In a possible implementation, the preset capacitance value reference range is [c (1-m%), c (1+m%)], where c is the capacitance reference value and m is the fluctuation range. In one possible implementation, the value of c can be: when the capacitor 101 to be measured is normal, the average value of the capacitance value collected within the capacitance change cycle of a collection point. The capacitance change cycle of one collection point refers to the time it takes for the capacitance value to change from the minimum value to the maximum value. It is understandable that the change pattern of the capacitance value of the collection point is from the minimum value to the maximum value, and then repeats. The value of m is 10-25, for example, 20, which means that the reasonable fluctuation range of the preset capacitance value is 20%.

[0065] In one embodiment of the present application, when the design space is sufficient, the display module 100 may include multiple test circuits, i.e., multiple capacitors to be tested, with the test circuits electrically connected to the capacitors to be tested in a one-to-one correspondence. The test circuits may be the test circuits provided in any of the aforementioned embodiments.

[0066] like Figure 10a 、 Figure 10b and Figure 10c As shown, in a possible implementation, the test circuit 130 includes at least two capacitors 101 to be tested. The test circuit 130 also includes a switch selection module 134, which is electrically connected to the detection switch module 131. The switch selection module 134 includes at least two selection switches, which are electrically connected to the capacitors 101 to be tested in a one-to-one correspondence. Among them, the capacitance sampling module 133 of the test circuit 130 can be Figure 10a The structure shown does not include the first operational amplifier; it can also be as shown in FIG. Figure 10b The structure shown includes the first operational amplifier, but does not include the first capacitor and the second capacitor; it can also be Figure 10c The structure shown includes a first operational amplifier, a first capacitor and a second capacitor.

[0067] In this implementation, in order to save resources, the test circuit 130 can use a time-division multiplexing method to test multiple capacitors 101 to be tested. The conduction state of the circuit between the target capacitor 101 to be tested and the test circuit 130 is controlled by the switch selection module 134. Among them, the target capacitor 101 to be tested is the selected capacitor 101 to be tested, that is, the capacitor 101 to be tested that is electrically connected to the selection switch in the switch selection module 134 that is in the conductive state. When the selection switch is in the conductive state, the circuit between the target capacitor 101 to be tested and the test circuit 130 is in the conductive state, thereby starting to test the target capacitor 101 to be tested.

[0068] In one possible implementation, the display module 100 includes a display driver chip. When the processing circuit 140 determines that there is an abnormality in the capacitor 101 to be tested, the processing circuit 140 sends an alarm message to the display driver chip. The display driver chip processes the alarm message and displays it through the display panel 110 to realize an alarm or warning.

[0069] In an embodiment of the present application, the capacitor to be measured 101 is charged by actively providing high and low level signals to the input terminal of the test circuit 130, and is isolated based on the first operational amplifier A1. At the same time, the third reset switch T10 is used to make the voltage of the sampling point follow the voltage of the first input terminal of the first operational amplifier A1, thereby effectively collecting an analog signal used to characterize the capacitance value of the capacitor to be measured 101, and then using the ADC to convert it to obtain a specific capacitance value, and determine whether the capacitance value is within a preset range, thereby realizing automatic detection of the capacitor to be measured 101.

[0070] An embodiment of the present application further provides a display device, comprising the display module 100 provided by any of the aforementioned embodiments.

[0071] The display device provided in the embodiment of the present application can be any device including a display module 100, such as a display screen, a mobile phone, a smart wearable product, a computer display screen, a handheld computer, a central control screen and other terminal products.

[0072] The display module 100 of the display device provided in the embodiment of the present application is the display module 100 provided in any of the aforementioned embodiments. Therefore, when the display module 100 is in the first state, the test circuit 130 is activated to detect the capacitor 101 to be tested, and the test result is transmitted to the processing circuit 140. The processing circuit 140 processes and calculates the test result to obtain the capacitance value of the sampling point in the test circuit 130, and determines whether the capacitor 101 to be tested has an abnormality based on the capacitance value of the sampling point. This achieves automatic detection of the capacitor 101 to be tested, thereby ensuring the stability of the power supply output signal.

[0073] The various embodiments or implementations of this specification may be combined with one another as long as no technical conflicts exist. Technical conflicts refer to technical features that contradict or cannot coexist within the same embodiment. In other words, the various embodiments or implementations of this specification may be combined as long as they are technically feasible and logically reasonable.

[0074] In this specification, reference may be made to the same or similar parts between the various embodiments or implementations. In particular, for the device embodiments and terminal embodiments, since they are basically similar to the method embodiments or implementations, the description is relatively simple, and the relevant parts may be referred to the description in the method embodiments.

Claims

1. A display module, characterized in that: It includes a display panel, a first chip and a capacitor to be tested; A capacitor to be measured, wherein a first end of the capacitor to be measured is electrically connected to the first chip, and a second end of the capacitor to be measured is grounded; The display module includes: a test circuit, wherein an input terminal of the test circuit is electrically connected to the first terminal of the capacitor to be tested; a processing circuit electrically connected to an output terminal of the test circuit; The display module includes a first state. Based on the display module being in the first state, the test circuit tests the capacitor to be tested. The processing circuit determines whether the capacitor to be tested is abnormal based on the test result of the test circuit.

2. The display module according to claim 1, wherein: The first chip is a touch control chip, a power chip or a display driver chip, and the test circuit and the processing circuit are integrated inside the touch control chip.

3. The display module according to claim 2, wherein: The test circuit reuses the capacitance detection circuit of the touch electrodes inside the touch chip, and the processing circuit reuses the capacitance detection processing circuit of the touch electrodes inside the touch chip.

4. The display module according to claim 1, wherein: The first chip is a touch control chip, a power chip or a display driver chip, and the test circuit is located outside the touch control chip.

5. The display module according to claim 4, wherein: The display panel includes a non-display area, and the test circuit is integrated in the display panel and located in the non-display area.

6. The display module according to claim 1, wherein: The test circuit includes: a detection switch module, a reset module and a capacitance sampling module; the detection switch module is electrically connected to the reset module; the detection switch module is used to control the opening or closing of the test circuit; the reset module is electrically connected to the capacitance sampling module; the reset module is used to perform high-level reset and low-level reset on the input end of the test circuit, so that the input end of the test circuit forms a voltage signal alternating between high and low levels; the capacitance sampling module is used to sample the capacitance value.

7. The display module according to claim 6, wherein: The reset module includes: a first reset switch and a second reset switch, wherein the first end of the first reset switch receives a first reset signal, and the second end of the first reset switch is electrically connected to the first end of the capacitor to be measured through the detection switch module; the first end of the second reset switch receives a second reset signal, and the second end of the second reset switch is electrically connected to the first end of the capacitor to be measured through the detection switch module.

8. The display module according to claim 6, wherein: The capacitance sampling module includes: a sampling and holding control switch, a first voltage-stabilizing capacitor, and a sampling control switch; a first end of the sampling and holding control switch is electrically connected to the detection switch module, a second end of the sampling and holding control switch is electrically connected to the first end of the first voltage-stabilizing capacitor, and a second end of the first voltage-stabilizing capacitor is grounded; a second end of the sampling and holding control switch is electrically connected to the first end of the sampling control switch, and a second end of the sampling control switch is electrically connected to the processing circuit.

9. The display module according to claim 6, wherein: The capacitance sampling module includes: a signal input switch, a first operational amplifier, a first level write switch, a second level write switch, a sampling and holding control switch, a first voltage-stabilizing capacitor, and a sampling control switch; a first end of the signal input switch is electrically connected to the detection switch module, and a second end of the signal input switch is electrically connected to the first input end of the first operational amplifier; a first end of the first level write switch is used to receive a first level signal, and a second end of the first level write switch is electrically connected to the second input end of the operational amplifier; a first end of the second level write switch is used to receive a second level signal, and a second end of the second level write switch is electrically connected to the second input end of the operational amplifier; a first end of the sampling and holding control switch is electrically connected to the output end of the operational amplifier, a second end of the sampling and holding control switch is electrically connected to the first end of the first voltage-stabilizing capacitor, and a second end of the first voltage-stabilizing capacitor is grounded; a second end of the sampling and holding control switch is electrically connected to the first end of the sampling control switch, and a second end of the sampling control switch is electrically connected to the processing circuit.

10. The display module according to claim 9, wherein: The capacitance sampling module further includes: a first capacitor, a second capacitor, and a third reset switch; the first capacitor is electrically connected to the first input terminal of the operational amplifier; the second capacitor is electrically connected between the first input terminal and the output terminal of the operational amplifier; and the third reset switch is electrically connected between the first input terminal and the output terminal of the operational amplifier.

11. The display module according to claim 1, wherein: The processing circuit determining whether the capacitor to be tested has an abnormality based on the test result of the test circuit includes: Based on the test result being outside a preset capacitance value reference range, the processing circuit determines that an abnormality exists in the capacitor to be tested.

12. The display module according to claim 11, wherein: The reference range of the preset capacitance value is [c (1-m%), c (1+m%)], where c is the reference capacitance value and m is the fluctuation range.

13. The display module according to claim 6, wherein: The test circuit includes at least two capacitors to be tested; the test circuit also includes a switch selection module, which is electrically connected to the detection switch module; the switch selection module includes at least two selection switches, which are electrically connected to the capacitors to be tested in a one-to-one correspondence.

14. A display device, characterized in that: A display module comprising any one of claims 1-12.

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