Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a pixel circuit and a light-emitting element. The light-emitting control signal comprises a plurality of light-emitting control cycles in sub-segments, each light-emitting control cycle comprises a light-emitting segment and a non-light-emitting segment, the plurality of sub-segments at least comprise a first sub-segment and a second sub-segment, the i1th reset stage in the first sub-segment is located in the j1th light-emitting control cycle in the first sub-segment, and the j1th reset stage in the second sub-segment is located in the j1th light-emitting control cycle in the second sub-segment. The i1th reset stage in the second sub-segment is located in the j1th light-emitting control period in the second sub-segment; the interval duration of the starting moment of the i1th reset stage in the first sub-segment and the starting moment of the light-emitting segment of the j1th light-emitting control period in the first sub-segment is t1, the interval duration of the starting moment of the i1th reset stage in the second sub-segment and the starting moment of the light-emitting segment of the j1th light-emitting control period in the second sub-segment is t2, i1 > = j1 > 1, and t1 is not equal to t2. According to the embodiment of the invention, the split screen problem of the display panel can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) display panels have many advantages such as self-luminescence, fast response, high brightness, and light weight, and have gradually become the mainstream in the display field.

[0003] With the continuous development of display technology, the public's requirements for screen performance have gradually become higher. However, display panels still have the problem of display splitting. Summary of the Invention

[0004] Embodiments of the present application provide a display panel and a display device, which can improve the split-screen problem of the display panel.

[0005] On the one hand, an embodiment of the present application provides a display panel, including a pixel circuit and a light-emitting element; the pixel circuit includes a light-emitting control module and a first reset module, the light-emitting control module controls whether the light-emitting element emits light based on a light-emitting control signal, and the first reset module resets the potential of the first electrode of the light-emitting element based on a first scanning signal; the working process of the pixel circuit includes multiple sub-segments, the light-emitting control signal includes multiple light-emitting control cycles in the sub-segment, the light-emitting control cycle includes a light-emitting segment and a non-light-emitting segment, the multiple sub-segments include at least a first sub-segment and a second sub-segment, and the first scanning signal includes both the first sub-segment and the second sub-segment. The method includes multiple reset stages, the i1th reset stage in the first subsegment is located in the j1th light-emitting control period in the first subsegment, and the i1th reset stage in the second subsegment is located in the j1th light-emitting control period in the second subsegment; the start time of the i1th reset stage in the first subsegment and the start time of the light-emitting segment of the j1th light-emitting control period in the first subsegment are separated by a time length t1, and the start time of the i1th reset stage in the second subsegment and the start time of the light-emitting segment of the j1th light-emitting control period in the second subsegment are separated by a time length t2, i1≥j1>1, t1≠t2.

[0006] On the other hand, an embodiment of the present application provides a display device, including the display panel provided in the embodiment of the first aspect.

[0007] According to the display panel and display device provided by the embodiments of the present application, the interval between the start time of the i-th reset stage in the first sub-segment and the start time of the light-emitting segment of the j-th light-emitting control cycle in the first sub-segment is t1, and the interval between the start time of the i-th reset stage in the second sub-segment and the start time of the light-emitting segment of the j-th light-emitting control cycle in the second sub-segment is t2, i1≥j1>1, t1≠t2; this is equivalent to changing the relative position of the first scanning signal in the i-th reset stage in the first sub-segment and the second sub-segment, which is equivalent to moving the position of the dark stripes in the display screen in the same sub-segment, thereby weakening the dark stripes that can be recognized by the human eye to improve the split screen problem. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Other features, objects and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals represent the same or similar features and the accompanying drawings are not drawn to scale.

[0009] Figure 1 A schematic diagram of a split screen in related art is shown;

[0010] Figure 2 Show Figure 1 A corresponding timing diagram;

[0011] Figure 3 A schematic structural diagram of a display panel provided in an embodiment of the present application is shown;

[0012] Figure 4 A schematic diagram showing a structure of a pixel circuit in a display panel provided by an embodiment of the present application is shown;

[0013] Figure 5 A timing diagram of a display panel provided by an embodiment of the present application is shown;

[0014] Figure 6 A display schematic diagram of a display panel provided by an embodiment of the present application is shown;

[0015] Figure 7 Another timing diagram of a display panel provided by an embodiment of the present application is shown;

[0016] Figure 8 Another timing diagram of the display panel provided by the embodiment of the present application is shown;

[0017] Figure 9 Another timing diagram of the display panel provided by the embodiment of the present application is shown;

[0018] Figure 10 Another timing diagram of the display panel provided by the embodiment of the present application is shown;

[0019] Figure 11 Another timing diagram of the display panel provided by the embodiment of the present application is shown;

[0020] Figure 12 Another timing diagram of the display panel provided by the embodiment of the present application is shown;

[0021] Figure 13 Another timing diagram of the display panel provided by the embodiment of the present application is shown;

[0022] Figure 14 Another timing diagram of the display panel provided by the embodiment of the present application is shown;

[0023] Figure 15 A schematic structural diagram of a display device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0024] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is merely to provide a better understanding of the present application by illustrating the examples of the present application.

[0025] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, the elements defined by the phrase "comprising..." do not exclude the presence of other identical elements in the process, method, article, or device comprising the elements.

[0026] It should be understood that the term "and / or" as used herein is merely a description of the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this document generally indicates that the associated objects are in an "or" relationship. In the embodiments of the present application, the term "electrically connected" can refer to a direct electrical connection between two components or an electrical connection between two components via one or more other components.

[0027] It will be apparent to those skilled in the art that various modifications and variations can be made in this application without departing from the spirit or scope of this application. Therefore, this application is intended to cover modifications and variations of this application that fall within the scope of the corresponding claims (technical solutions claimed for protection) and their equivalents. It should be noted that the embodiments provided in the examples of this application can be combined with each other without contradiction.

[0028] Before describing the technical solutions provided by the embodiments of the present application, in order to facilitate understanding of the embodiments of the present application, the present application first specifically describes the problems existing in the related art:

[0029] With the continuous development of display technology, the public's demand for screen performance has gradually increased. For example, to save power, low-temperature polycrystalline oxide (LTPO) pixel circuits have emerged. In these circuits, the light-emitting control signal EM is used to control whether the light-emitting element emits light, and the first scanning signal SPX is used to control whether the signal at the target signal terminal can be written into the pixel circuit. For example, the target signal terminal is used to provide a reset signal Vref2 or a bias adjustment signal DVH. The reset signal Vref2 is used to reset the first electrode (e.g., the anode) of the light-emitting element, and the bias adjustment signal DVH is used to adjust the bias state of the drive transistor in the pixel circuit.

[0030] like Figure 1 As shown, the light emitting control signal EM includes multiple light emitting control cycles in one frame, and the light emitting control cycle includes a light emitting segment and a non-light emitting segment ( Figure 1 The low level segment of the light emitting control signal EM is the light emitting segment, and the high level segment of the light emitting control signal EM is the non-light emitting segment).

[0031] The inventors have found that Figure 1 As shown, if the first scanning signal SPX has a valid level in multiple non-luminous segments within one frame ( Figure 1 In the figure, the effective level of the first scanning signal SPX is shown as a low level. For example, the first scanning signal SPX has an effective level in the three non-luminous segments within one frame. In the low grayscale and low brightness display scene, the display panel will appear as follows: Figure 1 The two darker areas in the display panel correspond to the low levels of the first scanning signal SPX in the second and third non-luminous segments, respectively.

[0032] The inventors have studied the causes of the above problems. Figure 2 As shown, a frame includes an active scanning phase and a blanking phase. During the active scanning phase, data signals are written into the pixel circuit row by row; during the blanking phase, no data signals are written. During the blanking phase, the reset signal Vref2 does not reset the first electrodes of at least some of the light-emitting elements. Therefore, during the blanking phase, the current corresponding to the signal end providing the reset signal Vref2 is small, and the voltage drop corresponding to the signal end providing the reset signal Vref2 is small, making the reset signal Vref2 more negative (the reset signal Vref2 is a negative voltage signal). As a result, the potential of the first electrodes of the light-emitting elements corresponding to the low level of the first scanning signal SPX in the second and third non-luminous segments is reset to a lower level, making the brightness of these light-emitting elements dim, thereby causing a split-screen display phenomenon.

[0033] In order to improve the split-screen problem of the display panel, the embodiments of the present application provide a display panel and its driving method, and a display device. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0034] Please refer to Figure 3 and Figure 4 The display panel 100 provided in the embodiment of the present application includes a pixel circuit 10 and a light-emitting element 20 .

[0035] The pixel circuit 10 includes a light emitting control module 11 and a first reset module 12 . The light emitting control module 11 controls whether the light emitting element 20 emits light based on a light emitting control signal EM. The first reset module 12 resets the potential of the first electrode of the light emitting element 20 based on a first scanning signal SPX.

[0036] Exemplarily, the light emitting control module 11 includes a first transistor M1 and a sixth transistor M6, and the first reset module 12 includes a seventh transistor M7. The pixel circuit 10 may further include a driving transistor M3.

[0037] A first electrode of the first transistor M1 is electrically connected to the first power supply terminal PVDD, a second electrode of the first transistor M1 is electrically connected to the first electrode of the driving transistor M3, and a gate of the first transistor M1 is connected to the light emitting control signal EM.

[0038] A first electrode of the sixth transistor M6 is electrically connected to the second electrode of the driving transistor M3 , a second electrode of the sixth transistor M6 is electrically connected to the first electrode of the light emitting element 20 , and a gate of the sixth transistor M6 is connected to the light emitting control signal EM.

[0039] A first electrode of the seventh transistor M7 is connected to the reset signal Vref2 , a second electrode of the seventh transistor M7 is electrically connected to the first electrode of the light emitting element 20 , and a gate of the seventh transistor M7 is connected to the first scan signal SPX.

[0040] The pixel circuit 10 may further include a second transistor M2 , a driving transistor M3 , a fourth transistor M4 , a fifth transistor M5 , and a storage capacitor Cst.

[0041] A first electrode of the second transistor M2 is connected to the data signal Vdata, a second electrode of the second transistor M2 is electrically connected to the first electrode of the driving transistor M3, and a gate of the second transistor M2 is connected to the second scan signal SP.

[0042] A first electrode of the fourth transistor M4 is electrically connected to the second electrode of the driving transistor M3 , a second electrode of the fourth transistor M4 is electrically connected to the gate of the driving transistor M3 , and the gate of the fourth transistor M4 receives the third scan signal S2N.

[0043] A first electrode of the fifth transistor M5 is connected to the reset signal Vref1 , a second electrode of the fifth transistor M5 is electrically connected to the gate of the driving transistor M3 , and a gate of the fifth transistor M5 is connected to the fourth scan signal S1N.

[0044] The storage capacitor Cst is electrically connected between the first power terminal PVDD and the gate of the driving transistor M3 .

[0045] In some examples, the pixel circuit may further include an eighth transistor M8, a first electrode of the eighth transistor M8 is connected to the bias adjustment signal DVH, a second electrode of the eighth transistor M8 is electrically connected to the first electrode of the driving transistor M3, and a gate of the eighth transistor M8 is connected to the first scan signal SPX.

[0046] It should be noted that Figure 4 The structure of the pixel circuit shown is only an example and is not intended to limit the present application. The technical concept of the present application is also applicable to pixel circuits of other structures.

[0047] like Figure 5 As shown, the operation process of the pixel circuit includes multiple sub-segments A. The light-emission control signal EM includes multiple light-emission control cycles b in sub-segments A. The light-emission control cycle b includes a light-emission segment b2 and a non-light-emission segment b1. The light-emitting element 20 can emit light in the light-emission segment b2 and does not emit light in the non-light-emission segment b1.

[0048] The plurality of sub-segments A include at least a first sub-segment A1 and a second sub-segment A2. The first sub-segment A1 may be located before the second sub-segment A2, or the first sub-segment A1 may be located after the second sub-segment A2. Figure 5 The first sub-segment A1 is located before the second sub-segment A2 for illustration, which is not intended to limit the present application.

[0049] The first scanning signal SPX includes multiple reset phases c in both the first and second sub-segments A1 and A2. In the reset phase c, the first scanning signal SPX is at an active level, and the reset signal Vref2 is transmitted to the first electrode of the light emitting element 20 to reset the light emitting element 20.

[0050] The i1th reset phase c_i1_A1 in the first subsegment A1 is within the j1th emission control period b_j1_A1 in the first subsegment A1, and the i1th reset phase c_i1_A2 in the second subsegment A2 is within the j1th emission control period b_j1_A2 in the second subsegment A2.

[0051] The interval between the start time of the i1th reset phase c_i1_A1 in the first sub-segment A1 and the start time of the light-emitting segment b2 of the j1th light-emitting control period b_j1_A1 in the first sub-segment A1 is t1, and the interval between the start time of the i1th reset phase c_i1_A2 in the second sub-segment A2 and the start time of the light-emitting segment b2 of the j1th light-emitting control period b_j1_A2 in the second sub-segment A2 is t2, i1≥j1>1, t1≠t2.

[0052] Exemplarily, different sub-segments A include the same number of light emitting control periods b.

[0053] It can be understood that the j1th light control period b_j1_A1 in the first sub-segment A1 and the j1th light control period b_j1_A2 in the second sub-segment A2 are in the same order, and the j1th light control period is the light control period after the first light control period in the sub-segment A.

[0054] For example, j1=2, or j1=3, etc.

[0055] As an example, each light emitting control period b includes a reset phase c, i1=j1>1. In this example, the first electrode of the light emitting element can be reset in any light emitting control period b, thereby ensuring a good reset effect.

[0056] As another example, at least one light emitting control period b does not include the reset phase c, and i1>j1>1.

[0057] As another example, in each sub-segment, the first light-emitting control period includes two reset phases c, and the other light-emitting control periods each include one reset phase c, and i1>j1>1. For example, in this example, i1=3, j1=2. For another example, i1=4, j1=3.

[0058] Exemplarily, different sub-segments A include the same number of light emitting control periods b.

[0059] Exemplarily, the durations of different light emitting control periods b are equal. It is understandable that in this case, the durations of different sub-segments A are equal.

[0060] Exemplarily, the duty cycles of different light emitting control periods b are the same.

[0061] When the durations of different luminous control periods b are equal and the duty cycles of different luminous control periods b are the same, the luminous durations of different luminous periods are equal, so that the luminous effects corresponding to different luminous periods tend to be consistent.

[0062] For example, the duration of the sub-segment A can cover the duration required for writing data signals to multiple rows of pixel circuits 10. In other words, within the duration of a sub-segment A, each row of pixel circuits 10 of the display panel can complete writing of data signals.

[0063] In the embodiment of the present application, the relative positions of the i1-th reset phase c_i1_A1 in the first sub-segment A1 and the i1-th reset phase c_i1_A2 in the second sub-segment A2 are changed. Figure 6 The relative positions of the 3rd reset stage c in the first sub-segment A1 and the 3rd reset stage c in the second sub-segment A2 are different, and the relative positions of the 4th reset stage c in the first sub-segment A1 and the 4th reset stage c in the second sub-segment A2 are different. The 3rd reset stage c in the first sub-segment A1 corresponds to the dark stripe area 1, the 4th reset stage c in the first sub-segment A1 corresponds to the dark stripe area 2, the 3rd reset stage c in the second sub-segment A2 corresponds to the dark stripe area 1', and the 4th reset stage c in the second sub-segment A2 corresponds to the dark stripe area 2'. Due to the different relative positions of the 3rd reset stage c in the first sub-segment A1 and the 3rd reset stage c in the second sub-segment A2, the dark stripe area 1' and the dark stripe area 1 are at least partially offset. Due to the different relative positions of the 4th reset stage c in the first sub-segment A1 and the 4th reset stage c in the second sub-segment A2, the dark stripe area 2' and the dark stripe area 2 are at least partially offset. Comparison reference Figure 1In each sub-segment A', the relative position of the first scanning signal SPX remains unchanged during each light-emission control cycle, resulting in the dark stripes always being in the same position. However, in the embodiment of the present application, by changing the relative position of the first scanning signal SPX during the i1th reset phase in the first sub-segment A1 and the second sub-segment A2, the positions of the dark stripes during the display process of the first and second sub-segments are shifted, thereby weakening the dark stripes that are visible to the human eye and improving the split-screen problem.

[0064] For example, please refer to Figure 5 and Figure 6 Taking t2>t1 as an example, it is equivalent to moving the position of the i1th reset stage c in the second sub-segment A2 forward, the dark stripe area 1' moves up relative to the dark stripe area 1, and the dark stripe area 2' moves up relative to the dark stripe area 2.

[0065] It should be noted that, in order to clearly illustrate the technical solution of the present application, in the timing diagram of the present application, the effective level of the first scanning signal SPX is taken as a low level, the low level period of the light-emitting control signal EM is taken as the light-emitting segment b2, and the high level period of the light-emitting control signal EM is taken as the non-light-emitting segment b1 for illustration, which is not used to limit the present application.

[0066] In some embodiments, the first sub-segment A1 and the second sub-segment A2 are two adjacent sub-segments.

[0067] For example, during the entire display process from power-up to power-down of the display panel, the operation process of the pixel circuit may include multiple sub-segments, and at least two adjacent sub-segments among the multiple sub-segments may be a first sub-segment and a second sub-segment, respectively. For example, multiple sub-segments in the first half of the entire display process are first sub-segments, and multiple sub-segments in the second half of the entire display process are second sub-segments.

[0068] In this embodiment, the position of the dark stripe can be moved at least once during the display process to avoid the dark stripe always being in the same position during the entire display process, thereby weakening the dark stripe recognizable to the human eye and improving the split-screen problem.

[0069] In some embodiments, one of any two adjacent sub-segments A in the plurality of sub-segments A is the first sub-segment A1, and the other is the second sub-segment A2. In other words, the first sub-segment A1 and the second sub-segment A2 are any two adjacent sub-segments.

[0070] For example, during the entire display process from power-on to power-off of the display panel, the operation process of the pixel circuit may include multiple sub-segments, and any two adjacent sub-segments among the multiple sub-segments are respectively the first sub-segment and the second sub-segment.

[0071] In this embodiment, it is equivalent to relatively moving the positions of the dark bars corresponding to any two adjacent sub-segments, so that the positions of the dark bars corresponding to any two adjacent sub-segments are relatively changed, so as to better weaken the dark bars recognizable to the human eye, thereby better improving the split-screen problem.

[0072] In some embodiments, as Figure 7 or Figure 8 As shown, the plurality of sub-segments A further includes a third sub-segment A3, and the second sub-segment A2 is located between the first sub-segment A1 and the third sub-segment A3. It is understood that for the same pixel circuit of the display panel, the first sub-segment A1 is executed first, followed by the second sub-segment A2, and then the third sub-segment A3; or the third sub-segment A3 is executed first, followed by the second sub-segment A2, and then the first sub-segment A1.

[0073] The i1th reset phase c_i1_A3 in the third subsegment A3 is within the j1th light-emitting control period b_j1_A3 in the third subsegment A3. The start time of the i1th reset phase c_i1_A3 in the third subsegment A3 is separated from the start time of the light-emitting segment b2 of the j1th light-emitting control period b_j1_A3 in the third subsegment A3 by a time interval t3, and t3≠t2.

[0074] It can be understood that the j1th light-emitting control period b_j1_A1 in the first sub-segment A1, the j1th light-emitting control period b_j1_A2 in the second sub-segment A2, and the j1th light-emitting control period b_j1_A3 in the third sub-segment A3 are the same, and the j1th light-emitting control period is the light-emitting control period after the first light-emitting control period in the sub-segment A.

[0075] In this embodiment, the relative position of the i1-th reset stage c_i1_A1 in the first subsegment A1 and the i1-th reset stage c_i1_A2 in the second subsegment A2 is changed, and the relative position of the i1-th reset stage c_i1_A3 in the third subsegment A3 and the i1-th reset stage c_i1_A2 in the second subsegment A2 is changed. In this way, it is equivalent to not only moving the position of the dark bars in the display image in the first and second subsegments, but also moving the position of the dark bars in the display image in the third and second subsegments. The position of the dark bars can be moved at least twice during the display process to better weaken the dark bars that are recognizable to the human eye, thereby better improving the split-screen problem.

[0076] In some embodiments, the second sub-segment A2 is adjacent to the first sub-segment A1 and the third sub-segment A3, and |t2-t1|=|t2-t3|.

[0077] like Figure 7 and Figure 8As shown, with respect to the emission control signal EM, the i1-th reset phase c_i1_A2 in the second sub-segment A2 shifts by a relative amount SL compared to the i1-th reset phase c_i1_A1 in the first sub-segment A1. The i1-th reset phase c_i1_A3 in the third sub-segment A3 also shifts by a relative amount SL compared to the i1-th reset phase c_i1_A2 in the second sub-segment A2. That is, |t2-t1|=|t2-t3|=SL.

[0078] In this embodiment, the relative movement of two adjacent subsegments in the first, second, and third subsegments A1, A2, and A3 during the i1th reset phase is equal. As a result, the relative timings for resetting the light-emitting elements in the first, second, and third subsegments A1, A2, and A3 vary regularly, thereby preventing significant differences in the resetting of the light-emitting elements in different subsegments.

[0079] Of course, in other embodiments, it can also be designed that |t2-t1|≠|t2-t3|.

[0080] In some embodiments, t1 = t3.

[0081] For example, Figure 7 As shown, with respect to the emission control signal EM, the i1-th reset phase c_i1_A2 in the second sub-segment A2 is shifted forward by SL compared to the i1-th reset phase c_i1_A1 in the first sub-segment A1; and the i1-th reset phase c_i1_A3 in the third sub-segment A3 is shifted backward by SL compared to the i1-th reset phase c_i1_A2 in the second sub-segment A2. In this example, t2>t1, and t1=t3.

[0082] In this embodiment, with respect to the light-emission control signal EM, the i1-th reset phase c_i1_A2 in the second subsegment A2 is shifted forward by SL relative to the i1-th reset phase c_i1_A1 in the first subsegment A1, and the i1-th reset phase c_i1_A3 in the third subsegment A3 is shifted backward by SL relative to the i1-th reset phase c_i1_A2 in the second subsegment A2. In other words, the position of the i1-th reset phase c_i1_A3 in the third subsegment A3 is shifted backward to the same position as the i1-th reset phase c_i1_A1 in the first subsegment A1. As a result, the relative timings at which the third subsegment A3 and the first subsegment A1 reset the light-emitting elements are identical, resulting in the same resetting effects on the light-emitting elements as the first subsegment A1.

[0083] In other embodiments, t1≠t3.

[0084] As an example, Figure 8 As shown, relative to the emission control signal EM, the i1-th reset phase c_i1_A2 in the second subsegment A2 is shifted forward by SL compared to the i1-th reset phase c_i1_A1 in the first subsegment A1; and the i1-th reset phase c_i1_A3 in the third subsegment A3 is further shifted forward by SL compared to the i1-th reset phase c_i1_A2 in the second subsegment A2. In this example, t2>t1, and t3>t2.

[0085] In this embodiment, with respect to the light-emitting control signal EM, the i1-th reset phase c_i1_A2 in the second subsegment A2 is shifted forward by SL relative to the i1-th reset phase c_i1_A1 in the first subsegment A1, and the i1-th reset phase c_i1_A3 in the third subsegment A3 is shifted forward by further SL relative to the i1-th reset phase c_i1_A2 in the second subsegment A2.

[0086] For example, when the pixel circuit first executes the first sub-segment A1 , then executes the second sub-segment A2 , and then executes the third sub-segment A3 , the i1 th reset phase of the latter sub-segment moves forward relative to the former sub-segment.

[0087] Alternatively, when the pixel circuit first executes the third sub-segment A3, then executes the second sub-segment A2, and then executes the first sub-segment A1, the i1-th reset phase of the latter sub-segment moves backward relative to the former sub-segment.

[0088] In this embodiment, the positions of the dark bars corresponding to any two sub-segments among the first sub-segment A1, the second sub-segment A2, and the third sub-segment A3 can be relatively moved to better weaken the dark bars recognizable to the human eye, thereby better improving the split-screen problem.

[0089] For example, the relative positions of the reset phases in different sub-segments can conform to a certain cycle period. This can not only shift the relative positions of the dark stripes in different sub-segments, but also prevent excessive differences in the resetting of the light-emitting elements in different sub-segments. The following describes some examples of the cycle period.

[0090] In some embodiments, as Figure 9 As shown, the operation process of the pixel circuit includes multiple cycles d, each cycle d including n sub-segments A, where n ≥ 2. Different cycles d include the same number of sub-segments A. Each cycle d includes at least one first sub-segment A1 and at least one second sub-segment A2.

[0091] The i2-th reset phase c_i2_Ak of ​​the k-th subsegment Ak within cycle d is within the j2-th light emitting control period b_j2_Ak of ​​the k-th subsegment Ak, i2 ≥ j2 > 1, n ≥ k ≥ 1. The k-th subsegment Ak within cycle d is any one of the multiple subsegments within cycle d.

[0092] In the mth cycle period d_m, the interval between the start time of the i2th reset phase c_i2_Ak in the kth sub-segment and the start time of the light-emitting segment of the j2th light-emitting control period b_j2_Ak in the kth sub-segment is t_m, m≥1; in the m+1th cycle period d_m+1, the interval between the start time of the i2th reset phase c_i2_Ak in the kth sub-segment and the start time of the light-emitting segment of the j2th light-emitting control period b_j2_Ak in the kth sub-segment is t_m+1; t_m=t_m+1.

[0093] It can be understood that the k-th subsegment in the m-th cycle d_m and the k-th subsegment in the m+1-th cycle d_m+1 are two subsegments with the same order in two adjacent cycles. The i2-th reset phase c_i2_Ak in the k-th subsegment in the m-th cycle d_m and the i2-th reset phase c_i2_Ak in the k-th subsegment in the m+1-th cycle d_m+1 have the same relative position.

[0094] Exemplarily, k is any number from 1 to n.

[0095] For example, the i2th reset phase c_i2_Ak in the 1st sub-segment in the mth cycle d_m and the i2th reset phase c_i2_Ak in the 1st sub-segment in the m+1th cycle d_m+1 have the same relative position; the i2th reset phase c_i2_Ak in the 2nd sub-segment in the mth cycle d_m and the i2th reset phase c_i2_Ak in the 2nd sub-segment in the m+1th cycle d_m+1 have the same relative position; and so on, the i2th reset phase c_i2_Ak in the nth sub-segment in the mth cycle d_m and the i2th reset phase c_i2_Ak in the nth sub-segment in the m+1th cycle d_m+1 have the same relative position.

[0096] In an embodiment of the present application, the relative positions of the i2-th reset stage c_i2_Ak in the k-th sub-segment in the m-th cycle d_m and the i2-th reset stage c_i2_Ak in the k-th sub-segment in the m+1-th cycle d_m+1 are the same. In this way, it can be ensured that the k-th sub-segment in the m-th cycle d_m and the k-th sub-segment in the m+1-th cycle d_m+1 have the same reset effect on the light-emitting element, thereby avoiding a large difference in display effects between the two stages; in addition, the cycle d includes at least one first sub-segment and at least one second sub-segment, so that the position of the dark stripe in the same cycle can move, thereby improving the screen flickering problem.

[0097] Exemplarily, in the same cycle, one of any two adjacent sub-segments is the first sub-segment, and the other is the second sub-segment.

[0098] In some embodiments, as Figure 9 As shown, n=2, t2>t1. In this embodiment, one cycle d includes two subsegments A, one of which is the first subsegment A1 and the other is the second subsegment A2. Each cycle is equivalent to moving the position of the i1th reset stage c in the second subsegment A2 forward, which is equivalent to moving the position of the dark stripe during the display process of each cycle. The reset difference of the light-emitting element in different cycles will not be too large.

[0099] When n=2, the position of the dark stripe corresponding to the i2-th reset phase of the first scanning signal SPX changes twice.

[0100] In some embodiments, as Figure 11 As shown, the cycle d includes n sub-segments A, where n>2.

[0101] In the same cycle d, the duration of the interval between the start moment of the i2th reset stage in the first sub-segment and the start moment of the light-emitting segment of the j2th light-emitting control period in the first sub-segment gradually increases to the start moment of the i2th reset stage in the n1th sub-segment and the start moment of the light-emitting segment of the j2th light-emitting control period in the n1th sub-segment, the duration of the interval between the start moment of the i2th reset stage in the n1+1th sub-segment and the start moment of the light-emitting segment of the j2th light-emitting control period in the n1+1th sub-segment, and the duration of the interval between the start moment of the i2th reset stage in the nth sub-segment and the start moment of the light-emitting segment of the j2th light-emitting control period in the nth sub-segment gradually decreases to the start moment of the i2th reset stage in the nth sub-segment and the start moment of the light-emitting segment of the j2th light-emitting control period in the nth sub-segment, n>n1>1.

[0102] For example, Figure 11In the figure, the cycle d includes 6 sub-segments A. In the same cycle, the third low level of the first scanning signal SPX in the first sub-segment A to the fourth sub-segment A gradually moves forward, the fourth low level of the first scanning signal SPX in the first sub-segment A to the fourth sub-segment A gradually moves forward, the third low level of the first scanning signal SPX in the fourth sub-segment A to the sixth sub-segment A gradually moves backward, and the fourth low level of the first scanning signal SPX in the fourth sub-segment A to the sixth sub-segment A gradually moves backward.

[0103] Or, as Figure 12 As shown, in the same cycle d, the interval between the start moment of the i2th reset stage in the first sub-segment and the start moment of the light-emitting segment of the j2th light-emitting control period in the first sub-segment gradually decreases to the start moment of the i2th reset stage in the n1th sub-segment and the start moment of the light-emitting segment of the j2th light-emitting control period in the n1th sub-segment, and the interval between the start moment of the i2th reset stage in the n1+1th sub-segment and the start moment of the light-emitting segment of the j2th light-emitting control period in the n1+1th sub-segment gradually increases to the start moment of the i2th reset stage in the nth sub-segment and the start moment of the light-emitting segment of the j2th light-emitting control period in the nth sub-segment.

[0104] For example, Figure 12 In the figure, the cycle d includes 6 sub-segments A. In the same cycle, the third low level of the first scanning signal SPX in the first sub-segment A to the fourth sub-segment A gradually moves backward, the fourth low level of the first scanning signal SPX in the first sub-segment A to the fourth sub-segment A gradually moves backward, the third low level of the first scanning signal SPX in the fourth sub-segment A to the sixth sub-segment A gradually moves forward, and the fourth low level of the first scanning signal SPX in the fourth sub-segment A to the sixth sub-segment A gradually moves forward.

[0105] Figure 11 and Figure 12 In the embodiment, the i2th reset phase in the first sub-segment of the m-th cycle d_m and the i2th reset phase in the first sub-segment of the m+1-th cycle d_m+1 have the same relative position, the i2th reset phase in the second sub-segment of the m-th cycle d_m and the i2th reset phase in the second sub-segment of the m+1-th cycle d_m+1 have the same relative position, and so on, the i2th reset phase in the sixth sub-segment of the m-th cycle d_m and the i2th reset phase in the sixth sub-segment of the m+1-th cycle d_m+1 have the same relative position.

[0106] As an example, in the same cycle d, the relative position offset of the i2 th reset phase in any two adjacent sub-segments A is SL.

[0107] In this embodiment, n is greater than 2, and the position of the dark stripe corresponding to the i2th reset phase of the first scanning signal SPX changes n times. The position of the dark stripe can be changed more times within one cycle, thereby better weakening the dark stripe recognizable to the human eye and better improving the split screen problem.

[0108] In some embodiments, as Figures 11 to 12 As shown, multiple sub-segments A include refresh frames and hold frames. One refresh frame is one sub-segment A, and one hold frame is one sub-segment A. During the refresh frame, the pixel circuit writes data signals. Specifically, during the refresh frame, multiple rows of pixel circuits can sequentially write data signals. During the hold frame, the pixel circuit does not write data signals, but instead holds the data signals written during the refresh frame.

[0109] The cycle d includes at least one refresh frame and at least one hold frame. In the same cycle, the i2-th reset phase of the first scan signal SPX has different relative positions in the refresh frame and the at least one hold frame.

[0110] During the refresh frame, a data signal is written to the pixel circuit, and the displayed image is refreshed based on the written data signal. During the hold frame, no data signal is written to the pixel circuit, and the image displayed during the hold frame and the image displayed during the refresh frame are the same image. In this embodiment, the cycle d includes at least one refresh frame and at least one hold frame. The i2-th reset phase of the first scanning signal SPX is at a different relative position between the refresh frame and the hold frame. This allows dark bars to be displayed differently between the refresh frame and the hold frame when the same image is displayed. This reduces dark bars that are visible to the human eye when displaying the same image, thereby improving the split-screen problem.

[0111] In some embodiments, as Figures 10 to 12 As shown, the cycle d includes at least two picture refresh frames F, and one picture refresh frame F includes a refresh frame and at least one hold frame.

[0112] As an example, the display panel includes a base frequency and supports changing the refresh frequency in a skip frame manner.

[0113] For example, the base frequency of the display panel is 120 Hz, the refresh frequency corresponding to the refresh frame is 120 Hz, and the refresh frequency corresponding to the hold frame is 120 Hz.

[0114] When the picture refresh frequency is 40 Hz, a picture refresh frame F includes a refresh frame and two hold frames.

[0115] When the picture refresh frequency is 30 Hz, a picture refresh frame F includes one refresh frame and three hold frames.

[0116] When the picture refresh frequency is 60 Hz, a picture refresh frame F includes a refresh frame and a hold frame.

[0117] Figures 10 to 12 In the example, the cycle d includes two picture refresh frames F, but Figures 10 to 12 In the embodiment, the shift rule of the reset phase (low level period) of the first scan signal SPX is different.

[0118] In this embodiment, the relative positions of the i2th reset stages of adjacent sub-segments within the cycle are different. Since the cycle includes at least two screen refresh frames, the reset stage has more optional positions, so that the dark bars within the cycle can have more variable positions, so as to better weaken the dark bars that are recognizable to the human eye and improve the split-screen problem.

[0119] In some embodiments, as Figure 13 As shown, multiple sub-segments include an active scanning phase and a porch blanking phase, and a cycle period d includes at least one active scanning phase and at least one porch blanking phase. During the active scanning phase, data signals are written to the pixel circuits in multiple rows one by one. During the porch blanking phase, no data signals are written to the pixel circuits.

[0120] The blanking phase porch is located between the active scanning phases of adjacent image refresh frames. The blanking phase porch can be used to prepare and transmit image data to provide the display driver chip (IC) with sufficient time to prepare to receive and process the next frame of image data, so that the display driver chip can complete the processing and output of the current frame data before receiving the next frame of image data, avoiding data loss, display abnormality and other problems.

[0121] For example, Figure 13 As shown, one active scanning phase corresponds to one subsegment A, and one blanking phase corresponds to one subsegment A. During the active scanning phase, the pixel circuit writes data signals. Specifically, during the active scanning phase, multiple rows of pixel circuits can sequentially write data signals. During the blanking phase, the pixel circuit does not write data signals, but instead retains the data signals written during the active scanning phase.

[0122] The cycle d includes at least one active scanning phase and at least one blanking phase porch. In the same cycle, the i2 th reset phase of the first scanning signal SPX has different relative positions in the active scanning phase and the at least one blanking phase porch.

[0123] During the scanning phase, data signals are written to the active pixel circuits, and the display image is refreshed based on the written data signals. During the blanking phase, data signals are not written to the porch pixel circuits. The image displayed by the display panel during the blanking phase and the porch is the same image as the image displayed during the active scanning phase. In this embodiment, cycle d includes at least one active scanning phase and at least one blanking phase. The i2th reset phase of the first scanning signal SPX has a different relative position between the active scanning phase and the at least one blanking phase. This allows the position of dark stripes to vary between the active scanning phase and the at least one blanking phase. This reduces the visible dark stripes when displaying the same image, thereby improving the split-screen issue.

[0124] In some embodiments, as Figure 13 As shown, the cycle d includes at least two picture refresh frames F, and one picture refresh frame F includes a scanning phase active and at least one blanking phase porch.

[0125] For example, a cycle d includes two refresh frames F, and one refresh frame F includes one active scanning phase and two porch blanking phases. Of course, the number of refresh frames F included in the cycle d and the number of porch blanking phases included in the refresh frame F can also be set according to actual needs.

[0126] In this embodiment, the relative positions of the i2th reset stages of adjacent sub-segments within the cycle are different. Since the cycle includes at least two screen refresh frames, the reset stage has more optional positions, so that the dark bars within the cycle can have more variable positions, so as to better weaken the dark bars that are recognizable to the human eye and improve the split-screen problem.

[0127] In some embodiments, as Figure 13 As shown, one scanning phase active is a subsegment A, and one blanking phase porch is a subsegment A. One picture refresh frame F includes multiple blanking phases porch. In the same picture refresh frame F, at least one blanking phase porch is a first subsegment A1, and at least another blanking phase porch is a second subsegment A2.

[0128] As introduced above, the relative positions of the first scanning signal SPX in the i1th reset phase in the first sub-segment A1 and the second sub-segment A2, and in the embodiment of the present application, at least two blanking phases in the same screen refresh frame are the first sub-segment A1 and the second sub-segment A2, which is equivalent to moving the position of the dark stripes during the display process of the same display screen, thereby weakening the dark stripes recognizable to the human eye to improve the split screen problem.

[0129] Exemplarily, in any two adjacent blanking phases porch, one is the first sub-segment A1 and the other is the second sub-segment A2.

[0130] Exemplarily, in adjacent scanning phases active and blanking phases porch, one is the first sub-segment A1 and the other is the second sub-segment A2.

[0131] It should be noted that Figure 13 The low-level pulse of the first scanning signal SPX indicated by the dotted line is used to represent the low-level pulse position of the first scanning signal SPX when no offset is performed. In this embodiment, the low level of the first scanning signal SPX is offset in the next sub-segment A relative to the previous sub-segment A, and the offset is SL.

[0132] In some embodiments, as Figure 14 As shown, in the same sub-segment A, the i4th reset stage c_i4 is located within the j4th light-emitting control period b_j4 in the sub-segment, and the i5th reset stage c_i5 is located within the j5th light-emitting control period b_j5 in the second sub-segment; i4≥j4>1, i5≥j5>1, i4≠i5, j4≠j5; the start time of the i4th reset stage c_i4 and the start time of the light-emitting segment of the j4th light-emitting control period b_j4 are separated by a time length t4, and the start time of the i5th reset stage c_i5 and the start time of the light-emitting segment of the j5th light-emitting control period b_j5 are separated by a time length t5, and t4=t5.

[0133] The j4th light control period b_j4 and the j5th light control period b_j5 are light control periods in different sequences in the same sub-segment A, and are light control periods subsequent to the first light control period in the sub-segment A.

[0134] For example, j4=2, j5=3.

[0135] In this embodiment, for the luminescence control cycles after the first luminescence control cycle, the relative positions of the corresponding reset phases are the same, thereby avoiding excessive differences in resetting the light emitting element in different luminescence control cycles after the first luminescence control cycle.

[0136] In some embodiments, as Figure 14 As shown, the first light emitting control period b_1 in sub-segment A includes at least two reset phases. For example, the first light emitting control period b_1 in sub-segment A includes two reset phases, namely a first reset phase c_1 and a second reset phase c_2.

[0137] Exemplarily, the first light emitting control period in the refresh frame and / or the active scanning phase includes at least two reset phases.

[0138] In this embodiment, the first light emitting control period b_1 includes multiple reset stages, and the light emitting element can be reset multiple times, which can better improve the afterimage or streaking problem.

[0139] Of course, in other embodiments, the first light emitting control period b_1 in the sub-segment A may also include only one reset phase.

[0140] In some embodiments, as Figures 9 to 13 As shown, the reset phase in the first light-emitting control cycle in sub-segment A is the first reset phase, and the start time of the first reset phase in different sub-segments is the same as the start time of the light-emitting segment in the first light-emitting control cycle.

[0141] That is to say, the relative positions of the reset phases in the first light emitting control cycles in different sub-segments are the same, so that the reset effects on the light emitting elements in the first light emitting control cycles in different sub-segments can be made consistent.

[0142] In the case that the first light emitting control period includes a plurality of reset phases, the relative positions of the first reset phases with the same sequence in the first light emitting control period in different subfields are the same.

[0143] In some embodiments, the durations of different reset stages are the same, so that the duration of each reset of the light emitting element is the same, so that the reset effects of the light emitting element in different reset stages tend to be consistent.

[0144] This application also provides a display device, including the display panel provided by this application. Figure 15 , Figure 15 It is a structural schematic diagram of a display device provided in an embodiment of the present application. Figure 15 The provided display device 1000 includes the display panel 100 provided by any of the above embodiments of the present application. Figure 15 The embodiment only uses a mobile phone as an example to illustrate the display device 1000. It is understandable that the display device provided in the embodiment of the present application can be a wearable product, a computer, a television, an in-vehicle display device, or other display device with a display function, and the present application does not impose specific limitations on this. The display device provided in the embodiment of the present application has the beneficial effects of the display panel provided in the embodiment of the present application. For details, please refer to the specific description of the display panel in the above embodiments, and this embodiment will not be repeated here.

[0145] While the embodiments described above are not exhaustive, they do not limit the present application to the specific embodiments described. Clearly, numerous modifications and variations are possible based on the above description. These embodiments are selected and described in detail in this specification to better explain the principles and practical applications of the present application, thereby enabling those skilled in the art to better utilize the present application and its modifications. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized in that: The device comprises a pixel circuit and a light-emitting element, wherein the pixel circuit comprises a light-emitting control module and a first reset module, wherein the light-emitting control module controls whether the light-emitting element emits light based on a light-emitting control signal, and the first reset module resets the potential of the first electrode of the light-emitting element based on a first scanning signal; The operation process of the pixel circuit includes multiple sub-segments, the light-emitting control signal includes multiple light-emitting control cycles in the sub-segments, the light-emitting control cycle includes a light-emitting segment and a non-light-emitting segment, the multiple sub-segments include at least a first sub-segment and a second sub-segment, the first scanning signal includes multiple reset phases in both the first sub-segment and the second sub-segment, the i1th reset phase in the first sub-segment is within the j1th light-emitting control cycle in the first sub-segment, and the i1th reset phase in the second sub-segment is within the j1th light-emitting control cycle in the second sub-segment; The interval between the start time of the i1th reset phase in the first sub-segment and the start time of the light-emitting segment of the j1th light-emitting control cycle in the first sub-segment is t1, and the interval between the start time of the i1th reset phase in the second sub-segment and the start time of the light-emitting segment of the j1th light-emitting control cycle in the second sub-segment is t2, i1≥j1>1, t1≠t2.

2. The display panel according to claim 1, wherein: The first sub-segment and the second sub-segment are two adjacent sub-segments.

3. The display panel according to claim 2, wherein: One of any two adjacent sub-segments in the plurality of sub-segments is the first sub-segment, and the other is the second sub-segment.

4. The display panel according to claim 1, wherein: The multiple sub-segments also include a third sub-segment, the second sub-segment is located between the first sub-segment and the third sub-segment, the i1th reset stage in the third sub-segment is located within the j1th light-emitting control cycle in the third sub-segment, and the start time of the i1th reset stage in the third sub-segment and the start time of the light-emitting segment of the j1th light-emitting control cycle in the third sub-segment are separated by a time interval t3, and t3≠t2.

5. The display panel according to claim 4, wherein: The second subsegment is adjacent to the first subsegment and the third subsegment, and |t2-t1|=|t2-t3|.

6. The display panel according to claim 4, wherein: t1=t3.

7. The display panel according to claim 4, wherein: t1≠t3.

8. The display panel according to claim 1, wherein: The operation process of the pixel circuit includes a plurality of cycles, each cycle includes n sub-segments, n≥2, and each cycle includes at least one first sub-segment and at least one second sub-segment; The i2th reset phase in the kth sub-segment within the cycle is located within the j2th light emitting control period in the kth sub-segment, i2≥j2>1, n≥k≥1; In the mth cycle, the interval between the start time of the i2th reset phase in the kth sub-segment and the start time of the light-emitting segment in the j2th light-emitting control period in the kth sub-segment is t_m, where m≥1; In the (m+1)th cycle, the interval between the start time of the i2th reset phase in the kth sub-segment and the start time of the light-emitting segment in the j2th light-emitting control period in the kth sub-segment is t_m+1; t_m=t_m+1.

9. The display panel according to claim 8, wherein: n=2, t2>t1.

10. The display panel according to claim 8, wherein n>2, in the cycle, the interval between the start time of the i2th reset phase in the first sub-segment and the start time of the light-emitting segment in the j2th light-emitting control period in the first sub-segment gradually increases to the start time of the i2th reset phase in the n1th sub-segment and the start time of the light-emitting segment in the j2th light-emitting control period in the n1th sub-segment, the interval between the start time of the i2th reset phase in the n1+1th sub-segment and the start time of the light-emitting segment in the j2th light-emitting control period in the n1+1th sub-segment, and the interval between the start time of the i2th reset phase in the nth sub-segment and the start time of the light-emitting segment in the j2th light-emitting control period in the nth sub-segment gradually decreases to the start time of the i2th reset phase in the nth sub-segment and the start time of the light-emitting segment in the j2th light-emitting control period in the nth sub-segment, n>n1>1; Alternatively, in the cycle, the duration of the interval between the start moment of the i2th reset stage in the first sub-segment and the start moment of the light-emitting segment of the j2th light-emitting control period in the first sub-segment gradually decreases to the start moment of the i2th reset stage in the n1th sub-segment and the start moment of the light-emitting segment of the j2th light-emitting control period in the n1th sub-segment, and the duration of the interval between the start moment of the i2th reset stage in the n1+1th sub-segment and the start moment of the light-emitting segment of the j2th light-emitting control period in the n1+1th sub-segment gradually increases to the start moment of the i2th reset stage in the nth sub-segment and the start moment of the light-emitting segment of the j2th light-emitting control period in the nth sub-segment.

11. The display panel according to claim 8, wherein The plurality of sub-segments include refresh frames and hold frames, and the cycle period includes at least one refresh frame and at least one hold frame; in the refresh frame, the pixel circuit writes a data signal.

12. The display panel according to claim 11, wherein: The cycle period includes at least two picture refresh frames, and one picture refresh frame includes one refresh frame and at least one hold frame.

13. The display panel according to claim 8, wherein The plurality of sub-segments include a scanning phase and a blanking phase, and the cycle includes at least one scanning phase and at least one blanking phase; During the scanning phase, data signals are written into the pixel circuits in the rows one by one.

14. The display panel according to claim 13, wherein: The cycle period includes at least two picture refresh frames, and one picture refresh frame includes one scanning phase and at least one blanking phase.

15. The display panel according to claim 14, wherein: One picture refresh frame includes a plurality of blanking stages. Within the same picture refresh frame, at least one blanking stage is the first subsegment, and at least another blanking stage is the second subsegment.

16. The display panel according to claim 1, wherein In the same sub-segment, the i4th reset phase is located within the j4th light emitting control period in the sub-segment, and the i5th reset phase is located within the j5th light emitting control period in the sub-segment; i4≥j4>1, i5≥j5>1, i4≠i5, j4≠j5; The interval between the start time of the i4th reset phase and the start time of the light-emitting segment of the j4th light-emitting control cycle is t4, and the interval between the start time of the i5th reset phase and the start time of the light-emitting segment of the j5th light-emitting control cycle is t5, t4=t5.

17. The display panel according to claim 1, wherein: The reset phase in the first light emitting control cycle is a first reset phase, and the start time of the first reset phase in different sub-segments is the same as the start time of the light emitting segment in the first light emitting control cycle.

18. The display panel according to claim 1, wherein The first light emitting control period includes at least two reset phases.

19. The display panel according to claim 1, wherein The durations of the different reset phases are the same.

20. The display panel according to claim 1, wherein The durations of the different light-emitting control periods are the same, and the duty cycles of the different light-emitting periods are the same.

21. The display panel according to claim 1, wherein Each of the light emitting control cycles includes the reset phase.

22. A display device, characterized in that: include: The display panel according to any one of claims 1 to 21.

Images