Dynamic frequency modulation method, circuit and device suitable for AXI stream transmission protocol

Abstract

The invention relates to the technical field of communication, in particular to a dynamic frequency modulation method, a dynamic frequency modulation circuit and a dynamic frequency modulation device suitable for an AXI stream transmission protocol. Effective data sent by a host are temporarily stored in a storage module, whether the effective data are sent to a slave or not is decided according to the state of a downstream slave, and the effective data are transmitted to the slave. Empty packets can be screened out before the data are added into the storage module, only effective data are cached, resources are saved, and meanwhile the data transmission efficiency is improved. The clock frequency signal is determined according to the size of the load, and the clock frequency signal is issued to the slave, so that the slave performs frequency increasing or frequency decreasing according to the clock frequency signal, the purpose of dynamically adjusting the clock frequency according to the upstream and downstream load conditions is achieved, the power consumption of the whole circuit is reduced on the premise of not influencing the performance, and load balancing is achieved; and the bandwidth performance of the system is not lost.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a dynamic frequency modulation method, circuit and device applicable to an AXI stream transmission protocol. Background Art

[0002] The AXI (Advanced eXtensible Interface) stream protocol is an evolution of the AXI bus. As a standard interface, the AXI4 stream protocol is primarily used to transmit data streams and connect high-bandwidth data processing units, such as those used in image / video processing, high-speed communication interfaces, and neural network processing. The AXI stream interface can be used to connect multiple hosts and slaves to form a universal interconnect fabric capable of upsizing, downsizing, and routing operations, offering high efficiency, high speed, and low latency.

[0003] However, in real-world applications, the concurrent writing of multiple data sources into the AXI stream channel (merging data streams from multiple sources into a single stream) can lead to data conflicts and loss. Furthermore, due to the mismatch in the number of masters and slaves, and the fact that masters do not always have data to transmit, it is often difficult to achieve load balancing between upstream and downstream devices. This means that system bandwidth utilization is often low. Common interconnect structures generally lack caching capabilities, resulting in resource waste if the clock frequency is too high, and data loss if the frequency is too low.

[0004] In view of this, overcoming the defects of the prior art is an urgent problem to be solved in this technical field. Summary of the Invention

[0005] The technical problem to be solved by the present invention is how to achieve upstream and downstream load balancing and improve the utilization rate of the system bandwidth of the AXI flow in practical applications.

[0006] The present invention adopts the following technical solutions: In a first aspect, a dynamic frequency modulation method applicable to an AXI stream transmission protocol is provided, comprising: Receive valid data from the host, store the valid data in a storage module, and determine the number of temporarily stored data packets based on the valid data received by the storage module in the current clock cycle and the valid data sent to the slave in the current clock cycle; Obtaining the load size of each clock cycle according to the number of temporarily stored data packets; Obtaining a clock frequency signal according to the load magnitude of a plurality of clock cycles; The clock frequency signal is sent to the slave machine, so that the slave machine adjusts its own clock frequency according to the clock frequency signal.

[0007] Preferably, the method further comprises: The total number of clock cycles N is set according to the capacity of the storage module; and the following operations are performed every N clock cycles: Obtaining a data change Δ of the storage module within N clock cycles according to the load size; The clock frequency signal is determined according to the total number N of clock cycles, the data variation Δ, and the data bit width of the slave.

[0008] Preferably, the method further comprises: The average load is obtained based on the total number of clock cycles N and the data change Δ, where the average load = Δ / N; The load ratio is obtained by taking the average load as the numerator and the data bit width of the slave as the denominator; When the load ratio is a positive number, the master control module sends a clock frequency signal suggesting that the slave device increase the frequency, and the frequency increase ratio is the load ratio; When the load ratio is a negative number, the master control module sends a clock frequency signal suggesting that the slave machine reduce the frequency, and the frequency reduction ratio is the absolute value of the load ratio.

[0009] Preferably, the method further comprises: When it is detected that the memory of the storage module is empty and the number of currently stored data packets is 0, no data is transmitted to the slave, and a power control signal is sent to the slave to inform the slave that it can power off and enter a low power consumption state.

[0010] Preferably, the method further comprises: When receiving valid data from the host and / or detecting that the storage module is not empty, sending a power control signal to the slave to inform the slave that data transmission is required and power-on is required; After waiting for the slave device to be powered on, valid data is sent to the slave device.

[0011] Preferably, the method further comprises: The counting module records the change in the number of temporarily stored data packets in each clock cycle in the storage module; Among them, in the initial state, the data volume of the storage module is 0. As the system runs, the counting module records the number of temporarily stored data packets of the current storage module in each clock cycle, and calculates the difference between the number of temporarily stored data packets in each clock cycle and the previous clock cycle to obtain the load size of each clock cycle.

[0012] In a second aspect, a dynamic frequency modulation circuit applicable to the AXI stream transmission protocol is provided, which is used to implement the dynamic frequency modulation method applicable to the AXI stream transmission protocol as described in the first aspect, comprising: a storage module, a counting module, a main control module, and a data sending module; the storage module is used to connect to a host, and the storage module is also respectively connected to the main control module, the counting module, and the data sending module; the main control module is respectively connected to the counting module, the data sending module, and at least one slave; the data sending module is used to connect to a slave; The storage module is used to receive valid data from the host and feed back the number of temporarily stored data packets currently stored to the counting module; The counting module is used to obtain the load size of each clock cycle according to the number of temporarily stored data packets; The master control module is further configured to obtain a clock frequency signal according to the load size, and send the clock frequency signal to the slave machine, so that the slave machine adjusts its own clock frequency according to the clock frequency signal to achieve load balancing.

[0013] Preferably, it further comprises a sub-control module and a data filter connected in sequence, wherein the sub-control module and the data filter are respectively used to connect to the host, and the data filter is also connected to the storage module; The sub-control module is used to receive configuration instructions from the host; The data filter is used to receive a data signal carrying data to be transmitted from a host; The sub-control module is used to control the data filter to filter out non-empty packets from the data to be transmitted according to the configuration instruction, so as to obtain the valid data.

[0014] In a third aspect, a dynamic frequency modulation apparatus applicable to an AXI stream transmission protocol is provided, wherein the dynamic frequency modulation apparatus applicable to the AXI stream transmission protocol comprises: a processor and a memory for storing processor executable instructions; The processor is configured to execute the dynamic frequency modulation method applicable to the AXI stream transmission protocol.

[0015] In a fourth aspect, a non-volatile computer storage medium is provided, wherein the computer storage medium stores computer executable instructions, which are executed by one or more processors to implement the dynamic frequency modulation method applicable to the AXI stream transmission protocol described in the first aspect.

[0016] In a fifth aspect, a chip is provided, comprising: a processor and an interface, for calling and running a computer program stored in a memory from a memory, and executing the dynamic frequency modulation method applicable to the AXI stream transmission protocol as described in the first aspect.

[0017] In a sixth aspect, a computer program product comprising instructions is provided. When the instructions are executed on a computer or a processor, the computer or the processor executes the dynamic frequency modulation method applicable to the AXI stream transmission protocol as described in the first aspect.

[0018] Compared with the prior art, the present invention has the following beneficial effects: The present invention temporarily stores the valid data sent by the host in the storage module, and decides whether to send the valid data to the slave according to the status of the downstream slave. Before adding the data to the storage module, empty packets can be filtered out and only valid data can be cached, which saves resources and improves data transmission efficiency. On the other hand, the clock frequency signal can be determined according to the load size, and the clock frequency signal can be sent to the slave to instruct the slave to increase or decrease the frequency, thereby achieving the purpose of dynamically adjusting the clock frequency according to the upstream and downstream load conditions, reducing the power consumption of the overall circuit without affecting the performance, and achieving load balancing by reasonably adjusting the clock frequency of the downstream slave without losing the system bandwidth performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0020] Figure 1 This is a flow chart of a dynamic frequency modulation method applicable to the AXI stream transmission protocol provided by an embodiment of the present invention; Figure 2 This is a schematic diagram of a process in which a host does not transmit data to a slave, provided by an embodiment of the present invention; Figure 3 This is a schematic diagram of a process of transmitting data from a host to a slave provided by an embodiment of the present invention; Figure 4 1 is a flow chart of a method for dynamically modulating the frequency of a slave device according to upstream data, provided by an embodiment of the present invention; Figure 5 This is a structural diagram of a dynamic frequency modulation circuit applicable to the AXI stream transmission protocol provided by an embodiment of the present invention; Figure 6 The present invention provides a structural diagram of a dynamic frequency modulation device suitable for an AXI stream transmission protocol. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0022] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as meaning open inclusion, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that the specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner, that is, although they may be carried in the embodiments or examples of the above terms due to reasons such as the order and position of appearance, it is not limited to that they can be carried in combination by one embodiment or example.

[0023] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "multiple" means two or more. In addition, for example, the description may also use the method of adding "A" and "B" at the end to describe the same type of nouns as two independent individuals. In this case, the corresponding features defined as "A" and "B" are only used to distinguish the description purposes of the same type of individuals, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated.

[0024] When describing some embodiments, the expressions “coupled”, “coupled” and “connected” and their derivatives may be used. For example, when describing some embodiments, the term “connected” may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term “coupled” may be used to indicate that two or more components are in direct physical or electrical contact. However, the term “connected” or “coupled” may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other, such as “optical coupling”, “wireless connection”, etc. The embodiments disclosed herein are not necessarily limited to the contents of the present invention.

[0025] In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0026] In order to solve the problems of the prior art, this embodiment proposes a dynamic frequency modulation method applicable to the AXI stream transmission protocol, such as Figure 1 Shown, including: Step 101: Receive valid data from the host, store the valid data in a storage module, and determine the number of temporarily stored data packets based on the valid data received by the storage module in the current clock cycle and the valid data sent to the slave in the current clock cycle.

[0027] In an AXI stream transmission protocol system, the valid data obtained after processing the data from the host is transmitted to the corresponding storage module according to the rules of the AXI stream protocol. The specific method of processing the data from the host will be described below.

[0028] During system operation, the storage module receives valid data from the host on the one hand, and on the other hand, transmits the valid data to the slave in real time for processing according to the processing method of the downstream slave. Since the number of upstream hosts and downstream slaves or their respective bit widths (i.e., processing rates) are inconsistent, it will lead to temporary storage of valid data, that is, the number of temporarily stored data packets of the storage module is the difference between the number of data packets from the host and the number of data packets transmitted to the slave.

[0029] In one embodiment, the storage module monitors its own memory usage in real time and reports the memory fullness status to the main control module. The main control module can determine the system load pressure based on the memory fullness status of the storage module. For example, if the memory is nearly full, it indicates that the host may be sending data too quickly and the storage module is about to reach its storage limit. Conversely, if the memory is idle for a long time, it indicates that the host is sending data slowly or the slave is processing data too quickly. The storage module reports the number of temporarily stored data packets to the counting module.

[0030] Step 102: Obtain the load size of each clock cycle according to the number of temporarily stored data packets.

[0031] The counting module determines the payload size based on the number of temporarily stored data packets, and the main control module sends a control signal to the data transmission module based on the payload size and the memory fullness of the storage module. In one embodiment, after receiving the number of temporarily stored data packets fed back by the storage module, the counting module calculates the payload size for each clock cycle. The specific calculation method will be described in detail below.

[0032] Step 103: Obtain a clock frequency signal according to the load size of multiple clock cycles; send the clock frequency signal to the slave, so that the slave adjusts its own clock frequency according to the clock frequency signal.

[0033] In one embodiment, the master control module further adjusts the clock frequency signal based on the load and issues a recommendation to the slave to increase or decrease the frequency to achieve load balancing. The master control module adjusts the clock frequency signal based on the load provided by the counting module. Clock frequency is a key factor affecting the speed at which slaves can process data. Slaves can adjust their operating speed after receiving the clock frequency signal.

[0034] When the load is heavy, the slave's processing speed may not keep up with the master's data transmission speed. In this case, the master control module will adjust the clock frequency signal and send a frequency increase suggestion to the slave, allowing the slave to operate at a higher frequency, speeding up data processing and reducing data backlogs in the storage module. Conversely, when the load is light, the slave's processing speed may be too fast, resulting in resource waste. The master control module will send a frequency reduction suggestion, instructing the slave to reduce its operating frequency to achieve load balancing.

[0035] In one embodiment, the dynamic frequency modulation method applicable to the AXI stream transmission protocol further includes: the data sending module receiving valid data from the storage module and sending the valid data to the slave device according to the control signal. The data sending module receives valid data from the storage module and sends the valid data received by the storage module to the slave device according to the control signal issued by the master control module.

[0036] To sum up, this embodiment temporarily stores the valid data sent by the host in the storage module, and decides whether to send the valid data to the slave according to the status of the downstream slave. Before adding the data to the storage module, empty packets can be filtered out and only valid data can be cached, which saves resources and improves data transmission efficiency. On the other hand, the clock frequency signal can be determined according to the load size, and the clock frequency signal can be sent to the slave, and the slave is instructed to increase or decrease the frequency, so as to achieve the purpose of dynamically adjusting the clock frequency according to the upstream and downstream load conditions, reduce the power consumption of the overall circuit without affecting the performance, and achieve load balancing by reasonably adjusting the clock frequency of the downstream slave without losing the system bandwidth performance.

[0037] In one embodiment, the dynamic frequency modulation method applicable to the AXI stream transmission protocol further includes: when it is detected that the memory of the storage module is empty and the number of currently stored data packets is 0, not transmitting data to the slave device, and sending a power control signal to the slave device to inform the slave device that it can be powered off and enter a low power consumption state. Figure 2As shown, when the host does not send data to the slave, the method further includes: Step 201: The storage module feeds back to the main control module that the memory is empty, and feeds back to the counting module that the number of currently temporarily stored data packets is 0.

[0038] The storage module monitors its own memory status in real time. When the host stops sending data to the slave, as the valid data in the storage module is gradually transferred to the slave, the valid data in the storage module will continue to decrease until it is empty. At this time, the storage module will feedback the empty memory information to the main control module.

[0039] At the same time, when the host stops sending data and all valid data in the storage module are processed, the number of temporarily stored data packets in the storage module becomes 0. The storage module feeds back the information that the number of temporarily stored data packets becomes 0 to the counting module, which can calculate the load size based on this information.

[0040] Step 202: The counting module calculates the load size and feeds the load size back to the main control module. The main control module generates a power control signal to inform the slave device to power off and enter a low power consumption state.

[0041] After the counting module receives the information that the number of temporarily stored data packets is 0 from the storage module, since there is no valid data in the storage module at this time, the load size is 0. After the main control module receives the information that the load size is 0 and the memory is empty signal sent by the storage module (here, since when the number of temporarily stored data packets is 0, it may also mean that the rate at which the host sends valid data matches the rate at which the slave processes valid data, it is also necessary to combine the memory empty signal sent by the storage module for subsequent judgment), it is judged that the current system is in an idle state, that is, there is no data that needs to be processed by the slave. In order to reduce the power consumption of the system and improve energy utilization efficiency, the main control module generates an electric control signal to the slave. The electric control signal is used to inform the slave that it can perform a power-off operation and enter a low-power consumption state. In the low-power consumption state, some circuits or functional modules of the slave will be turned off or the operating frequency will be reduced, thereby reducing energy consumption.

[0042] Step 203: The master control module further sends a control signal to the data sending module to control the data sending module not to transmit data to the slave device.

[0043] In addition to controlling the slave device to enter a low-power state, the master control module also sends a control signal to the data transmission module. This control signal prevents the data transmission module from transmitting invalid data to the slave device when the master device is not sending data, thereby avoiding unnecessary energy consumption and waste of system resources. Upon receiving the control signal from the master control module, the data transmission module stops transmitting data to the slave device and suspends its data transmission operation until the master device resumes sending data or the master control module issues a new instruction.

[0044] Through the above steps, when the host does not send data to the slave, the system can automatically enter a low-power state, reducing unnecessary energy consumption and avoiding the transmission of invalid data, thereby improving the energy efficiency and stability of the entire system.

[0045] The dynamic frequency modulation method applicable to the AXI stream transmission protocol further includes: when receiving valid data from the host and / or detecting that the storage module is not empty, sending a power control signal to the slave to inform the slave that data transmission is required and power-on is required; after waiting for the slave to complete power-on, sending valid data to the slave. In one embodiment, Figure 3 As shown, when the host starts to send data to the slave, the method includes: Step 301: The storage module receives valid data from the host and feeds back to the main control module that the memory is not empty. The main control module generates a power control signal to inform the slave that there is data transmission and it needs to be powered on.

[0046] When the host begins sending data to the slave, the storage module receives valid data from the host according to the AXI stream transmission protocol. As valid data from the host continues to be input, the memory state within the storage module changes from empty to not empty. The storage module monitors its own memory state in real time and feeds back information indicating a not empty memory state to the master control module.

[0047] After receiving information from the storage module indicating that the memory is not empty, the master control module determines that there is data that needs to be processed by the slave. To enable the slave to process this data, the master control module sends an electrical control signal to the slave, informing it that data is being transmitted and that it needs to be powered on. After receiving the electrical control signal, the slave initiates its own power-on process, preparing to enter a working state to process the incoming data.

[0048] Step 302: the master control module waits for the slave device to be powered on and then sends a control signal to the data sending module to control the data sending module to send valid data to the slave device.

[0049] After the master control module issues an electrical control signal to power on the slave, it waits for the slave to complete the power-up process. Once the master control module confirms that the slave has completed power-up, it sends a control signal to the data transmission module. Upon receiving the control signal from the master control module, the data transmission module reads valid data from the storage module and transmits it to the slave in accordance with the AXI stream transmission protocol. During data transmission, the data transmission module ensures data integrity and accuracy, transmitting data according to the specified timing and format.

[0050] Through the above two steps, when the host starts to send data to the slave, the system can automatically respond, so that the slave can power on in time and receive data for processing, ensuring the continuity and efficiency of data transmission in the AXI stream transmission system, and realizing the automatic control and coordination of the system during the data transmission process.

[0051] In one embodiment, the load size of each clock cycle is obtained based on the number of temporarily stored data packets, specifically including: a counting module records the change in the number of temporarily stored data packets in each clock cycle in the storage module; wherein, in an initial state, the data volume of the storage module is 0, and as the system runs, the counting module records the number of temporarily stored data packets in the current storage module in each clock cycle, and calculates the difference between the number of temporarily stored data packets in each clock cycle and the previous clock cycle to obtain the load size of each clock cycle.

[0052] In one embodiment, for example, in the storage module, the number of temporarily stored data packets in the first clock cycle is cycle cnt=0 (Byte), the number of temporarily stored data packets in the second clock cycle is cycle cnt=20 (Byte), the number of temporarily stored data packets in the third clock cycle is cycle cnt=30 (Byte), the number of temporarily stored data packets in the fourth clock cycle is cycle cnt=50 (Byte), and the number of temporarily stored data packets in the fifth clock cycle is cycle cnt=80 (Byte). The counting module calculates the difference between the number of temporarily stored data packets in each clock cycle and the number of temporarily stored data packets in the previous clock cycle and reports it to the main control module, that is, 0-0=0, 20-0=20, 30-20=10, 50-30=20, and 80-50=30; and reports 0, 20, 10, 20, and 30 (i.e., the load size corresponding to each clock cycle, respectively) to the main control module.

[0053] In order to monitor the AXI stream data load in real time, dynamically adjust the slave frequency, and achieve efficient and stable load balancing, in one embodiment, as shown in FIG. Figure 4As shown, the clock frequency signal is obtained according to the load size of multiple clock cycles, including: setting the total number of clock cycles N according to the capacity of the storage module; performing the following operations every N clock cycles: obtaining the data change Δ of the storage module within N clock cycles according to the load size; and determining the clock frequency signal according to the total number of clock cycles N, the data change Δ and the data bit width of the slave.

[0054] Among them, the clock frequency signal is determined according to the total number of clock cycles N, the data change Δ and the data bit width of the slave, including: obtaining an average load according to the total number of clock cycles N and the data change Δ, wherein the average load = Δ / N; using the average load as a numerator and the data bit width of the slave as a denominator to obtain a load ratio; when the load ratio is a positive number, the master control module sends a clock frequency signal to recommend that the slave machine increase the frequency, and the frequency increase ratio is the load ratio; when the load ratio is a negative number, the master control module sends a clock frequency signal to recommend that the slave machine reduce the frequency, and the frequency reduction ratio is the absolute value of the load ratio.

[0055] The main control module first sets the total number of clock cycles N based on the capacity of the storage module. The capacity of the storage module determines the upper limit of the amount of data that the system can store. If the storage module capacity is large, it means that the system has more buffer space to cope with data fluctuations. In this case, a larger N value can be set to more accurately reflect the long-term load of the system; conversely, if the storage module capacity is small, the N value should be set to a relatively small value to respond to changes in the system load in a timely manner. For example, when the storage module capacity is 1GB, N may be set to 1000 clock cycles; and when the storage module capacity is 100MB, N can be set to 100 clock cycles. In one embodiment, the total number of clock cycles N can also be 5, 10, 20, or 50.

[0056] In one embodiment, every N clock cycles, the master control module calculates the data change Δ of the storage module during these N clock cycles based on the load. After obtaining the data change Δ, the master control module calculates the average load based on the total number of clock cycles N and the data change Δ. Finally, the master control module uses the calculated average load as the numerator and the data bit width of the slave as the denominator to obtain a load ratio. The data bit width of the slave refers to the amount of data that the slave can process within one clock cycle.

[0057] A positive load ratio indicates that the amount of data in the storage module has generally increased over these N clock cycles. This means that the upstream (host) is sending data faster than the slave can process it. In this case, the master control module sends a signal suggesting that the slave increase its clock frequency by a factor equal to the load ratio. For example, a load ratio of 0.5 means that the slave needs to increase its clock frequency by 50% to speed up data processing, reduce data backlogs in the storage module, and achieve load balancing.

[0058] When the load ratio is a negative number, it indicates that within these N clock cycles, the amount of data in the storage module is generally reduced, that is, the speed at which the slave processes data exceeds the speed at which the upstream sends data. In order to avoid wasting resources, the master control module will issue a clock frequency signal that recommends the slave to reduce the frequency, and the frequency reduction ratio is the absolute value of the load ratio. For example, if the load ratio is -0.5, the slave needs to reduce the clock frequency by 50% to match the transmission speed of the upstream data and achieve the purpose of load balancing. It should be noted that the master control module in this embodiment only gives the slave a suggestion to adjust the clock frequency and cannot directly control the clock frequency of the slave.

[0059] Taking the number of temporarily stored data packets in the storage module over five clock cycles as an example, the load size for each clock cycle is: 0-0 = 0, 20-0 = 20, 30-20 = 10, 50-30 = 20, and 80-50 = 30. Therefore, the data change in the storage module over five clock cycles is Δ = 0 + 20 + 10 + 20 + 30 = 80 bytes. The average load is Δ / N = 80 / 5 = 16. If the slave device's bit width is 16, the load ratio is 16 / 16 = 1. Therefore, the master control module needs to issue a corresponding signal recommending that the slave device increase its clock frequency by 100% to ensure load balancing.

[0060] Through the above steps, the master control module can monitor the AXI stream data load in real time and dynamically adjust the slave machine frequency according to the load situation, thereby achieving efficient and stable load balancing and improving the performance and stability of the entire AXI stream transmission system.

[0061] In order to further illustrate the dynamic frequency modulation method applicable to the AXI stream transmission protocol described in the above embodiment, this embodiment proposes a dynamic frequency modulation circuit applicable to the AXI stream transmission protocol, such as Figure 5As shown, it includes: a storage module, a counting module, a main control module and a data sending module; the storage module is used to connect to the host, and the storage module is also respectively connected to the main control module, the counting module and the data sending module; the main control module is respectively connected to the counting module, the data sending module and at least one slave; the data sending module is used to connect to the slave; the storage module is used to receive valid data (such as valid data 1 and valid data 2) from the host, and feedback the memory empty or full status (i.e., empty / full signal) to the main control module, and feedback the number of temporarily stored data packets currently stored to the counting module; the counting module The number module is used to obtain the load size of each clock cycle according to the number of temporarily stored data packets, and the main control module is used to send a control signal to the data sending module according to the load size and the memory fullness of the storage module; the main control module is also used to obtain a clock frequency signal according to the load size, and send the clock frequency signal to the slave machine, so that the slave machine adjusts its own clock frequency according to the clock frequency signal to achieve load balancing; the data sending module is used to receive valid data (including valid data and validity indication signal) from the storage module, and send the valid data to the slave machine according to the control signal.

[0062] In one embodiment, referring to Figure 5 The dynamic frequency modulation circuit for the AXI stream transmission protocol further includes a sub-control module and a data filter connected in sequence. The sub-control module and the data filter are each configured to connect to a host, and the data filter is further configured to connect to the storage module. The sub-control module and the data filter are configured to work together to filter out null packets from data received from the host according to the AXI stream standard protocol to obtain valid data. The number of sub-control modules and data filters is determined by the number of hosts, and all other modules are unique. The sub-control module is configured to receive configuration instructions (i.e., configuration instruction 1 and configuration instruction 2) from the host; the data filter is configured to receive data signals (i.e., data signal 1 and data signal 2) from the host carrying data to be transmitted; and the sub-control module (including sub-control module 1 and sub-control module 2) is configured to control the data filter (including data filter 1 and data filter 2) according to the configuration instructions (including configuration instruction 1 and configuration instruction 2) to filter out non-null packets from the data to be transmitted to obtain valid data (including valid data 1 and valid data 2).

[0063] Among them, reference Figure 5For configuration instruction 3 and data signal 3, the data transmission module sends instructions to the slave device through configuration instruction 3 and sends valid data to be transmitted to the slave device through data signal 3. Configuration instruction 3 is used to convey control information (such as operation type, address, data length, etc.) and is used to indicate the start, direction, format, and destination of data transmission. Data signal 3 is used to carry the actual data content (i.e., valid data) for transmission.

[0064] in, Figure 5 As shown in the figure, there are two hosts (ie, host 1 and host 2) and one slave (ie, slave). Since there are two hosts, the corresponding ones include sub-control module 1, sub-control module 2, data filter 1 and data filter 2.

[0065] In one embodiment, taking host 1 as an example, when host 1 begins transmitting data to a slave, it transmits the data to be transmitted via configuration instructions 1 and data signals 1 to sub-control module 1 and data filter 1. Sub-control module 1 and data filter 1 filter empty packets from the host data according to the AXI stream standard protocol to obtain valid data 1, which is then sent to the storage module. The storage module uses an empty / full signal to notify the master control module that the host is sending data. The master control module then sends a power control signal to the slave. After the slave is powered on, it transmits a power-on signal to the master control module to notify the master control module that power has been applied and that data can be received. The master control module then uses control signals to control the data transmission module to read the corresponding valid data from the storage module. In one embodiment, the storage module and the data transmission module communicate via a handshake protocol (i.e., a validity indication signal and valid data) to read the valid data from the storage module and transmit the valid data to the slave, completing the transition from the slave being powered off to receiving valid data after powering on. The data transmission operation of host 2 is similar to the above process and will not be further described here.

[0066] In one embodiment, a conventional interconnect bus typically lacks a cache function and simply routes data input from multiple hosts to different slaves after arbitration. Internally, it typically consists of only an arbitration module and a routing module. This embodiment incorporates a storage module into the circuit, so data is not directly output to the slaves. Data sent from the host is first processed and temporarily stored in the storage module, with the decision to send it later based on downstream status. This has the advantage that the AXI stream transport protocol allows for the sending of empty packets and placeholder bytes. The addition of the storage module allows empty packets to be filtered out, caching only valid data, saving resources and improving efficiency.

[0067] To further illustrate the dynamic frequency modulation method of the embodiment of the present invention, refer to Figure 4 and Figure 5For example, consider a system consisting of two masters and one slave. The system operates at a 100M clock, and the data width of both the master and slave is 16 bytes. If the master doesn't send empty packets and the system is fully loaded, the storage module will add 16x2–16x1=16 bytes of valid data per clock cycle (this is the number of temporarily stored data packets mentioned above, with specific restrictions on the master and slave, so the number of temporarily stored data packets increases by 16 bytes per clock cycle). Therefore, the slave's clock rate must be twice the master's to achieve load balancing.

[0068] In one embodiment, the number of temporarily stored data packets in 5 clock cycles is respectively: 16, 32, 48, 64, and 80. The load size of each clock cycle is 16. Based on the load size, the data change of the storage module in N clock cycles is obtained as Δ=16x5=80Byte. The average load = Δ / N=80 / 5=16. The bit width of the slave is 16, and the load ratio = 16 / 16=1. Then, the master control module needs to send a corresponding clock frequency signal to recommend that the slave increase the frequency by 100%, that is, the clock rate of the slave is twice the clock rate of the master, thereby satisfying load balancing.

[0069] Through the above steps, the master control module can monitor the AXI stream data load in real time and dynamically adjust the slave machine frequency according to the load situation, thereby achieving efficient and stable load balancing and improving the performance and stability of the entire AXI stream transmission system.

[0070] Based on the dynamic frequency modulation method applicable to the AXI stream transmission protocol provided in the previous embodiment, a dynamic frequency modulation device applicable to the AXI stream transmission protocol will be proposed in this embodiment. The dynamic frequency modulation device applicable to the AXI stream transmission protocol includes: a processor and a memory for storing processor-executable instructions; wherein, the processor is configured to execute the dynamic frequency modulation method applicable to the AXI stream transmission protocol.

[0071] like Figure 6 As shown, the dynamic frequency modulation device applicable to the AXI stream transmission protocol includes a processor 21 and a memory 22, wherein the processor 21 and the memory 22 can be connected via a bus or other means.

[0072] The processor 21 may be a central processing unit (CPU). The processor 21 may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or a combination of these chips.

[0073] Memory 22, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer-executable programs, and modules, such as the program instructions / modules corresponding to the dynamic frequency modulation method applicable to the AXI stream transmission protocol in the embodiments of the present invention. The processor executes various functional applications and training processes of the processor by running the non-transitory software programs, instructions, and modules stored in memory.

[0074] The memory 22 may include a program storage area and a training storage area, wherein the program storage area may store an operating system and applications required for at least one function; the training storage area may store training created by the processor, etc. In addition, the memory may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 22 may optionally include a memory remotely located relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned networks include but are not limited to the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof. The one or more modules are stored in the memory 22, and when executed by the processor 21, execution is performed as follows. Figure 1 The dynamic frequency modulation method applicable to the AXI stream transmission protocol is shown in FIG. The specific details of the dynamic frequency modulation method applicable to the AXI stream transmission protocol can be referred to in FIG. Figure 1 、 Figure 2 and Figure 3 The corresponding descriptions and effects in the embodiments shown in the figure can be understood and will not be repeated here.

[0075] This embodiment further provides a computer storage medium, wherein the storage medium stores a computer program. The computer program can be executed by a processor to implement a dynamic frequency modulation method applicable to the AXI stream transmission protocol.

[0076] The computer storage medium stores computer-executable instructions that can execute the dynamic frequency modulation method for the AXI stream transmission protocol in any of the above-mentioned method embodiments. The storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), a random access memory (RAM), a flash memory (full name in English: Flash Memory), a hard disk drive (HDD), or a solid-state drive (SSD); the storage medium can also include a combination of the above-mentioned types of memory.

[0077] The specific steps of the dynamic frequency modulation method applicable to the AXI stream transmission protocol are shown in the above embodiment and will not be repeated in this embodiment.

[0078] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A dynamic frequency modulation method applicable to the AXI stream transmission protocol, characterized in that: include: Receive valid data from the host, store the valid data in a storage module, and determine the number of temporarily stored data packets based on the valid data received by the storage module in the current clock cycle and the valid data sent to the slave in the current clock cycle; Obtaining the load size of each clock cycle according to the number of temporarily stored data packets; Obtaining a clock frequency signal according to the load magnitude of a plurality of clock cycles; The clock frequency signal is sent to the slave machine, so that the slave machine adjusts its own clock frequency according to the clock frequency signal.

2. The dynamic frequency modulation method applicable to the AXI stream transmission protocol according to claim 1, characterized in that: Also includes: The total number of clock cycles N is set according to the capacity of the storage module; and the following operations are performed every N clock cycles: Obtaining a data change Δ of the storage module within N clock cycles according to the load size; The clock frequency signal is determined according to the total number N of clock cycles, the data variation Δ, and the data bit width of the slave.

3. The dynamic frequency modulation method applicable to the AXI stream transmission protocol according to claim 2, characterized in that: Also includes: The average load is obtained based on the total number of clock cycles N and the data change Δ, where the average load = Δ / N; The load ratio is obtained by taking the average load as the numerator and the data bit width of the slave as the denominator; When the load ratio is a positive number, the master control module sends a clock frequency signal suggesting that the slave device increase the frequency, and the frequency increase ratio is the load ratio; When the load ratio is a negative number, the master control module sends a clock frequency signal suggesting that the slave machine reduce the frequency, and the frequency reduction ratio is the absolute value of the load ratio.

4. The dynamic frequency modulation method applicable to the AXI stream transmission protocol according to claim 1, characterized in that: Also includes: When it is detected that the memory of the storage module is empty and the number of currently stored data packets is 0, no data is transmitted to the slave, and a power control signal is sent to the slave to inform the slave that it can power off and enter a low power consumption state.

5. The dynamic frequency modulation method applicable to the AXI stream transmission protocol according to claim 1, characterized in that: Also includes: When receiving valid data from the host and / or detecting that the storage module is not empty, sending a power control signal to the slave to inform the slave that data transmission is required and power-on is required; After waiting for the slave device to be powered on, valid data is sent to the slave device.

6. The dynamic frequency modulation method applicable to the AXI stream transmission protocol according to claim 1, characterized in that: Also includes: The counting module records the change in the number of temporarily stored data packets in each clock cycle in the storage module; Among them, in the initial state, the data volume of the storage module is 0. As the system runs, the counting module records the number of temporarily stored data packets of the current storage module in each clock cycle, and calculates the difference between the number of temporarily stored data packets in each clock cycle and the previous clock cycle to obtain the load size of each clock cycle.

7. A dynamic frequency modulation circuit suitable for AXI stream transmission protocol, characterized in that: A method for implementing a dynamic frequency modulation method applicable to an AXI stream transmission protocol according to any one of claims 1 to 6, comprising: a storage module, a counting module, a master control module, and a data sending module; the storage module is connected to a host, and the storage module is further connected to the master control module, the counting module, and the data sending module respectively; the master control module is connected to the counting module, the data sending module, and at least one slave respectively; and the data sending module is connected to a slave; The storage module is used to receive valid data from the host and feed back the number of temporarily stored data packets currently stored to the counting module; The counting module is used to obtain the load size of each clock cycle according to the number of temporarily stored data packets; The master control module is further configured to obtain a clock frequency signal according to the load size, and send the clock frequency signal to the slave machine, so that the slave machine adjusts its own clock frequency according to the clock frequency signal to achieve load balancing.

8. The dynamic frequency modulation circuit applicable to the AXI stream transmission protocol according to claim 7, characterized in that: It also includes a sub-control module and a data filter connected in sequence, wherein the sub-control module and the data filter are respectively used to connect to the host, and the data filter is also connected to the storage module; The sub-control module is used to receive configuration instructions from the host; The data filter is used to receive a data signal carrying data to be transmitted from a host; The sub-control module is used to control the data filter to filter out non-empty packets from the data to be transmitted according to the configuration instruction, so as to obtain the valid data.

9. A dynamic frequency modulation device suitable for AXI stream transmission protocol, characterized in that: The dynamic frequency modulation device applicable to the AXI stream transmission protocol includes: a processor and a memory for storing processor executable instructions; The processor is configured to execute the dynamic frequency modulation method applicable to the AXI stream transmission protocol according to any one of claims 1 to 6.

10. A non-volatile computer storage medium, characterized in that The computer storage medium stores computer-executable instructions, which are executed by one or more processors to implement the dynamic frequency modulation method applicable to the AXI stream transmission protocol according to any one of claims 1 to 6.

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