Data transmission method, storage medium, electronic device and computer program product

Abstract

The embodiment of the invention provides a data transmission method, a storage medium, an electronic device and a computer program product. The method comprises the steps that an adaptation module determines a bit width conversion rule and configuration information according to a data transmission scene of a data conversion serial interface protocol JESD204C and a standard inter-core-particle interconnection interface UCIe; and the adaptive module performs cross-clock domain bit width conversion on data transmitted between the JESD204C and the UCIe according to the bit width conversion rule and the configuration information, so that the JESD204C and the UCIe are transmitted at the same total transmission rate. Through the embodiment of the invention, the problem that the transmission rate is not matched due to the difference between the data bit width and the clock domain when the transmission is carried out between the JESD204C and the UCIe is solved, and the consistency of the transmission rate of the JESD204C and the UCIe is ensured.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of communications, and specifically, to a data transmission method, a storage medium, an electronic device, and a computer program product. Background Art

[0002] With the increasing demand for inter-die interconnection and data throughput, chip size continues to expand, facing challenges such as limited mask size and reduced yield. At the same time, due to the significant increase in chip manufacturing and R&D costs brought about by process improvements, the integration of multiple smaller chiplets within a package has become an industry trend. Inter-chiplet communication via a die-to-die (D2D) interconnect interface not only enhances chip process flexibility and distributes the high cost of advanced process design across multiple dies, but also shortens chip design time and reduces R&D costs. Therefore, inter-chiplet interconnection transmission technology is one of the key technologies for the widespread application of multi-die architectures.

[0003] To improve the integration of mid-RF front-end chips, multiple mid-RF chips are integrated on a single substrate to form a mid-RF chiplet. Transmission between mid-RF chiplets requires inter-die interconnection transmission devices. As an open inter-die interconnection interface standard, UCIe's compatibility and efficiency can be applied to inter-die interconnection transmission devices. At the same time, to achieve flexible transmission of information between mid-RF, the protocol layer selects the JESD204C data conversion serial interface protocol, taking into account factors such as transmission stream data type, real-time requirements, and coding efficiency. Therefore, an adapter module between the JESD204C protocol and UCIe is proposed. Through flexible configuration, it can meet the transmission requirements in different scenarios. This is an urgent problem to be solved in the inter-die transmission of mid-RF chiplets. Summary of the Invention

[0004] The embodiments of the present application provide a data transmission method, storage medium, electronic device and computer program product, which at least solve the transmission rate mismatch problem caused by data bit width and clock domain differences when transmitting between JESD204C and UCIe in the related art.

[0005] According to one embodiment of the present application, a data transmission method is provided, including: an adaptation module determines a bit width conversion rule and configuration information according to a data transmission scenario of a data conversion serial interface protocol JESD204C and a standard inter-chip interconnection interface UCIe; the adaptation module performs cross-clock domain bit width conversion on data transmitted between JESD204C and UCIe according to the bit width conversion rule and configuration information, so that JESD204C and UCIe are transmitted at the same total transmission rate.

[0006] According to another embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored. The computer program is configured to execute the steps in the above method embodiment when running.

[0007] According to another embodiment of the present application, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in the above method embodiment.

[0008] According to another embodiment of the present application, a computer program product is provided, including a computer program, which implements the steps in the above method embodiment when executed by a processor.

[0009] Through the above-mentioned embodiments of the present application, the bit width is dynamically adjusted between JESD204C and UCIe to ensure that both are transmitted at the same total transmission rate. This rate matching mechanism avoids delays, packet loss or error accumulation caused by rate mismatch during data transmission, thereby achieving efficient and lossless transmission of data. And because JESD204C and UCIe usually operate at different clock frequencies, the adapter module solves the problem of data transmission synchronization between asynchronous clock domains by converting the bit width across clock domains. Through the embodiments of the present application, the transmission rate mismatch problem caused by the difference in data bit width and clock domain when transmitting between JESD204C and UCIe is solved, ensuring the consistency of the transmission rates of JESD204C and UCIe. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a hardware structure block diagram of a computer terminal according to the data transmission method of an embodiment of the present application;

[0011] Figure 2 is a flowchart of a data transmission method according to an embodiment of the present application;

[0012] Figure 3 This is a schematic diagram of the overall structure of data transmission between Dies;

[0013] Figure 4 This is a connection diagram for the adaptation between JESD204C and UCIe;

[0014] Figure 5 It is the flow chart of data processing inside the adaptation module;

[0015] Figure 6 This is the FDI interface transmission handshake timing diagram. DETAILED DESCRIPTION

[0016] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0017] It should be noted that the terms "first", "second", etc. in the description and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0018] The method embodiments provided in the embodiments of the present application can be executed in a mobile terminal, a computer terminal or a similar computing device. Taking running on a computer terminal as an example, Figure 1 1 is a hardware structure diagram of a computer terminal according to the data transmission method of an embodiment of the present application. Figure 1 As shown, the computer terminal may include one or more ( Figure 1 Only one is shown) a processor 102 (the processor 102 may include but is not limited to a microprocessor MCU or a programmable logic device FPGA and other processing devices) and a memory 104 for storing data. The computer terminal may also include a transmission device 106 and an input / output device 108 for communication functions. It will be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above-mentioned computer terminal. For example, the computer terminal may also include Figure 1 More or fewer components than shown, or with Figure 1 Different configurations shown.

[0019] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the data transmission method in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, implementing the above-mentioned method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include a memory remotely located relative to the processor 102, and these remote memories may be connected to the computer terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0020] The transmission device 106 is used to receive or transmit data via a network. A specific example of the aforementioned network may include a wireless network provided by a communications provider of a computer terminal. In one embodiment, the transmission device 106 includes a network interface controller (NIC), which can be connected to other network devices via a base station to enable communication with the Internet. In another embodiment, the transmission device 106 may be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0021] Figure 2 is a flow chart of a data transmission method according to an embodiment of the present application, such as Figure 2 As shown, the process includes the following steps:

[0022] In step S202 , the adaptation module determines a bit width conversion rule and configuration information according to a data conversion serial interface protocol JESD204C and a data transmission scenario of a standard inter-chip interconnect interface UCIe.

[0023] JESD204C is a serial data interface standard for high-performance chips, used to transmit high-speed data streams within or between chips. It aims to overcome the limitations of parallel interfaces, such as pin count and signal integrity issues, by providing a low-pin-count, high-speed serial data transmission mechanism to achieve data transmission rates far exceeding those of parallel interfaces. JESD204C features include high bandwidth and support for data transmission rates of up to 32.44032Gbps, making it suitable for high-performance communications and data processing systems that require large data throughput. JESD204C also features multi-channel support: allowing multiple data channels to be transmitted in parallel on the same link, and each channel can be independently configured to adapt to different data rate requirements.

[0024] UCIe is an open chiplet interconnect standard designed to optimize and standardize inter-die communication in multi-chip modules and chiplet architectures to accommodate a wide range of applications, from high-performance computing to mobile devices. UCIe features include high efficiency: it defines an efficient data transmission mechanism, including flexible configuration of data bit width and clock frequency to accommodate different transmission rate requirements.

[0025] In step S204 , the adaptation module performs cross-clock domain bit width conversion on the data transmitted between JESD204C and UCIe according to the bit width conversion rule and configuration information, so that JESD204C and UCIe are transmitted at the same total transmission rate.

[0026] In one embodiment, the adapter module is a Gearbox module, which includes at least a bit width conversion circuit. This circuit, located at the core of the adapter module, contains a set of programmable logic circuits for dynamically adjusting the bit width during data transmission. The adapter module may also include a cross-clock domain synchronization circuit, which consists of an asynchronous FIFO (first-in, first-out buffer) responsible for synchronizing data between the different clock domains of JESD204C and UCIe.

[0027] In an exemplary embodiment of the present application, when the data transmission rate of the JESD204C channel required for the data transmission scenario is less than or equal to the data transmission rate of the UCIe channel, the mapping relationship between the JESD204C channel and the UCIe channel includes: one JESD204C channel corresponds to one UCIe channel or multiple JESD204C channels correspond to one UCIe channel.

[0028] It should be noted that when the data transmission rate of the JESD204C channel is equal to the data transmission rate of the UCIe channel, the adapter module maps the data of the JESD204C channel directly to the UCIe channel without the need for additional data rate or bit width adjustments. When the data transmission rate of the JESD204C channel is lower than the data transmission rate of the UCIe channel, the adapter module can merge the data of multiple JESD204C channels and map them to a single UCIe channel for transmission. This mapping relationship is achieved through bit width conversion rules and configuration information. While ensuring that the total transmission data rate matches UCIe, it also maximizes the utilization efficiency of the UCIe channel and reduces the number of channels for inter-die communication.

[0029] In an exemplary embodiment of the present application, when the data transmission rate of the JESD204C channel required for the data transmission scenario is less than or equal to the data transmission rate of the UCIe channel, the bit width conversion rule and configuration information satisfy S*Wi=S*Ni*fi=No*fo=Wo; wherein S is a positive integer greater than or equal to 1, Wi is the data transmission rate of the JESD204C channel, Ni is the parallel data bit width of the JESD204C channel, No is the parallel data bit width of the UCIe channel, fo is the working clock of the JESD204C channel, and Wo is the data transmission rate of the UCIe channel.

[0030] In an exemplary embodiment of the present application, data on S JESD204C lanes is transmitted on one UCIe lane, and the bit width is converted between S*Ni and No.

[0031] By merging the data of S JESD204C channels into the UCIe channel, the adapter module can effectively utilize the high transmission bandwidth of a single UCIe channel. Even when the data transmission rate of the JESD204C channel is low, it can achieve high-speed, low-latency inter-die data stream transmission, avoiding the additional packaging complexity and cost brought by multi-channel UCIe.

[0032] In an exemplary embodiment of the present application, when the data transmission rate of the JESD204C channel required by the data transmission scenario is greater than the data transmission rate of the UCIe channel, the mapping relationship between the JESD204C channel and the UCIe channel includes: one JESD204C channel corresponds to multiple UCIe channels.

[0033] In an exemplary embodiment of the present application, when the channel data transmission rate of JESD204C required for the data transmission scenario is greater than the channel data transmission rate of UCIe, the bit width conversion rule and configuration information satisfy Wi=Ni*fi=S*No*fo=S*Wo; wherein S is a positive integer greater than or equal to 1, Wi is the data transmission rate of the JESD204C channel, Ni is the parallel data bit width of the JESD204C channel, No is the parallel data bit width of the UCIe channel, fo is the working clock of the JESD204C channel, and Wo is the data transmission rate of the UCIe channel.

[0034] In an exemplary embodiment of the present application, data on one JESD204C channel is transmitted on S UCIe channels, and the bit width is converted between Ni and S*No.

[0035] In an exemplary embodiment of the present application, the traffic transmission capability of JESD204C is less than or equal to the traffic transmission capability of UCIe.

[0036] As a universal chip interconnect interface, UCIe has a configurable transmission rate, adapting to varying transmission rate requirements by varying the bit width and operating clock. While JESD204C, designed specifically for mid-range RF data streams and offering high-bandwidth, multi-channel data transmission capabilities, does not fully align with UCIe's transmission rate. To enable JESD204C and UCIe to work together in inter-die transmission, an adapter module is used to ensure that the total JESD204C traffic does not exceed the total UCIe traffic. This is a crucial prerequisite for achieving data rate matching, avoiding data overflow, and ensuring transmission integrity.

[0037] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0038] In order to facilitate the understanding of the technical solutions provided by the application embodiments, the embodiments are described below in conjunction with specific scenarios.

[0039] The embodiments of the present application relate to the field of high-speed interconnect interfaces between chiplets, and more particularly to configuration and methods for implementing inter-chiplet transmission using medium-frequency (RF) chiplets.

[0040] Figure 3 This is a schematic diagram of the overall structure of inter-die data transmission. The JESD204C protocol features deterministic latency, high bandwidth, and multiple channels. UCIe is a standard inter-chip interconnect interface. Through the embodiments of this application, inter-die transmission can be achieved by coupling and adapting with UCIe, that is, transmission between Die0 and Die1.

[0041] Figure 4 This is a schematic diagram of the connection between JESD204C and UCIe, which includes the internal processing layers of the JESD204C protocol, the internal processing layers of UCIe, and the adaptation module (Gearbox module) of the embodiment of the present application.

[0042] The JESD204C transport layer is responsible for framing and channel mapping received IQ stream data, while the link layer performs scrambling and 64b / 66b encoding on the channel data to form multi-channel data streams. By configuring different operating clocks, data rates such as 6.08256Gbps, 8.11008Gbps, 12.16512Gbps, 16.22016Gbps, 24.33024Gbps, and 32.44032Gbps can be achieved. Instead of using the JESD204C-compatible PHY-Serdes physical layer for inter-die interconnection, the inter-die interconnection is innovatively combined with UCIe.

[0043] The UCIe standard chip interconnect interface is defined as three layers: the protocol layer, the adaptation layer, and the physical layer. The protocol layer is responsible for specific protocol processes, channel management, and flow control; the adaptation layer is responsible for error detection and correction, retransmission, link, and power management; and the physical layer is responsible for signal transmission over the link, which varies significantly depending on the package type and circuit implementation. In streaming mode, the UCIe protocol layer supports streaming protocols. Therefore, adding a coupling adapter module, the Gearbox module, between the JESD204C link layer and the UCIe adaptation layer enables data transmission between JESD204C and UCIe.

[0044] UCIe can operate at rates of 4Gbps, 8Gbps, 12Gbps, 16Gbps, 24Gbps, and 32Gbps. The data-link clock provided by UCIe to the protocol layer is fixed, and different data transmission rates are achieved by varying the data bit width. To ensure that the UCIe transmission rate fully matches the JESD204C transmission rate, the system must provide UCIe with a reference clock of appropriate accuracy, enabling UCIe to output an appropriate link clock and ensure that the transmission rate matches JESD204C.

[0045] Data processed by the Gearbox module is connected to the UCIe adaptation layer via the FDI interface. In Streaming mode, the UCIe adaptation layer operates in RAW mode, bypassing error detection, correction, and retransmission functions, allowing data to be transmitted transparently. It then connects to the UCIe physical layer via the RDI interface, where it transmits data to other cores.

[0046] In an embodiment of the present application, based on the differences between JESD204C and UCIe in data transmission rate, associated clock, and data bit width, flexible mapping can be achieved between JESD204C channels and UCIe channels to meet various transmission scenarios. The mapping relationships include: one JESD204C channel corresponds to one UCIe channel, one JESD204C channel corresponds to multiple UCIe channels, and multiple JESD204C channels correspond to one UCIe channel. The mapping relationship can be selected through register configuration.

[0047] The adapter module Gearbox mainly implements the parallel data cross-clock domain bit width conversion function, which requires the following information: JESD204C channel parallel data bit width Ni, working clock fi, number of channels Li; UCIe channel parallel data bit width No, accompanying clock fo, number of channels Lo.

[0048] The transmission between JESD204C and UCIe requires that the traffic transmission capabilities at both ends meet Ni*fi*Li≤No*fo*Lo. If they are equal, the traffic matching at both ends just meets the transmission requirements. If the total traffic transmitted on JESD204C is less than the total traffic transmitted on UCIe, UCIe can close the redundant channels. This is a non-standard UCIe internal processing method, but it can achieve the purpose of saving power.

[0049] If the channel data transmission rate Wi of JESD204C required by the transmission scenario is less than or equal to the channel data transmission rate Wo of UCIe, then you can flexibly select one JESD204C channel corresponding to one UCIe channel, multiple JESD204C channels corresponding to one UCIe channel, etc. according to the scenario. The conversion rules and configuration information should satisfy S*Wi=S*Ni*fi=No*fo=Wo, (S≥1), and the data on S JESD204C channels is transmitted on one UCIe channel, and the bit width is converted between S*Ni and No; if Wi is greater than Wo, you can flexibly select a transmission method in which one JESD204C channel corresponds to multiple UCIe channels. The conversion rules and configuration information should satisfy Wi=Ni*fi=S*No*fo=S*Wo, (S≥1), and the bit width is converted between Ni and S*No.

[0050] According to the above embodiment, the conversion feature determines whether the data transmission rates before and after the conversion are consistent based on the channel correspondence, including whether the product of the parallel data bit width before conversion and its corresponding clock frequency is the same as the product of the parallel data bit width after conversion and its corresponding clock frequency. Furthermore, the cross-clock domain bit width conversion configuration information can be adjusted based on the transmission scenario.

[0051] Figure 5 It is the flow chart of data processing inside the adapter module, such as Figure 5 As shown, the transmission scenario is first analyzed. Based on the relationship between the JESD204C channel line rate and the UCIe channel line rate, various channel mapping relationships can be flexibly selected, such as one JESD204C channel corresponding to one UCIe channel, one JESD204C channel corresponding to multiple UCIe channels, or multiple JESD204C channels corresponding to one UCIe channel. While ensuring the consistency of the total data transmission rate before and after the conversion, bit width conversion can be flexibly achieved through register configuration.

[0052] Because the UCIe channel data interface has a fixed bit width, the data in the transmit gearbox (TX gearbox) must be padded with zeros after bit width conversion. Cross-clock domain operations synchronize the data from the JESD204C link layer clock to the UCIe associated clock. Afterward, signal handshaking is completed via the FDI interface, transmitting the data to the UCIe. The UCIe internal interface can then flexibly retrieve valid data based on the scenario.

[0053] The data processing flow in the receiving gearbox (RX gearbox) is the reverse of the above process. After completing the handshake with the FDI interface and receiving the data, the data is down-converted from the UCIe channel clock domain to the JESD204C link layer. Then, based on the bit width conversion information obtained from the transmission scenario, valid bits are selected from the received channel data for bit width conversion. Finally, the converted data is sent to the JESD204C link layer for subsequent processing.

[0054] Figure 6 This is the FDI interface transmission handshake timing diagram. The Gearbox module not only processes data and analyzes the transmission scenario to obtain bit width conversion information and complete cross-clock domain bit width conversion, but also generates signals that meet the UCIe FDI interface handshake timing. After the JESD204C module is powered on and reset, the TX Gearbox module pulls the 1p_irdy signal high, indicating that it is ready to send data. After detecting that the UCIe output p1_ready signal is high (indicating that the UCIe is ready to receive data), it pulls the 1p_valid signal high (indicating that the JESD204C to UCIe data transmission is valid) and begins data transmission to the UCIe. Data is valid when both the p1_ready and 1p_valid signals are high. If the UCIe output p1_ready signal is detected to be low, the 1p_valid signal is pulled low and the output data is changed to 0, making the transmitted data invalid.

[0055] The RX Gearbox module receives data transmitted by UCIe when it detects that the p1_valid signal output by UCIe is pulled high (indicating that the data transmitted by UCIe to JESD204C is valid).

[0056] At the same time, the Gearbox module also has an abnormality monitoring and reporting function. Abnormal situations include two categories: cross-clock domain jitter detection abnormalities and abnormal handshake signals output by UCIe indicating the operating status. Cross-clock domain jitter detection is to detect the read and write addresses of the cross-clock domain cache module according to the set period. If the relative offset of the read and write addresses is within the set jitter range tolerance, the read and write addresses are maintained. If the relative offset of the read and write addresses is not within the set jitter range tolerance, the read and write addresses are recovered according to the read and write recovery address and reported to the CPU; the abnormality detection of the handshake signal status output by UCIe is to detect the p1_ready signal and p1_ready signal output by UCIe. If a falling edge is detected after being pulled high, the corresponding Gearbox signal status is changed and reported to the CPU.

[0057] In summary, the embodiment of the present application proposes a device for implementing inter-die transmission using a mid-RF chiplet. By configuring the above information on the adaptation module, multiple channel mapping methods can be implemented between the JESD204C protocol layer and UCIe, and inter-die transmission scenarios such as data transmission rate mismatch and different line rates can be flexibly implemented, thereby achieving the purpose of efficient and flexible configuration of the inter-die interface.

[0058] In the embodiment of the present application, in response to the application scenario requirements of the medium-frequency diversified chiplet, taking into account factors such as the transmission stream data type, real-time performance, and coding efficiency, the JESD204C data conversion serial interface protocol is selected, and UCIe is used as a universal chiplet interconnection interface to support inter-die transmission. The present invention innovatively adopts a combination of JESD204C and UCIe, adding an adapter module between JESD204C and UCIe to achieve high-speed transmission of streaming data. Through different transmission scenario configurations, different line rates and different lanes can be selected to achieve flexible mapping between JESD204C channels and UCIe channels, solving the structural design problem of transmission between medium-frequency dies. The adapter module is simple in design and achieves the purpose of efficient and flexible configuration of the transmission interface.

[0059] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any of the above method embodiments when run.

[0060] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0061] An embodiment of the present application further provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0062] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0063] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail here.

[0064] Obviously, those skilled in the art should understand that the modules or steps of the present application described above can be implemented using a general-purpose computing device, they can be concentrated on a single computing device, or distributed across a network composed of multiple computing devices, they can be implemented using program code executable by the computing device, and thus, they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be performed in a different order than herein, or they can be fabricated into separate integrated circuit modules, or multiple modules or steps can be fabricated into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0065] The above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. made within the principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A data transmission method, characterized in that: include: The adapter module determines the bit width conversion rules and configuration information based on the data transmission scenarios of the data conversion serial interface protocol JESD204C and the standard inter-chip interconnect interface UCIe; The adaptation module performs cross-clock domain bit width conversion on the data transmitted between the JESD204C and the UCIe according to the bit width conversion rule and configuration information, so that the JESD204C and the UCIe are transmitted at the same total transmission rate.

2. The method according to claim 1, characterized in that When the data transmission rate of the JESD204C channel required for the data transmission scenario is less than or equal to the data transmission rate of the UCIe channel, the mapping relationship between the JESD204C channel and the UCIe channel includes: one JESD204C channel corresponds to one UCIe channel or multiple JESD204C channels correspond to one UCIe channel.

3. The method according to claim 2, characterized in that When the channel data transmission rate of the JESD204C required by the data transmission scenario is less than or equal to the channel data transmission rate of the UCIe, the bit width conversion rule and configuration information meet S*W i =S*N i *f i =N o *f o =W o ; Where S is a positive integer greater than or equal to 1, W i is the data transmission rate of the JESD204C channel, N i N is the parallel data width of the JESD204C channel. o is the parallel data bit width of the UCIe channel, f o The working clock of the JESD204C channel, W o is the data transmission rate of the UCIe channel.

4. The method according to claim 3, characterized in that The data on S JESD204C channels is transmitted on one UCIe channel with a bit width of S*N. i With N o Convert between.

5. The method according to claim 1, wherein When the data transmission rate of the JESD204C channel required by the data transmission scenario is greater than the data transmission rate of the UCIe channel, the mapping relationship between the JESD204C channel and the UCIe channel includes: one JESD204C channel corresponds to multiple UCIe channels.

6. The method according to claim 5, characterized in that When the data transmission rate of the JESD204C channel required by the data transmission scenario is greater than the data transmission rate of the UCIe channel, the bit width conversion rules and configuration information meet the W i =N i *f i =S*N o *f o =S*W o ; Where S is a positive integer greater than or equal to 1, W i is the data transmission rate of the JESD204C channel, N i N is the parallel data width of the JESD204C channel. o is the parallel data bit width of the UCIe channel, f o is the working clock of the JESD204C channel, and Wo is the data transmission rate of the UCIe channel.

7. The method according to claim 6, characterized in that in, The data on one JESD204C channel is transmitted on S UCIe channels with a bit width of N i With S*N o Convert between.

8. The method according to claim 1, characterized in that in, The traffic transmission capability of the JESD204C is less than or equal to the traffic transmission capability of the UCIe.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the steps of the method described in any one of claims 1 to 8 are implemented.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 8 are implemented.

11. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 8 are implemented.

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