Multi-FPGA interconnection method, electronic device and medium based on data hub

Abstract

The present invention relates to the field of integrated circuit technology, and more particularly to a data hub-based method, electronic device, and medium for interconnecting multiple FPGAs. The method first determines an initial topology structure formed by multiple groups of FPGA data hubs, then obtains a time-division multiplexing proportional gain for each group of FPGAs with communication requirements whose virtual path sets are not empty, assumes the addition of a direct-connected virtual cable, updates the virtual path combination set and the virtual path sets of all FPGA groups until all virtual path sets are empty, determines a target path combination, and then, based on the target path combination, establishes interconnections between corresponding FPGAs via the data hub on the basis of the initial topology structure. The present invention improves the system frequency of communication between multiple FPGAs and optimizes the system performance of communication between multiple FPGAs.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a method, electronic equipment and medium for interconnecting multiple FPGAs based on a data hub. Background Art

[0002] In a multi-FPGA system, the topology of the connections between FPGAs significantly impacts the communication frequency and overall system performance. The existing approach is to manually plug and unplug cables between FPGAs to achieve a customized topology. This is not only labor-intensive, but the repeated plugging and unplugging of FPGAs can reduce system security and lifespan. Furthermore, once the topology between FPGAs is established, it cannot be flexibly adjusted, making it difficult to optimize the system frequency. Therefore, reducing manual intervention in multi-FPGA interconnection and enabling flexible adjustments to increase the system frequency and optimize the system performance of multi-FPGA communication have become urgent technical challenges. Summary of the Invention

[0003] The purpose of the present invention is to provide a method, electronic device and medium for interconnecting multiple FPGAs based on a data hub, thereby improving the system frequency of communication between multiple FPGAs and optimizing the system performance of communication between multiple FPGAs.

[0004] According to a first aspect of the present invention, a method for interconnecting multiple FPGAs based on a data hub is provided, comprising:

[0005] Step S1: obtaining an initial topology structure consisting of multiple FPGAs and data hubs, wherein each FPGA is connected to a port of at least one data hub, the data hub including multiple ports, and an initial interconnection line is provided in the data hub;

[0006] Step S2: Obtain the nth group of FPGA identifiers with communication requirements. n ,F2 n}, and {F1 n ,F2 n}corresponding virtual path set {P1 n ,P2 n ,...,P i n ,...,P f(n) n}, the value range of n is 1 to N, N is the total number of FPGA groups with communication requirements, P i n For {F1 n ,F2 n} corresponds to the i-th virtual path, the value of i ranges from 1 to f(n), and f(n) is {F1 n,F2 n The total number of virtual paths corresponding to}, f(n) changes dynamically, and the virtual path is F1 n and F2 n Assuming that the paths connected directly through the data hubs, the initial topology satisfies any set of {F1 n ,F2 n} having at least one communication line;

[0007] Step S3, respectively obtain the current virtual topology structure and add each current f(n)≠0 {F1 n ,F2 n The time division multiplexing proportional gain of the corresponding directly connected virtual cable is the initial virtual topology;

[0008] Step S4: In the current virtual topology, the time division multiplexing ratio gain is the highest. n ,F2 n}Add a new virtual cable, update the virtual path combination set and all {F1 n ,F2 n} corresponding virtual path set, the virtual path combination set is used to store the virtual path combinations corresponding to all virtual cables added in the current virtual topology structure, and each added virtual cable in the virtual topology structure occupies the corresponding {F1 n ,F2 n}, the initial state of the virtual path combination set is empty;

[0009] Step S5: If all f(n)=0, execute step S6; otherwise, return to execute step S3;

[0010] Step S6: determining a target path combination based on the current virtual path combination set, and establishing interconnections between corresponding FPGAs based on the initial topology structure through a data hub based on the target path combination.

[0011] According to a second aspect of the present invention, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executed by the at least one processor, the instructions being configured to execute the method described in the first aspect of the present invention.

[0012] According to a third aspect of the present invention, a computer-readable storage medium is provided, storing computer-executable instructions, wherein the computer instructions are used to execute the method according to the first aspect of the present invention.

[0013] The present invention has significant advantages and beneficial effects compared to existing technologies. Through the above technical solution, the present invention provides a multi-FPGA interconnection method, electronic device, and medium based on a data hub, which can achieve considerable technological advancement and practicality, and has wide industrial application value, and has at least the following beneficial effects:

[0014] The embodiment of the present invention first establishes an initial topology structure composed of multiple groups of FPGA data hubs. Then, based on the assumption that each virtual path set is not empty and that the FPGA group has communication requirements, the time-division multiplexing proportional gain of the directly connected virtual cable is added. The virtual path combination set and the virtual path sets of all FPGA groups are updated until all virtual path sets are empty. The target path combination is determined, and then, based on the target path combination, interconnections between corresponding FPGAs are established through the data hub on the basis of the initial topology structure. The present invention improves the system frequency of communication between multiple FPGAs and optimizes the system performance of communication between multiple FPGAs. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0016] Figure 1 This is a flow chart of a method for interconnecting multiple FPGAs based on a data hub provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0017] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0018] The embodiment of the present invention provides a method for interconnecting multiple FPGAs based on a data hub. Figure 1 Shown include:

[0019] Step S1: Obtain an initial topology structure consisting of multiple FPGAs and data hubs. Each FPGA is connected to a port of at least one data hub. The data hub includes multiple ports, and initial interconnect lines are set in the data hub.

[0020] It should be noted that some initial interconnection lines will be pre-established in the data hub to ensure that two FPGAs with communication needs have at least one corresponding communication line.

[0021] Step S2: Obtain the nth group of FPGA identifiers with communication requirements. n ,F2 n}, and {F1 n ,F2 n}corresponding virtual path set {P1 n ,P2 n ,...,P i n ,...,P f(n) n}, the value range of n is 1 to N, N is the total number of FPGA groups with communication requirements, P i n For {F1 n ,F2 n} corresponds to the i-th virtual path, the value of i ranges from 1 to f(n), and f(n) is {F1 n ,F2 n The total number of virtual paths corresponding to}, f(n) changes dynamically, and the virtual path is F1 n and F2 n Assuming that the paths connected directly through the data hubs, the initial topology satisfies any set of {F1 n ,F2 n}Has at least one communication line.

[0022] It should be noted that {F1 n ,F2 n}The corresponding virtual path set refers to {F1 n ,F2 n}The corresponding set of selectable virtual paths will result in some {F1 n ,F2 n}The virtual path in the corresponding virtual path set cannot be selected, so f(n) changes dynamically.

[0023] Step S3, respectively obtain the current virtual topology structure and add each current f(n)≠0 {F1 n ,F2 n}The time division multiplexing proportional gain of the corresponding directly connected virtual cable, the initial virtual topology structure is the initial topology structure.

[0024] It should be noted that when f(n)=0, the corresponding {F1 n ,F2 n}There is no selectable virtual path, so in step S3, only the current f(n)≠0 {F1 n ,F2 n The time division multiplexing proportional gain of the corresponding directly connected virtual cable. The virtual topology structure in the initial state is the initial topology structure. Then, each time steps S3 to S5 are executed, a virtual cable is added to the virtual topology structure, and the virtual topology structure is continuously updated.

[0025] Step S4: In the current virtual topology, the time division multiplexing ratio gain is the highest. n ,F2 n}Add a new virtual cable, update the virtual path combination set and all {F1 n ,F2 n} corresponding virtual path set, the virtual path combination set is used to store the virtual path combinations corresponding to all virtual cables added in the current virtual topology structure, and each added virtual cable in the virtual topology structure occupies the corresponding {F1 n ,F2 n}, the initial state of the virtual path combination set is empty.

[0026] It should be noted that each virtual path combination corresponds to a physical implementation of the current virtual topology structure.

[0027] Step S5: If all f(n)=0, execute step S6; otherwise, return to execute step S3.

[0028] It should be noted that when f(n)=0, it means that there is no optional virtual path currently, so step S6 is directly executed.

[0029] Step S6: determining a target path combination based on the current virtual path combination set, and establishing interconnections between corresponding FPGAs based on the initial topology structure through a data hub based on the target path combination.

[0030] The initial topology structure may specifically be a topology structure based on one group of FPGAs, or a topology structure based on multiple groups of FPGAs, which is described below through two specific embodiments.

[0031] Example 1

[0032] The multiple FPGAs can be specifically a group of FPGAs. The FPGAs in a group can be arranged hierarchically. For example, a group of FPGAs can include three FPGA packages, each FPGA package includes four FPGA slices, each FPGA slice includes three FPGA boards, and each FPGA board includes four FPGAs. A total of 144 FPGAs can be present in a group of FPGAs. A data hub can be installed within a group of FPGAs to interconnect FPGAs within the group.

[0033] Example 2

[0034] The data hub includes a first data hub arranged within an FPGA group and a second data hub arranged between FPGA groups. The first data hub includes multiple ports, and the second data hub includes multiple ports. Each FPGA is connected to a port of at least one first data hub in the corresponding first data hub group. The second data hub is used to interconnect first data hubs in different groups. Both the first and second data hubs have multiple ports. The number of ports on the first and second data hubs can be the same or different, but the number of ports on the first and second data hubs must meet the interconnection requirements between multiple FPGA groups. Each port on the first data hub can only establish a connection with one external port and one internal port. The external port corresponding to the first data hub is either an FPGA port or a port of the second data hub. Each port on the second data hub can only establish a connection with one external port and one internal port. The external port corresponding to the second data hub is a port of the first data hub.

[0035] In one embodiment, the second data hub is connected to ports of first data hubs in at least two different first data hub groups. In each first data hub group, at least one internal port of the first data hub includes an initial interconnection line, and at least one internal port of the second data hub includes an initial interconnection line, so that any two FPGAs with communication requirements have at least one communication line. It should be noted that in the initial topology, only a small number of internal connections exist within the first and second data hubs, sufficient to ensure that any two FPGAs with communication requirements have at least one communication line.

[0036] As a preferred embodiment, the first data hub and the second data hub have the same structure and the same number of ports, which facilitates unified design and verification of the first data hub and the second data hub.

[0037] As a preferred embodiment, the connections between each group of FPGAs and the corresponding first data hub are evenly distributed, and the connections between the first data hub and the second data hub are evenly distributed, so as to improve the performance of the system.

[0038] As an embodiment, the FPGAs in each group can be arranged in a hierarchical manner. For example, a group of FPGAs includes three FPGA packages, each FPGA package includes four FPGA slices, each FPGA slice includes three FPGA circuit boards, and each FPGA circuit board includes four FPGAs. A total of 144 FPGAs exist in a group of FPGAs. In the initial topology, an initial connection relationship can be established between the FPGAs on each circuit board, and an initial connection can be established between the FPGA circuit boards to achieve FPGA interconnection across FPGA slices. An initial connection can also be established between FPGA slices to achieve FPGA interconnection between FPGA slices. FPGA packages cannot be directly interconnected. Therefore, FPGAs in different FPGA packages need to be interconnected through the first data hub within the group. FPGAs in different groups of FPGAs need to be interconnected through the second data hub and the first data hub within the group. It will be understood that the above hierarchical structure and the relationship between the number of FPGAs between levels are only examples and can be adjusted according to specific application requirements.

[0039] As an embodiment, step S2 includes:

[0040] Step S21: Split the simulation design, and set the split simulation design on the FPGA. Any two FPGAs with communication requirements have at least one corresponding communication line.

[0041] It should be noted that setting the split simulation design on the FPGA is based on the premise that the current topology structure can meet the interconnection requirements between the FPAGs that need to communicate.

[0042] Step S22: Delete the unused initial interconnection lines in the data hub.

[0043] It should be noted that some initial interconnections are pre-established in the data hub to ensure that two FPGAs with communication needs have at least one corresponding communication line. After the actual division simulation design, some unused initial interconnections may exist. By deleting them in step S22, more optional virtual paths can be provided for FPGAs with communication needs in the future, thereby improving the optimization space for system performance.

[0044] Step S23: Based on the current topology and the communication requirements of the simulation design, obtain the nth group of FPGA identifiers with communication requirements. n ,F2 n}, and {F1n ,F2 n}corresponding virtual path set {P1 n ,P2 n ,...,P i n ,...,P f(n) n}.

[0045] As an embodiment, step S3 includes:

[0046] Step S31: Obtain the time division multiplexing ratio TDR corresponding to the current virtual topology structure 0 , the initial virtual topology is the initial topology.

[0047] Step S32: Get the current virtual topology and add each current f(n)≠0 {F1 n ,F2 n Time division multiplexing ratio TDR after the corresponding direct virtual cable n 1 .

[0048] Step S33, obtain each current f(n)≠0 {F1 n ,F2 n The time division multiplexing proportional gain G of the corresponding direct virtual cable n :

[0049] G n =TDR n 1 -TDR 0 .

[0050] The step S31 and the step S32 may use the same method to obtain the time division multiplexing ratio. As an embodiment, the step S31 and the step S32 obtain the time division multiplexing ratio based on the following steps:

[0051] Step S10, obtain each {F1 n ,F2 n}The shortest path set {R1 in the corresponding virtual topology n ,R2 n ,...,R k n ,...,R g(n) n}, R k n For {F1 n ,F2 n}corresponding to the kth shortest path, {F1 n ,F2 n Each corresponding virtual cable is equivalent to a shortest path.

[0052] It should be noted that the shortest path is the path with the least number of hops. In the calculation process of the virtual cable, the bandwidth needs to be equivalent to {F1 n ,F2 n}The bandwidth after the corresponding shortest path hop count is the same.

[0053] Step S20, obtain {F1 n ,F2 n}Communication signal selection R k n The probability value A kn and R k n The corresponding original time division multiplexing ratio sum B kn ;

[0054] Step S30: Based on {F1 n ,F2 n}In the corresponding virtual topology, all R k n Corresponding A kn and B kn Get the time division multiplexing ratio corresponding to the topology structure :

[0055] .

[0056] It should be noted that if the gain is calculated directly based on the original time division multiplexing ratio, the calculation result will be inaccurate. Therefore, the embodiment of the present invention adopts the same n ,F2 n}Communication signal selection R k n The probability value A kn The combined time division multiplexing ratio improves the accuracy of the results.

[0057] It should be noted that when the step S31 is implemented through the steps S10 to S30, the virtual topology is the current virtual topology. When the step S32 is implemented through the steps S10 to S30, the virtual topology is the current virtual topology with each current f(n)≠0 added. n ,F2 n}The virtual topology structure after the corresponding direct-connected virtual cable.

[0058] As an embodiment, step S20 includes:

[0059] Step S201: According to R k n The cable width W of the yth jumper cable y nk, confirm{F1 n ,F2 n}Communication signal selection R k n The probability value A kn .

[0060] Among them, if R k n is a virtual cable, then W y nk R k n The corresponding equivalent cable width, W y nk =WA nk ÷h(nk), the value of y is 1, WA nk R k n The corresponding actual cable width.

[0061] If R k n is a non-virtual cable, then W y nk R k n The actual cable width of the corresponding y-th signal line, y ranges from 1 to h(nk), h(nk) is {F1 n ,F2 n}The number of hops of the shortest path corresponding to .

[0062] Step S202: Based on A kn and {F1 n ,F2 n The number of communication signals D n 、A kn 、R k n The cable width W of the yth jumper cable y nk Determine R k n The original time division multiplexing ratio U corresponding to the y-th jump line y nk ;

[0063] U y nk =H y nk ÷W y nk ,

[0064] H y nk For all {F1 n ,F2 n}The communication signal passes through Rk n The sum of all signal quantities of the y-th jumper connection, {F1 n ,F2 n}The communication signal passes through R k n The number of signals in the yth jumper connection is D n ×A kn .

[0065] It should be noted that R k n The first jumper connection may also be other {F1 n ,F2 n}, the original time division multiplexing ratio of the same connection needs to be calculated based on the number of signals passing through the connection, and the original time division multiplexing ratio value of the same connection is unique. n ,F2 n}, the group {F1 n ,F2 n}The communication signal passes through R k n The number of signals in the yth jumper connection is D n ×A kn It is understandable that, in the same way, other groups {F1 n ,F2 n}The number of communication signals passing through each jump line. When calculating R k n When the original time division multiplexing ratio corresponding to the y-th jump line is obtained, first obtain all {F1 n ,F2 n}The communication signal passes through R k n The total number of all signals in the y-th jump line H y nk Then compare it with R k n The cable width W of the yth jumper cable y nk , you can get R k n The original time division multiplexing ratio U corresponding to the y-th jump line y nk .

[0066] Step S203: k n The sum of the original time division multiplexing ratios of all corresponding connections is determined as R k n The corresponding original time division multiplexing ratio sum B kn .

[0067] As an embodiment, step S201 includes:

[0068] Step S2011: According to R k n The cable width of each connection in each R k n The first parameter E k n .

[0069] If R k n is a virtual cable, then E k n =1 / W y nk .

[0070] If R k n If it is a non-virtual cable, .

[0071] Step S2012: Based on each {F1 n ,F2 n} corresponding to R k n The first parameter E k n OK{F1 n ,F2 n}Communication signal selection R k n The probability value A kn :

[0072] .

[0073] As an embodiment, step S4 includes:

[0074] Step S41: In the current virtual topology, the time division multiplexing ratio gain is the highest. n ,F2 n}Add a new virtual cable.

[0075] Step S42: The virtual topology structure with the highest time division multiplexing ratio gain is n ,F2 n}Confirm as pending{F1 n ,F2 n}.

[0076] Step S43, from the pending {F1 n ,F2 n}Select a virtual path from the current corresponding virtual path set and combine it with the current virtual path combination in the current virtual path combination set to generate a new virtual path combination set.

[0077] It should be noted that step S43 requires the pending {F1 n ,F2 n}Each virtual path in the current corresponding virtual path set is added to each current virtual path combination in the current virtual path combination set for recombining, wherein the virtual path combination without path conflict after adding becomes an element in the updated virtual path set.

[0078] Step S44, delete all {F1 n ,F2 n}The virtual path in the corresponding virtual path set can no longer be selected.

[0079] It should be noted that after updating the virtual path combination set, some {F1 n ,F2 n}The virtual paths in the corresponding virtual path set can no longer be selected, so all {F1 n ,F2 n}The virtual path in the corresponding virtual path set can no longer be selected, update {F1 n ,F2 n}The corresponding virtual path set avoids subsequent calculation errors or useless calculations.

[0080] As an embodiment, step S6 includes:

[0081] Step S61: If there is only one virtual path combination in the current virtual path combination set, directly determine the virtual path combination as the target path combination.

[0082] Step S62: If there are multiple virtual path combinations in the current virtual path combination set, select one of the multiple virtual path combinations as the target path combination.

[0083] Step S63: Based on each virtual path in the target path combination, establish a connection between the internal ports of the data hub in the initial topology structure, thereby establishing the corresponding virtual path through the data hub. n ,F2 n}interconnection between them.

[0084] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used herein in the specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0085] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the steps as sequential processes, many of the steps can be performed in parallel, concurrently, or simultaneously. In addition, the order of the steps can be rearranged. A process can be terminated when its operation is completed, but can also have additional steps not included in the accompanying drawings. A process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0086] An embodiment of the present invention also provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executed by the at least one processor, and the instructions are configured to execute the method described in the embodiment of the present invention.

[0087] An embodiment of the present invention further provides a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the embodiment of the present invention.

[0088] The embodiment of the present invention first determines an initial topology structure formed by multiple groups of FPGA data hubs, then obtains the time-division multiplexing proportional gain of each group of FPGAs with communication requirements whose virtual path sets are not empty, assumes the addition of a direct-connected virtual cable, updates the virtual path combination set and the virtual path sets of all FPGA groups until all virtual path sets are empty, determines the target path combination, and then, based on the target path combination, establishes interconnections between corresponding FPGAs through the data hub on the basis of the initial topology structure. The present invention improves the system frequency of communication between multiple FPGAs and optimizes the system performance of communication between multiple FPGAs.

[0089] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Any technician familiar with the present profession can make slight changes or modifications to equivalent embodiments using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A method for interconnecting multiple FPGAs based on a data hub, characterized in that: include: Step S1: obtaining an initial topology structure consisting of multiple FPGAs and data hubs, wherein each FPGA is connected to a port of at least one data hub, the data hub including multiple ports, and an initial interconnection line is provided in the data hub; Step S2: Obtain the nth group of FPGA identifiers with communication requirements. n ,F2 n }, and {F1 n ,F2 n }corresponding virtual path set {P1 n ,P2 n ,...,P i n ,...,P f(n) n }, the value range of n is 1 to N, N is the total number of FPGA groups with communication requirements, P i n For {F1 n ,F2 n } corresponds to the i-th virtual path, the value of i ranges from 1 to f(n), and f(n) is {F1 n ,F2 n The total number of virtual paths corresponding to}, f(n) changes dynamically, and the virtual path is F1 n and F2 n Assuming that the paths connected directly through the data hubs, the initial topology satisfies any set of {F1 n ,F2 n } having at least one communication line; Step S3, respectively obtain the current virtual topology structure and add each current f(n)≠0 {F1 n ,F2 n The time division multiplexing proportional gain of the corresponding directly connected virtual cable is the initial virtual topology; Step S4: In the current virtual topology, the time division multiplexing ratio gain is the highest. n ,F2 n }Add a new virtual cable, update the virtual path combination set and all {F1 n ,F2 n } corresponding virtual path set, the virtual path combination set is used to store the virtual path combinations corresponding to all virtual cables added in the current virtual topology structure, and each added virtual cable in the virtual topology structure occupies the corresponding {F1 n ,F2 n }, the initial state of the virtual path combination set is empty; Step S5: If all f(n)=0, execute step S6; otherwise, return to execute step S3; Step S6: determining a target path combination based on the current virtual path combination set, and establishing interconnections between corresponding FPGAs based on the initial topology structure through a data hub based on the target path combination.

2. The method according to claim 1, characterized in that The step S2 comprises: Step S21: Split the simulation design into pieces, and set the split simulation design on the FPGA, so that any two FPGAs with communication requirements have at least one corresponding communication line; Step S22: deleting unused initial interconnect lines in the data hub; Step S23: Based on the current topology and the communication requirements of the simulation design, obtain the nth group of FPGA identifiers with communication requirements. n ,F2 n }, and {F1 n ,F2 n }corresponding virtual path set {P1 n ,P2 n ,...,P i n ,...,P f(n) n }.

3. The method according to claim 1, characterized in that The step S3 comprises: Step S31: Obtain the time division multiplexing ratio TDR corresponding to the current virtual topology structure 0 , the initial virtual topology is the initial topology; Step S32: Get the current virtual topology and add each current f(n)≠0 {F1 n ,F2 n Time division multiplexing ratio TDR after the corresponding direct virtual cable n 1 ; Step S33, obtain each current f(n)≠0 {F1 n ,F2 n The time division multiplexing proportional gain G of the corresponding direct virtual cable n : G n =TDR n 1 -TDR 0 。 4. The method according to claim 3, characterized in that Steps S31 and S32 are based on the following steps to obtain the time division multiplexing ratio: Step S10, obtain each {F1 n ,F2 n }The shortest path set {R1 in the corresponding virtual topology n ,R2 n ,...,R k n ,...,R g(n) n }, R k n For {F1 n ,F2 n }corresponding to the kth shortest path, {F1 n ,F2 n Each corresponding virtual cable is equivalent to a shortest path; Step S20, obtain {F1 n ,F2 n }Communication signal selection R k n The probability value A kn and R k n The corresponding original time division multiplexing ratio sum B kn ; Step S30: Based on {F1 n ,F2 n }In the corresponding virtual topology, all R k n Corresponding A kn and B kn Get the time division multiplexing ratio corresponding to the topology structure : 。 5. The method according to claim 4, characterized in that The step S20 includes: Step S201: According to R k n The cable width W of the yth jumper cable y nk , confirm{F1 n ,F2 n }Communication signal selection R k n The probability value A kn ; Among them, if R k n is a virtual cable, then W y nk R k n The corresponding equivalent cable width, W y nk =WA nk ÷h(nk), the value of y is 1, WA nk R k n The corresponding actual cable width; If R k n is a non-virtual cable, then W y nk R k n The actual cable width of the corresponding y-th signal line, y ranges from 1 to h(nk), h(nk) is {F1 n ,F2 n }The number of hops of the corresponding shortest path; Step S202: Based on A kn and {F1 n ,F2 n The number of communication signals D n 、A kn 、R k n The cable width W of the yth jumper cable y nk Determine R k n The original time division multiplexing ratio U corresponding to the y-th jump line y nk ; U y nk =H y nk ÷W y nk , H y nk For all {F1 n ,F2 n }The communication signal passes through R k n The sum of all signal quantities of the y-th jumper connection, {F1 n ,F2 n }The communication signal passes through R k n The number of signals in the yth jumper connection is D n ×A kn ; Step S203: k n The sum of the original time division multiplexing ratios of all corresponding connections is determined as R k n The corresponding original time division multiplexing ratio sum B kn .

6. The method according to claim 5, characterized in that The step S201 includes: Step S2011: According to R k n The cable width of each connection in each R k n The first parameter E k n , If R k n is a virtual cable, then E k n =1 / W y nk ; If R k n If it is a non-virtual cable, ; Step S2012: Based on each {F1 n ,F2 n } corresponding to R k n The first parameter E k n OK{F1 n ,F2 n }Communication signal selection R k n The probability value A kn : 。 7. The method according to claim 1, characterized in that The step S4 comprises: Step S41: In the current virtual topology, the time division multiplexing ratio gain is the highest. n ,F2 n }Add a new virtual cable; Step S42: The virtual topology structure with the highest time division multiplexing ratio gain is n ,F2 n }Confirm as pending{F1 n ,F2 n }; Step S43, from the pending {F1 n ,F2 n } Select a virtual path from the current corresponding virtual path set and combine it with the current virtual path combination in the current virtual path combination set to generate a new virtual path combination set; Step S44, delete all {F1 n ,F2 n }The virtual path in the corresponding virtual path set can no longer be selected.

8. The method according to claim 1, characterized in that The step S6 comprises: Step S61: If there is only one virtual path combination in the current virtual path combination set, directly determine the virtual path combination as the target path combination; Step S62: If there are multiple virtual path combinations in the current virtual path combination set, select one of the multiple virtual path combinations as the target path combination; Step S63: Based on each virtual path in the target path combination, connect the corresponding port inside the data hub of the initial topology structure, thereby establishing the corresponding virtual path through the data hub. n ,F2 n }interconnection between them.

9. An electronic device, characterized in that: include: at least one processor; and, a memory communicatively coupled to the at least one processor; The memory stores instructions to be executed by the at least one processor, wherein the instructions are configured to execute the method according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that The computer-executable instructions are stored, and the computer-executable instructions are used to execute the method according to any one of the preceding claims 1 to 8.

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