Memory controller, memory module and memory system

Abstract

A memory system is provided. A memory system includes first memory devices, second memory devices, and a memory controller configured to control a plurality of the first memory devices and the second memory devices. Each first memory device is configured to store a first data set comprising a first set of data bits at different bit positions, each bit position corresponding to a burst order and a DQ. The second memory device is configured to store a second data set including parity bits for a plurality of first data sets respectively stored in the plurality of first memory devices. Second groups of data bits corresponding to first parity bits of the parity bits are respectively included in the plurality of first data sets, and at least two data bits of the second groups of data bits have different bit positions.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2024-0031613 filed in the Korean Intellectual Property Office on March 5, 2024, Korean Patent Application No. 10-2024-0054152 filed in the Korean Intellectual Property Office on April 23, 2024, and Korean Patent Application No. 10-2024-0162503 filed in the Korean Intellectual Property Office on November 14, 2024, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a memory controller, a memory module, and a memory system. Background Art

[0004] Memory devices are used to store data and can be categorized as either volatile or nonvolatile. Volatile memory devices lose their stored data when their power supply is interrupted. Dynamic random access memory (DRAM) is a type of volatile memory used in various applications, such as mobile systems, servers, and graphics devices.

[0005] Multiple memory devices can be mounted on a single substrate and provided in the form of a memory module to achieve higher performance and larger capacity. A portion of the memory devices mounted on the memory module can store parity data to correct errors that occur in the data stored in other memory devices. Summary of the Invention

[0006] One or more example embodiments provide a memory system that performs an error correction operation with improved performance.

[0007] According to one aspect of an example embodiment, a memory system includes: a plurality of first memory devices, a second memory device, and a memory controller configured to control the plurality of first memory devices and the second memory device. Each of the plurality of first memory devices is configured to store a first data set including a first group of data bits at different bit positions, each bit position corresponding to a burst order and a DQ. The second memory device is configured to store a second data set including parity bits for the plurality of first data sets respectively stored in the plurality of first memory devices. A second group of data bits corresponding to a first parity bit in the parity bits is respectively included in the plurality of first data sets, and at least two data bits in the second group of data bits have different bit positions.

[0008] According to another aspect of an example embodiment, a memory module includes: a plurality of first memory devices; and a second memory device. Each of the plurality of first memory devices is configured to store a first data set including a first set of data bits having bit positions, each bit position corresponding to a burst order and a DQ. The second memory device is configured to store a second data set including first parity bits for the plurality of first data sets respectively stored in the plurality of first memory devices. A second set of data bits corresponding to one of the first parity bits is respectively included in the plurality of first data sets, and at least two data bits in the second set of data bits have different bit positions.

[0009] According to another aspect of the example embodiment, a method for operating a memory controller to control a memory module including a plurality of first memory devices and a second memory device is provided. The method includes: storing a plurality of first data sets in the plurality of first memory devices, respectively; and storing a second data set in the second memory device, the second data set including parity bits for the plurality of first data sets. Each of the plurality of first data sets includes a first group of data bits having bit positions, each bit position corresponding to a burst order and a DQ. A second group of data bits corresponding to a first parity bit in the parity bits is included in the plurality of first data sets, respectively, and the bit positions of at least two data bits in the second group of data bits are different from each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects and features of the present disclosure will be more clearly understood through the following description of example embodiments with reference to the accompanying drawings, in which:

[0011] Figure 1 is a block diagram of an electronic system according to an example embodiment;

[0012] Figure 2A is a diagram illustrating bit positions of bits included in a data set according to an example embodiment;

[0013] Figure 2B is a diagram showing a related parity check map;

[0014] Figure 2C is a diagram illustrating a parity map according to an example embodiment;

[0015] Figure 3 is a diagram illustrating a memory bank according to an example embodiment;

[0016] Figure 4 is a block diagram of a memory device according to an example embodiment;

[0017] Figure 5 is a block diagram of a memory controller according to an example embodiment;

[0018] Figure 6 is a flowchart illustrating a method of operating a memory system according to an example embodiment;

[0019] Figure 7A and Figure 7B is a diagram illustrating a method of operating a memory system according to example embodiments;

[0020] Figure 8 is a flowchart illustrating a method of operating a memory system according to an example embodiment;

[0021] Figure 9A 、 Figure 9B 、 Figure 9C and Figure 9D is a diagram illustrating a method of operating a memory system according to example embodiments;

[0022] Figure 10A and Figure 10B is a diagram illustrating limitations of error correction operations during correlation parity mapping;

[0023] Figure 11A 、 Figure 11B 、 Figure 11C and Figure 11D is a diagram illustrating a method of operating a memory system according to example embodiments; and

[0024] Figure 12 is a block diagram of an electronic system according to an example embodiment. DETAILED DESCRIPTION

[0025] Hereinafter, example embodiments will be described with reference to the accompanying drawings.

[0026] Figure 1 is a block diagram illustrating a configuration of an electronic system according to example embodiments.

[0027] refer to Figure 1 , the electronic system 10 may include a host 15 and a memory system 20. The memory system 20 may include a memory controller 100 and a memory module 2000. The memory module 2000 may include a plurality of memory devices 200p, 200d_1 to 200d_n. The plurality of memory devices 200p, 200d_1 to 200d_n may include a plurality of data storage devices 200d_1 to 200d_n and a single parity memory device 200p.

[0028] Each of the plurality of memory devices 200p, 200d_1 to 200d_n can input or output bits in units of a prefetch size. Hereinafter, a set of bits stored in a memory device by a single write operation or output from a memory device by a single read operation corresponding to the prefetch size is referred to as a "data set."

[0029] The prefetch size is determined based on the number of DQs used by each memory device (ie, data bus width or number of data pins) and the burst length so that the bits contained in the data set can have bit positions defined by the burst order and DQs.

[0030] According to example embodiments, each of the plurality of data storage devices 200d_1 to 200d_n may store a first data set including data bits, and the parity memory device 200p may store a second data set including parity bits for the plurality of first data sets respectively stored in the plurality of data storage devices 200d_1 to 200d_n.

[0031] A data bit corresponding to one of the parity bits included in the second data set is included in a different first data set and may have a different bit position.

[0032] As described above, parity bits mapped to data bits having different bit positions in each first data set may be stored in the parity storage device 200 p , thereby allowing the memory system 20 to perform error correction operations with improved performance.

[0033] Now refer to Figure 1 A detailed description is provided. The host 15 can communicate with the memory system 20 using an interface protocol such as Peripheral Component Interconnect-Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), or Serial Attached SCSI (SAS). The interface protocol between the host 15 and the memory system 20 is not limited to the above examples, and may be one of other interface protocols such as a Universal Serial Bus (USB) protocol, an MMC protocol, an Enhanced Small Disk Interface (ESDI) protocol, or an Integrated Drive Electronics (IDE) protocol.

[0034] The memory controller 100 may control the overall operation of the memory system 20. The memory controller 100 may control the overall data exchange between the host 15 and the memory module 2000. For example, the memory controller 100 may control the memory devices 200p, 200d_1 to 200d_n to write or read data in response to a request from the host 15. In addition, the memory controller 100 may control the operation of the memory devices 200p, 200d_1 to 200d_n by applying commands and / or addresses to control the memory devices 200p, 200d_1 to 200d_n.

[0035] According to example embodiments, the memory controller 100 may control the storage of a plurality of first data sets in a plurality of data storage devices 200d_1 to 200d_n. Furthermore, the memory controller 100 may control the storage of (i.e., storage of) a second data set in the parity storage device 200p. Each parity bit included in the second data set may have a value based on an XOR operation of corresponding data bits. For example, each parity bit may have an even XOR parity, but example embodiments are not limited thereto. In some example embodiments, each parity bit may have an odd XOR parity.

[0036] The memory controller 100 may receive a plurality of first and second data sets from the plurality of data storage devices 200d_1 through 200d_n and the parity memory device 200p and may perform an error correction operation on the received data sets.

[0037] For example, when the host 15 requests data, the memory controller 100 may apply a read command to the plurality of data storage devices 200d_1 to 200d_n and the parity storage device 200p to receive a plurality of first and second data sets. The memory controller 100 may then perform a parity check on the plurality of first and second data sets to determine a candidate error bit position for each of the plurality of first and second data sets.

[0038] The memory controller 100 may obtain a first flag corresponding to each of the plurality of first and second data sets. Each first flag may indicate the result of an error correction operation performed on each of the memory devices 200p, 200d_1, 200d_n. For example, the first flag may include the results of multiple error correction operations, each of which is performed on multiple first data sets in the plurality of data storage devices 200d_1, 200d_n. Furthermore, the first flag may include the result of an error correction operation performed on the second data set in the parity memory device 200p. Therefore, based on the received first flag, the memory controller 100 may determine an erroneous data set including an error bit among the plurality of first and second data sets.

[0039] According to an example embodiment, when the first flag has a specific value, the memory controller 100 can determine an error data set. Even when the first flag does not have a specific value, the memory controller 100 can perform an iterative operation to determine an error data set again, which will be described later. Therefore, the probability of detecting an error data set can be increased. As described above, this is because the parity bits are mapped to data bits with different bit positions in each first data set and stored in the parity storage device 200p.

[0040] Therefore, the memory controller 100 may flip a bit corresponding to a candidate error bit position among bits included in the error data set to perform an error correction operation.

[0041] According to example embodiments, the memory controller 100 may include a system error correction code (ECC) circuit 120. The system ECC circuit 120 may perform operations related to error correction operations among operations of the memory controller 100. For example, the system ECC circuit 120 may perform operations such as mapping data bits and parity bits by changing bit positions, performing a parity check to determine a candidate error bit position, determining an error data set based on a flag, and flipping a bit corresponding to a candidate error bit position among bits included in the error data set, but example embodiments are not limited thereto.

[0042] Each of the plurality of memory devices 200p, 200d_1 to 200d_n may receive a data set from the memory controller 100 and store the received data set. In addition, each of the plurality of memory devices 200p, 200d_1 to 200d_n may read the stored data set in response to a request from the memory controller 100 and transmit the read data set to the memory controller 100.

[0043] According to example embodiments, memory module 2000 may be a dual in-line memory module (DIMM). For example, memory module 2000 may be a registered DIMM (RDIMM), a load-reduced DIMM (LRDIMM), an unbuffered DIMM (UDIMM), a fully buffered DIMM (FB-DIMM), or a small form-factor DIMM (SO-DIMM). However, example embodiments are not limited thereto, and memory module 2000 may also be another memory module, such as a single in-line memory module (SIMM).

[0044] According to example embodiments, each of the plurality of memory devices 200p, 200d_1 to 200d_n may be a memory device including volatile memory cells. For example, the memory device 200 may be various dynamic random access memory (DRAM) devices, such as a double data rate synchronous DRAM (DDR SDRAM) device, a DDR2 SDRAM device, a DDR3 SDRAM device, a DDR4 SDRAM device, a DDR5 SDRAM device, a DDR6 SDRAM device, a low power double data rate (LPDDR) SDRAM device, an LPDDR2 SDRAM device, an LPDDR3 SDRAM device, an LPDDR4 SDRAM device, an LPDDR4X SDRAM device, an LPDDR5 SDRAM device, a graphics double data rate synchronous graphics random access memory (GDDR SGRAM) device, a GDDR2 SGRAM device, a GDDR3 SGRAM device, a GDDR4 SGRAM device, a GDDR5 SGRAM device, or a GDDR6 SGRAM device.

[0045] According to example embodiments, each of the plurality of memory devices 200 p , 200 d_1 through 200 d_n may be a memory device in which DRAM dies are stacked, such as a high bandwidth memory (HBM), HBM2, or HBM3.

[0046] According to example embodiments, each of the plurality of memory devices 200 p , 200 d_1 through 200 d_n may be an SRAM device, a NAND flash memory device, a NOR flash memory device, an RRAM device, a FRAM device, a PRAM device, a TRAM device, or an MRAM device.

[0047] According to example embodiments, the plurality of data storage devices 200d_1 to 200d_n can provide data corresponding to a cache line size. Therefore, the number of the plurality of data storage devices 200d_1 to 200d_n can be determined based on the prefetch size of each of the plurality of data storage devices 200d_1 to 200d_n. When the cache line size is 64 bytes (=512 bits) and the prefetch size of each of the plurality of data storage devices 200d_1 to 200d_n is 128 bits, the number of the plurality of data storage devices 200d_1 to 200d_n can be four. When the cache line size is 64 bytes (=512 bits) and the prefetch size of each of the plurality of data storage devices 200d_1 to 200d_n is 256 bits, the number of the plurality of data storage devices 200d_1 to 200d_n can be two.

[0048] According to example embodiments, multiple memory devices 200p, 200d_1, through 200d_n may each include an on-chip ECC circuit 350p, 350d_1, through 350d_n that generates the aforementioned first flag. For example, each of the on-chip ECC circuits 350p, 350d_1, through 350d_n may use a parity check matrix (or H-matrix) to perform an error correction operation on a data set input or output by the corresponding memory device and generate a first flag indicating the result of the error correction operation. The first flag may indicate a non-uncorrectable error (non-UE) when it is determined that no error has occurred or that the error has been corrected, or an uncorrectable error (UE) when it is determined that an uncorrectable error has occurred. The generated first flag may be provided to the memory controller 100 upon request from the memory controller 100.

[0049] According to example embodiments, each of the plurality of data storage devices 200d_1 through 200d_n may be referred to as a data chip. In addition, the parity memory device 200p may be referred to as a module ECC chip, a system ECC chip, etc., but example embodiments are not limited thereto.

[0050] As described above, the memory system 20 according to one or more example embodiments may perform an error correction operation with improved performance.

[0051] Figure 2A is a diagram illustrating bit positions of bits included in a data set according to an example embodiment. Figure 2A In the example, for the convenience of description, the pre-fetch size of the data set is 16 bits.

[0052] like Figure 2A As shown, a memory device using data set 30 has a burst length (BL) of 4 and uses four DQs. The data set may include 16 bits corresponding to the 16 bit positions defined by the burst order BL0, BL1, BL2, and BL3 and DQ0, DQ1, DQ2, and DQ3, respectively.

[0053] Similarly, bits included in data sets having other prefetch sizes may also have bit positions defined by the burst order and DQ.

[0054] Figure 2B is a diagram showing a related parity map. Figure 2B Shown are first data sets, Data 1 and Data 2, stored in two data storage devices having a prefetch size of 16 bits, and a second data set stored in a parity storage device.

[0055] refer to Figure 2BIn the case of the related art, parity bits for data bits having the same bit position in the first data sets Data 1 and Data 2 may be stored in the same bit position in the second data set Parity.

[0056] For example, the parity bit "0" of the data bits "11" at bit positions BL0 and DQ0 in Data 1 and Data 2 can be stored at bit positions BL0 and DQ0 in Parity. Furthermore, for example, the parity bit "1" of the data bits "01" at bit positions BL2 and DQ3 in Data 1 and Data 2 can be stored at bit positions BL2 and DQ3 in Parity. The same applies to the remaining data bits and parity bits.

[0057] Figure 2C is a diagram illustrating a parity map according to an example embodiment. Figure 2C Shown are first data sets Data 1 and Data 2 stored in two data storage devices having a 16-bit prefetch size, and a second data set Parity stored in a parity storage device.

[0058] According to example embodiments, at least two data bits among data bits corresponding to one of the parity bits included in the second data set Parity may have different bit positions in the corresponding at least two first data sets, respectively.

[0059] refer to Figure 2C , the parity bit “0” of the data bit “1” having the bit position BL0 and DQ0 in Data 1 and the data bit “1” having the bit position BL0 and DQ3 in Data 2 can be stored at the bit position BL0 and DQ2 in the parity. In addition, for example, the data bit “0” having the bit position BL2 and DQ3 in Data 1 and the parity bit “1” having the bit position BL2 and DQ2 in Data 2 can be stored at the bit position BL2 and DQ1 in the parity. As described above, according to example embodiments, each data bit and the corresponding parity bit can be mapped to have different DQ positions. As Figure 2C As shown, DQ0 of Data 1, DQ3 of Data 2, and DQ2 in parity are mapped to each other, DQ1 of Data 1, DQ0 of Data 2, and DQ3 in parity are mapped to each other, DQ2 of Data 1, DQ1 of Data 2, and DQ0 in parity are mapped to each other, and DQ3 of Data 1, DQ2 of Data 2, and DQ1 in parity are mapped to each other.

[0060] However, example embodiments are not limited thereto, and each data bit and corresponding parity bit may be mapped to have a different BL position, or each data bit and corresponding parity bit may be mapped to have a different BL position and a different DQ position.

[0061] Figure 3 is a diagram illustrating a memory bank according to example embodiments. Figure 3 The memory bank 300 may be Figure 1 One of a plurality of memory banks included in each of the plurality of memory devices 200p, 200d_1 to 200d_n.

[0062] refer to Figure 3 The memory bank 300 may include a memory bank array 310_1, a row decoder 260_1, and a column decoder 270_1. The memory bank array 310_1 may include a plurality of memory cells. The plurality of memory cells may be electrically connected to a plurality of word lines WL1 to WLj and a plurality of column select lines CSL1 to CSLi.

[0063] The bank array 310_1 may include a normal cell area NA in which a data set is stored and a parity cell area PA in which parity bits for the data set stored in the normal cell area NA are stored.

[0064] The row decoder 260_1 may activate one of the plurality of rows ROW1 to ROWj in response to the row address RA. For example, the plurality of rows ROW1 to ROWj may correspond to the plurality of word lines WL1 to WLj, respectively.

[0065] The column decoder 270_1 may activate one of a plurality of column selection lines CSL1 to COLi in response to a column address CA.

[0066] For example, when the memory bank 300 is included in the data storage devices 200d_1 to 200d_n, a first data set including data bits may be stored in the normal cell area NA, and parity bits of the first data set may be stored in the parity cell area PA.

[0067] When the memory bank 300 is included in the parity memory device 200p, a second data set including parity bits of a plurality of first data sets respectively stored in a plurality of data storage devices 200d_1 to 200d_n may be stored in the normal cell area NA, and the parity bits of the second data set may be stored in the parity cell area PA.

[0068] Figure 4 is a block diagram of a memory device according to example embodiments. Figure 4 The memory device 200 may correspond to Figure 1One of the plurality of memory devices 200p, 200d_1 to 200d_n.

[0069] refer to Figure 4 The memory device 200 may include a control logic circuit 210, an address register 220, a memory bank control circuit 230, a refresh control circuit 400, a row address multiplexer 240, a column address latch 250, a row decoder group 260, a column decoder group 270, a memory cell array 310, a sense amplifier group 285, an input / output selection circuit 290, an on-chip ECC circuit 350, and a data input / output buffer 320.

[0070] The memory cell array 310 may include a plurality of memory bank arrays 310_1 to 310_n. Each of the plurality of memory bank arrays 310_1 to 310_n may include a plurality of memory cells. For example, each of the plurality of memory cells may be formed at an intersection of a corresponding word line and a corresponding bit line. Each of the plurality of memory bank arrays 310_1 to 310_n may correspond to Figure 3 The memory bank array 310_1 is shown in FIG. 3 , but example embodiments are not limited thereto.

[0071] The row decoder group 260 may include a plurality of row decoders 260_1 through 260_n. Each of the plurality of row decoders 260_1 through 260_n may be connected to a corresponding memory bank array among the plurality of memory bank arrays 310_1 through 310_n.

[0072] The sense amplifier group 285 may include a plurality of sense amplifiers 285_1 to 285_n. Each of the plurality of sense amplifiers 285_1 to 285_n may be connected to a corresponding memory bank array among the plurality of memory bank arrays 310_1 to 310_n.

[0073] The column decoder group 270 may include a plurality of column decoders 270_1 to 270_n. Each of the plurality of column decoders 270_1 to 270_n may be connected to a corresponding memory bank array among the plurality of memory bank arrays 310_1 to 310_n through a column selection line.

[0074] The address register 220 may receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from the memory controller 100. The address register 220 may provide the received bank address BANK_ADDR to the bank control circuit 230, provide the received row address ROW_ADDR to the row address multiplexer 240, and provide the received column address COL_ADDR to the column address latch 250.

[0075] The bank control circuit 230 may generate a bank control signal in response to the bank address BANK_ADDR. For example, a row decoder corresponding to the bank address BANK_ADDR among the plurality of row decoders 260_1 to 260_n may be activated in response to the bank control signal. A column decoder corresponding to the bank address BANK_ADDR among the plurality of column decoders 270_1 to 270_n may be activated in response to the bank control signal.

[0076] The row address multiplexer 240 may receive a row address ROW_ADDR from the address register 220 and a refresh row address REF_ADDR from the refresh control circuit 400. The row address multiplexer 240 may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 240 may be applied to each of the plurality of row decoders 260_1 to 260_n.

[0077] The refresh control circuit 400 may sequentially increment or decrement the refresh row address REF_ADDR in response to a refresh signal from the control logic circuit 210 in the normal refresh mode.

[0078] The refresh control circuit 400 may receive a hammer address HADDR in the hammer refresh mode and may output an address of a word line adjacent to a densely accessed word line as a refresh row address REF_ADDR based on the hammer address HADDR.

[0079] A row decoder selected among the plurality of row decoders 260_1 to 260_n by the bank control circuit 230 may activate a word line corresponding to the row address RA output from the row address multiplexer 240. For example, the selected row decoder may apply a word line driving voltage to the word line corresponding to the row address.

[0080] The column address latch 250 may receive the column address COL_ADDR from the address register 220 and temporarily store the received column address COL_ADDR.

[0081] According to an example embodiment, the memory device 200 may perform a burst operation in a burst mode. A burst operation may refer to an operation that writes or reads a large amount of data by sequentially decrementing or incrementing the address from an initial address received by the memory device 200 from the memory controller 100. The basic unit of such a burst operation may be a burst length. For example, the burst length may be the number of times data is continuously read or written by decrementing or incrementing the address from the initial address. In an example embodiment, when the burst length is 8, the memory device 200 may continuously perform a burst read operation or a burst write operation 8 times from the initial address in response to the clock signal CLK.

[0082] For example, the column address latch 250 may increment the received column address COL_ADDR in a burst mode.The column address latch 250 may apply the temporarily stored or incremented column address COL_ADDR′ to each of the plurality of column decoders 270_1 to 270_n.

[0083] A column decoder activated by the bank control circuit 230 among the plurality of column decoders 270_1 to 270 — n may activate a sense amplifier corresponding to a bank address BANK_ADDR and a column address COL_ADDR through the input / output gating circuit 290 .

[0084] The input / output gating circuit 290 may include a circuit for gating input / output data. In addition, the input / output gating circuit 290 may include a data latch for storing codewords output from the plurality of memory bank arrays 310_1 to 310_n, and a write driver for writing data in the plurality of memory bank arrays 310_1 to 310_n.

[0085] In an example embodiment, during a read operation, a codeword CW read from a selected memory bank array among the plurality of memory bank arrays 310_1 to 310_n may be detected by a sense amplifier corresponding to the selected memory bank array and stored in a data latch of the input / output strobe circuit 290. Furthermore, the codeword CW stored in the data latch may be ECC-decoded by the on-chip ECC circuit 350 to be provided as data DTA to the data input / output buffer 320. The data input / output buffer 320 may generate a data signal DQ based on the data DTA and provide the data signal DQ together with the strobe signal DQS to the memory controller 100.

[0086] In an example embodiment, during a write operation, data DTA to be written to a selected memory bank array among the plurality of memory bank arrays 310_1 to 310_n may be received by the data input / output buffer 320 as a data signal DQ. The data input / output buffer 320 may convert the data signal DQ into data DTA and provide the data DTA to the on-chip ECC circuit 350. The on-chip ECC circuit 350 may generate parity bits or parity data based on the data DTA and provide a codeword CW including the data DTA and the parity bits to the input / output strobe circuit 290. The input / output strobe circuit 290 may write the codeword CW to the normal cell area NA and the parity cell area PA of the selected memory bank array.

[0087] During a write operation, the data input / output buffer 320 may convert the data signal DQ into data DTA and provide the data DTA to the on-chip ECC circuit 350. During a read operation, the data input / output buffer 320 may convert the data DTA provided from the on-chip ECC circuit 350 into the data signal DQ.

[0088] The on-chip ECC circuit 350 may perform ECC encoding on the data DTA during a write operation. The on-chip ECC circuit 350 may perform ECC decoding on the codeword CW during a read operation.

[0089] According to an example embodiment, the on-chip ECC circuit 350 may perform an error correction operation on a data set input or output through the memory device 200 based on a codeword CW and a parity check matrix (or H matrix) during a read operation, and may generate a first flag regarding the result of performing the error correction operation. The first flag may indicate a non-uncorrectable error (non-UE) or an uncorrectable error (UE). No UE indicates that there are no errors in the data set, or that there are errors but the errors have been corrected, while UE indicates that an uncorrectable error has occurred in the data set.

[0090] In example embodiments, the on-chip ECC circuit 350 included in each of the plurality of memory devices 200p, 200d_1 through 200d_n may be a corresponding device. For example, the on-chip ECC circuit 350 provided in each of the plurality of memory devices 200p, 200d_1 through 200d_n may be the same model or product.

[0091] The control logic circuit 210 may control the operation of the memory device 200. For example, the control logic circuit 210 may generate control signals so that the memory device 200 performs a write operation, a read operation, a normal refresh operation, and a hammer refresh operation. The control logic circuit 210 may include a command decoder 211 that decodes a command CMD received from the memory controller 100, and a mode register set (MRS) 212 that sets an operation mode of the memory device 200.

[0092] The command decoder 211 may decode the command CMD to generate internal command signals, such as an internal active signal IACT, an internal precharge signal IPRÉ, an internal read signal IRD, and an internal write signal IWR. Furthermore, the command decoder 211 may decode a chip select signal and a command / address signal to generate a control signal corresponding to the command CMD.

[0093] According to example embodiments, a new read command (hereinafter referred to as, for example, a read retry command) may be defined to request a first flag and a data set generated by the on-chip ECC circuit 350. When the read retry command is received from the memory controller 100, the command decoder 211 may decode the read retry command and control the operation of the memory device 200 to provide the first flag together with the data set.

[0094] The mode register set 212 may set an operation mode of the memory device 200. According to an example embodiment, the mode register set 212 may include a mode register that sets the operation mode of the memory device 200 to a first mode or a second mode. The first mode may be a mode in which the memory device 200 operates to provide only a data set in response to a normal read command, and the second mode may be a mode in which the memory device 200 operates to provide a first flag generated by the on-chip ECC circuit 350 together with the data set in response to a normal read command.

[0095] For example, when a first value is set in the mode register, the memory device 200 can operate in the first mode. Furthermore, when a second value different from the first value is set in the mode register, the memory device 200 can operate in the second mode. The memory controller 100 can change the set value of the mode register by, for example, issuing a mode register write (MRW) command to change the operating mode of the memory device 200.

[0096] According to example embodiments, the memory device 200 may include a pin assigned to output a first flag regarding a result of an error correction operation performed by the on-chip ECC circuit 350. The memory device 200 may apply a signal corresponding to the first flag generated by the on-chip ECC circuit 350 to the pin, and the memory controller 100 may obtain the first flag based on the signal applied to the pin.

[0097] Alternatively, according to example embodiments, the memory device 200 may extend the burst length. For example, the memory device 200 may select a single burst length from a plurality of burst lengths and operate based on the selected burst length. Thus, during operation based on a first burst length selected from a plurality of burst lengths, the memory device 200 may extend the burst length by changing the burst length to a second burst length that is relatively larger than the first burst length. The memory device 200 may use the burst added based on the extended burst length to provide the memory controller 100 with a first flag generated by the on-chip ECC circuit 350.

[0098] Figure 5 is a block diagram of a memory controller according to an example embodiment. Figure 5 The memory controller 100 may correspond to, for example Figure 1 The memory controller 100 is configured to:

[0099] refer to Figure 5 , the memory controller 100 may include a processor 110 , a system ECC circuit 120 , a refresh logic (ie, refresh logic circuit) 130 , a host interface 140 , a scheduler (ie, scheduler circuit) 150 , and a memory interface 160 , all of which are connected to each other via a bus.

[0100] The processor 110 may control the overall operation of the memory controller 100. For example, the processor 110 may control each of the system ECC circuit 120, the refresh logic 130, the host interface 140, the scheduler 150, and the memory interface 160.

[0101] The refresh logic 130 may generate a command to perform a normal refresh operation on the plurality of word lines of the memory device 200. For example, the refresh logic 130 may generate an auto-refresh command for sequentially refreshing the plurality of word lines according to a refresh cycle.

[0102] The host interface 140 can interface with the host 15 .

[0103] The scheduler 150 may manage the scheduling and transmission of command sequences generated within the memory controller 100 .

[0104] The memory interface 160 may interface with the memory module 2000 .

[0105] The system ECC circuit 120 may store a second data set in the parity storage device 200p. The second data set may include parity bits for the plurality of first data sets stored in the plurality of data storage devices 200d_1 to 200d_n. According to an example embodiment, one of the parity bits included in the second data set and the data bit corresponding to the parity bit may have different bit positions. To this end, the system ECC circuit 120 may map each data bit and the corresponding parity bit to different bit positions. For example, the system ECC circuit 120 may map data bits and corresponding parity bits selected from the plurality of first data sets to different DQs (or DQ positions). Furthermore, the system ECC circuit 120 may map data bits and corresponding parity bits selected from the plurality of first data sets to different burst orders (or BL positions). Furthermore, the system ECC circuit 120 may map data bits and corresponding parity bits selected from the plurality of first data sets to different BL positions and DQ positions.

[0106] The system ECC circuit 120 may perform a system ECC operation based on the plurality of first and second data sets obtained through a read operation from the memory module 2000. The system ECC operation may include various operations for correcting an error included in one of the plurality of first data sets based on the second data set.

[0107] For example, when a plurality of first and second data sets are received from a plurality of data storage devices 200 d_1 through 200 d_n and the parity memory device 200 p , the system ECC circuit 120 may perform a parity check on the received data.

[0108] According to an example embodiment, the parity bits included in the second data set may be even XOR parity. The system ECC circuit 120 may compare the result of the XOR operation of the data bits with the parity bits to perform a parity check. For example, when the result of the XOR operation matches the parity bit, it can be determined that the parity bit and the data bits mapped to the parity bit do not include an error bit. When the result of the XOR operation does not match the parity bit, it can be determined that an error bit exists between the parity bit and the data bits mapped to the parity bit.

[0109] For example, a parity check may be performed to determine whether an error has occurred in the plurality of first and second data sets.Furthermore, a parity check may be performed to identify candidate error bit positions in each of the plurality of first and second data sets.

[0110] However, even when performing the parity check, it is not specified which of the plurality of first and second data sets includes an actual error bit. Therefore, the system ECC circuit 120 can specify an error data set including an error bit by performing the following operations.

[0111] For example, when obtaining a first flag corresponding to each of the plurality of first and second data sets, the system ECC circuit 120 may determine an error data set including error bits among the plurality of first and second data sets based on the obtained first flag.

[0112] According to an example embodiment, when the first flag has a specific value, the system ECC circuit 120 can determine an erroneous data set. In addition, according to an example embodiment, even when the first flag does not have a specific value, the system ECC circuit 120 can perform additional iterative operations to determine an erroneous data set, which will be described later. According to an example embodiment, the system ECC circuit 120 may include a parity check matrix used by the on-chip ECC circuit 350 of the memory device 200, and may perform iterative operations using the parity check matrix. Alternatively, according to an example embodiment, the system ECC circuit 120 may perform iterative operations using multiple data storage devices 200d_1 to 200d_n and the parity storage device 200p. This will be described in detail later.

[0113] As described above, when a candidate error bit position and an error data set are identified, the system ECC circuit 120 may perform an error correction operation by flipping a bit corresponding to the candidate error bit position among bits included in the error data set.

[0114] In the following, reference will be made to Figures 6 to 11D System ECC operations according to example embodiments are described in detail.

[0115] Figure 6 is a flowchart illustrating a method of operating a memory system according to example embodiments. Figure 6 The memory controller 100 and the memory module 2000 may correspond to Figure 1 The memory system 20 includes a memory controller 100 and a memory module 2000. Figure 6 In the embodiment, the plurality of data storage devices 200d_1 to 200d_n included in the memory module 2000 respectively store the plurality of first data sets. In addition, the parity storage device 200p included in the memory module 2000 stores the second data set.

[0116] refer to Figure 6 In operation S605, the memory controller 100 may send a read command to the memory module 2000. The read command may be a normal read command, but example embodiments are not limited thereto. For example, when the host 15 requests data, the memory controller 100 may send a read command to each of the plurality of data storage devices 200d_1 to 200d_n and the parity memory device 200p.

[0117] In operation S610 , each of the plurality of data storage devices 200 d_1 through 200 d_n and the parity memory device 200 p may perform a read operation in response to a read command and provide a plurality of first and second data sets Data and Parity to the memory controller 100 .

[0118] In operation S615 , the memory controller 100 may perform a parity check on the plurality of first and second data sets. When no error is detected through the parity check in operation S615 , the flow proceeds to operation S620 , where the memory controller 100 may send the plurality of first data sets to the host 15 .

[0119] When a candidate error bit position is identified through parity checking in operation S615, the memory controller 100 may obtain a first flag Flag_1 corresponding to each of the plurality of first and second data sets from the plurality of data storage devices 200d_1 to 200d_n and the parity storage device 200p, respectively. The first flag Flag_1 may indicate an uncorrectable error (UE) or a non-uncorrectable error (no UE). However, example embodiments are not limited thereto, and the first flag Flag_1 may further include no error (NE) indicating that no error was detected, a correctable error (CE) indicating that the error was corrected, or an uncorrectable error (UE). NE and CE may correspond to no UE.

[0120] According to example embodiments, in operation S625, the memory controller 100 may transmit a read retry command to the plurality of data storage devices 200d_1 through 200d_n and the parity memory device 200p. Accordingly, in operation S630, each of the plurality of data storage devices 200d_1 through 200d_n and the parity memory device 200p may provide the memory controller 100 with a first flag Flag_1 in response to the read retry command.

[0121] According to example embodiments, each of the plurality of data storage devices 200d_1 through 200d_n and the parity memory device 200p may include Figure 4 The memory controller 100 may use a mode register write command to change the set value of the mode register to a second value. Then, the memory controller 100 may send a normal read command to each of the plurality of data storage devices 200d_1 to 200d_n and the parity memory device 200p to obtain the first flag Flag_1.

[0122] In operation S635 , the memory controller 100 may attempt to identify an erroneous data set based on the first flag Flag_1 . For example, when only one first flag Flag_1 is UE, the memory controller 100 may identify the data set corresponding to UE among the plurality of first and second data sets as an erroneous data set.

[0123] When an error data set is identified in operation S635, the process proceeds to operation S640, where the memory controller 100 may flip the bits included in the error data set corresponding to the candidate error bit position. Thus, an error that has occurred in one of the plurality of first and second data sets may be corrected.

[0124] According to example embodiments, one of the plurality of first data sets may be an error data set. In operation S645 , the memory controller 100 may transmit the remaining first data sets except the error data set and the error data set in which bits corresponding to the candidate error bit positions are flipped to the host 15 .

[0125] When only one first flag Flag_1 indicates no UE in operation S635, for example, when no error data set is identified, the process proceeds to operation S650, where the memory controller 100 may perform an iterative operation. For example, when all first flags Flag_1 indicate no UE in operation S635, the process proceeds to operation S650, where the memory controller 100 may perform an iterative operation. Figure 8 Describe the iterative operation in detail.

[0126] Figure 7A and 7B is a diagram illustrating a method of operating a memory system according to example embodiments. Figure 7A Shown are first data sets Data 1 and Data 2 each having a 16-bit prefetch size stored in two data storage devices, and a second data set Parity stored in a parity storage device. Figure 7B Shown in the Figure 7A The state of the data set after the error correction operation of the memory system 20 is performed.

[0127] Figure 7A and Figure 7B Shown as Figure 2C Each data bit and corresponding parity bit is shown mapped as an example with different DQ positions. Figure 7A and Figure 7B In FIG. 1 , the operation of the memory system 20 will be described by taking an example in which three errors indicated by “X” occur in Data 1.

[0128] When a read operation receives Figure 7A When Data 1, Data 2, and Parity are shown, the memory controller 100 may perform a parity check on Data 1, Data 2, and Parity and identify candidate error bit positions.

[0129] refer to Figure 7A, errors exist in the bit positions (BL0, DQ3), (BL1, DQ1), and (BL3, DQ2) among the bit positions of Data 1. Therefore, the memory controller 100 can recognize that errors have occurred in the bit positions (BL0, DQ1), (BL1, DQ3), and (BL3, DQ0) (indicated by “!”) among the bit positions of Parity through the parity check between the mapped data bits and the parity bits.

[0130] Therefore, the memory controller 100 can identify (BL0, DQ3) of Data 1 and (BL0, DQ2) of Data 2, which are mapped to (BL0, DQ1) of Parity, along with (BL0, DQ1) of Parity, as candidate error bit locations. Furthermore, the memory controller 100 can identify (BL1, DQ1) of Data 1 and (BL1, DQ0) of Data 2, which are mapped to (BL1, DQ3) of Parity, along with (BL1, DQ3) of Parity, as candidate error bit locations. Furthermore, the memory controller 100 can identify (BL3, DQ2) of Data 1 and (BL3, DQ1) of Data 2, which are mapped to (BL3, DQ0) of Parity, along with (BL3, DQ0) of Parity, as candidate error bit locations.

[0131] As a result, the memory controller 100 can identify the candidate error bit positions of Data 1 as (BL0, DQ3), (BL1, DQ1), and (BL3, DQ2), the candidate error bit positions of Data 2 as (BL0, DQ2), (BL1, DQ0), and (BL3, DQ1), and the candidate error bit positions of Parity as (BL0, DQ1), (BL1, DQ3), and (BL3, DQ0).

[0132] The candidate error bit positions have been identified so that the memory controller 100 can obtain the first flag Flag_1 corresponding to Data 1 , Data 2 , and Parity.

[0133] In example embodiments, the two data storage devices corresponding to Data 1 and Data 2 and the parity storage device corresponding to Parity may each include an on-chip ECC circuit 350 using a single error correction double error detection (SECDED) Hamming code. Figure 7AAs shown, there are three error bits in Data 1, so the on-chip ECC circuit 350 of the data storage device corresponding to Data 1 can generate UE as the first flag Flag_1. In addition, there are no errors in Data 2, so the on-chip ECC circuit 350 of the data storage device corresponding to Data 2 can generate no UE as the first flag Flag_1. In addition, there are no errors in Parity, so the on-chip ECC circuit 350 of the parity storage device can generate no UE as the first flag Flag_1.

[0134] According to example embodiments, the memory controller 100 may obtain the first flag Flag_1 generated from each memory device using a read retry command or a mode register.

[0135] The memory controller 100 may attempt to identify an erroneous data set based on the obtained first flag Flag_1. For example, when only one of the first flags Flag_1 is UE, the memory controller 100 may identify the data set corresponding to UE among the plurality of first and second data sets as an erroneous data set. Figure 7A , only the first flag Flag_1 corresponding to Data 1 is UE, so the memory controller 100 can identify the data set Data 1 corresponding to UE as an error data set.

[0136] Therefore, the memory controller 100 may flip the bit corresponding to the candidate error bit position among the bits included in the error data set. Figure 7A In the example of , the error data set is Data 1, and the candidate error bit positions of Data 1 are identified as (BL0, DQ3), (BL1, DQ1), and (BL3, DQ2). Therefore, the memory controller 100 may flip the bits corresponding to (BL0, DQ3), (BL1, DQ1), and (BL3, DQ2) among the bits of Data 1. Figure 7B As shown, three error bits included in Data 1 can be corrected.

[0137] Figure 8 is a flowchart illustrating a method of operating a memory system according to example embodiments. Figure 8 The operation can be Figure 6 An example of an iterative operation in operation S650. Figure 6 As described above, according to example embodiments, when the first flag Flag_1 is all non-UE, the memory controller 100 may perform an iterative operation.

[0138] refer to Figure 8In operation S651, the memory controller 100 may flip the bits corresponding to the candidate error bit positions in each of the plurality of first and second data sets. Thus, a plurality of third data sets corresponding to the plurality of first data sets and a fourth data set corresponding to the second data set may be generated.

[0139] In operation S652 , the memory controller 100 may perform an error correction operation on each of the plurality of third and fourth data sets using a parity check matrix (or H matrix), and may generate a second flag Flag_2 regarding the error correction operation performed on each of the plurality of third and fourth data sets.

[0140] The second flag Flag_2 can indicate no error (NE), correctable error (CE), or uncorrectable error (UE). NE can indicate that no error was detected. CE can indicate that the error was corrected. UE can indicate that an uncorrectable error has occurred.

[0141] According to example embodiments, the parity check matrix used by the memory controller 100 to generate the second flag Flag_2 may be the same as the parity check matrix used by the on-chip ECC circuit 350 included in each of the plurality of memory devices 200 p , 200 d_1 through 200 d_n.

[0142] In operation S653, the memory controller 100 may attempt to identify an erroneous data set based on the second flag Flag_2. For example, when only one of the second flags Flag_2 corresponding to each of the plurality of third and fourth data sets is NE, the memory controller 100 may identify the data set corresponding to NE among the plurality of first and second data sets as an erroneous data set. For example, the second flag Flag_2 corresponds to the plurality of third and fourth data sets, but the plurality of third data sets respectively correspond to the plurality of first data sets and the fourth data set corresponds to the second data set, so that the data set corresponding to NE among the plurality of first and second data sets can be identified.

[0143] When an error data set is identified in operation S653, the process proceeds to operation S654, where the memory controller 100 may flip the bit corresponding to the candidate error bit position among the bits included in the error data set. Thus, an error occurring in one of the plurality of first and second data sets may be corrected.

[0144] According to example embodiments, one of the plurality of first data sets may be an error data set. In operation S655, the memory controller 100 may transmit the remaining first data sets except the error data set and the error data set in which bits corresponding to the candidate error bit positions are flipped to the host 15.

[0145] If only one second flag Flag_2 is not NE in operation S653, for example, if no error data set has been identified, the process proceeds to operation S656, where the memory controller 100 may determine that an error has been detected in the plurality of first and second data sets, but the error is uncorrectable. This situation may be referred to as a detected uncorrectable error (DUE), but example embodiments are not limited thereto. For example, if two or more second flags Flag_2 are NE in operation S653, the memory controller 100 may determine that a DUE has occurred.

[0146] Although an example has been provided in which the memory controller 100 performs the iterative operation in operations S651 to S656 , example embodiments are not limited thereto.

[0147] For example, when the memory controller 100 does not identify an erroneous data set in operation S635, the memory controller 100 may control the plurality of memory devices 200p, 200d_1 to 200d_n to flip bits corresponding to candidate erroneous bit positions in each of the plurality of first and second data sets, thereby generating a plurality of third and fourth data sets.

[0148] In addition, the memory controller 100 may control the plurality of memory devices 200p, 200d_1 to 200d_n to perform an error correction operation on each of the plurality of third and fourth data sets, thereby generating a second flag Flag_2. Each second flag Flag_2 may be generated by the on-chip ECC circuit 350 included in each of the plurality of memory devices 200p, 200d_1 to 200d_n.

[0149] In addition, the memory controller 100 may control the plurality of memory devices 200 p , 200 d_1 to 200 d_n to transmit the generated second flag Flag_2 .

[0150] Therefore, the memory controller 100 may perform an iterative operation by performing operations S653 to S656 based on the obtained second flag Flag_2 .

[0151] As described above, the memory system 20 can increase the probability of detecting an erroneous data set by iterating the operation. In addition, when an erroneous data set is not identified, the memory system 20 can eliminate the possibility of silent data corruption (SDC), in which data that should be corrected is not corrected and data that should not be corrected is corrected, by treating this situation as DUE and not performing further error correction operations.

[0152] 9A to 9D is a diagram illustrating a method of operating a memory system according to example embodiments. Figure 9A Shown in Figure 7A In the same situation, the on-chip ECC circuit 350 of the data storage device corresponding to Data 1 fails to detect the error in Data 1. Figure 9A In FIG, three errors in Data 1 are indicated by "X", and the bit position of Parity recognized by the memory controller 100 through the parity check between the mapped data bits and the parity bits is indicated by "!". The on-chip ECC circuit 350 cannot detect 100% of the errors included in the data set, so this situation may occur.

[0153] Regardless of the fact that the on-chip ECC circuit 350 corresponding to Data 1 fails to detect an error in Data 1, the memory controller 100 can detect an error in Data 1 by performing a parity check operation on Data 1, Data 2, and Parity (e.g., Figure 6 The candidate error bit position is identified by the operation S615. Figure 7A Same as those described in .

[0154] Therefore, the memory controller 100 may obtain the first flag Flag_1 from each memory device and attempt to identify an error data set (eg, Figure 6 Operation S635).

[0155] However, if Figure 9A As shown, all first flags Flag_1 obtained by the memory controller 100 from each memory device indicate non-UE, so that an erroneous data set cannot be identified. The memory controller 100 can perform an iterative operation (eg, Figure 6 Operation S650).

[0156] For example, the memory controller 100 may flip the bits corresponding to the candidate error bit positions in each of Data 1, Data 2, and Parity to generate new data sets Data 3, Data 4, Parity′, as shown in FIG. Figure 9B As shown (for example, Figure 8 Operation S651).

[0157] refer to Figure 9B , Data 3 can be generated by flipping the bits corresponding to the candidate error bit positions in Data 1, so that the errors existing in Data 1 no longer exist in Data 3. There are no errors in Data 2 and Parity, so errors indicated by "X" may appear in Data 4 and Parity' generated by flipping the bits corresponding to the candidate error bit positions.

[0158] The memory controller 100 may perform an error correction operation on each of Data 3, Data 4, and Parity' using a parity check matrix (e.g., a parity check matrix used in a memory device storing Data 1, Data 2, and Parity), and may generate a second flag Flag_2 regarding the error correction operation (e.g., Figure 8 Operation S652).

[0159] Figure 9C FIG. 2 shows a second flag Flag_2 generated for each of Data 3, Data 4, and Parity'. Figure 9C , there is no error in Data 3, so the second flag Flag_2 of Data 3 can be NE. In addition, there are errors in Data 4 and Parity' (indicated by "X"), so the second flag Flag_2 of Data 4 and Parity' can be CE or UE.

[0160] The memory controller 100 may attempt to identify an erroneous data set based on the second flag Flag_2 (eg, Figure 8 For example, when only one of the second flags Flag_2 is NE, the memory controller 100 may identify the data set corresponding to NE among Data 1, Data 2, and Parity as an error data set. Figure 9C In the example of , only the second flag Flag_2 corresponding to Data 3 is NE, so the memory controller 100 can identify Data 1 corresponding to Data 3 among Data 1, Data 2, and Parity as an error data set.

[0161] Therefore, the memory controller 100 may flip the bit corresponding to the candidate error bit position among the bits included in the error data set. Figure 9A In the example of , the error data set is Data 1, and the candidate error bit positions of Data 1 are identified as (BL0, DQ3), (BL1, DQ1), and (BL3, DQ2), so that the memory controller 100 can flip the bits of Data 1 corresponding to (BL0, DQ3), (BL1, DQ1), and (BL3, DQ2) in Data 1. Therefore, Figure 9D As shown, three error bits included in Data 1 can be corrected.

[0162] Figure 10A and Figure 10B is a diagram illustrating the limitations of error correction operations during correlation parity mapping. Figure 10A and Figure 10BIn the case of the related art, parity bits for data bits having the same bit position in a first data set Data 1 and another first data set Data 2 may be stored in the same bit position of a second data set Parity.

[0163] Figure 10A Shown as Figure 9A In the example shown, an error occurs in Data 1, but the on-chip ECC circuit 350 of the data storage device corresponding to Data 1 fails to detect the error and generates the first flag Flag_1 as NE. There are no errors in Data 2 and Parity, so the corresponding on-chip ECC circuit 350 can also generate the first flag Flag_1 as NE. Figure 10A , three errors in Data1 are indicated by “X”, and the bit position of Parity identified by the parity between the mapped data bits and the parity bits is indicated by “!”.

[0164] The first flag Flag_1 is all NE or non-UE, so that the candidate error bit position can be identified by the parity check operation on Data 1, Data 2 and Parity, while the error data set is not identifiable.

[0165] In the case of the related art, new data sets Data 3, Data 4, and Parity' are generated by flipping the bits corresponding to the candidate error bit positions among the bits included in Data 1, Data 2, and Parity, as shown in FIG. Figure 10B Reference Figure 10B , Data 3 can be generated by flipping the bits corresponding to the candidate error bit positions in Data 1, so that the errors present in Data 1 no longer exist in Data 3. There are no errors in Data 2 and Parity, so errors indicated by "X" may appear in Data 4 and Parity' generated by flipping the bits corresponding to the candidate error bit positions. However, in the case of the related art, even if the second flag Flag_2 is obtained for each of Data 3, Data 4, and Parity', an error data set cannot be identified.

[0166] For example, the on-chip ECC circuit 350 of the data storage device corresponding to Data 1, the on-chip ECC circuit 350 of the data storage device corresponding to Data 2, and the on-chip ECC circuit 350 of the parity storage device may be the same product. For example, if the on-chip ECC circuit 350 of the data storage device corresponding to Data 1 fails to detect errors in (BL0, DQ3), (BL1, DQ1), and (BL3, DQ2), this means that the on-chip ECC circuits 350 of the other storage devices also fail to detect errors occurring in (BL0, DQ3), (BL1, DQ1), and (BL3, DQ2).

[0167] Therefore, even when Figure 10B As shown, when the second flag Flag_2 is obtained using Data 3, Data 4, and Parity', the second flag Flag_2 all becomes NE, and the error data set is no longer identifiable.

[0168] In an example embodiment, parity mapping is performed to have different bit positions so that additional error data sets can be detected through iterative operations even when the same on-chip ECC circuit 350 or the same parity check matrix is ​​used.

[0169] 11A to 11D is a diagram illustrating a method of operating a memory system according to example embodiments. An error in data is indicated by an "X," and a bit position of Parity identified by parity between mapped data bits and parity bits is indicated by a "!". Figure 11A and Figure 11B Shown respectively with Figure 9A and Figure 9B Therefore, in order to avoid redundancy, repeated descriptions are omitted.

[0170] After the iterative operation starts and new data sets Data 3 , Data 4 , and Parity ′ are generated, the memory controller 100 may generate a second flag Flag_2 for Data 3 , Data 4 , and Parity ′.

[0171] Figure 11C FIG. 2 shows a second flag Flag_2 generated for each of Data 3, Data 4, and Parity'. Figure 11C , there is no error in Data 3, so the second flag Flag_2 of Data 3 can be NE.

[0172] There are errors in Data 4 and Parity', so the second flag Flag_2 of Data 4 and Parity' can be CE or UE, as described above. However, as described above, the probability of the on-chip ECC circuit 350 detecting an error is not 100%, which means that the second flag of at least one of Data 4 and Parity' may be NE. Figure 11C The case where the second flag Flag_2 of Data 4 is NE is shown.

[0173] When the second flag Flag_2 of Data 4 is NE, and Data 2 is also identified as an erroneous data set, flipping the candidate error bit positions of Data 2 may cause silent data corruption (SDC), in which data that should not be corrected is erroneously corrected. Therefore, according to example embodiments, when two or more of the second flags Flag_2 are NE, the memory controller 100 may determine that errors have been detected for the plurality of first and second data sets, but the errors are uncorrectable. Correction operations are not performed on the data that should not be corrected, thereby preventing SDC from occurring.

[0174] For example, reference Figure 11C For example, the second flag Flag_2 of Data 3 and Data 4 is NE, indicating that the memory controller 100 can interpret this situation as an error detected in Data 1, Data 2 and Parity but uncorrectable. Figure 11D As shown, error correction operations may no longer be performed on Data 1, Data 2, and Parity.

[0175] Figure 12 1 is a block diagram of an electronic system according to an example embodiment. Although the description has been provided for an example in which the system ECC circuit 120 is included in the memory controller 100, the example embodiment is not limited thereto. For example, the system ECC circuit 120 that performs the above-described system ECC operation may be implemented independently of the memory controller 100.

[0176] refer to Figure 12 , except that the system ECC circuit 120 is included in the host 15 and is external to the memory controller 100, the electronic system 10 ′ may have Figure 1 The electronic system 10 has the same configuration as that of the electronic system 10. Therefore, redundant description is omitted. In addition to the data exchange with the memory module 2000 performed by the above-mentioned memory controller 100, various system ECC operations can be performed by the system ECC circuit 120 included in the host 15.

[0177] The technology for correcting all errors in a single data chip among the data chips that make up a cache line is called chipkill or single device data correction (SDDC). Typically, two parity memory chips are required for each cache line size to implement chipkill. However, according to various exemplary embodiments, a single system ECC chip can be used to implement high-performance chipkill.

[0178] While aspects of the example embodiments have been particularly shown and described, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A memory system comprising: a plurality of first storage devices; a second storage device; as well as a memory controller configured to control the plurality of first memory devices and the second memory device, wherein each of the plurality of first storage devices is configured to store a first data set, the first data set comprising a first set of data bits at different bit positions, each of the bit positions corresponding to a burst order and a DQ, wherein the second storage device is configured to store a second data set, the second data set including parity bits for a plurality of first data sets respectively stored in the plurality of first storage devices; and A second group of data bits corresponding to a first parity bit in the parity bits are respectively included in the plurality of first data sets, and at least two data bits in the second group of data bits have different bit positions.

2. The memory system according to claim 1, wherein: The value of the first parity bit is based on an exclusive-OR (XOR) operation performed on the second set of data bits.

3. The memory system according to claim 1, wherein: The at least two data bits have different burst orders or different DQs in the corresponding at least two first data sets.

4. The memory system according to claim 1, wherein: Each of the plurality of first storage devices and the second storage device is further configured to: perform a first error correction operation on a data set input or output through the corresponding storage device using a parity check matrix, and generate a first flag regarding a result of the first error correction operation; and The memory controller is further configured to: perform a parity check on the multiple first data sets and the second data sets received from the multiple first storage devices and the second storage devices, and obtain the first flag from the multiple first storage devices and the second storage devices, so as to obtain the first flag based on identifying the candidate error bit position of each of the multiple first data sets and the second data sets through the parity check.

5. The memory system according to claim 4, wherein: The memory controller is further configured to send the plurality of first data sets to a host based on failure to identify the candidate error bit position through the parity check. The memory system according to claim 4 , wherein: The memory controller is further configured to obtain the first flag based on a new read command or based on a setting value in a mode register included in each of the plurality of first memory devices and the second memory device, Each of the plurality of first storage devices and the second storage device is configured to: provide the first flag and a corresponding data set regarding a result of the first error correction operation based on the new read command, and Wherein, each of the plurality of first storage devices and the second storage device is configured to: selectively operate in a first mode and a second mode based on the setting value, wherein in the first mode, only the corresponding data set is provided based on a normal read command, and in the second mode, the first flag and the corresponding data set regarding the result of the first error correction operation are provided based on the normal read command.

7. The memory system according to claim 4, wherein: Each of the plurality of first memory devices and the second memory device is further configured to provide the first flag to the memory controller through a pin assigned to the first flag or by using an extended burst length.

8. The memory system according to claim 4, wherein: Based on determining that no error exists or the error has been corrected, the first flag indicates a non-uncorrectable error Non-UE, and based on determining that an uncorrectable error has occurred, the first flag indicates an uncorrectable error UE, and The memory controller is further configured to: based on the fact that only one of the first flags indicates a UE, identify an error data set corresponding to the first flag indicating the UE in the multiple first data sets and the second data sets, and flip the bits corresponding to the candidate error bit positions included in the identified error data set to generate a flipped error data set.

9. The memory system according to claim 8, wherein: The memory controller is further configured to transmit the remaining first data sets excluding the error data set and the overturned error data set to the host based on the error data set being included in the plurality of first data sets.

10. The memory system according to claim 4, wherein: The memory controller is further configured to: Based on all the first flags indicating Non-UE, generating a plurality of third data sets respectively corresponding to the plurality of first data sets and a fourth data set corresponding to the second data set by flipping a bit corresponding to the candidate error bit position among bits included in each of the plurality of first data sets and the second data set; as well as A second error correction operation is performed on each of the plurality of third data sets and the fourth data set using the parity check matrix, and a second flag indicating a result of the second error correction operation is generated for each of the plurality of third data sets and the fourth data set. The memory system according to claim 10 , wherein: Based on determining that no error exists, the second flag indicates no error NE, based on determining that the error has been corrected, the second flag indicates a correctable error CE, and based on determining that an uncorrectable error has occurred, the second flag indicates an uncorrectable error UE, and Wherein, the memory controller is further configured to: identifying an erroneous data set corresponding to the NE among the plurality of first data sets and the second data sets based on only one of the second flags corresponding to the plurality of third data sets and the fourth data set indicating an NE; and The bits included in the identified error data set and corresponding to the candidate error bit positions are flipped to generate a flipped error data set.

12. The memory system according to claim 11, wherein: The memory controller is further configured to transmit the remaining first data sets excluding the error data set and the overturned error data set to the host based on the error data set being included in the plurality of first data sets.

13. The memory system according to claim 11, wherein: The memory controller is further configured to determine that errors are detected but uncorrectable for the plurality of first data sets and the second data set based on two or more indications NE in the second flag.

14. A memory module comprising: a plurality of first storage devices; as well as a second storage device, wherein each of the plurality of first storage devices is configured to store a first data set, the first data set comprising a first set of data bits having bit positions, each of the bit positions corresponding to a burst order and a DQ, wherein the second storage device is configured to store a second data set, the second data set including first parity bits for a plurality of first data sets respectively stored in the plurality of first storage devices; and A second group of data bits corresponding to one of the first parity bits are respectively included in the plurality of first data sets, and at least two data bits in the second group of data bits have different bit positions.

15. The memory module according to claim 14, wherein: The at least two data bits have different burst orders or different DQs in the corresponding at least two first data sets.

16. The memory module according to claim 14, wherein: Each of the plurality of first memory devices and the second memory device includes: a memory bank array including a plurality of memory cells, and an on-chip error correction code (ECC) circuit; The memory bank array of each of the plurality of first memory devices and the second memory device includes: a normal area for storing a data set, and a parity area for storing a second parity bit for the data set stored in the normal area, and The on-chip ECC circuit of each of the plurality of first storage devices and the second storage device is further configured to: perform an error correction operation on a data set input or output through the corresponding storage device based on a codeword including the second parity check bits and a parity check matrix, and generate a first flag regarding a result of the error correction operation.

17. The memory module according to claim 16, wherein: Each of the plurality of first storage devices and the second storage device includes a mode register configured to store a setting value indicating a first mode or a second mode, and Wherein, each of the plurality of first storage devices and the second storage device is further configured to: when the setting value indicates the first mode, provide only the corresponding data set based on a normal read command, and when the setting value indicates the second mode, provide the first flag and the corresponding data set regarding the result of the error correction operation based on the normal read command.

18. The memory module according to claim 16, wherein: Each of the plurality of first memory devices and the second memory device is further configured to provide the first flag regarding a result of the error correction operation to an external entity through a pin assigned to the first flag or by using an extended burst length.

19. A method of operating a memory controller to control a memory module including a plurality of first memory devices and a second memory device, the method comprising: storing a plurality of first data sets in the plurality of first storage devices respectively; as well as storing a second data set in the second storage device, the second data set including parity bits for the plurality of first data sets, wherein each of the plurality of first data sets comprises a first set of data bits having bit positions, each of the bit positions corresponding to a burst order and a DQ, and A second group of data bits corresponding to a first parity bit in the parity bits are respectively included in the plurality of first data sets, and bit positions of at least two data bits in the second group of data bits are different from each other.

20. The method according to claim 19, comprising: receiving the plurality of first data sets and the second data set from the plurality of first storage devices and the second storage device; performing a parity check on the plurality of first data sets and the second data set to identify a candidate error bit position for each of the plurality of first data sets and the second data set; obtaining a first flag regarding a result of an error correction operation performed on each of the plurality of first data sets and the second data set by receiving a first flag from each of the plurality of first storage devices and the second storage device; as well as Based on the first flag, a data set including an error bit among the plurality of first data sets and the second data set is identified.

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