Driving method of series-parallel switched capacitor converter and power supply driving chip

Abstract

The embodiment of the invention provides a driving method of a series-parallel switched capacitor converter and a power supply driving chip. The driving method comprises the following steps: when the series-parallel switched capacitor converter works at a first phase, cutting off the connection between the plurality of flying capacitors and the voltage input end, the connection between the plurality of flying capacitors and the voltage output end and the connection between two adjacent flying capacitors in the plurality of flying capacitors according to a first switching signal, after a first duration, each of the plurality of flying capacitors is sequentially connected between the voltage output end and the ground according to a first sequence so as to control the series-parallel switched capacitor converter to work at a second phase, so that the charge and discharge loss of the output capacitor of the switching tube can be reduced, and the switching loss is reduced; therefore, the conversion efficiency of the series-parallel switched capacitor converter is improved.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of integrated circuit technology, and in particular to a driving method and a power driver chip for a series-parallel switched capacitor converter. Background Art

[0002] Switched capacitor converters (SCCs) are widely used in various power management modules due to their extremely high conversion efficiency. The five most common SCC topologies are voltage doubler, series-parallel, Fibonacci, Dickson, and trapezoidal. SCCs in series-parallel configurations offer greater flexibility in achieving different transformation ratios, while the other types have relatively fixed transformation ratios. For example, a three-stage series-parallel SCC can achieve transformation ratios of 4:1, 3:1, 2:1, and 1:1.

[0003] Conversion efficiency is one of the most important indicators of a switched-capacitor converter. The main losses in a switched-capacitor converter include switching loss, flying capacitor charge-sharing loss, and switch on-resistance and flying capacitor equivalent series resistance (ESR) losses. Switching loss includes switch switching loss, drive loss, switch output capacitor charge-discharge loss, and body diode freewheeling loss. The switch output capacitor charge-discharge loss is positively correlated with the voltage applied to the output capacitor.

[0004] In the prior art, when the flying capacitors in a series-parallel switched capacitor converter switch between the series state and the parallel state, the voltage difference of each node changes greatly, resulting in large switching losses in the series-parallel switched capacitor converter, which is not conducive to improving the conversion efficiency. Summary of the Invention

[0005] The present disclosure provides a driving method for a series-parallel switched capacitor converter and a power driver chip, which can improve conversion efficiency.

[0006] In a first aspect, the present disclosure provides a driving method for a series-parallel switched capacitor converter, wherein the series-parallel switched capacitor converter includes a plurality of flying capacitors. In a first phase, the plurality of flying capacitors are connected in series between a voltage input terminal and a voltage output terminal of the series-parallel switched capacitor converter. In a second phase, the plurality of flying capacitors are connected in parallel between the voltage output terminal and ground.

[0007] The driving method includes:

[0008] When the series-parallel switched capacitor converter operates in the first phase, the connections between the plurality of flying capacitors and the voltage input terminal, the connections between the plurality of flying capacitors and the voltage output terminal, and the connections between two adjacent flying capacitors in the plurality of flying capacitors are disconnected according to a first switching signal. After a first time period, each of the plurality of flying capacitors is sequentially connected between the voltage output terminal and ground in a first sequence to control the series-parallel switched capacitor converter to operate in the second phase, where the first sequence is any sequence other than from the first to the last flying capacitor in the plurality of flying capacitors.

[0009] In some embodiments of the present disclosure, the first order is from the last flying capacitor to the first flying capacitor.

[0010] In some embodiments of the present disclosure, sequentially connecting each of the plurality of flying capacitors between the voltage output terminal and the ground in a first order includes:

[0011] Connecting the lower plate of the last flying capacitor to the ground; after the second time period, simultaneously connecting the upper plate of the latter of the two adjacent flying capacitors to the voltage output terminal and the lower plate of the preceding flying capacitor to the ground in the first order, with the time interval between the two adjacent flying capacitors being connected to the voltage output terminal and the ground being the second time period; after the second time period, connecting the upper plate of the first flying capacitor to the voltage output terminal.

[0012] In some embodiments of the present disclosure, the driving method further includes:

[0013] When the series-parallel switched capacitor converter operates in the second phase, the connection between the upper plate of each flying capacitor and the voltage output terminal, and the connection between the lower plate of each flying capacitor and the ground are cut off according to the second switching signal. After the third time period, the upper plate of the latter flying capacitor of the two adjacent flying capacitors is connected to the lower plate of the previous flying capacitor in the second order to connect the two adjacent flying capacitors in series. After the fourth time period, the multiple flying capacitors connected in series are connected between the voltage output terminal and the voltage input terminal to control the series-parallel switched capacitor converter to operate in the first phase.

[0014] In some embodiments of the present disclosure, the second order is from the first flying capacitor to the last flying capacitor.

[0015] In some embodiments of the present disclosure, connecting the plurality of flying capacitors connected in series between the voltage output terminal and the voltage input terminal includes:

[0016] The lower plate of the last flying capacitor is connected to the voltage output terminal; after the fifth time period, the upper plate of the first flying capacitor is connected to the voltage input terminal.

[0017] In some embodiments of the present disclosure, the plurality of flying capacitors include a first flying capacitor, a second flying capacitor, and a third flying capacitor, and the series-parallel switched capacitor converter further includes a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a fifth switching transistor, and a sixth switching transistor. The upper plate of the first flying capacitor is connected to the voltage output terminal via the first switching transistor, the lower plate of the first flying capacitor is grounded via the second switching transistor, the upper plate of the second flying capacitor is connected to the voltage output terminal via the third switching transistor, the lower plate of the second flying capacitor is grounded via the fourth switching transistor, the upper plate of the third flying capacitor is connected to the voltage output terminal via the fifth switching transistor, and the lower plate of the third flying capacitor is grounded via the sixth switching transistor.

[0018] Connecting the lower plate of the last flying capacitor to the ground comprises:

[0019] Turn on the sixth switch tube.

[0020] The step of simultaneously connecting the upper plate of the rear flying capacitor of the two adjacent flying capacitors to the voltage output terminal and the lower plate of the front flying capacitor to the ground in the first order comprises:

[0021] The fifth switch tube and the fourth switch tube are turned on to connect the third flying capacitor between the voltage output terminal and the ground; after the second time period, the third switch tube and the second switch tube are turned on to connect the second flying capacitor between the voltage output terminal and the ground.

[0022] Connecting the upper plate of the first flying capacitor to the voltage output terminal includes:

[0023] The first switch tube is turned on to connect the first flying capacitor between the voltage output terminal and the ground.

[0024] In some embodiments of the present disclosure, the plurality of flying capacitors include a first flying capacitor, a second flying capacitor, and a third flying capacitor, and the series-parallel switched capacitor converter includes a seventh switching transistor, an eighth switching transistor, a ninth switching transistor, and a tenth switching transistor. The upper plate of the third flying capacitor is connected to the lower plate of the second flying capacitor via the ninth switching transistor, the upper plate of the second flying capacitor is connected to the lower plate of the first flying capacitor via the eighth switching transistor, the upper plate of the first flying capacitor is connected to the voltage input terminal via the seventh switching transistor, and the lower plate of the third flying capacitor is connected to the voltage output terminal via the tenth switching transistor.

[0025] The step of connecting the upper plate of the latter flying capacitor to the lower plate of the former flying capacitor in the second order to connect the two adjacent flying capacitors in series comprises:

[0026] The eighth switch tube is turned on to connect the first flying capacitor and the second flying capacitor in series; after a sixth time period, the ninth switch tube is turned on to connect the second flying capacitor and the third flying capacitor in series.

[0027] In some embodiments of the present disclosure, connecting the lower plate of the last flying capacitor to the voltage output terminal includes:

[0028] The tenth switch tube is turned on to connect the lower plate of the third flying capacitor to the voltage output terminal.

[0029] Connecting the upper plate of the third flying capacitor to the voltage input terminal includes:

[0030] The seventh switch tube is turned on to connect the upper plate of the first flying capacitor to the voltage input terminal.

[0031] In a second aspect, the present disclosure provides a power driver chip for executing the steps of any driving method provided in the first aspect.

[0032] The technical solution disclosed herein provides a driving method for a series-parallel switched capacitor converter. When the series-parallel switched capacitor converter operates in a first phase, the connection between multiple flying capacitors and the voltage input terminal, the connection between the multiple flying capacitors and the voltage output terminal, and the connection between two adjacent flying capacitors in the multiple flying capacitors are cut off according to a first switching signal. After a first time period, each of the multiple flying capacitors is connected in sequence between the voltage output terminal and ground in a first order to control the series-parallel switched capacitor converter to operate in a second phase. This can reduce the charging and discharging loss of the output capacitor of the switching tube, thereby reducing the switching loss and improving the conversion efficiency of the series-parallel switched capacitor converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. It should be noted that the drawings described below only relate to some embodiments of the present disclosure and are not intended to limit the present disclosure.

[0034] Figure 1 A circuit diagram of a series-parallel switched capacitor converter provided by an embodiment of the present disclosure.

[0035] Figure 2 A flowchart of a driving method provided in an embodiment of the present disclosure.

[0036] Figure 3A schematic diagram of a driving timing provided by an embodiment of the present disclosure.

[0037] Figure 4 A flowchart of another driving method provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0039] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal manner unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" together shall mean that the parts are joined together either directly or through one or more intermediate components.

[0040] References to "embodiments" in this disclosure mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase "embodiment" in various places in the specification does not necessarily refer to the same embodiment, nor does it refer to independent or alternative embodiments that are mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described in this disclosure may be combined with other embodiments.

[0041] In addition, the terms "first", "second", etc. in the description and claims of the present disclosure or the above-mentioned drawings are used to distinguish different objects rather than to describe a specific order, and may explicitly or implicitly include one or more such features.

[0042] In this disclosure, the term "and / or" simply describes an association relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent the following three situations: A exists, A and B exist at the same time, and B exists. In addition, the character " / " in this document generally indicates that the related objects are in an "or" relationship.

[0043] In the description of the present disclosure, unless otherwise specified, "multiple" and "at least two" mean more than two (including two). Similarly, "multiple groups" and "at least two groups" mean more than two groups (including two).

[0044] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.

[0045] The series-parallel switched capacitor converter provided by the present disclosure includes multiple flying capacitors. In a first phase, the multiple flying capacitors are connected in series between the voltage input terminal and the voltage output terminal of the series-parallel switched capacitor converter. In a second phase, the multiple flying capacitors are connected in parallel between the voltage output terminal and the ground.

[0046] The series-parallel switched capacitor converter also includes a drive circuit and a control circuit. The control circuit includes multiple switching transistors, with the control terminal of each switching transistor connected to the output terminal of the drive circuit. One end of the flying capacitor is connected to the voltage output terminal through the switching transistor, and the other end of the flying capacitor is grounded through the switching transistor. Two adjacent flying capacitors are connected through the switching transistors, with the first flying capacitor connected to the voltage input terminal through the switching transistor, and the last flying capacitor connected to the voltage output terminal through the switching transistor.

[0047] For example, Figure 1 A circuit diagram of a series-parallel switched capacitor converter provided by an embodiment of the present disclosure is shown in FIG. Figure 1 As shown, the series-parallel switched capacitor converter 100 is a three-stage series-parallel switched capacitor converter, including a first flying capacitor CFLY1 , ​​a second flying capacitor CFLY2 , a third flying capacitor CFLY3 , a driving circuit (not shown) and a control circuit.

[0048] The control circuit includes a first switch tube M1, a second switch tube M2, a third switch tube M3, a fourth switch tube M4, a fifth switch tube M5, a sixth switch tube M6, a seventh switch tube M7, an eighth switch tube M8, a ninth switch tube M9 and a tenth switch tube M10. The control end of the first switch tube M1, the control end of the second switch tube M2, the control end of the third switch tube M3, the control end of the fourth switch tube M4, the control end of the fifth switch tube M5, the control end of the sixth switch tube M6, the control end of the seventh switch tube M7, the control end of the eighth switch tube M8, the control end of the ninth switch tube M9 and the control end of the tenth switch tube M10 are connected to the output end of the drive circuit.

[0049] The top plate of the first flying capacitor CFLY1 is connected to the voltage output terminal OUT via the first switching transistor M1. The top plate of the first flying capacitor CFLY1 is connected to the voltage input terminal IN via the seventh switching transistor M7. The bottom plate of the first flying capacitor CFLY1 is grounded via the second switching transistor M2. The bottom plate of the first flying capacitor CFLY1 is connected to the top plate of the second flying capacitor CFLY2 via the eighth switching transistor M8. The top plate of the second flying capacitor CFLY2 is connected to the voltage output terminal OUT via the third switching transistor M3. The bottom plate of the second flying capacitor CFLY2 is grounded via the fourth switching transistor M4. The bottom plate of the second flying capacitor CFLY2 is connected to the top plate of the third flying capacitor CFLY3 via the ninth switching transistor M9. The top plate of the third flying capacitor CFLY3 is connected to the voltage output terminal OUT via the fifth switching transistor M5. The bottom plate of the third flying capacitor CFLY3 is grounded via the sixth switching transistor M6. The bottom plate of the third flying capacitor CFLY3 is connected to the voltage output terminal OUT via the tenth switching transistor M10.

[0050] The connection point between the first flying capacitor CFLY1, the first switching transistor M1, and the seventh switching transistor M7 is a first high node CT1. The connection point between the second flying capacitor CFLY2, the third switching transistor M3, and the eighth switching transistor M8 is a second high node CT2. The connection point between the third flying capacitor CFLY3, the fifth switching transistor M5, and the ninth switching transistor M9 is a third high node CT3. The connection point between the first flying capacitor CFLY1, the second switching transistor M2, and the eighth switching transistor M8 is a first low node CB1. The connection point between the second flying capacitor CFLY2, the fourth switching transistor M4, and the ninth switching transistor M9 is a second low node CB2. The connection point between the third flying capacitor CFLY3, the sixth switching transistor M6, and the tenth switching transistor M10 is a third low node CB3.

[0051] When the seventh switch M7, the eighth switch M8, the ninth switch M9, and the tenth switch M10 are turned on, and the first switch M1, the second switch M2, the third switch M3, the fourth switch M4, the fifth switch M5, and the sixth switch M6 are turned off, the first flying capacitor CFLY1, the second flying capacitor CFLY2, and the third flying capacitor CFLY3 are connected in series between the voltage input terminal IN and the voltage output terminal OUT, and the series-parallel switched capacitor converter 100 operates in the first phase.

[0052] At this time, the first flying capacitor CFLY1, the second flying capacitor CFLY2, and the third flying capacitor CFLY3 are in a charging state, and in a steady state, the first high node voltage VCT1 is 4Vout, the first low node voltage VCB1 is 3Vout, the second high node voltage VCT2 is 3Vout, the second low node voltage VCB2 is 2Vout, the third high node voltage VCT3 is 2Vout, and the third low node voltage VCB3 is Vout. Vout is the output voltage of the series-parallel switched capacitor converter 100.

[0053] When the seventh switch M7, the eighth switch M8, the ninth switch M9, and the tenth switch M10 are turned off, and the first switch M1, the second switch M2, the third switch M3, the fourth switch M4, the fifth switch M5, and the sixth switch M6 are turned on, the first flying capacitor CFLY1, the second flying capacitor CFLY2, and the third flying capacitor CFLY3 are connected in parallel between the voltage input terminal IN and ground, and the series-parallel switched capacitor converter 100 operates in the second phase.

[0054] At this time, the first flying capacitor CFLY1, the second flying capacitor CFLY2 and the third flying capacitor CFLY3 are in a discharging state, and in a steady state, the first high node voltage VCT1 is Vout, the first low node voltage VCB1 is 0, the second high node voltage VCT2 is Vout, the second low node voltage VCB2 is 0, the third high node voltage VCT3 is Vout, and the third low node voltage VCB3 is 0.

[0055] In this way, by switching between the first phase and the second phase, the series-parallel switched capacitor converter 100 can convert the input voltage Vin into Vin / 4 and output it, achieving a 4:1 transformation ratio, ie, Vout=Vin / 4.

[0056] When the fifth, seventh, eighth, and ninth switches M5, M7, M8, and M9 are turned on, and the first, second, third, fourth, sixth, and tenth switches M1, M2, M3, M4, M6, and M10 are turned off, the first flying capacitor CFLY1 and the second flying capacitor CFLY2 are connected in series between the voltage input terminal IN and the voltage output terminal OUT, and the series-parallel switched capacitor converter 100 operates in the third phase. At this time, the first flying capacitor CFLY1 and the second flying capacitor CFLY2 are in a charging state, and in a steady state, the first high node voltage VCT1 is 3Vout, the first low node voltage VCB1 is 2Vout, the second high node voltage VCT2 is 2Vout, and the second low node voltage VCB2 is Vout.

[0057] When the first, second, third, and fourth switches M1, M2, M3, and M4 are turned on, and the fifth, sixth, seventh, eighth, ninth, and tenth switches M5, M6, M7, M8, M9, and M10 are turned off, the first flying capacitor CFLY1 and the second flying capacitor are connected in parallel between the voltage output terminal OUT and ground, and the series-parallel switched capacitor converter 100 operates in the fourth phase. At this time, the first flying capacitor CFLY1 and the second flying capacitor CFLY2 are in a discharging state, and in a steady state, the first high node voltage VCT1 is Vout, the first low node voltage VCB1 is 0, the second high node voltage VCT2 is Vout, and the second low node voltage VCB2 is 0.

[0058] In this way, by switching between the third phase and the fourth phase, the series-parallel switched capacitor converter 100 can convert the input voltage Vin into Vin / 3 and output it, achieving a transformation ratio of 3:1, ie, Vout=Vin / 3.

[0059] When the third, seventh, and eighth switches M3, M7, and M8 are turned on, and the first, second, fourth, fifth, sixth, ninth, and tenth switches M1, M2, M4, M5, M6, M9, and M10 are turned off, the first flying capacitor CFLY1 is connected between the voltage input terminal IN and the voltage output terminal OUT, and the series-parallel switched capacitor converter 100 operates in the fifth phase. At this time, the first flying capacitor CFLY1 is in a charging state, and in a steady state, the first high node voltage VCT1 is 2Vout, and the first low node voltage VCB1 is Vout.

[0060] When the first and second switches M1, M2 are turned on, and the third, fourth, fifth, sixth, seventh, seventh, eighth, ninth, and tenth switches M3, M4, M5, M6, M7, M8, M9, and M10 are turned off, the first flying capacitor CFLY1 is connected between the voltage output terminal OUT and ground, and the series-parallel switched capacitor converter 100 operates in the sixth phase. At this point, the first flying capacitor CFLY1 is in a discharging state, and in a steady state, the first high-order node voltage VCT1 is Vout, and the first low-order node voltage VCB1 is 0.

[0061] In this way, by switching between the fifth phase and the sixth phase, the series-parallel switched capacitor converter 100 can convert the input voltage Vin into Vin / 2 and output it, achieving a 2:1 transformation ratio, ie, Vout=Vin / 2.

[0062] When the first switch M1 and the seventh switch M7 are turned on, and the second switch M2, the third switch M3, the fourth switch M4, the fifth switch M5, the sixth switch M6, the eighth switch M8, the ninth switch M9, and the tenth switch M10 are turned off, the series-parallel switched capacitor converter 100 operates in the seventh phase. At this time, the input voltage Vin can be stably output, achieving a 1:1 transformation ratio, that is, Vout = Vin.

[0063] In other embodiments, the series-parallel switched capacitor converter 100 may also be a two-stage series-parallel switched capacitor converter, a four-stage series-parallel switched capacitor converter, or a series-parallel switched capacitor converter with more than four stages, and the present disclosure does not impose any specific restrictions on this.

[0064] The driving circuit in the embodiment of the present disclosure is used to execute the steps of any method embodiment provided by the present disclosure. The method provided by the present disclosure is described in detail below with reference to several specific embodiments.

[0065] Figure 2 A schematic diagram of a driving method provided in an embodiment of the present disclosure is shown in FIG. Figure 2 As shown, the specific steps of the driving method include:

[0066] S101, when the series-parallel switched capacitor converter operates in a first phase, disconnecting, according to a first switching signal, connections between a plurality of flying capacitors and a voltage input terminal, connections between a plurality of flying capacitors and a voltage output terminal, and connections between two adjacent flying capacitors among the plurality of flying capacitors.

[0067] For example, Figure 3 A schematic diagram of a driving timing provided by an embodiment of the present disclosure is shown in FIG. Figure 3 As shown, the drive circuit can provide a first drive signal Drv1, a second drive signal Drv2, a third drive signal Drv3, a fourth drive signal Drv4, a fifth drive signal Drv5, a sixth drive signal Drv6, a seventh drive signal Drv7, an eighth drive signal Drv8, a ninth drive signal Drv9 and a tenth drive signal Drv10 to the first switch tube M1, the second switch tube M2, the third switch tube M3, the fourth switch tube M4, the fifth switch tube M5, the sixth switch tube M6, the seventh switch tube M7, the eighth switch tube M8, the ninth switch tube M9 and the tenth switch tube M10, respectively.

[0068] When the first drive signal Drv1, the second drive signal Drv2, the third drive signal Drv3, the fourth drive signal Drv4, the fifth drive signal Drv5, and the sixth drive signal Drv6 are at a low level, and the seventh drive signal Drv7, the eighth drive signal Drv8, the ninth drive signal Drv9, and the tenth drive signal Drv10 are at a high level, the seventh switch M7, the eighth switch M8, the ninth switch M9, and the tenth switch M10 are turned on, and the first switch M1, the second switch M2, the third switch M3, the fourth switch M4, the fifth switch M5, and the sixth switch M6 are turned off, and the series-parallel switched capacitor converter 100 operates in the first phase.

[0069] At time T1, the driving circuit pulls down the seventh driving signal Drv7, the eighth driving signal Drv8, the ninth driving signal Drv9 and the tenth driving signal Drv10 according to the first switching signal. Figure 3 As shown in FIG. , the driving circuit can turn off the seventh switch tube M7 according to the seventh driving signal Drv7 to cut off the connection between the first flying capacitor CFLY1 and the voltage input terminal IN, turn off the eighth switch tube M8 according to the eighth driving signal Drv8 to cut off the connection between the first flying capacitor CFLY1 and the second flying capacitor CFLY2, turn off the ninth switch tube M9 according to the ninth driving signal Drv9 to cut off the connection between the third flying capacitor CFLY3 and the second flying capacitor CFLY2, and turn off the tenth switch tube M10 according to the tenth driving signal Drv10 to cut off the connection between the third flying capacitor CFLY3 and the voltage output terminal OUT.

[0070] S102 , after the first time period, connecting each of the plurality of flying capacitors between the voltage output terminal and the ground in sequence according to a first order, so as to control the series-parallel switched capacitor converter to operate in the second phase.

[0071] The first order is any order other than from the first flying capacitor to the last flying capacitor among the plurality of flying capacitors.

[0072] For example, Figure 3As shown, at time T2, which is after time T1 and separated from time T1 by a first time duration Δt1, the drive circuit pulls the first drive signal Drv1, the second drive signal Drv2, the third drive signal Drv3, the fourth drive signal Drv4, the fifth drive signal Drv5, and the sixth drive signal Drv6 high in a certain order. Based on the first drive signal Drv1, the second drive signal Drv2, the third drive signal Drv3, the fourth drive signal Drv4, the fifth drive signal Drv5, and the sixth drive signal Drv6, the drive circuit can turn on the first switch M1, the second switch M2, the third switch M3, the fourth switch M4, the fifth switch M5, and the sixth switch M6 in the order in which the signals are pulled high, thereby connecting the first flying capacitor CFLY1, the second flying capacitor CFLY2, and the third flying capacitor CFLY3 in the first order between the voltage output terminal OUT and ground.

[0073] The first order may be from the last flying capacitor to the first flying capacitor, for example, for Figure 1 In the series-parallel switched capacitor converter 100 shown, the first order is from the third flying capacitor CFLY3 to the first flying capacitor CFLY1 , ​​that is, from the third flying capacitor CFLY3 to the second flying capacitor CFLY2 and then to the first flying capacitor CFLY1 .

[0074] A possible implementation method for executing S102 is described as follows:

[0075] After the first duration, the lower plate of the last flying capacitor is connected to ground. After the second duration, the upper plate of the second flying capacitor of two adjacent flying capacitors is connected to the voltage output terminal and the lower plate of the first flying capacitor is connected to ground in the first order. After the second duration, the upper plate of the first flying capacitor is connected to the voltage output terminal. The time interval between the connection of two adjacent flying capacitors to the voltage output terminal and ground is the second duration.

[0076] Exemplarily, first at time T2, the driving circuit pulls up the sixth driving signal Drv6 and turns on the sixth switch M6 according to the sixth driving signal Drv6.

[0077] Then, at time T3, which is after time T2 and separated from time T2 by a second time interval Δt2, the driving circuit simultaneously pulls up the fourth driving signal Drv4 and the fifth driving signal Drv5, and turns on the fourth switch M4 and the fifth switch M5 according to the fourth driving signal Drv4 and the fifth driving signal Drv5, so as to connect the third flying capacitor CFLY3 between the voltage output terminal OUT and the ground at time T3.

[0078] Next, at time T4, which is after time T3 and separated from time T3 by a second time duration Δt2, the driving circuit simultaneously pulls up the second driving signal Drv2 and the third driving signal Drv3, and turns on the second switch M2 and the third switch M3 according to the second driving signal Drv2 and the third driving signal Drv3, so as to connect the second flying capacitor CFLY2 between the voltage output terminal OUT and the ground at time T4.

[0079] Finally, at time T5, which is after time T4 and separated from time T4 by a second time interval Δt2, the driving circuit pulls up the first driving signal Drv1 and turns on the first switch M1 according to the first driving signal Drv1, so as to connect the first flying capacitor CFLY1 between the voltage output terminal OUT and the ground at time T5.

[0080] At this time, the first drive signal Drv1, the second drive signal Drv2, the third drive signal Drv3, the fourth drive signal Drv4, the fifth drive signal Drv5, and the sixth drive signal Drv6 are at a high level, and the seventh drive signal Drv7, the eighth drive signal Drv8, the ninth drive signal Drv9, and the tenth drive signal Drv10 are at a low level. Then, the seventh switch M7, the eighth switch M8, the ninth switch M9, and the tenth switch M10 are turned off, and the first switch M1, the second switch M2, the third switch M3, the fourth switch M4, the fifth switch M5, and the sixth switch M6 are turned on. The series-parallel switched capacitor converter 100 operates in the second phase.

[0081] based on Figure 3 The driving timing from the first phase to the second phase shown, the changes of the first high node voltage VCT1, the first low node voltage VCB1, the second high node voltage VCT2, the second low node voltage VCB2, the third high node voltage VCT3 and the third low node voltage VCB3 are shown in Table 1.

[0082] Table 1 Changes in voltage of each node under the driving timing from the first phase to the second phase provided by the present disclosure

[0083]

[0084]

[0085] Among them, Vd in Table 1 is the forward conduction voltage drop of the body diode in the switch tube, and Vd is usually about 0.6V.

[0086] As shown in Table 1, at time T1, the first high node voltage VCT1, the first low node voltage VCB1, the second high node voltage VCT2, the second low node voltage VCB2, the third high node voltage VCT3, and the third low node voltage VCB3 remain consistent with when the seventh switch M7, the eighth switch M8, the ninth switch M9, and the tenth switch M10 are turned on. Therefore, the seventh switch M7, the eighth switch M8, the ninth switch M9, and the tenth switch M10 do not generate charge and discharge losses in the output capacitance of the switch tubes.

[0087] At time T2, the third low node voltage VCB3 decreases from Vout to 0. Since the voltage difference across the third flying capacitor CFLY3 cannot change suddenly, the third high node voltage VCT3 decreases from 2Vout to Vout. Due to the presence of the body diode in the ninth switch tube M9, the second low node voltage VCB2 decreases from 2Vout to Vout+Vd. Similarly, the second high node voltage VCT2 decreases from 3Vout to 2Vout+Vd, the first low node voltage VCB1 decreases from 3Vout to 2Vout+2Vd, and the first high node voltage VCT1 decreases from 4Vout to 3Vout+2Vd. The output capacitor charge and discharge loss of the sixth switch tube M6 is:

[0088] P Coss_CB1_M6 =0.5×C CB1 ×(Vout-2Vd) 2 ×f sw

[0089] P Coss_CT1_M6 =0.5×C CT1 ×(Vout-2Vd) 2 ×f sw

[0090] P Coss_CB2_M6 =0.5×C CB2 ×(Vout-Vd) 2 ×f sw

[0091] P Coss_CT2_M6 =0.5×C CT2 ×(Vout-Vd) 2 ×f sw

[0092] P Coss_CB3_M6 =0.5×C CB3 ×Vout 2 ×f sw

[0093] P Coss_CT3_M6 =0.5×C CT3 ×Vout2 ×f sw

[0094] Among them, f sw is the switching frequency, C CB1 is the total capacitance from the first low-order node CB1 to ground, C CB2 is the total capacitance from the second low-order node CB2 to ground, C CB3 is the total capacitance from the third low-order node CB3 to ground, C CT1 is the total capacitance from the first high node CT1 to ground, C CT2 is the total capacitance from the second high node CT2 to ground, C CT3 is the total capacitance from the third high node CT3 to ground.

[0095] P COSS_CB1_M6 is the charge and discharge loss of the output capacitor of the sixth switch tube M6 caused by the change of the first low node voltage VCB1, P COSS_CT1_M6 is the charge and discharge loss of the output capacitor of the sixth switch tube M6 caused by the change of the first high node voltage VCT1, P COSS_CB2_M6 is the charge and discharge loss of the output capacitor of the sixth switch tube M6 caused by the change of the second low node voltage VCB2, P COSS_CT2_M6 is the charge and discharge loss of the output capacitor of the sixth switch tube M6 caused by the change of the second high node voltage VCT2, P COSS_CB3_M6 is the charge and discharge loss of the output capacitor of the sixth switch tube M6 caused by the change of the third low node voltage VCB3, P COSS_CT3_M6 It is the charge and discharge loss of the output capacitor of the sixth switch tube M6 caused by the change of the third high node voltage VCT3.

[0096] At time T3, the second low node voltage VCB2 decreases from Vout+Vd to 0, the second high node voltage VCT2 decreases from 2Vout+Vd to Vout, the first low node voltage VCB1 decreases from 2Vout+2Vd to Vout+Vd, and the first high node voltage VCT1 decreases from 3Vout+2Vd to 2Vout+Vd. Then, the charge and discharge loss of the output capacitor of the fourth switch tube M4 is:

[0097] P Coss_CB1_M4 =0.5×C CB1 ×(Vout+Vd) 2 ×f sw

[0098] P Coss_CT1_M4 =0.5×C CT1 ×(Vout+Vd) 2 ×f sw

[0099] P Coss_CB2_M4 =0.5×CCB2 ×(Vout+Vd) 2 ×f sw

[0100] P Coss_CT2_M4 =0.5×C CT2 ×(Vout+Vd) 2 ×f sw

[0101] Among them, P COSS_CB1_M4 is the charge and discharge loss of the output capacitor of the fourth switch tube M4 caused by the change of the first low node voltage VCB1, P COSS_CT1_M4 is the charge and discharge loss of the output capacitor of the fourth switch tube M4 caused by the change of the first high node voltage VCT1, P COSS_CB2_M4 is the charge and discharge loss of the output capacitor of the fourth switch tube M4 caused by the change of the second low node voltage VCB2, P COSS_CT2_M4 It is the charge and discharge loss of the output capacitor of the fourth switch tube M4 caused by the change of the second high node voltage VCT2.

[0102] At time T4, the first low node voltage VCB1 decreases from Vout+Vd to 0, and the first high node voltage VCT1 decreases from 2Vout+Vd to Vout. Then, the charge and discharge loss of the output capacitor of the second switch tube M2 is:

[0103] P Coss_CB1_M2 =0.5×C CB1 ×(Vout+Vd) 2 ×f sw

[0104] P Coss_CT1_M2 =0.5×C CT1 ×(Vout+Vd) 2 ×f sw

[0105] Among them, P COSS_CB1_M2 is the charge and discharge loss of the output capacitor of the second switch tube M2 caused by the change of the first low node voltage VCB1, P COSS_CT1_M2 It is the charge and discharge loss of the output capacitor of the second switch tube M2 caused by the change of the first high node voltage VCT1.

[0106] At time T5, the first high node voltage VCT1, the first low node voltage VCB1, the second high node voltage VCT2, the second low node voltage VCB2, the third high node voltage VCT3 and the third low node voltage VCB3 do not change, so the first switch tube M1 does not generate the switch tube output capacitance charge and discharge loss.

[0107] Thus, based on the driving timing from the first phase to the second phase provided by the present disclosure, during the process of switching from the first phase to the second phase, the charge and discharge loss of the output capacitor of the switch tube P1 = Vout 2 ×f sw ×(1.5C CB1 +1.5C CT1 +C CB2 +C CT2 +0.5C CB2 +0.5C CT2 )+(3C CB1 +3C CT1 +C CB2 +C CT2 )×Vd 2 ×f sw .

[0108] However, based on the existing driving timing from the first phase to the second phase, changes in the first high node voltage VCT1, the first low node voltage VCB1, the second high node voltage VCT2, the second low node voltage VCB2, the third high node voltage VCT3 and the third low node voltage VCB3 are as shown in Table 2.

[0109] Table 2 Changes in voltage of each node during the existing driving sequence from the first phase to the second phase

[0110] VCB3 VCT3 VCB2 VCT2 VCB1 VCT1 T1' moment Vout 2Vout 2Vout 3Vout 3Vout 4Vout T2' moment 0 Vout 0 Vout 0 Vout

[0111] At time T1', the first switch tube M1, the second switch tube M2, the third switch tube M3, the fourth switch tube M4, the fifth switch tube M5, the sixth switch tube M6, the seventh switch tube M7, the eighth switch tube M8, the ninth switch tube M9 and the tenth switch tube M10 are turned off. At time T2', the first switch tube M1, the second switch tube M2, the third switch tube M3, the fourth switch tube M4, the fifth switch tube M5 and the sixth switch tube M6 are turned on at the same time.

[0112] Thus, based on the existing driving sequence from the first phase to the second phase, during the process of switching from the first phase to the second phase, the charge and discharge loss of the output capacitor of the switch tube P1'=Vout 2 ×f sw ×(4.5C CB1 +4.5C CT1 +2C CB2 +2C CT2 +0.5C CB2 +0.5C CT2 ). Since Vd is less than Vout, Vd 2 ×f sw ×(3C CB1 +3C CT1 +CCB2 +C CT2 ) less than (3C CB1 +3C CT1 +C CB2 +C CT2 ) × Vd 2 × f sw If so, P1 < P1', so the driving timing from the first phase to the second phase provided by the present disclosure can reduce the charge and discharge loss of the output capacitance of the switching tube, thereby reducing the switching loss when the series-parallel switched-capacitor converter 100 is operating, and further improving the conversion efficiency of the series-parallel switched-capacitor converter 100.

[0113] In other embodiments, the first order may also be an order other than from the last flying capacitor to the first flying capacitor. For example, as Figure 1 shown in the series-parallel switched-capacitor converter 100, the first order may also be from the third flying capacitor CFLY3 to the first flying capacitor CFLY1 and then to the second flying capacitor CFLY2, from the second flying capacitor CFLY2 to the first flying capacitor CFLY1 and then to the third flying capacitor CFLY3, from the second flying capacitor CFLY2 to the third flying capacitor CFLY3 and then to the first flying capacitor CFLY1, or from the first flying capacitor CFLY1 to the third flying capacitor CFLY3 and then to the second flying capacitor CFLY2. The present disclosure does not make specific limitations thereto, only limiting that the first order is not from the first flying capacitor to the last flying capacitor.

[0114] In the embodiments of the present disclosure, when the series-parallel switched-capacitor converter operates in the first phase, by disconnecting the connections between the multiple flying capacitors and the voltage input terminal, the connections between the multiple flying capacitors and the voltage output terminal, and the connections between adjacent two flying capacitors among the multiple flying capacitors according to the first switching signal, and then connecting each flying capacitor among the multiple flying capacitors to between the voltage output terminal and the ground in sequence according to the first order after the first duration, so as to control the series-parallel switched-capacitor converter to operate in the second phase, the charge and discharge loss of the output capacitance of the switching tube can be reduced, thereby reducing the switching loss and improving the conversion efficiency of the series-parallel switched-capacitor converter.

[0115] In some embodiments, Figure 4 is a schematic flowchart of a driving method provided by an embodiment of the present disclosure. Based on the embodiment shown in Figure 2 , the driving method further includes:

[0116] S201, when the series-parallel switched-capacitor converter operates in the second phase, disconnect the connection between the upper plate of each flying capacitor and the voltage output terminal, and the connection between the lower plate of each flying capacitor and the ground according to the second switching signal.

[0117] Exemplarily, when the first drive signal Drv1, the second drive signal Drv2, the third drive signal Drv3, the fourth drive signal Drv4, the fifth drive signal Drv5, and the sixth drive signal Drv6 are at a high level, and the seventh drive signal Drv7, the eighth drive signal Drv8, the ninth drive signal Drv9, and the tenth drive signal Drv10 are at a low level, the seventh switch tube M7, the eighth switch tube M8, the ninth switch tube M9, and the tenth switch tube M10 are turned off, and the first switch tube M1, the second switch tube M2, the third switch tube M3, the fourth switch tube M4, the fifth switch tube M5, and the sixth switch tube M6 are turned on, and the series-parallel switched capacitor converter 100 operates in the second phase.

[0118] like Figure 3 As shown, at time T6, the drive circuit pulls down the first drive signal Drv1, the second drive signal Drv2, the third drive signal Drv3, the fourth drive signal Drv4, the fifth drive signal Drv5, and the sixth drive signal Drv6 according to the second switching signal. The drive circuit can turn off the first switch M1 according to the first drive signal Drv1 to disconnect the top plate of the first flying capacitor CFLY1 from the voltage output terminal OUT, and turn off the second switch M2 according to the second drive signal Drv2 to disconnect the bottom plate of the first flying capacitor CFLY1 from ground.

[0119] The drive circuit turns off the third switch M3 in response to the third drive signal Drv3 to disconnect the upper plate of the second flying capacitor CFLY2 from the voltage output terminal OUT. The drive circuit turns off the fourth switch M4 in response to the fourth drive signal Drv4 to disconnect the lower plate of the second flying capacitor CFLY2 from the ground. The drive circuit turns off the fifth switch M5 in response to the fifth drive signal Drv5 to disconnect the upper plate of the third flying capacitor CFLY3 from the voltage output terminal OUT. The drive circuit turns off the sixth switch M6 in response to the sixth drive signal Drv6 to disconnect the lower plate of the third flying capacitor CFLY3 from the ground.

[0120] S202 , after the third time period, connect the upper plate of the latter flying capacitor to the lower plate of the former flying capacitor in the second order, so as to connect the two adjacent flying capacitors in series.

[0121] For example, Figure 3 As shown, at time T7, which is after time T6 and separated from time T6 by a third time Δt3, the drive circuit pulls up the eighth drive signal Drv8 and the ninth drive signal Drv9 in the second sequence. Based on the eighth drive signal Drv8 and the ninth drive signal Drv9, the drive circuit can turn on the eighth switch M8 and the ninth switch M9 in the second sequence, thereby connecting the first flying capacitor CFLY1, the second flying capacitor CFLY2, and the third flying capacitor CFLY3 in series in the second sequence.

[0122] The second order may be from the first flying capacitor to the last flying capacitor, for example, for Figure 1 In the series-parallel switched capacitor converter 100 shown, the first order is from the first flying capacitor CFLY1 to the third flying capacitor CFLY3 , that is, from the first flying capacitor CFLY1 to the second flying capacitor CFLY2 and then to the third flying capacitor CFLY3 .

[0123] like Figure 3 As shown, at time T7, the driving circuit pulls up the eighth driving signal Drv8, and turns on the eighth switch tube M8 according to the eighth driving signal Drv8 to connect the lower plate of the first flying capacitor CFLY1 with the upper plate of the second flying capacitor CFLY2, thereby connecting the first flying capacitor CFLY1 and the second flying capacitor CFLY2 in series.

[0124] At time T8, which is after time T7 and separated from time T7 by a sixth time interval Δt6, the driver circuit pulls up the ninth drive signal Drv9 and turns on the ninth switch M9 based on the ninth drive signal Drv9, thereby connecting the lower plate of the second flying capacitor CFLY2 to the upper plate of the third flying capacitor CFLY3, thereby connecting the second flying capacitor CFLY2 and the third flying capacitor CFLY3 in series. At this point, the first flying capacitor CFLY1, the second flying capacitor CFLY2, and the third flying capacitor CFLY3 are connected in series.

[0125] In other embodiments, the second order may also be from the last flying capacitor to the first flying capacitor, for example, Figure 1 In the series-parallel switched capacitor converter 100 shown, the second sequence may also be from the third flying capacitor CFLY3 to the first flying capacitor CFLY1 , ​​which is not specifically limited in the present disclosure.

[0126] S203 , after a fourth time period, connecting the plurality of flying capacitors connected in series between the voltage output terminal and the voltage input terminal to control the series-parallel switched capacitor converter to operate in the first phase.

[0127] For example, a specific description of a possible implementation method when executing S203 is as follows:

[0128] After the fourth time period, the lower plate of the last flying capacitor is connected to the voltage output terminal. After the fifth time period, the upper plate of the first flying capacitor is connected to the voltage input terminal.

[0129] like Figure 3 As shown, at time T9 which is after time T8 and separated from time T8 by a fourth time interval Δt4, the driving circuit pulls up the tenth driving signal Drv10, and turns on the tenth switch tube M10 according to the tenth driving signal Drv10, so as to connect the lower plate of the third flying capacitor CFLY3 to the voltage output terminal OUT.

[0130] At time T10, which is after time T9 and separated from time T9 by a fifth time interval Δt5, the driving circuit pulls up the seventh driving signal Drv7 and turns on the seventh switch M7 according to the seventh driving signal Drv7 to connect the upper plate of the first flying capacitor CFLY1 to the voltage input terminal IN.

[0131] At this time, when the first drive signal Drv1, the second drive signal Drv2, the third drive signal Drv3, the fourth drive signal Drv4, the fifth drive signal Drv5 and the sixth drive signal Drv6 are at a low level, and the seventh drive signal Drv7, the eighth drive signal Drv8, the ninth drive signal Drv9 and the tenth drive signal Drv10 are at a high level, the seventh switch M7, the eighth switch M8, the ninth switch M9 and the tenth switch M10 are turned on, and the first switch M1, the second switch M2, the third switch M3, the fourth switch M4, the fifth switch M5 and the sixth switch M6 are turned off, and the series-parallel switched capacitor converter 100 operates in the first phase.

[0132] based on Figure 3 The driving timing from the second phase to the first phase shown, the changes of the first high node voltage VCT1, the first low node voltage VCB1, the second high node voltage VCT2, the second low node voltage VCB2, the third high node voltage VCT3 and the third low node voltage VCB3 are shown in Table 3.

[0133] Table 3 Changes in voltage of each node under the driving timing from the second phase to the first phase provided by the present disclosure

[0134] VCB3 VCT3 VCB2 VCT2 VCB1 VCT1 T6 Moment 0 Vout 0 Vout 0 Vout T7 Moment 0 Vout 0 Vout Vout 2Vout T8 Moment 0 Vout Vout 2Vout 2Vout 3Vout T9 Moment Vout 2Vout 2Vout 3Vout 3Vout 4Vout T10 Moment Vout 2Vout 2Vout 3Vout 3Vout 4Vout

[0135] As shown in Table 3, at time T6, the first high node voltage VCT1, the first low node voltage VCB1, the second high node voltage VCT2, the second low node voltage VCB2, the third high node voltage VCT3, and the third low node voltage VCB3 remain consistent with when the first switch M1, the second switch M2, the third switch M3, the fourth switch M4, the fifth switch M5, and the sixth switch M6 are turned on. Therefore, the first switch M1, the second switch M2, the third switch M3, the fourth switch M4, the fifth switch M5, and the sixth switch M6 do not generate charge and discharge losses in the output capacitance of the switches.

[0136] At time T7, the first low node voltage VCB1 is charged from 0 to Vout, the first high node voltage VCT1 rises from Vout to 2Vout due to charge redistribution, and the second low node voltage VCB2, the second high node voltage VCT2, the third low node voltage VCB3, and the third high node voltage VCT3 remain unchanged. Then, the charge and discharge loss of the output capacitor of the eighth switch tube M8 is:

[0137] P Coss_CB1_M8 =0.5×C CB1 ×Vout 2 ×f sw

[0138] P Coss_CT1_M8 =0.5×C CT1 ×Vout 2 ×f sw

[0139] Among them, P COSS_CB1_M8 is the charge and discharge loss of the output capacitor of the eighth switch tube M8 caused by the change of the first low node voltage VCB1, P COSS_CT1_M8 It is the charge and discharge loss of the output capacitor of the eighth switch tube M8 caused by the change of the first high node voltage VCT1.

[0140] At time T8, the second low node voltage VCB2 is charged from 0 and rises to Vout. The second high node voltage VCT2 rises from Vout to 2Vout due to charge redistribution. The first low node voltage VCB1 rises from Vout to 2Vout. The first high node voltage VCT1 rises from 2Vout to 3Vout. The third low node voltage VCB3 and the third high node voltage VCT3 remain unchanged. Then, the charge and discharge loss of the output capacitor of the ninth switch tube M9 is:

[0141] P Coss_CB1_M9 =0.5×C CB1 ×Vout 2 ×f sw

[0142] P Coss_CT1_M9 =0.5×C CT1 ×Vout 2 ×f sw

[0143] P Coss_CB2_M9 =0.5×C CB2 ×Vout 2 ×f sw

[0144] P Coss_CT2_M9 =0.5×C CT2 ×Vout 2 ×fsw

[0145] Among them, P COSS_CB1_M9 is the charge and discharge loss of the output capacitor of the ninth switch tube M9 caused by the change of the first low node voltage VCB1, P COSS_CT1_M9 P is the charge and discharge loss of the output capacitor of the ninth switch tube M9 caused by the change of the first high node voltage VCT1. COSS_CB2_M9 is the charge and discharge loss of the output capacitor of the ninth switch tube M9 caused by the change of the second low node voltage VCB2, P COSS_CT2_M9 It is the charge and discharge loss of the output capacitor of the ninth switch tube M9 caused by the change of the second high node voltage VCT2.

[0146] At time T9, the third low node voltage VCB3 is charged and rises from 0 to Vout. The third high node voltage VCT3 rises from Vout to 2Vout due to charge redistribution. The second low node voltage VCB2 rises from Vout to 2Vout. The second high node voltage VCT2 rises from 2Vout to 3Vout. The first low node voltage VCB1 rises from 2Vout to 3Vout. The first high node voltage VCT1 rises from 3Vout to 4Vout. The charge and discharge loss of the output capacitor of the tenth switch tube M10 is:

[0147] P Coss_CB1_M10 =0.5×C CB1 ×Vout 2 ×f sw

[0148] P Coss_CT1_M10 =0.5×C CT1 ×Vout 2 ×f sw

[0149] P Coss_CB2_M10 =0.5×C CB2 ×Vout 2 ×f sw

[0150] P Coss_CT2_M10 =0.5×C CT2 ×Vout 2 ×f sw

[0151] P Coss_CB3_M10 =0.5×C CB3 ×Vout 2 ×f sw

[0152] P Coss_CT3_M10 =0.5×C CT3 ×Vout 2 ×fsw

[0153] Among them, P COSS_CB1_M10 is the charge and discharge loss of the output capacitor of the tenth switch tube M10 caused by the change of the first low node voltage VCB1, P COSS_CT1_M10 is the charge and discharge loss of the output capacitor of the tenth switch tube M10 caused by the change of the first high node voltage VCT1. COSS_CB2_M10 is the charge and discharge loss of the output capacitor of the tenth switch tube M10 caused by the change of the second low node voltage VCB2, P COSS_CT2_M10 is the charge and discharge loss of the output capacitor of the tenth switch tube M10 caused by the change of the second high node voltage VCT2. COSS_CB3_M10 is the charge and discharge loss of the output capacitor of the tenth switch tube M10 caused by the change of the third low node voltage VCB3, P COSS_CT3_M10 It is the charge and discharge loss of the output capacitor of the tenth switch tube M10 caused by the change of the third high node voltage VCT3.

[0154] At time T10, the first high node voltage VCT1, the first low node voltage VCB1, the second high node voltage VCT2, the second low node voltage VCB2, the third high node voltage VCT3 and the third low node voltage VCB3 do not change, so the seventh switch tube M7 does not generate the switch tube output capacitance charge and discharge loss.

[0155] Thus, based on the driving timing from the second phase to the first phase provided by the present disclosure, during the process of switching from the second phase to the second phase, the charge and discharge loss of the output capacitor of the switch tube P2 = Vout 2 ×f sw ×(1.5C CB1 +1.5C CT1 +C CB2 +C CT2 +0.5C CB2 +0.5C CT2 ). Therefore, in the 4:1 transformation ratio working mode, the switching tube output capacitor charge and discharge loss P = P1 + P2 = Vout 2 ×f sw ×(3C CB1 +3C CT1 +2C CB2 +2C CT2 +C CB2 +C CT2 )+(3C CB1 +3C CT1 +C CB2 +C CT2 )×Vd 2 ×f sw .

[0156] However, based on the existing driving timing from the second phase to the first phase, the variations of the first high node voltage VCT1, the first low node voltage VCB1, the second high node voltage VCT2, the second low node voltage VCB2, the third high node voltage VCT3, and the third low node voltage VCB3 are shown in Table 4.

[0157] Table 4 Variations of the node voltages in the existing driving timing from the second phase to the first phase

[0158] VCB3 VCT3 VCB2 VCT2 VCB1 VCT1 T6' moment 0 Vout 0 Vout 0 Vout T7' moment Vout 2Vout 2Vout 3Vout 3Vout 4Vout

[0159] At time T6', the first switching transistor M1, the second switching transistor M2, the third switching transistor M3, the fourth switching transistor M4, the fifth switching transistor M5, the sixth switching transistor M6, the seventh switching transistor M7, the eighth switching transistor M8, the ninth switching transistor M9, and the tenth switching transistor M10 are turned off. At time T7', the seventh switching transistor M7, the eighth switching transistor M8, the ninth switching transistor M9, and the tenth switching transistor M10 are turned on simultaneously.

[0160] Thus, based on the existing driving timing from the second phase to the first phase, during the process of switching from the second phase to the first phase, the charge and discharge loss P2' of the switching transistor output capacitance = Vout 2 ×f sw ×(4.5C CB1 +4.5C CT1 +2C CB2 +2C CT2 +0.5C CB2 +0.5C CT2 ). Obviously, P2 < P2'. Then, in the working mode with a 4:1 voltage transformation ratio, P1 + P2 < P1' + P2'. Therefore, the driving timing from the second phase to the first phase provided by the present disclosure can further reduce the charge and discharge loss of the switching transistor output capacitance, thereby further reducing the switching loss of the series-parallel switching capacitor converter 100 during operation, so as to further improve the conversion efficiency of the series-parallel switching capacitor converter 100.

[0161] It should be noted that S201 to S203 are executed before S101 and also after S102, that is, S101 to S102 and S201 to S203 are executed alternately.

[0162] In an embodiment of the present disclosure, when the series-parallel switched capacitor converter operates in the second phase, the connection between the upper plate of each flying capacitor and the voltage output terminal, and the connection between the lower plate of each flying capacitor and the ground are cut off according to the second switching signal. After a third time period, the upper plate of the latter of two adjacent flying capacitors is connected to the lower plate of the previous flying capacitor in a second order to connect the two adjacent flying capacitors in series. After a fourth time period, the plurality of flying capacitors connected in series are connected between the voltage output terminal and the voltage input terminal to control the series-parallel switched capacitor converter to operate in the first phase. This can further reduce the charge and discharge loss of the output capacitor of the switching tube, thereby further reducing the switching loss and further improving the conversion efficiency of the series-parallel switched capacitor converter.

[0163] The present disclosure also provides a power driver chip for executing the steps of any of the above method embodiments, having functional modules corresponding to the method embodiments, and having the beneficial effects of the method embodiments, which will not be described in detail here.

[0164] Unless the context clearly indicates otherwise, as used herein and in the appended claims, the singular includes the plural, and vice versa. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the words "include" and "comprising" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, the "example" is merely illustrative and should not be considered exclusive or comprehensive.

[0165] Several embodiments of the present disclosure have been described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The scope of protection of the present disclosure is defined by the appended claims.

Claims

1. A driving method for a series-parallel switched capacitor converter, characterized in that: The series-parallel switched capacitor converter includes a plurality of flying capacitors, wherein in a first phase, the plurality of flying capacitors are connected in series between a voltage input terminal and a voltage output terminal of the series-parallel switched capacitor converter, and in a second phase, the plurality of flying capacitors are connected in parallel between the voltage output terminal and ground; The driving method includes: When the series-parallel switched capacitor converter operates in the first phase, disconnecting the plurality of flying capacitors from the voltage input terminal, disconnecting the plurality of flying capacitors from the voltage output terminal, and disconnecting two adjacent flying capacitors from the plurality of flying capacitors according to a first switching signal; After the first time period, each of the multiple flying capacitors is connected between the voltage output terminal and the ground in sequence according to a first order to control the series-parallel switched capacitor converter to operate in the second phase, where the first order is any order other than from the first flying capacitor to the last flying capacitor among the multiple flying capacitors.

2. The driving method according to claim 1, wherein: The first order is from the last flying capacitor to the first flying capacitor.

3. The driving method according to claim 2, wherein: Connecting each of the plurality of flying capacitors between the voltage output terminal and the ground in sequence according to a first order includes: Connecting the lower plate of the last flying capacitor to the ground; After the second time period, the upper plate of the rear flying capacitor of the two adjacent flying capacitors is connected to the voltage output terminal, and the lower plate of the front flying capacitor is connected to the ground in the first order, and the time interval between the connection of the two adjacent flying capacitors to the voltage output terminal and the ground is the second time period; After the second time period, the upper plate of the first flying capacitor is connected to the voltage output terminal.

4. The driving method according to claim 1, wherein: The driving method further includes: When the series-parallel switched capacitor converter operates in the second phase, disconnecting the upper plate of each flying capacitor from the voltage output terminal and disconnecting the lower plate of each flying capacitor from the ground according to a second switching signal; After the third time period, connecting the upper plate of the latter flying capacitor to the lower plate of the former flying capacitor in the second order, so as to connect the two adjacent flying capacitors in series; After a fourth time period, the plurality of flying capacitors connected in series are connected between the voltage output terminal and the voltage input terminal to control the series-parallel switched capacitor converter to operate in the first phase.

5. The driving method according to claim 4, wherein: The second order is from the first flying capacitor to the last flying capacitor.

6. The driving method according to claim 4, wherein: Connecting the plurality of flying capacitors connected in series between the voltage output terminal and the voltage input terminal comprises: Connecting the lower plate of the last flying capacitor to the voltage output terminal; After the fifth time period, the upper plate of the first flying capacitor is connected to the voltage input terminal.

7. The driving method according to claim 3, wherein: The plurality of flying capacitors include a first flying capacitor, a second flying capacitor, and a third flying capacitor, and the series-parallel switched capacitor converter further includes a first switching tube, a second switching tube, a third switching tube, a fourth switching tube, a fifth switching tube, and a sixth switching tube; The upper plate of the first flying capacitor is connected to the voltage output terminal through the first switching transistor, the lower plate of the first flying capacitor is grounded through the second switching transistor, the upper plate of the second flying capacitor is connected to the voltage output terminal through the third switching transistor, the lower plate of the second flying capacitor is grounded through the fourth switching transistor, the upper plate of the third flying capacitor is connected to the voltage output terminal through the fifth switching transistor, and the lower plate of the third flying capacitor is grounded through the sixth switching transistor; Connecting the lower plate of the last flying capacitor to the ground comprises: Turning on the sixth switch tube; The step of simultaneously connecting the upper plate of the rear flying capacitor of the two adjacent flying capacitors to the voltage output terminal and the lower plate of the front flying capacitor to the ground in the first order comprises: Turning on the fifth switch tube and the fourth switch tube to connect the third flying capacitor between the voltage output terminal and the ground; After the second time period, turning on the third switch tube and the second switch tube to connect the second flying capacitor between the voltage output terminal and the ground; Connecting the upper plate of the first flying capacitor to the voltage output terminal includes: The first switch tube is turned on to connect the first flying capacitor between the voltage output terminal and the ground.

8. The driving method according to claim 6, wherein: The plurality of flying capacitors include a first flying capacitor, a second flying capacitor, and a third flying capacitor, and the series-parallel switched capacitor converter includes a seventh switching tube, an eighth switching tube, a ninth switching tube, and a tenth switching tube; The upper plate of the third flying capacitor is connected to the lower plate of the second flying capacitor through the ninth switching transistor, the upper plate of the second flying capacitor is connected to the lower plate of the first flying capacitor through the eighth switching transistor, the upper plate of the first flying capacitor is connected to the voltage input terminal through the seventh switching transistor, and the lower plate of the third flying capacitor is connected to the voltage output terminal through the tenth switching transistor; The step of connecting the upper plate of the latter flying capacitor to the lower plate of the former flying capacitor in the second order to connect the two adjacent flying capacitors in series comprises: Turning on the eighth switch tube to connect the first flying capacitor and the second flying capacitor in series; After the sixth time period, the ninth switch tube is turned on to connect the second flying capacitor and the third flying capacitor in series.

9. The driving method according to claim 8, wherein: Connecting the lower plate of the last flying capacitor to the voltage output terminal includes: Turning on the tenth switch tube to connect the lower plate of the third flying capacitor to the voltage output terminal; Connecting the upper plate of the third flying capacitor to the voltage input terminal includes: The seventh switch tube is turned on to connect the upper plate of the first flying capacitor to the voltage input terminal.

10. A power driver chip, characterized in that: Used to execute the driving method according to any one of claims 1 to 9.

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