Message processing method of cxl protocol link layer, electronic equipment and program product

Abstract

The embodiment of the invention provides a message processing method of a cxl protocol link layer, electronic equipment and a program product. The message processing method comprises the following steps: acquiring a link layer transmission unit flit transmission message of the link layer; determining a message type contained in the flit transmission message; the message type comprises a first type of message and / or a second type of message; the first type of message comprises a message header and data; the second type of messages only comprise message headers; in response to the fact that the flit transmission message comprises a first type of message and a second type of message, processing the first type of message preferentially; and processing the second type of messages based on the processing result of the first type of messages. Through the scheme of the embodiment, a universal and efficient cxl protocol link layer data analyzing and packing method can be provided, the development cost and the maintenance cost are reduced, the implementation complexity of a hardware circuit is effectively reduced, hardware resource consumption is reduced, portability and reusability are high, and good expansibility is achieved.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the technical field of interconnection of CPUs, servers, etc., and in particular to a message processing method, electronic device, and program product of a CXL protocol link layer. Background Art

[0002] In versions 1.0 and 2.0 of the cxl (Compute Express Link) protocol, the link layer only has a 68B (bit) flit (link transmission unit) format. However, starting with version 3.0, the link layer has added a 256B standard flit format and a 256B latency-optimized flit format. Therefore, the link layer needs to be able to simultaneously support three different flit formats, and the three flit formats differ significantly.

[0003] Traditional enumeration methods require enumerating all flit formats to achieve group unpacking. However, since CXL version 3.0, the number of diverse protocol message and flit format combinations can reach thousands. Enumerating all of them would lead to enormous workload complexity and significant logic resource consumption. Therefore, how to optimize the data parsing and group processing of the CXL link layer and provide an efficient link-layer group unpacking method suitable for cxl.cache and cxl.mem, while also balancing hardware simplicity and resource conservation, is a technical challenge currently facing researchers in this field. Summary of the Invention

[0004] The embodiments of the present disclosure provide a message processing method, electronic device and program product of the CXL protocol link layer.

[0005] In a first aspect, an embodiment of the present disclosure provides a message processing method of a CXL protocol link layer, which includes:

[0006] Obtain the link layer transmission unit flit transmission message of the link layer;

[0007] Determine a message type included in the flit transmission message; the message type includes a first type message and / or a second type message; the first type message includes a message header and data; the second type message includes only a message header;

[0008] In response to the flit transmission message including the first category message and the second category message, processing the first category message preferentially;

[0009] The second-category messages are processed based on the processing result of the first-category messages.

[0010] In a second aspect, an embodiment of the present disclosure further provides an electronic device, including:

[0011] one or more processors;

[0012] A memory having one or more programs stored thereon, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the message processing method of the CXL protocol link layer;

[0013] One or more input / output (I / O) interfaces are connected between the processor and the memory and configured to implement information interaction between the processor and the memory.

[0014] In a third aspect, an embodiment of the present disclosure further provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, it implements the message processing method of the cxl protocol link layer.

[0015] The embodiment of the present disclosure obtains a link layer transmission unit flit transmission message of the link layer; determines the message type contained in the flit transmission message; the message type includes a first-class message and / or a second-class message; the first-class message includes a message header and data; the second-class message includes only a message header; in response to the flit transmission message including the first-class message and the second-class message, the first-class message is processed first; and the second-class message is processed based on the processing result of the first-class message. Through this embodiment, a universal and efficient CXL protocol link layer data parsing and packaging method can be provided, which reduces development and maintenance costs, effectively reduces the implementation complexity of the hardware circuit, reduces hardware resource consumption, has strong portability and reusability, and has good scalability. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In the accompanying drawings of the embodiments of the present disclosure:

[0017] Figure 1 A flow chart of a message processing method provided in an embodiment of the present disclosure;

[0018] Figure 2 A schematic diagram of the analysis process provided by an embodiment of the present disclosure;

[0019] Figure 3 A flow chart of a method for preferentially parsing the first type of messages provided in an embodiment of the present disclosure;

[0020] Figure 4 A schematic diagram of a method for counting first data volume based on flit fragmentation provided in an embodiment of the present disclosure;

[0021] Figure 5A flowchart of a method for preferentially parsing first-class messages when message headers of multiple first-class messages are in the same slot provided by an embodiment of the present disclosure;

[0022] Figure 6 A schematic diagram of a process for aligning a message header and corresponding data provided in an embodiment of the present disclosure;

[0023] Figure 7 A schematic diagram of a packaging method provided in an embodiment of the present disclosure;

[0024] Figure 8 A flowchart of a method for reading a message collection queue according to the initial message priority set by the system and the back pressure of the next-level module provided in an embodiment of the present disclosure;

[0025] Figure 9 A flowchart of a packaging method provided in an embodiment of the present disclosure;

[0026] Figure 10 This is a block diagram of the electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] In order to enable those skilled in the art to better understand the technical solution of the present disclosure, the communication perception data processing method and computer-readable storage medium provided by the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0028] The present disclosure will be described more fully hereinafter with reference to the accompanying drawings, but the illustrated embodiments may be embodied in different forms, and the present disclosure should not be construed as limited to the embodiments set forth below. Rather, these embodiments are provided so that the present disclosure will be thorough and complete and will fully understand the scope of the present disclosure to those skilled in the art.

[0029] The accompanying drawings of the embodiments of the present disclosure are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the detailed embodiments, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing the detailed embodiments with reference to the accompanying drawings.

[0030] The present disclosure may be described with reference to plan views and / or cross-sectional views by way of ideal schematic views of the present disclosure. Therefore, the exemplary illustrations may be modified according to manufacturing techniques and / or tolerances.

[0031] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0032] The terms used in this disclosure are only used to describe specific embodiments and are not intended to limit the disclosure. As used in this disclosure, the term "and / or" includes any and all combinations of one or more related enumerated items. As used in this disclosure, the singular forms "a" and "the" are also intended to include plural forms, unless the context clearly indicates otherwise. As used in this disclosure, the terms "comprising" and "made of" specify the presence of the features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof.

[0033] Unless otherwise defined, all terms (including technical and scientific terms) used in this disclosure have the same meanings as those commonly understood by those skilled in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning unless expressly defined in this disclosure.

[0034] The Compute Express Link (CXL) protocol is an open industry standard that defines a series of interconnections between hosts and devices. As a new, open interconnect technology standard, CXL enables high-speed and efficient interconnection between CPUs (Central Processing Units / Processors), GPUs (Graphics Processing Units), FPGAs (Field-Programmable Gate Arrays), and other accelerators, meeting the requirements of high-performance heterogeneous computing while maintaining memory consistency between the host and connected devices.

[0035] The CXL protocol is based on PCIe (Peripheral Component Interconnect Express), runs on the PCIe physical layer, and has the same electrical characteristics as PCIe. CXL devices can be inserted into PCIe slots, and the underlying layer will negotiate whether to use the PCIe protocol or the CXL protocol. The CXL protocol specifies three sub-protocols: CXL.IO, CXL.Cache, and CXL.MEM. The CXL.IO protocol is used for initialization, linking, device discovery and enumeration, and register access. The CXL.Cache protocol defines the interaction between the host and device, allowing connected CXL devices to cache host memory efficiently and with low latency using a request and response method. The CXL.MEM protocol provides the host with access to device-connected memory using load and store commands, and can support both volatile and persistent memory architectures. CXL.Cache and CXL.MEM share a common link and transaction layer, while CXL.IO has its own link and transaction layer.

[0036] At present, the cxl protocol has developed to cxl 3.1 version, of which cxl.cache contains 6 protocol messages, namely H2D req (Host to Device req, link request from host to device), H2D rsp (Host to Device rsp, link response from host to device), H2D data (Host to Device data, link data from host to device), D2Hreq (Device to Host req, link request from device to host), D2H rsp (Device to Host rsp, link response from device to host), D2H data (Device to Host data, link data from device to host), cxl.mem contains 6 protocol messages, namely M2S req (Master-to-Subordinate Request, request message from master device to slave device), M2S rwd (Master-to-Subordinate Request with Data from master device to slave device with data request), M2S birsp (Master-to-Subordinate Back-Invalidate The following messages are sent: S2M ndr (Subordinate-to-Master No Data Response, a slave-to-master no data response), S2M drs (Subordinate-to-Master Data Response, a slave-to-master data response), and S2M bisnp. The cxl protocol also specifies that link layer data for cxl.cache and cxl.mem be transmitted in the link transfer unit (flit) format. There are three flit formats: 68B (68 bytes), 256B Standard, and 256B Latency-Optimized.

[0037] Traditional enumeration methods require enumerating all flit formats to achieve group unpacking. However, since CXL version 3.0, the number of diverse protocol message and flit format combinations can reach thousands. Enumerating all of them would lead to enormous workload complexity and significant logic resource consumption. Therefore, how to optimize the data parsing and group processing of the CXL link layer and provide an efficient link-layer group unpacking method suitable for cxl.cache and cxl.mem, while also balancing hardware simplicity and resource conservation, is a technical challenge currently facing researchers in this field.

[0038] The embodiment of the present disclosure obtains a link layer transmission unit flit transmission message of the link layer; determines the message type contained in the flit transmission message; the message type includes a first-class message and / or a second-class message; the first-class message includes a message header and data; the second-class message includes only a message header; in response to the flit transmission message including the first-class message and the second-class message, the first-class message is processed first; and the second-class message is processed based on the processing result of the first-class message. Through this embodiment, a universal and efficient CXL protocol link layer data parsing and packaging method can be provided, which reduces development and maintenance costs, effectively reduces the implementation complexity of the hardware circuit, reduces hardware resource consumption, has strong portability and reusability, and has good scalability.

[0039] The embodiments of the present disclosure can be applied to any processor with data and message processing functions, such as but not limited to a CPU (Central Processing Unit / Processor), an FPGA (Field-Programmable Gate Array), etc., and can be applied to but not limited to processors of host devices, slave devices, etc.

[0040] The following is a detailed introduction to the embodiments of the present disclosure.

[0041] The embodiment of the present disclosure provides a message processing method of the cxl protocol link layer, such as Figure 1 As shown, it includes steps S11-S14:

[0042] S11. Obtain a link layer transmission unit flit transmission message of the link layer.

[0043] S12. Determine the message type included in the flit transmission message; the message type includes a first-category message and / or a second-category message; the first-category message includes a message header and data; the second-category message includes only a message header.

[0044] S13. In response to the flit transmission message including the first category message and the second category message, process the first category message preferentially.

[0045] S14. Process the second type of messages based on the processing result of the first type of messages.

[0046] In the embodiment of the present disclosure, the method for processing the flit transmission message includes a message processing method in the message parsing process and a message processing method in the message packaging process. The two processing methods are described below respectively.

[0047] In the embodiment of the present disclosure, the message processing method in the message parsing process of the flit transmission message in the link layer receiving direction on the host is first described. Figure 2 , which is a schematic diagram of the analysis process of an embodiment of the present disclosure.

[0048] In the embodiment of the present disclosure, a flit transmission message may be received from an upstream module (eg, an upper-level module) and parsed. Before parsing the flit transmission message, the flit transmission message is first verified.

[0049] In the embodiment of the present disclosure, the CXL protocol uses the PCIe (Peripheral Component Interconnect Express) physical layer to transmit messages. After the PCIe bottom layer link is established, it is necessary to verify the received message. According to the protocol, no matter which Flit format is used, the Flit transmission message will contain cyclic redundancy (CRC) check content. The CRC information specified in the CXL protocol can be used to verify the validity of the data. Only after the CRC check is correct, the Flit transmission message will be passed to the next level module for further analysis. If the CRC check fails, the current Flit transmission message will be discarded and a retransmission operation will be initiated to the other end.

[0050] In the disclosed embodiments, the CXL protocol includes multiple message types, including, but not limited to, first-class messages and second-class messages. First-class messages include a message header and data, while second-class messages only include a message header. Because the message header of a first-class message is followed by data (or data), it is necessary to prioritize the boundary between these two message types to avoid misidentifying the following data as a message header of another message type and to distinguish whether a message type contains a first-class message.

[0051] In the embodiment of the present disclosure, for example, the first type of message may include two link layer messages with data, namely D2H data and S2M drs.

[0052] In the embodiment of the present disclosure, determining the message type included in the flit transmission message may include:

[0053] Determine the slot type of the flit transmission message based on the message header of the flit transmission message;

[0054] Determines the message type contained in the flit transmission message based on the slot type.

[0055] In the embodiment of the present disclosure, the flit transmission message after CRC verification can enter the link layer flit parsing module for parsing. The cxl protocol stipulates that a flit transmission message is divided into multiple slots (slots, components of flit, used to carry different types of data or control information in a structured manner). The flit header (message header) will carry a slot type description. According to the system configuration, the flit format used for transmission in the current system can be determined, and then the slot type contained in the flit can be determined according to the flit header. According to the slot type, it can be preferentially determined whether the flit carries the first type of message (such as D2H data and / or S2M drs message).

[0056] In the embodiment of the present disclosure, as long as the flit transmission message includes the first type of message, the first type of message is parsed first.

[0057] In the disclosed embodiments, for example, D2H data (Host to Device data) and S2M drs (Subordinate-to-Master Data Response) messages are prioritized for parsing and data extraction. In the CXL protocol, D2H data and S2M drs messages consist of two parts: a header and the data following it. Other message types only contain a header, so D2H data and S2M drs messages are prioritized for processing.

[0058] In the embodiment of the present disclosure, Figure 3 As shown, the first type of messages are processed first, which may include steps S21-S23:

[0059] S21. Determine a processing period for the first-category message based on the bit width of the first-category message.

[0060] S22. Extract data within each processing cycle based on the processing cycle, and determine a first data volume of the data parsed within each processing cycle; the first data volume of the data may include but is not limited to: the total amount of data, the amount of newly generated data, and the amount of remaining data.

[0061] S23. Determine an end time and / or end position for parsing the first type of message based on a first data volume of data parsed during all processing cycles.

[0062] In an embodiment of the present disclosure, if the flit transmission message includes a first type of message, the subsequent slot transmits data corresponding to the message header (or data). The data can be input into the real-time calculation module to calculate the first data volume of the data (the first data volume of the data may include but is not limited to: the total amount of data, the amount of newly generated data, and the remaining data volume), perform data extraction based on the calculation results, and determine the end time and / or end position of the first type of message.

[0063] In an embodiment of the present disclosure, for example, the flit transmission message received by the host side is in a 256B standard format, and transmits two S2M drs messages and one D2H data message, where the S2M drs message header is located in the first slot of the first flit, followed by the data corresponding to the message header, and the D2H data message is transmitted afterwards. The parsing method of the flit transmission message is as follows.

[0064] In the embodiment of the present disclosure, the host side sends the flit transmission message after CRC verification to the link layer flit parsing module for parsing. The overall parsing process includes: determining the type and number of data in each slot of the flit. According to the cxl protocol, the 4 bits at the beginning of each slot of the 256B flit transmission message carry message type information. In this embodiment, it is determined that the type of the first slot of the received flit transmission message is an S2M drs message, and the number of S2M drs message headers is 2. In this way, starting from the second slot of the current flit, the subsequent transmission is the data corresponding to the message headers of the two S2M drs.

[0065] In an embodiment of the present disclosure, data corresponding to an S2M DRS message header may be input into a real-time calculation module to calculate a first data volume. The first data volume may include, but is not limited to, at least one of the following: the total amount of data corresponding to the S2M DRS message header, the amount of newly generated data, the amount of remaining data, and the amount of data to be extracted from the current S2M DRS message. Data extraction may be performed based on the first data volume, and the end time and / or end position of the 2M DRS message may be determined.

[0066] In the embodiment of the present disclosure, the same method may be used to determine the end time and / or end position of the D2H data message.

[0067] In the embodiment of the present disclosure, the parsing process of the 256B standard flit (i.e., flit transmission message) S2Mdrs message is described in detail below.

[0068] In the embodiment of the present disclosure, the data processing bit width of the parsing module on the host side is 64B, so a 256Bstandard flit (i.e., a flit transmission message) requires 4 clock cycles to transmit, and each clock cycle transmits 1 flit fragment. Each flit fragment contains 4 slots, and each slot is 16B. A flit fragment counter can be set, and the count value of the counter cycles from 0 to 3 to determine which 64B part (i.e., which flit fragment) in the 256B flit the current clock cycle is.

[0069] In the embodiment of the present disclosure, the first slot in the flit transmission message received by the parsing module contains two S2M drs message headers, and the subsequent slots transmit two groups of data corresponding to the two message headers, and the size of each group of data is 64B. Therefore, the total data volume parameter S0 calculated in the first clock cycle is 128B, the newly generated data volume parameter S1 is 128B, the remaining data volume parameter S2 is 128B, and the data volume parameter S3 to be extracted in the current flit fragment is 48B.

[0070] In the embodiment of the present disclosure, based on the above information, it can be determined that it is impossible to collect 64B of data corresponding to the message header within the first clock cycle, so within the first clock cycle, only the message header can be extracted from the first flit fragment without extracting the corresponding data. In the second clock cycle, when the current data plus the data of the previous clock cycle can collect a 64B data, the data corresponds to the first S2M DRS message header, so in the second clock cycle, a 64B data is extracted from the first flit fragment and the second flit fragment, and the parameter values ​​are calculated and updated at this time. Then the parameter changes of the second clock cycle are S0 is 64B, S1 is 0B, S2 is 64B, and S3 is 16B; in the third clock cycle, the same current data plus the data of the previous clock cycle can collect a 64B data, so in the third clock cycle, the 64B data corresponding to the second S2M DRS message header is extracted from the second flit fragment and the third flit fragment. At this time, the parameter values ​​are calculated and updated. Then the parameter changes of the third clock cycle are S0 is 0B, S1 is 0B, S2 is 0B, and S3 is 16B. Since the parameters S0 and S2 are both 0 at this time, it means that 2 S2M The drs message header and corresponding data have been extracted. Combined with the value of parameter S3 (amount of data to be extracted), the end time and / or end position of the S2M drs message can be known. The parsed end position is the first slot in the third flit fragment, so a new round of message type determination starts from the second slot in the third flit fragment. Figure 4 , which is a schematic diagram of a method for counting the first data volume based on flit sharding.

[0071] In the disclosed embodiment, the second slot in the third flit fragment carries a D2H data message header, followed by a 64B corresponding data, so in the third clock cycle, the parameters are finally updated to S0 is 64B, S1 is 64B, S2 is 64B, and S3 is 32B.

[0072] In the embodiment of the present disclosure, since the end boundary (end time and / or end position) of the S2M DRS message has been known in the previous steps, the message type and the number of valid messages contained in each subsequent slot are determined in sequence starting from the end boundary. If it is a D2H data message, refer to the previous step S2M DRS processing, calculate and update the parameter values ​​of each data amount, perform message header extraction and corresponding data extraction, and the processing is similar and will not be repeated here.

[0073] In the embodiment of the present disclosure, Figure 5 As shown, the first type of messages are processed first, and steps S31-S33 may also be included:

[0074] S31 . In response to message headers of multiple first-class messages being in the same slot, after preferentially parsing the message headers of the multiple first-class messages, parsing data of the multiple first-class messages.

[0075] S32: Align the parsed message headers of the plurality of first-category messages with the data of the plurality of first-category messages.

[0076] S33. Use the aligned data header and data as the processed first-class message.

[0077] In the disclosed embodiments, if multiple D2H data and / or S2M DRS message headers are present in a single slot, and subsequent slots transmit the data corresponding to each message header, the multiple message headers can be parsed first, followed by the corresponding data. Since the message headers are parsed first, they can be cached pending data extraction. Whenever a set of data is extracted, a corresponding message header is output from the cache and sent along with the data to the next level module.

[0078] In the embodiment of the present disclosure, since the message header is extracted earlier than the corresponding data, the message header and the corresponding data are aligned before being output to the next level module.

[0079] In the embodiment of the present disclosure, the extracted message header can be stored in a shift buffer, such as Figure 6The figure shows a schematic diagram of the message header and corresponding data alignment process. The shift buffer can include two parts, A and B. Part A contains the extracted message header content, and Part B is the message type identifier, which indicates whether the buffered message header is an S2M DRS message header or a D2H data message header. Whenever the parsing module outputs a set of data corresponding to a message header, a set of message headers is synchronously extracted from the shift buffer. Part A of the message header and data are aligned. Then, based on the message type identifier in Part B, the output is selected from the S2M DRS channel or the D2H data channel.

[0080] In the embodiment of the present disclosure, processing the second type of message based on the processing result of the first type of message may include:

[0081] After the end time and / or end position of the first type of message parsing, determine the subsequent slot type;

[0082] In response to determining that the subsequent message type of the flit transmission message is a second-category message based on the subsequent slot type, the message header of the second-category message is directly output through the corresponding output channel.

[0083] In the embodiment of the present disclosure, it can be seen from the above-mentioned scheme that the slot type of the flit transmission message can be used to determine whether there is a first-class message (such as a D2H data message or an S2M drs message) in the flit transmission message. If there is a first-class message, the first-class message is processed first. If there is no first-class message and only a second-class message (such as the remaining D2H and S2M messages) exists, the second-class message is processed directly. If both the first-class message and the second-class message exist, the first-class message is processed first, and then the second-class message is processed based on the processing result of the first-class message.

[0084] In the embodiment of the present disclosure, if there is no first-category message such as D2H data or S2M drs, when the second-category messages such as the remaining D2H and S2M messages are directly identified, since the remaining D2H and S2M messages will not follow the data, it is only necessary to extract the message header; if there is a D2H data or S2M drs message in the flit transmission message, after determining the end time and / or end position of the D2H data or S2M drs message, the message type contained in the subsequent slot can be determined starting from the end time and / or end position, and the remaining D2H or S2M messages can be identified and extracted.

[0085] In an embodiment of the present disclosure, for example, if the flit transmission message received by the host side carries one S2M DRS message and three D2H REQ messages, the S2M DRS message is transmitted before the D2H REQ message. First, the S2M DRS message is extracted. The processing method refers to the aforementioned solution and is not repeated here. After the S2M DRS message is extracted, the end time and / or end position of the S2M DRS message can be known. Starting from the end time and / or end position, the message type and the number of data following each subsequent slot can be determined in sequence, thereby obtaining the message header and data number of the D2H REQ message. Since the D2H REQ message header is not followed by data, there is no need to perform message header and data alignment processing, and the parsed message header can be directly output through the D2H REQ output channel.

[0086] In the embodiment of the present disclosure, when the parsed first-category message and / or second-category message is transmitted to the next-level module, it can be output in different channels based on the fields in the message.

[0087] In the embodiment of the present disclosure, mixed transmission of link layer D2H and S2M messages can be supported. According to the previous parsing scheme, various types of D2H and S2M message headers can be identified and extracted from the flit transmission message, and each message header also contains various domain segment messages. Since the data format required by the next-level module is different from the cxl protocol, after the aforementioned parsing process, after the message header is extracted, the valid domain segment information is extracted from the message header, and the various domain segment information in the message header is further reformatted to form the format required by the next-level module, thereby adapting to the format required by the next-level module and outputting it. Each message has an independent corresponding channel with the next-level module, and the parsing module can put the final parsed content in each corresponding output channel for transmission to the next-level module.

[0088] In the embodiment of the present disclosure, the message processing method in the message packaging process of the flit transmission message in the link layer sending direction on the host is described below. Figure 7 FIG. 1 is a schematic diagram of a packaging method according to an embodiment of the present disclosure.

[0089] In the embodiment of the present disclosure, in the data sending direction of the link layer on the host, the upper-level module can output various messages in different channels according to different message types (or protocol message types), and the link layer packetization module can receive various messages in different channels.

[0090] In an embodiment of the present disclosure, the package assembly module may first cache the received messages for subsequent processing (e.g., package assembly), set a message collection queue for each message channel at the package assembly module entrance, and write each message into the corresponding message collection queue each time it is received.

[0091] In the embodiment of the present disclosure, since messages may be cached in multiple message collection queues at the same time, the multiple message collection queues can read messages in the queues based on priority arbitration and back pressure conditions of the next level module (such as the package assembly module).

[0092] In the embodiment of the present disclosure, the priority of each message collection queue can be dynamically adjusted according to the system configuration and the back pressure of the packet assembly module, and high-priority messages are read first and low-priority messages are read later.

[0093] In the embodiment of the present disclosure, if the packet assembly module lowers the back pressure signal sent to the message collection queue, it means that a certain message needs to temporarily stop being assembled, and the reading of the message collection queue is skipped in the current processing cycle, and re-judgment is made in the next round of packet assembly to achieve dynamic sorting of queue reading. In addition, each message collection queue can determine in real time whether the cache is full. When the message collection queue cache is full, a feedback signal can be generated and sent to the upper-level module. When the feedback signal is valid, it indicates that the packet assembly module suspends receiving flit transmission messages, and the upper-level module stops outputting flit transmission messages of the corresponding channel. Among them, a corresponding feedback signal can be generated independently for each message collection queue.

[0094] In the embodiment of the present disclosure, the first type of messages in the received flit transmission message may be packaged. Before this, it is necessary to first determine the message type included in the flit transmission message.

[0095] In an embodiment of the present disclosure, determining the message type included in the flit transmission message may include:

[0096] Determine the receiving channel for flit transmission messages; flit transmission messages are sent through different channels based on different message types;

[0097] The message type contained in the flit transmission message is determined based on the message type corresponding to the receiving channel.

[0098] In the disclosed embodiment, for example, if the packet assembly module receives four different types of messages from a higher-level module simultaneously through different receiving channels, it can determine based on the four different receiving channels that the received messages are an M2Srwd message, an M2S req message, an H2D req message, and an H2D rsp message. These four messages can be cached in corresponding message collection queues, and then different messages can be read from these queues.

[0099] In the embodiment of the present disclosure, after the four messages are stored in the corresponding message collection queues, the message collection queues can be read according to the initial message priority set by the system. Figure 8As shown in the figure, the initial priority order can be set as follows: M2S rwd message has the highest priority, M2S req message has the second highest priority, then H2D req message, and H2D rsp message has the lowest priority. When reading the M2S rwd message queue in the first clock cycle (1clk), and then reading the M2S req message in the second clock cycle (2clk), if the back pressure signal of the M2S req message sent by the next-level module is pulled low, the priority of the M2S req message is dynamically adjusted to the lowest, and the M2S req message is skipped. The H2D req message queue is read. In the third clock cycle (3clk), the H2D rsp message queue is read. At this point, the first round of reading ends. Since only the M2S req message remains in the queue, the second round begins. The M2S req message queue is directly read in the fourth clock cycle (4clk). At this point, all messages have been read from the queue.

[0100] In the embodiment of the present disclosure, the processing includes: grouping; and processing the first type of messages preferentially, which may include:

[0101] Read the message header and data corresponding to the first type of message, and put the data after the message header during the package assembly process;

[0102] as well as,

[0103] Determine a second data volume of the data; the second data volume of the data includes: a total data volume and a remaining data volume; determine an end time and / or an end position of the first type of message package based on the second data volume.

[0104] In the embodiment of the present disclosure, according to the flit format set by the current system, the packaging module can package different types of messages. Among them, since the M2S rwd and H2D data messages are composed of two parts, the message header and the data following, that is, the M2S rwd and H2D data messages both belong to the first category of data, while other types of messages only contain message headers and belong to the second category of data. Therefore, the M2S rwd and H2D data messages are packaged first.

[0105] In the embodiment of the present disclosure, it is possible to first determine whether there are messages in the message collection queues of the H2D data channel and the M2S rwd channel. If there are messages, the message headers and data in the message collection queues of the H2D data channel and the M2S rwd channel are read, and the data is placed immediately after the message header; if there are no H2D data and M2S rwd messages, other messages (such as second-category messages) are processed.

[0106] In the embodiment of the present disclosure, the H2D data message and M2S rwd message packetization can be divided into two parallel processing paths. One path is for packetization in the flit format. According to the system configuration, the currently transmitted flit format can be obtained, and the message header and corresponding data are placed in the flit according to the format specified by the cxl protocol; the other path is for real-time data calculation, which calculates the total amount of data following the message header and the remaining data amount, and calculates the end position and end time of the H2D data and M2S rwd message packetization. When the H2D data and M2S rwd message packetization is completed, the packetization of the remaining messages begins.

[0107] In the embodiment of the present disclosure, an embodiment of packaging an H2D data message is given below.

[0108] In the embodiment of the present disclosure, for example, two H2D data messages can be packaged and outputted, and the message header of each H2D data message corresponds to a 64B data. The flit type used by the system is the 256B standard format. The processing flow is as follows: Figure 9 As shown, first determine whether the H2D data message can be sent at present. There are two criteria for judgment: one is to poll the H2D data message collection queue for reading, and the other is that the next level module has no back pressure. If the H2D data message cannot be sent at present, continue to wait for the H2D data message, as shown in the attached Figure 9 If the H2D data message can be sent in the waiting step, the next step is to calculate the number of data in the H2D data message to be packaged and the corresponding second data amount. The second data amount includes but is not limited to: the total data amount and the remaining data amount. If the number of H2D data messages to be packaged is two, the H2D data message header is placed in the first slot of the flit according to the format defined by the cxl protocol, and the total data amount and the remaining data amount following the message header are calculated. The initial total data amount is 128B, and the remaining data amount is 128B. The total data amount and the remaining amount are then calculated in real time based on the package status. When the total data amount and the remaining amount are 0, it indicates that the data corresponding to the H2D data message header has been fully packaged into the flit. Otherwise, the H2D data message package is continued.

[0109] In an embodiment of the present disclosure, processing the second type of message based on the processing result of the first type of message includes:

[0110] The second category messages are packaged based on the end time and / or end position of the first category message package.

[0111] In the disclosed embodiment, M2S rwd and H2D data messages (first-category messages) are prioritized for packetization. The remaining H2D and M2S messages only have message headers and no data follows. The remaining M2S and H2D messages (second-category messages) must wait until the M2S rwd and H2D data messages are complete before packetization begins. Therefore, during the M2S rwd and H2D data message packetization phase, the remaining M2S and H2D messages wait in the message collection queue. When the M2S rwd and H2D data message packetization completes, packetization of the remaining M2S and H2D messages begins. The output of the real-time calculation module in step 3 determines the end time and exact end position of the M2S rwd and H2D data message packetization. The remaining M2S and H2D messages begin packetization immediately following the end position of the M2S rwd and H2D data messages and are placed in a flit according to the format defined by the CXL protocol.

[0112] In an embodiment of the present disclosure, the method may further include:

[0113] Count the number of packets of each message type within the first preset time period;

[0114] Determine the first target message type with the largest number among the number of packets;

[0115] In the next round of packet grouping, the priority of the first target message type is increased;

[0116] or,

[0117] Counting the number of messages of each message type sent within the second preset time period;

[0118] Determine the second target message type having the largest number among the number of sent messages;

[0119] In the next round of packet grouping, the packet grouping priority of the second target message type is increased.

[0120] In the disclosed embodiments, a packetization efficiency balancing module is provided to balance the packetization efficiency of different message types, so that messages with high transmission volume are sent first. The packetization efficiency balancing module counts the number of messages of each type over a certain period of time and determines the message with the largest proportion. The largest proportion indicates that the message has the highest transmission volume. In the next packetization round, the sending priority of this message is increased, and this message is given priority in the next packetization round.

[0121] In the embodiment of the present disclosure, the package priority of each message is not fixed. The efficiency balancing module can be used to dynamically adjust the package priority of each message so that messages with a larger demand for sending within a certain period of time can be sent first, avoiding long-term blocking of messages with a large sending volume.

[0122] In the disclosed embodiment, for example, there are three types of messages that need to be grouped and sent: M2S req, H2D req, and H2D rsp. The efficiency balancing module can count the number of grouped messages for these three types of messages within a certain period of time, with the system setting the statistical duration to be N clock cycles. During the first statistical duration, the three messages are grouped according to the initial priority set by the system, with M2S req having the highest priority, H2D req having the second highest priority, and H2D rsp having the lowest priority. After N clock cycles, the efficiency balancing module calculates that the number of H2D req messages sent accounts for the largest proportion, indicating that the demand for H2D req messages to be sent was the highest during this period. Therefore, during the second statistical duration, the grouping priority of H2D req messages is adjusted to the highest, and a new round of grouping is performed. The message sending proportions continue to be counted in the new cycle, achieving a dynamic balance between the priorities of each message.

[0123] In the disclosed embodiment, according to the CXL protocol, each flit carries cyclic redundancy (CRC) information. Therefore, after packet assembly, a CRC calculation is performed on the flit to generate a CRC checksum. This calculated CRC checksum is then entered into the flit in the format specified by the CXL protocol and sent to the next-level module for subsequent processing.

[0124] The embodiments of the present disclosure include at least the following advantages:

[0125] 1. Unlike traditional enumeration methods, the disclosed embodiments utilize a dynamic, real-time computational approach to achieve group unpacking. This approach is applicable to all current flit combinations. Furthermore, when new flit formats evolve in the future, the computational parameters can be modified accordingly to accommodate these new formats, resulting in broad versatility and flexibility. Furthermore, the disclosed embodiments are described from the perspective of the host, but the disclosed embodiments are not limited to the host and are equally applicable to slave devices.

[0126] 2. The embodiment of the present disclosure provides a general and efficient CXL protocol link layer data parsing and packaging method. This method has low hardware circuit complexity and good scalability. In the context of the current CXL protocol that is still changing and evolving, it is of great significance and value.

[0127] The present disclosure also provides an electronic device 100, such as Figure 10Shown, including:

[0128] One or more processors 101;

[0129] a memory 102 storing one or more programs, which, when executed by the one or more processors, enables the one or more processors 101 to implement the message processing method of the CX 1 protocol link layer;

[0130] One or more input / output (I / O) interfaces 103 are connected between the processor 101 and the memory 102 and configured to implement information exchange between the processor 101 and the memory 102 .

[0131] An embodiment of the present disclosure further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the message processing method of the CXL protocol link layer is implemented.

[0132] The embodiment of the present disclosure also provides a computer program product, which includes a computer program. When the computer program is executed by a processor, it implements the message processing method of the CXL protocol link layer.

[0133] In the embodiments of the present disclosure, any embodiment of the aforementioned CXL protocol link layer message processing method is applicable to the electronic device, storage medium and program product embodiments, and will not be described one by one here.

[0134] Those skilled in the art will appreciate that all or some of the functional modules / units disclosed above may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0135] In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation.

[0136] Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit (CPU), a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As is well known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH) or other disk storage; compact disc (CD-ROM), digital versatile disc (DVD) or other optical disc storage; magnetic cassettes, tapes, disk storage or other magnetic storage; any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, as is well known to those skilled in the art, communication media typically embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0137] The present disclosure has disclosed example embodiments, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for purposes of limitation. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly indicated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A message processing method for a CXL protocol link layer, comprising: Obtain the link layer transmission unit flit transmission message of the link layer; Determine a message type included in a flit transmission message; the message type includes a first type message and / or a second type message; the first type message includes a message header and data; the second type message includes only a message header; In response to the flit transmission message including the first category message and the second category message, processing the first category message preferentially; The second-category messages are processed based on the processing result of the first-category messages.

2. The message processing method of the cxl protocol link layer according to claim 1, wherein: The message processing method is a message processing method in the message parsing process; The determining the message type included in the flit transmission message includes: Determine the slot type of the flit transmission message according to the message header of the flit transmission message; The message type included in the flit transmission message is determined based on the slot type.

3. The message processing method of the cxl protocol link layer according to claim 1, wherein: The message processing method is a message processing method in the message parsing process; The prioritizing processing of the first category of messages includes: determining a processing period of the first type of messages based on the bit width of the first type of messages; Extracting the data in each processing cycle based on the processing cycle, and determining a first data volume of the data parsed in each processing cycle; the first data volume of the data includes at least one of the following: a total amount of data corresponding to a message header of the first category of messages, an amount of newly generated data, an amount of remaining data, and an amount of data to be extracted from the current first category of messages; An end time and / or end position of parsing of the first type of messages is determined based on a first data volume of the data parsed during all the processing cycles.

4. The message processing method of the cxl protocol link layer according to claim 3, wherein: The prioritizing processing of the first type of messages further includes: In response to the message headers of the plurality of first-category messages being in the same slot, after preferentially parsing the message headers of the plurality of first-category messages, parsing the data of the plurality of first-category messages; aligning the parsed message headers of the plurality of first-category messages with the data of the plurality of first-category messages; The aligned data header and the data are used as the processed first-category message.

5. The message processing method of the cxl protocol link layer according to claim 3, wherein: The processing of the second-category message based on the processing result of the first-category message includes: After the end time and / or end position of the parsing of the first type of message, determining the subsequent sl ot type; In response to determining that the subsequent message type of the flit transmission message is the second-category message based on the subsequent slot type, the message header of the second-category message is directly output through the corresponding output channel.

6. The message processing method of the cxl protocol link layer according to claim 1, wherein: The message processing method is a message processing method in the message packaging process; The determining the message type included in the flit transmission message includes: Determining a receiving channel for the flit transmission message; the flit transmission message is sent through different channels based on different message types; The message type included in the flit transmission message is determined based on the message type corresponding to the receiving channel.

7. The message processing method of the cxl protocol link layer according to claim 1, wherein: The message processing method is a message processing method in the message packaging process; The prioritizing processing of the first category of messages includes: Reading a message header and data corresponding to the first type of message, and placing the data after the message header during packet assembly; as well as, Determine a second data volume of the data; the second data volume of the data includes: the total data volume and / or the remaining data volume; determine the end time and / or end position of the first type of message package based on the second data volume.

8. The message processing method of the cxl protocol link layer according to claim 7, wherein: The processing of the second-category message based on the processing result of the first-category message includes: The second category messages are grouped based on the end time and / or end position of the first category message grouping.

9. The message processing method of the cxl protocol link layer according to claim 1, wherein: The message processing method is a message processing method in the message packaging process; The method further comprises: Count the number of packets of each message type within the first preset time period; Determine the first target message type with the largest number among the number of packets; In the next round of packet grouping, the priority of the first target message type is increased; or, Counting the number of messages of each message type sent within the second preset time period; Determine the second target message type having the largest number among the number of sent messages; In the next round of packet grouping, the packet grouping priority of the second target message type is increased.

10. An electronic device comprising: one or more processors; A memory having one or more programs stored thereon, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the message processing method of the CXL protocol link layer according to any one of claims 1 to 9; One or more input / output (I / O) interfaces are connected between the processor and the memory and configured to implement information interaction between the processor and the memory.

11. A computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements the message processing method of the CX 1 protocol link layer according to any one of claims 1 to 9.

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