Event-driven fair arbitration reading method for silicon pixel detector

Abstract

The invention provides an event-driven fair arbitration read-out method for a silicon pixel detector, which comprises the following steps of: performing asynchronous reset and synchronous release processing on a reset signal through a pulse initialization circuit to generate an initial single pulse signal, transmitting bit by bit according to a pixel sequence to form a polling chain, triggering address decoding and data coding of the pixel under preset logic, and reading out the event-driven fair arbitration read-out data of the silicon pixel detector. Transmitting to the next hit pixel; the non-hit pixels are directly skipped; after the signal is transmitted to the last pixel, delaying a clock period, and re-transmitting the signal to the first pixel to form a closed-loop polling mechanism; a Valid signal is generated through logic and operation of a single pulse signal and a FLAG signal, a gating device is controlled to only output the address and data of a hit pixel, and output of a previous effective pixel is kept when the hit pixel is not hit; through the technical combination of pulse polling, closed-loop feedback and zero compression, collaborative optimization of fairness, efficiency and hardware complexity is realized on the hardware level, and a foundation is laid for large-scale application of the silicon pixel detector.

Description

Technical Field

[0001] The present invention relates to the technical field of nuclear electronics pixel detection, and in particular to an event-driven fair arbitration readout method for a silicon pixel detector. Background Art

[0002] Silicon pixel detectors, with their advantages of high spatial resolution, high count rate, and low power consumption, have become core detection devices in modern high-energy physics experiments. However, traditional readout methods face significant bottlenecks in fairness, efficiency, and hardware complexity in high-intensity environments.

[0003] Related technologies usually adopt rolling shutter readout, priority readout and token ring readout. Specifically, the rolling shutter readout method scans all pixels row by row or frame by frame, and reads data regardless of whether they are hit or not. However, this method has serious data redundancy, a long time, and is prone to distortion in high-speed motion scenes. It is more suitable for low-intensity, low-speed imaging scenes and has been gradually eliminated; the priority readout method presets the priority according to the pixel position (such as row, column or area priority), and high-priority pixels are read out first. However, when high-priority pixels continue to respond, low-priority pixels may be blocked for a long time, which cannot meet the full pixel coverage requirements under high-intensity beams, and requires complex priority arbitration logic, which increases the chip area and power consumption. It is more suitable for medium and low-intensity experiments with low fairness requirements; the token ring readout method circulates tokens between pixels, and pixels holding tokens can read data, but the token transmission path of this method is fixed, and the delay will increase when the pixel array scale is expanded. It is more suitable for medium-sized pixel arrays;

[0004] This shows that existing priority readout methods pursue efficiency at the expense of fairness, while token ring readout takes fairness into account but has limited efficiency. They cannot simultaneously meet the requirement of reading all hit pixels within a fixed period in high-current scenarios. Moreover, rolling shutter and token ring readouts do not achieve true zero compression, and a large amount of invalid data transmission leads to bandwidth waste and increased dead time. Priority arbitration logic and token passing circuits increase chip area and power consumption, limiting the integration of detectors.

[0005] Therefore, there is an urgent need in the art for an event-driven fair arbitration readout method for silicon pixel detectors to solve the above problems. Summary of the Invention

[0006] The present invention aims to provide an event-driven fair arbitration readout method for silicon pixel detectors. Through a technical combination of pulse polling, closed-loop feedback, and zero compression, it achieves coordinated optimization of fairness, efficiency, and hardware complexity at the hardware level, laying the foundation for the large-scale application of silicon pixel detectors.

[0007] In one aspect, the present invention provides an event-driven fair arbitration readout method for a silicon pixel detector, comprising the following steps:

[0008] Step 1: Perform asynchronous reset and synchronous release processing on the reset signal through the pulse initialization circuit to generate an initial single pulse signal and start the pixel readout process;

[0009] Step 2: The initial single pulse signal is used as the input signal of the first pixel, so that the single pulse signal is transmitted bit by bit in pixel order to form a patrol chain. When the pulse reaches a pixel and the FLAG signal of the pixel is high, the address decoding and data encoding of the pixel are triggered, and the pulse is transmitted to the next hit pixel; the pixels that are not hit are directly skipped;

[0010] Step 3: After the pulse reaches the last pixel, the feedback unit circuit delays the pulse by one clock cycle and retransmits it to the first pixel, forming a closed-loop patrol mechanism.

[0011] Step 4: Generate a Valid signal by performing a logical AND operation on the single pulse signal and the FLAG signal. The address decoding and data encoding circuits are used to control the gate to output only the address and data of the hit pixel. If the pixel is not hit, the output of the last valid pixel is maintained.

[0012] In another aspect, the present invention provides a computer device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the event-driven fair arbitration readout method for silicon pixel detectors.

[0013] On the other hand, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the above-mentioned event-driven fair arbitration readout method for silicon pixel detectors when executed by a processor.

[0014] Compared with the prior art, the present invention has the following advantages:

[0015] 1. This application implements event-driven fair arbitration readout. Through a pulse round-robin transmission mechanism, it eliminates pixel priority weights, allowing each hit pixel to be equally accessed in a closed-loop cycle. This solves the problem of low-priority pixels waiting for a long time when high-priority pixels respond multiple times in existing methods, and is compatible with applications under high- and low-intensity beam flows.

[0016] 2. This application implements zero data compression, reading only the address and data of the hit pixel and directly skipping the unhit pixels, thus reducing the readout dead time and data volume and improving data transmission efficiency.

[0017] 3. The hardware structure of this application is relatively simple. Through the design of pulse generation and transmission circuits, address decoding and data encoding circuits, the circuit complexity and cost are reduced while ensuring functionality.

[0018] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the written description and the accompanying drawings.

[0019] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings are used to provide further understanding of the present invention and constitute a part of the specification. They are used to explain the present invention together with the embodiments of the present invention and do not constitute a limitation of the present invention.

[0021] In the attached figure:

[0022] Figure 1 This is a flow chart of an event-driven fair arbitration readout method for a silicon pixel detector provided by the present invention;

[0023] Figure 2 This is a timing diagram of a pulse generation and transmission circuit provided in Example 1 of the present invention;

[0024] Figure 3 This is a timing diagram of the data encoding and address decoding circuit provided in Example 1 of the present invention;

[0025] Figure 4 This is a structural diagram of a computer device provided in Example 2 of the present invention. DETAILED DESCRIPTION

[0026] The preferred embodiments of the present invention are described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0027] Example 1:

[0028] Please refer to Figure 1-3 An embodiment of the present invention provides an event-driven fair arbitration readout method for a silicon pixel detector, comprising the following steps:

[0029] Step 1: Perform asynchronous reset and synchronous release processing on the reset signal through the pulse initialization circuit to generate an initial single pulse signal Pulse_start and start the pixel readout process;

[0030] Among them, the pulse initialization circuit includes an asynchronous reset synchronous release unit composed of two-stage triggers. The reset signal Rst_n generates a delayed reset signal Sync_rst after synchronous release, and then generates an initial single pulse signal Pulse_start with a width of one clock cycle through a logical AND operation.

[0031] Specifically, the reset signal Rst_n passes through an asynchronous reset synchronous release circuit composed of two flip-flops to output a reset signal Sync_rst. Sync_rst passes through the next-level flip-flop to output the signal Sync_rst_dly. After the Sync_rst_dly signal passes through a NOT gate, it performs an AND logic operation with the signal Sync_rst, thereby generating an initialization single pulse signal Pulse_start.

[0032] Step 2: The initial single pulse signal Pulse_start is used as the input signal Pulse_in[0] of the first pixel, so that the single pulse signal Pulse_in is transmitted bit by bit in pixel order to form a patrol chain. When the pulse reaches a pixel and the FLAG signal (Hit Flag Signal) of the pixel is high, the address decoding and data encoding of the pixel are triggered, and the pulse is passed to the next hit pixel; the unhit pixels are directly skipped;

[0033] The pulse transfer logic is as follows: when the pixel's FLAG signal is high and the single pulse signal Pulse_in is low, the output pulse signal Pulse_out is set high and maintained for one clock cycle, triggering the pixel readout and then transferring the pulse to the next pixel's single pulse signal Pulse_in. When multiple pixels are triggered, the round-robin transfer mechanism reads out the address and data of each triggered pixel in the order of pulse transfer. This readout order is determined by the pulse transfer path and is independent of the pixel position priority.

[0034] Specifically, in order to achieve event-driven readout and fair arbitration at the same time, the module needs to set Pulse_out to a high level when the pixel Flag is high and Pulse_in is low, and when the next clock arrives, set Pulse_out to a low level and maintain it for one clock length. In other cases, Pulse_out is equal to Pulse_in.

[0035] Step 3: After the pulse reaches the last pixel, the feedback unit circuit delays the pulse by one clock cycle and retransmits it to the first pixel, forming a closed-loop patrol mechanism.

[0036] The feedback unit circuit delays the last pixel's output pulse signal, Pulse_out, through two stages of triggers, performs a logical AND operation on the initial single pulse signal, Pulse_start, and then feeds it back to the first pixel's input signal, Pulse_in[0], after a delay of one clock cycle. The closed-loop patrol mechanism's cycle is the product of the total number of pixels hit and the processing time of a single pixel, ensuring that each pixel is visited equally in the loop.

[0037] Specifically, the signal Pulse_out[n] passes through two levels of triggers and performs logic AND with the initialized single pulse signal before being passed to Pulse_in[0]. This implements the function of waiting for one clock cycle after the single pulse signal is passed to the last pixel n and then passing the single pulse signal to pixel 0 again.

[0038] In one embodiment, Figure 2 As shown, clk is the clock signal, Rst_n is the reset signal, sync_rst is the global reset signal, sync_rst_dly is the delayed reset signal, Pulse_start is the initial single pulse signal, Flag[3:0] is the hit flag signal, and Pulse_in[0] to Pulse_in[3] are single pulse input signals; this embodiment shows the working timing of the pulse generation and transfer circuit of 4 pixels, the reset signal Rst_n is valid at a low level, and the global reset signal sync_rst signal is output after passing through the asynchronous reset synchronous release circuit. After the reset signal is released, sync_rst generates the initial single pulse signal Pulse_start, and the single pulse signal Pulse_in[0] is initialized at the same time. Due to the hit flag signal Flag[3:0] are both low, so the single pulse signal is transferred from Pulse_in[0] to Pulse_in[3] within one clock cycle, and then transferred back to Pulse_in[0] after waiting for one clock cycle, and so on; when Flag[0] and Flag[1] of the 0th and 1st pixels are set to high at the same time, the 0th pixel waits for the single pulse signal, Pulse_in[0] is pulled low while Pulse_in[3:1] is pulled high, and after the next clock rising edge arrives, Pulse_in[1] is pulled low and lasts for one clock length; at this time, Flag[1] is effectively high, so after the next clock rising edge arrives, Pulse_in[2] is pulled low and lasts for one clock length; this avoids the situation where the same pixel responds continuously;

[0039] Reference Figure 2Each signal in the circuit is synchronized by a clock, forming a timing chain of "reset → pulse initialization → patrol transmission → hit trigger → closed-loop feedback". This can intuitively demonstrate how the pulse generation and transmission circuit interacts with the Pulse_in and Flag signals to achieve event-driven and fair arbitration readout, avoid continuous response of the same pixel, and ensure that each hit pixel is read out in sequence.

[0040] Step 4: Generate a Valid signal (ValidControl Signal) by performing a logical AND operation on the single pulse signal and the FLAG signal. The address decoding and data encoding circuits are used to control the gate to output only the address and data of the hit pixel. If the pixel is not hit, the output of the previous valid pixel is maintained.

[0041] In step 4, the address decoding and data encoding circuit includes n+1 selectors, n+1 AND gates, and flip-flops. The Valid signal selects the address and data lines of the corresponding pixels, enabling zero-compression readout of the information of unaffected pixels. When the Valid signal is inactive, the address decoding and data encoding circuit maintains the address and data output of the last valid pixel.

[0042] Specifically, the main function of the address decoding and data encoding circuit is to implement pixel address decoding and data encoding under the control of a single pulse signal. Both the data encoding and address encoding circuits are composed of two n+1-way selection circuits, n+1 AND logic gates, and a trigger. The single pulse signal Pulse_in[n:0] passes through an inverter and is bitwise ANDed with the Flag[n:0] signal to output Valid[n:0]. This signal serves as the control signal for address decoding and data encoding to control the address and data readout of the corresponding pixel. When any bit in valid[n:0] is high, the address and data information of the corresponding pixel is output after the next clock rising edge. When Valid[n:0] is low, the address and data information of the previous valid pixel are kept output.

[0043] In one embodiment, please refer to Figure 3 , where token_in[0] to token_in[3] are single pulse input signals, namely Pulse_in[0] to Pulse_in[3], indicating whether the pulse reaches the corresponding pixel. Data is the data bus output, reflecting the data value of the currently selected pixel in real time; Data[0], Data[1], and Data[3] are the specific data values ​​when pixels 0, 1, and 3 are hit, respectively (in the example, pixel 2 is not hit, and no Data[2] is output). Addr is the address signal;

[0044] This embodiment also takes the data encoding and address decoding circuit of four pixels as an example. When no pixel detector is hit, Flag[3:0] are all low level, and the single pulse signal is transmitted from Pulse_in[0] to Pulse_in[3] in sequence within one clock cycle, and then returns to Pulse_in[0] after waiting for one clock cycle, and the cycle is executed. When pixels 0, 1, and 3 are hit, Flag[0], Flag[1], and Flag[3] are set to high level, and pixel 0 waits for the single pulse signal, and Pulse_in[0] is low level. After the next clock rising edge arrives, the address information 00 and data information Data[0] of pixel 0 are output, and the single pulse signal is passed to Pulse_in[1]. After the next clock rising edge arrives, the address information 01 and data information Data[1] of pixel 1 are output, and the single pulse signal is passed to Pulse_in[2]. Since pixel 2 is not hit, Flag[2] is low level, skipping this pixel, and passing the single pulse signal to Pulse_in[3], achieving data zero compression. After the next clock rising edge arrives, the address information 11 and data information Data[3] of pixel 3 are output. Since no pixel is hit afterwards, the address and data information of the last hit pixel 3 are kept output.

[0045] Reference Figure 3 In the no-hit state, Flag[3:0] are all low, token_in signals are pulled low in sequence but do not trigger readout, and Data and Addr maintain the output of the last valid pixel (if it has never been hit, it remains in the initial state). In the hit state (pixels 0, 1, and 3 are hit), Pulse_in[0] is pulled low and Flag[0] is high, and the rising edge of the clock outputs Addr=00 and Data=Data[0]; Pulse_in[1] is pulled low and Flag[1] is high, and the next rising edge of the clock outputs Addr=01 and Data=Data[1]; Pulse_in[2] is pulled low but Flag[2] is low, skipping pixel 2, and Pulse_in[0] is passed to Pulse_in[3]; Pulse_in[3] is pulled low and Flag[3] is high, and the next rising edge of the clock outputs Addr=11 and Data=Data[3]; after all hit pixels are read out, Data and Addr maintain the output of pixel 3 until a new hit event occurs.

[0046] Each signal is synchronized through a clock, demonstrating how the data encoding and address decoding circuit uses the Pulse_in and Flag signals to generate the Valid control signal, realizing the address and data selection output of the hit pixel, and skipping the unhit pixels through the "zero compression" mechanism. At the same time, when there is no new hit event, the previous valid data is maintained, ensuring efficient and accurate data transmission.

[0047] Example 2:

[0048] In an exemplary embodiment, a computer device is provided. The computer device may be a server or a terminal. The internal structure diagram thereof may be as follows: Figure 4 As shown. The computer device includes a processor, a memory, an input / output interface (Input / Output, abbreviated as I / O) and a communication interface. The processor, memory and input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and computer program in the non-volatile storage medium. The database of the computer device is used to store vertical observation data. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a greenhouse gas source analysis method is implemented.

[0049] Those skilled in the art will understand that Figure 4 The structure shown in the figure is merely a block diagram of a portion of the structure related to the solution of the present invention and does not constitute a limitation on the computer device to which the solution of the present invention is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0050] In an exemplary embodiment, a computer device is further provided, including a memory and a processor. The memory stores a computer program, and the processor implements the above method embodiments when executing the computer program.

[0051] In an exemplary embodiment, a computer-readable storage medium is provided, storing a computer program, which implements the above-mentioned method embodiments when executed by a processor.

[0052] In an exemplary embodiment, a computer program product is provided, including a computer program. When the computer program is executed by a processor, the above method embodiments are implemented.

[0053] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in the present invention are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0054] Those skilled in the art will appreciate that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, database or other media used in the embodiments provided by the present invention can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM may be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM).

[0055] The database involved in each embodiment provided by the present invention may include at least one of a relational database and a non-relational database. Non-relational databases may include, but are not limited to, distributed databases based on blockchain. The processor involved in each embodiment provided by the present invention may be, but is not limited to, a general-purpose processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic unit, a data processing logic unit based on quantum computing, etc.

[0056] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. An event-driven fair arbitration readout method for a silicon pixel detector, characterized in that: The following steps are involved: Step 1: Perform asynchronous reset and synchronous release processing on the reset signal through the pulse initialization circuit to generate an initial single pulse signal and start the pixel readout process; Step 2: The initial single pulse signal is used as the input signal of the first pixel, so that the single pulse signal is transmitted bit by bit in pixel order to form a patrol chain. When the pulse reaches a pixel and the FLAG signal of the pixel is high, the address decoding and data encoding of the pixel are triggered, and the pulse is transmitted to the next hit pixel; the pixels that are not hit are directly skipped; Step 3: After the pulse reaches the last pixel, the feedback unit circuit delays the pulse by one clock cycle and retransmits it to the first pixel, forming a closed-loop patrol mechanism. Step 4: Generate a Valid signal by performing a logical AND operation on the single pulse signal and the FLAG signal. The address decoding and data encoding circuits are used to control the gate to output only the address and data of the hit pixel. If the pixel is not hit, the output of the last valid pixel is maintained.

2. The event-driven fair arbitration readout method for a silicon pixel detector according to claim 1, characterized in that: In step one, the pulse initialization circuit includes an asynchronous reset synchronous release unit composed of two-stage triggers. After the reset signal is synchronously released, a delayed reset signal is generated, and then the initial single pulse signal with a width of one clock cycle is generated through a logic AND operation.

3. The event-driven fair arbitration readout method for a silicon pixel detector according to claim 1, characterized in that: In step 2, the logic of the pulse transmission is: When the pixel FLAG signal is high and the single pulse signal is low, the output pulse signal is set to high and maintained for one clock cycle, triggering the pixel to read out and then passing the pulse to the single pulse signal end of the next pixel.

4. The event-driven fair arbitration readout method for a silicon pixel detector according to claim 1, characterized in that: In step three, the feedback unit circuit delays the output pulse signal of the last pixel through two-stage triggers, performs a logic AND operation on the initial single pulse signal, and feeds back the signal to the input signal terminal of the first pixel after a delay of one clock cycle.

5. The event-driven fair arbitration readout method for a silicon pixel detector according to claim 1, wherein: In step 4, the address decoding and data encoding circuit includes n+1 selectors, n+1 AND gates and triggers, and selects the address line and data line of the corresponding pixel through the Valid signal to achieve zero compression readout of the unhit pixel information.

6. The event-driven fair arbitration readout method for a silicon pixel detector according to claim 3, characterized in that: In step 2, when multiple pixels are hit, the round-robin transmission mechanism reads out the address and data of each hit pixel in sequence according to the pulse transmission order. The readout order is determined by the pulse transmission path and has nothing to do with the priority of the pixel position.

7. The event-driven fair arbitration readout method for a silicon pixel detector according to claim 5, characterized in that: In step 4, when the Valid signal is invalid, the address decoding and data encoding circuit maintains the address and data output of the last valid pixel.

8. The event-driven fair arbitration readout method for a silicon pixel detector according to claim 1, characterized in that: In step three, the cycle of the closed-loop patrol mechanism is the product of the total number of hit pixels and the processing time of a single pixel, so as to ensure that each pixel is visited equally in the cycle.

9. A computer device comprising: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the event-driven fair arbitration readout method for a silicon pixel detector according to any one of claims 1 to 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the event-driven fair arbitration readout method for a silicon pixel detector according to any one of claims 1 to 8 is implemented.

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