Phase change memory

Abstract

The invention relates to a phase change memory, the phase change memory comprises a plurality of memory unit groups arranged at intervals, and each memory unit group comprises at least one first memory unit and at least one second memory unit which are alternately stacked along a first direction; the first storage unit comprises a first gate layer and a first storage layer which are sequentially stacked in the first direction, and the second storage unit comprises a second storage layer and a second gate layer which are sequentially stacked in the first direction; or, the first storage unit comprises a first storage layer and a first gate layer which are sequentially stacked in the first direction, and the second storage unit comprises a second gate layer and a second storage layer which are sequentially stacked in the first direction. Through the film layers symmetrically arranged between the adjacent storage units, the operation polarity difference introduced by the film layer stacking difference is eliminated, the difficulty of circuit design is reduced, and the consistency of multi-layer storage of the phase change memory is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a phase change memory. Background Art

[0002] The development of artificial intelligence and integrated storage and computing technologies has placed higher demands on data storage and computing capabilities. In the current von Neumann computing architecture, large amounts of data must be read and stored between dynamic random access memory (DRAM) and solid-state drives (SSDs). This significant performance gap between the two has led to a performance bottleneck in the current von Neumann computing system. Currently, the use of storage-class memory (SCM) to bridge DRAM and SSDs is being proposed to improve the current storage architecture. Among the emerging storage-class memories, phase-change memory is the most mature, with three-dimensional phase-change memory showing the greatest promise, offering advantages such as large capacity, high speed, non-volatility, and excellent cycle performance.

[0003] In a phase-change memory with multiple layers of stacked memory cells, the shared conductors are word lines or bit lines. Current entering from these lines flows from opposite directions into the memory cells above and below. In traditional three-dimensional stacked structures, all memory cells use the same film stack to improve process transferability. The combination of direction and film asymmetry results in polarity differences in the operation of adjacent memory cells. This polarity difference between different memory cells has a direct impact on the consistency of the memory array, significantly increasing the difficulty of process and circuit design. Summary of the Invention

[0004] The embodiments of the present application provide a phase change memory that can eliminate polarity differences between adjacent memory cells, thereby reducing differences in threshold voltages of the memory cells and lowering the difficulty of process design and circuit design.

[0005] An embodiment of the present application provides a phase change memory, comprising: a plurality of memory cell groups arranged at intervals, each of the memory cell groups comprising at least one first memory cell and at least one second memory cell alternately stacked along a first direction; the first memory cell comprising a first selection layer and a first storage layer stacked in sequence along the first direction, and the second memory cell comprising a second storage layer and a second selection layer stacked in sequence along the first direction; or, the first memory cell comprising a first storage layer and a first selection layer stacked in sequence along the first direction, and the second memory cell comprising a second selection layer and a second storage layer stacked in sequence along the first direction.

[0006] In some embodiments, the first gate layer has a first threshold voltage, the second gate layer has a second threshold voltage, and a difference between the first threshold voltage and the second threshold voltage is between 0V and 0.5V.

[0007] In some embodiments, a critical dimension of the first memory cell is different from a critical dimension of the second memory cell.

[0008] In some embodiments, the critical dimensions of the first memory cell and the second memory cell are both in the range of 10 nm to 30 nm, and the ratio of the critical dimensions of the first memory cell to the critical dimensions of the second memory cell is in the range of 0.8 to 1.2.

[0009] In some embodiments, in the first direction, a thickness of the first gating layer is different from a thickness of the second gating layer; and / or a thickness of the first storage layer is different from a thickness of the second storage layer.

[0010] In some embodiments, a ratio of a thickness of the first memory unit to a thickness of the second memory unit is in a range of 0.8 to 1.2.

[0011] In some embodiments, the thickness of the first gating layer and the thickness of the second gating layer are both in the range of 10 nm to 30 nm.

[0012] In some embodiments, a material of the first gating layer is different from a material of the second gating layer; and / or a material of the first storage layer is different from a material of the second storage layer.

[0013] In some embodiments, the material of the first gating layer includes a first matrix material, the material of the second gating layer includes a second matrix material, and the first matrix material has the same elemental composition as the second matrix material but has a different content of at least one element.

[0014] In some embodiments, the material of the first storage layer includes a third matrix material, the material of the second storage layer includes a fourth matrix material, and the third matrix material includes elements having the same elemental composition as the fourth matrix material but having a different content of at least one element.

[0015] In the phase-change memory of the embodiment of the present application, because the first direction and the second direction are opposite, the gating layer and the storage layer in two adjacent memory cells in the present application are mirror-symmetric. For the first and second memory cells with symmetrical film layers, that is, when an electrical signal flows from the first conductive line to the second conductive line on the side of the first memory cell, it passes through the first gating layer and the first storage layer in sequence, and when the electrical signal flows from the first conductive line to the second conductive line on the side of the second memory cell, it passes through the second gating layer and the second storage layer in sequence. By symmetrically arranging the film layers between adjacent memory cells, the difference in operating polarity introduced by differences in film layer stacking is eliminated, the difficulty of circuit design is reduced, and the consistency of multi-layer storage of the phase-change memory is improved.

[0016] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] To more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. Those skilled in the art can also derive other drawings based on these drawings without inventive effort.

[0018] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same drawing numbers represent the same parts in the following description.

[0019] Figure 1 It is a schematic diagram of the cross-sectional structure of a phase change memory;

[0020] Figure 2 1 is a schematic cross-sectional structural diagram of several memory cell groups in a phase change memory provided by an embodiment of the present application;

[0021] Figure 3 yes Figure 2 A schematic cross-sectional structure diagram of any storage unit group;

[0022] Figure 4 1 is a schematic cross-sectional structural diagram of several memory cell groups in a phase change memory provided by an embodiment of the present application;

[0023] Figure 5 yes Figure 4 A schematic cross-sectional structure diagram of any storage unit group;

[0024] Figure 6 1 is a schematic cross-sectional structural diagram of several memory cell groups in a phase change memory provided by an embodiment of the present application;

[0025] Figure 7 yes Figure 6A schematic cross-sectional structure diagram of any storage unit group;

[0026] Figure 8 1 is a schematic cross-sectional structural diagram of several memory cell groups in a phase change memory provided by an embodiment of the present application;

[0027] Figure 9 1 is a schematic diagram of the cross-sectional structure of several storage unit groups in a memory provided by an embodiment of the present application;

[0028] Figure 10 yes Figure 9 A schematic cross-sectional structure diagram of any storage unit group;

[0029] Figure 11 1 is a schematic diagram of the cross-sectional structure of several storage unit groups in a memory provided by an embodiment of the present application;

[0030] Figure 12 yes Figure 11 A schematic cross-sectional structure diagram of any storage unit group;

[0031] Figure 13 1 is a schematic diagram of the cross-sectional structure of several storage unit groups in a memory provided by an embodiment of the present application;

[0032] Figure 14 yes Figure 13 A schematic cross-sectional structure diagram of any storage unit group;

[0033] Figure 15 1 is a schematic diagram of the cross-sectional structure of several storage unit groups in a memory provided by an embodiment of the present application;

[0034] Figure 16 yes Figure 15 A schematic diagram of the cross-sectional structure of any storage unit group.

[0035] Reference numerals:

[0036] 10-phase change memory; 300-memory cell group; 310-first memory cell; 320-second memory cell; 100-first conductive line; 200-second conductive line; 110-first adhesion layer; 120-second adhesion layer; 210-third adhesion layer; 220-fourth adhesion layer; Z1-first direction; Z2-second direction; X-third direction; BE1-first bottom electrode; OTS1-first selection layer; ME1-first intermediate electrode; TE1-first top electrode; PCM1-first storage layer; BE2-second bottom electrode; OTS2-second selection layer; ME2-second intermediate electrode; TE2-second top electrode; PCM2-second storage layer. DETAILED DESCRIPTION

[0037] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0038] Figure 1 This is a schematic cross-sectional view of a phase-change memory device. Taking a three-dimensional phase-change memory device in which each memory cell group 300' comprises two stacked layers of memory cells as an example, the upper and lower layers of memory cells are separated by a common first conductive line 100'. A second conductive line 200' is provided on the side of the upper memory cell C2 away from the first conductive line 100', and a second conductive line 200' is provided on the side of the lower memory cell C1 away from the first conductive line 100'. The lower memory cell C1 includes a first bottom electrode BE1', a first selection layer OTS1', a first middle electrode ME1', a first storage layer PCM1', and a first top electrode TE1', which are sequentially stacked on the second conductive line 200'. The upper memory cell C2 includes a second bottom electrode BE2', a second selection layer OTS2', a second middle electrode ME2', a second storage layer PCM2', and a second top electrode TE2', which are sequentially stacked on the first conductive line 100'. The material of the first selection layer OTS1 ′ is the same as the material of the second selection layer OTS2 ′. The same material means that the element composition and element concentration are the same.

[0039] It should be noted that each memory cell has a SET state threshold voltage and a RESET state threshold voltage. In each memory cell, the gating layer has an on-state threshold voltage, and the storage layer has a low-resistance state threshold voltage and a high-resistance state threshold voltage. Taking the lower-layer memory cell C1 as an example, a voltage signal is applied to the first conductive line and the second conductive line electrically connected to the first memory cell. When the voltage divided by the two sides of the first gating layer (the first bottom electrode and the first middle electrode) is greater than the on-state threshold voltage, the first gating layer is in the on-state, and the first storage layer is still in the low-resistance state (i.e., the SET state). When the voltage signal is increased, when the voltage divided by the two sides of the first storage layer (the first middle electrode and the first top electrode) is greater than the high-resistance threshold voltage, the first storage layer is in the high-resistance state (i.e., the RESET state). Therefore, the on-state threshold voltage of the first gating layer is the SET state threshold voltage of the first memory cell, and the high-resistance state threshold voltage of the first storage layer is the RESET state threshold voltage of the first memory cell. In other words, adjusting the threshold voltage of the gating layer is equivalent to adjusting the on-state threshold voltage of the memory cell. Matching the threshold voltages of the gating layers means matching the SET state threshold voltages of the memory cells.

[0040] It is understandable that the function of the gating layer is to facilitate correct addressing and reduce misreading, miswriting, and leakage current. The gating layer has a threshold switching characteristic. When the voltage applied on both sides of the gating layer is higher than its threshold voltage, it is converted to a low-resistance state (i.e., on state). When the voltage applied on both sides of the gating layer is lower than its threshold voltage, it is converted to a high-resistance state (i.e., off state). This allows the current to be conducted and blocked, thus achieving the addressing function.

[0041] In the pair Figure 1 When conducting an electrical test on the threshold voltages of the first selection layer OTS1' and the second selection layer OTS2', a high-level signal is applied to the first conductive line 100', and a low-level signal is applied to the second conductive line 200' on the upper memory cell C2 or the lower memory cell C1. When a low-level signal is applied to the second conductive line 200' on the upper memory cell C2, the current flows from the first conductive line 100' to the second conductive line 200' on the upper memory cell C2. When a low-level signal is applied to the second conductive line 200' on the lower memory cell C1, the current flows from the first conductive line 100' to the second conductive line 200' on the lower memory cell C1. This means that the two layers of memory cells share a high-level electrical signal, but the electrical signal is applied in opposite directions. The stacking directions of the upper and lower layers of memory cells are consistent, but the electrical signal is applied in opposite directions. This results in significant polarity differences when operating the adjacent upper and lower memory cells, leading to differences in threshold voltage. The threshold voltage of the upper memory cell C2 differs by 100mV to 200mV from that of the lower memory cell C1. This means that the threshold voltage of the second selection layer OTS2' differs by 100mV to 200mV from that of the first selection layer OTS1'. This difference in threshold voltages directly impacts the consistency of the memory array, significantly increasing the difficulty of process and circuit design, complicating electrical signal design, and reducing device reliability.

[0042] Therefore, an embodiment of the present application provides a phase change memory, which includes: a plurality of memory cell groups arranged at intervals, each memory cell group including at least one first memory cell and at least one second memory cell alternately stacked along a first direction; the first memory cell includes a first selection layer and a first storage layer stacked in sequence along the first direction, and the second memory cell includes a second storage layer and a second selection layer stacked in sequence along the first direction; or, the first memory cell includes a first storage layer and a first selection layer stacked in sequence along the first direction, and the second memory cell includes a second selection layer and a second storage layer stacked in sequence along the first direction.

[0043] Because the first direction and the second direction are opposite, the gating layer and the storage layer in two adjacent memory cells in the present application are mirror-symmetric. For the first memory cell and the second memory cell with symmetrical film layers, that is, when the electrical signal flows from the first conductive line to the second conductive line on the side of the first memory cell, it passes through the first gating layer and the first storage layer in sequence, and when the electrical signal flows from the first conductive line to the second conductive line on the side of the second memory cell, it passes through the second gating layer and the second storage layer in sequence. By symmetrically arranging the film layers between adjacent memory cells, the difference in operating polarity introduced by the difference in film layer stacking is eliminated, the difficulty of circuit design is reduced, and the consistency of multi-layer storage of the phase change memory is improved.

[0044] The following describes the structure of the phase change memory 10 provided by some embodiments of the present application in conjunction with the accompanying drawings. Figure 2 and Figure 3 , Figure 2 1 is a schematic cross-sectional view of a plurality of memory cell groups 300 in a phase change memory 10 provided in an embodiment of the present application. The phase change memory 10 may include a plurality of memory cell groups 300, and the plurality of memory cell groups 300 are arranged along a third direction X. Figure 2 In the illustrated embodiment, each memory cell group 300 includes a first memory cell 310 and a second memory cell 320 stacked along a first direction Z1. The first memory cell 310 includes a first gate layer OTS1 and a first memory layer PCM1 stacked along the first direction Z1. The second memory cell 320 includes a second gate layer OTS2 and a second memory layer PCM2 stacked along a second direction Z2, which is opposite to the first direction Z1.

[0045] exist Figure 2 In the illustrated embodiment, it can be seen that the critical dimension of the first memory cell 310 is the same as the critical dimension of the second memory cell 320. The critical dimension refers to the physical size of the space occupied by a single phase-change memory cell on a chip, including the width of film layers such as the memory layer and the gate layer in the third direction X, as well as the spacing between them.

[0046] exist Figure 2 In the illustrated embodiment, the thickness of the first selection layer OTS1 is the same as the thickness of the second selection layer OTS2. The thickness of the first storage layer PCM1 is the same as the thickness of the second storage layer PCM2. The thickness of the storage layer or selection layer refers to the thickness of the storage layer or selection layer in the first direction. The thickness of the storage layer and the selection layer will affect the performance of the memory. Maintaining the same thickness of the film layers in the first storage cell 310 and the second storage cell 320 can maintain the consistency of the phase change memory 10 and improve the performance of the phase change memory 10.

[0047] In some embodiments, the material of the first gate layer OTS1 is the same as the material of the second gate layer OTS2. The material of the first storage layer PCM1 is the same as the material of the second storage layer PCM2. The same storage layer and gate layer materials ensure a uniform manufacturing process when fabricating different memory cell layers. This eliminates the need to adjust process parameters for different materials, reduces the complexity and difficulty of process adjustments, and improves process adaptability.

[0048] Figure 3 yes Figure 2 A schematic cross-sectional view of the structure of any one of the storage unit groups 300 is provided. Figure 3 In the illustrated embodiment, the memory cell group 300 includes a first memory cell 310 and a second memory cell 320 stacked along a first direction Z1. The first memory cell 310 includes a first bottom electrode BE1, a first gate layer OTS1, a first intermediate electrode ME1, a first storage layer PCM1, and a first top electrode TE1 stacked along the first direction Z1. The second memory cell 320 includes a second bottom electrode BE2, a second gate layer OTS2, a second intermediate electrode ME2, a second storage layer PCM2, and a second top electrode TE2 stacked along a second direction Z2. Figure 3 As shown, the first intermediate electrode ME1 is located between the first gate layer OTS1 and the first storage layer PCM1, the first bottom electrode BE1 is located on a side of the first gate layer OTS1 away from the first intermediate electrode ME1, and the first top electrode TE1 is located on a side of the first storage layer PCM1 away from the first intermediate electrode ME1. The second intermediate electrode ME2 is located between the second gate layer OTS2 and the second storage layer PCM2, the second bottom electrode BE2 is located on a side of the second gate layer OTS2 away from the second intermediate electrode ME2, and the second top electrode TE2 is located on a side of the second storage layer PCM2 away from the second intermediate electrode ME2.

[0049] In some embodiments, each conductive wire may be in direct contact with the electrode to which it is electrically connected, or an adhesive layer may be provided between the conductive wire and the electrode to which it is electrically connected to improve adhesion. Figure 3 In the illustrated embodiment, the first memory cell 310 further includes a first adhesion layer 110 and a second adhesion layer 120. The first adhesion layer 110 is disposed between the first top electrode TE1 and the first memory layer PCM1, and the second adhesion layer 120 is disposed between the first memory layer PCM1 and the first middle electrode ME1. The second memory cell 320 further includes a third adhesion layer 210 and a fourth adhesion layer 220. The third adhesion layer 210 is disposed between the second top electrode TE2 and the second memory layer PCM2, and the fourth adhesion layer 220 is disposed between the second memory layer PCM2 and the second middle electrode ME2. Figure 3Also shown is a first conductive line 100 and two second conductive lines 200. The first conductive line 100 is located between the first memory cell 310 and the second memory cell 320. The film layer distribution in the first memory cell 310 and the second memory cell 320 is mirror-symmetrical around the first conductive line 100. The first conductive line 100 is electrically connected to both the first top electrode TE1 and the second top electrode TE2, that is, the first conductive line 100 is electrically connected to both the first memory cell 310 and the second memory cell 320. The two second conductive lines 200 are electrically connected to the first memory cell 310 and the second memory cell 320, respectively. Electrical signals are applied to the electrodes via the conductive lines or sub-conductive lines. When the voltage signal applied between the different electrodes reaches the threshold voltage, the switching state of the gating layer and the high and low resistance states of the storage layer are changed.

[0050] In an embodiment of the present application, the first selection layer OTS1 has a first threshold voltage, the second selection layer OTS2 has a second threshold voltage, and the difference between the first threshold voltage and the second threshold voltage is within a preset range. For example, the preset range can be 0V to 0.5V. When the preset range is extremely small, it can be considered that the difference between the first threshold voltage and the second threshold voltage is very small, that is, the first threshold voltage and the second threshold voltage are substantially the same, so that the first storage unit 310 and the second storage unit 320 can be successfully operated using the same electrical signal. As can be seen from the substantially identical threshold voltages, the phase change memory 10 provided by the present application eliminates the difference in operating polarity caused by the asymmetric film layer stacking between different storage cells, reduces the difficulty of circuit design, and improves the consistency of multi-layer storage in the phase change memory 10. In addition, since the adjustment of the threshold voltage does not require changing the material of the storage layer or the phase change layer, the same film layer material can improve the adaptability of the process in manufacturing.

[0051] In some embodiments, the memory cell group 300 may be disposed on a substrate, which may be silicon (Si), germanium (Ge), a SiGe substrate, a silicon on insulator (SOI), or a germanium on insulator (GOI).

[0052] Please refer to Figure 4 and Figure 5 , Figure 4 is a schematic cross-sectional structural diagram of several memory cell groups 300 in a phase change memory 10 provided in one embodiment of the present application. Figure 5 yes Figure 4 A schematic cross-sectional view of the structure of any one of the storage unit groups 300. Figure 4In the illustrated embodiment, each memory cell group 300 includes a first memory cell 310 and a second memory cell 320 stacked along a second direction Z2. The first memory cell 310 includes a first gate layer OTS1 and a first memory layer PCM1 stacked along the first direction Z1. The second memory cell 320 includes a second gate layer OTS2 and a second memory layer PCM2 stacked along the second direction Z2, which is opposite to the first direction Z1.

[0053] Figure 5 yes Figure 4 A schematic cross-sectional view of the structure of any one of the storage unit groups 300 is provided. Figure 5 In the illustrated embodiment, the memory cell group 300 includes a first memory cell 310 and a second memory cell 320 stacked along a second direction Z2. The first memory cell 310 includes a first bottom electrode BE1, a first gate layer OTS1, a first intermediate electrode ME1, a first memory layer PCM1, and a first top electrode TE1, stacked along the first direction Z1. The second memory cell 320 includes a second bottom electrode BE2, a second gate layer OTS2, a second intermediate electrode ME2, a second memory layer PCM2, and a second top electrode TE2, stacked along the second direction Z2. The first memory cell 310 also includes a first adhesion layer 110 and a second adhesion layer 120. The first adhesion layer 110 is disposed between the first top electrode TE1 and the first memory layer PCM1, and the second adhesion layer 120 is disposed between the first memory layer PCM1 and the first intermediate electrode ME1. The second memory cell 320 further includes a third adhesive layer 210 and a fourth adhesive layer 220 . The third adhesive layer 210 is disposed between the second top electrode TE2 and the second memory layer PCM2 . The fourth adhesive layer 220 is disposed between the second memory layer PCM2 and the second middle electrode ME2 . Figure 5 Also shown is a first conductive line 100 and two second conductive lines 200. The first conductive line 100 is located between the first memory cell 310 and the second memory cell 320. The film layer distribution in the first memory cell 310 and the second memory cell 320 is mirror-symmetrical around the first conductive line 100. The first conductive line 100 is electrically connected to both the first top electrode TE1 and the second top electrode TE2, that is, the first conductive line 100 is electrically connected to both the first memory cell 310 and the second memory cell 320. The two second conductive lines 200 are electrically connected to the first memory cell 310 and the second memory cell 320, respectively. Electrical signals are applied to the electrodes via the conductive lines or sub-conductive lines. When the voltage signal applied between the different electrodes reaches the threshold voltage, the switching state of the gating layer and the high and low resistance states of the storage layer are changed.

[0054] Please refer to Figure 6 and Figure 7 , Figure 6is a schematic cross-sectional structural diagram of several memory cell groups 300 in a phase change memory 10 provided in one embodiment of the present application. Figure 7 yes Figure 6 A schematic cross-sectional view of the structure of any one of the storage unit groups 300. Figure 6 In the illustrated embodiment, each storage unit group 300 includes two first storage units 310 and one second storage unit 320 , and the second storage unit 320 is located between the two first storage units 310 .

[0055] Figure 7 yes Figure 6 A schematic cross-sectional view of the structure of any one of the storage unit groups 300 is provided. Figure 7 In the illustrated embodiment, the memory cell group 300 includes a first memory cell 310, a second memory cell 320, and a first memory cell 310 stacked in sequence along a first direction Z1. The first memory cell 310 includes a first bottom electrode BE1, a first gate layer OTS1, a first intermediate electrode ME1, a first storage layer PCM1, and a first top electrode TE1, stacked along the first direction Z1. The second memory cell 320 includes a second bottom electrode BE2, a second gate layer OTS2, a second intermediate electrode ME2, a second storage layer PCM2, and a second top electrode TE2, stacked along a second direction Z2. The first memory cell 310 also includes a first adhesion layer 110 and a second adhesion layer 120. The first adhesion layer 110 is disposed between the first top electrode TE1 and the first storage layer PCM1, and the second adhesion layer 120 is disposed between the first storage layer PCM1 and the first intermediate electrode ME1. The second memory cell 320 further includes a third adhesive layer 210 and a fourth adhesive layer 220 . The third adhesive layer 210 is disposed between the second top electrode TE2 and the second memory layer PCM2 . The fourth adhesive layer 220 is disposed between the second memory layer PCM2 and the second middle electrode ME2 . Figure 7 Also shown are two first conductive lines 100 and two second conductive lines 200. The first conductive line 100 is located between the first memory cell 310 and the second memory cell 320. The film layer distribution in adjacent first memory cells 310 and second memory cells 320 is mirror-symmetrical about the first conductive line 100. The first conductive line 100 is electrically connected to both the first top electrode TE1 and the second top electrode TE2, meaning that the first conductive line 100 is electrically connected to both the first memory cell 310 and the second memory cell 320. The two second conductive lines 200 are electrically connected to the first memory cell 310 and the second memory cell 320, respectively. Electrical signals are applied to the electrodes via the conductive lines or sub-conductive lines. When the voltage signal applied between the different electrodes reaches the threshold voltage, the switching state of the gating layer and the high and low resistance states of the storage layer are changed.

[0056] In some embodiments, the storage unit group 300 includes two second storage units 320 and one first storage unit 310 , and the first storage unit 310 is located between the two second storage units 320 .

[0057] See also Figure 8 , Figure 8 FIG. 1 is a schematic cross-sectional view of a plurality of memory cell groups 300 in a phase change memory 10 provided in an embodiment of the present application. Figure 8 In the illustrated embodiment, a memory cell group 300 includes two first memory cells 310 and two second memory cells 320, with one second memory cell 320 located between the two first memory cells 310. Each memory cell group 300 includes a first memory cell 310, a second memory cell 320, and a first memory cell 310 and a second memory cell 320 stacked along a first direction Z1. A first conductive line 100 is located between adjacent first memory cells 310 and second memory cells 320. The stacking of film layers in the first memory cells 310 and second memory cells 320 is mirror-symmetrical with respect to the first conductive line 100. That is, the first memory layers PCM1 and PCM2 on either side of the first conductive line 100 are close to the first conductive line 100, while the first selection layers OTS1 and OTS2 are far away from the first conductive line 100. Alternatively, the first memory layers PCM1 and PCM2 on either side of the first conductive line 100 are far away from the first conductive line 100, while the first selection layers OTS1 and OTS2 are close to the first conductive line 100.

[0058] In some embodiments, the storage unit group 300 includes two first storage units 310 and two second storage units 320 , and one first storage unit 310 is located between the two second storage units 320 .

[0059] Figure 2-Figure 8 The number of storage cells in the storage cell group 300 shown in the embodiment is 2-4, while in some other embodiments of the present application, the number of storage cells in the storage cell group 300 is not limited.

[0060] In some embodiments, the critical dimension of the first memory cell is different from the critical dimension of the second memory cell. Adjustment of the critical dimension can change the threshold voltage of the memory cell, narrowing the gap between the first threshold voltage of the first memory cell and the second threshold voltage of the second memory cell, thereby achieving threshold voltage matching between the first memory cell and the second memory cell.

[0061] The following describes the structure of the phase change memory 10 provided by some embodiments in conjunction with the accompanying drawings. Figure 9 and Figure 10 , Figure 9This is a schematic diagram of the cross-sectional structure of several memory cell groups 300 in the phase change memory 10 provided in an embodiment of the present application. It can be seen that the critical dimension of the first memory cell 310 is different from the critical dimension of the second memory cell 320. The critical dimension reflects the size of the physical space occupied by a single phase change memory cell on the chip. The threshold voltage of the memory cell can be changed by adjusting the critical dimension. For example, reducing the critical dimension of the second memory layer PCM2 can increase the resistance of the second memory layer PCM2, thereby increasing the second threshold voltage, so as to reduce the difference between the second threshold voltage and the first threshold voltage and achieve threshold voltage matching. In some embodiments, the critical dimension of the first memory cell and the critical dimension of the second memory cell are both in the range of 10nm to 30nm, and the ratio of the critical dimension of the first memory cell to the critical dimension of the second memory cell is in the range of 0.8 to 1.2.

[0062] exist Figure 9 In the illustrated embodiment, the material of the first selection layer OTS1 and the material of the second selection layer OTS2 are the same. The material of the first storage layer PCM1 and the material of the second storage layer PCM2 are the same. The same storage layer and selection layer materials ensure a uniform manufacturing process when preparing different memory cell layers. This eliminates the need to adjust process parameters for different materials, reduces the complexity and difficulty of process adjustments, and improves process adaptability. In other embodiments, the material of the first selection layer OTS1 and the material of the second selection layer OTS2 can be different. The material of the first storage layer PCM1 and the material of the second storage layer PCM2 can also be different.

[0063] Figure 10 yes Figure 9 A schematic cross-sectional view of the structure of any one of the storage unit groups 300 is provided. Figure 10 In the illustrated embodiment, the memory cell group 300 includes a first memory cell 310 and a second memory cell 320 stacked along a first direction Z1. The first memory cell 310 includes a first bottom electrode BE1, a first gate layer OTS1, a first intermediate electrode ME1, a first storage layer PCM1, and a first top electrode TE1 stacked along the first direction Z1. The second memory cell 320 includes a second bottom electrode BE2, a second gate layer OTS2, a second intermediate electrode ME2, a second storage layer PCM2, and a second top electrode TE2 stacked along a second direction Z2. Figure 10As shown, the first intermediate electrode ME1 is located between the first gate layer OTS1 and the first storage layer PCM1, the first bottom electrode BE1 is located on a side of the first gate layer OTS1 away from the first intermediate electrode ME1, and the first top electrode TE1 is located on a side of the first storage layer PCM1 away from the first intermediate electrode ME1. The second intermediate electrode ME2 is located between the second gate layer OTS2 and the second storage layer PCM2, the second bottom electrode BE2 is located on a side of the second gate layer OTS2 away from the second intermediate electrode ME2, and the second top electrode TE2 is located on a side of the second storage layer PCM2 away from the second intermediate electrode ME2.

[0064] In some embodiments, in a first direction Z1, the thickness of the first gating layer is different from the thickness of the second gating layer, and / or the thickness of the first storage layer is different from the thickness of the second storage layer. Adjusting the thickness can change the threshold voltage of the storage cell, narrowing the gap between the first threshold voltage of the first storage cell and the second threshold voltage of the second storage cell, thereby achieving threshold voltage matching between the first and second storage cells. In some embodiments, the ratio of the thickness of the first storage cell to the thickness of the second storage cell is in a range of 0.8 to 1.2. The thickness of the first gating layer and the thickness of the second gating layer are both in a range of 10 nm to 30 nm.

[0065] Please refer to Figure 11 and Figure 12 , Figure 11 is a schematic cross-sectional structural diagram of several memory cell groups 300 in a phase change memory 10 provided in one embodiment of the present application. Figure 12 yes Figure 11 A schematic cross-sectional view of the structure of any one of the storage unit groups 300. Figure 11 In the illustrated embodiment, each memory cell group 300 includes a first memory cell 310 and a second memory cell 320 stacked along a first direction Z1. The first memory cell 310 includes a first gate layer OTS1 and a first memory layer PCM1 stacked along the first direction Z1. The second memory cell 320 includes a second gate layer OTS2 and a second memory layer PCM2 stacked along a second direction Z2, which is opposite to the first direction Z1.

[0066] exist Figure 12 In the illustrated embodiment, it can be seen that in the first direction Z1, the thickness of the first memory cell 310 is different from the thickness of the second memory cell 320. By adjusting the thickness, the threshold voltage of the memory cell can be changed. For example, increasing the thickness of the second selection layer OTS2 in the first direction Z1 can increase the resistance of the second selection layer OTS2, thereby increasing the second threshold voltage, reducing the difference between the second threshold voltage and the first threshold voltage, and achieving threshold voltage matching.

[0067] exist Figure 12 In the illustrated embodiment, the material of the first selection layer OTS1 and the material of the second selection layer OTS2 are the same. The material of the first storage layer PCM1 and the material of the second storage layer PCM2 are the same. The same storage layer and selection layer materials ensure a uniform manufacturing process when preparing different memory cell layers. This eliminates the need to adjust process parameters for different materials, reduces the complexity and difficulty of process adjustments, and improves process adaptability. In other embodiments, the material of the first selection layer OTS1 and the material of the second selection layer OTS2 can be different. The material of the first storage layer PCM1 and the material of the second storage layer PCM2 can also be different.

[0068] exist Figure 12 In the illustrated embodiment, the critical dimension of the first memory cell 310 is the same as the critical dimension of the second memory cell 320. In other embodiments, the critical dimensions of the first memory cell 310 and the second memory cell 320 may be different.

[0069] In some embodiments, the material of the first gating layer is different from the material of the second gating layer, and / or the material of the first storage layer is different from the material of the second storage layer. By adjusting the elemental ratio of the materials of the first gating layer and the second gating layer, the difference between the first threshold voltage of the first storage cell and the second threshold voltage of the second storage cell is reduced, thereby achieving threshold voltage matching between the first storage cell and the second storage cell. Furthermore, the adjustment of the critical dimension and the adjustment of the gating layer material can be performed separately or simultaneously to achieve better threshold voltage matching, eliminate the difference in operating polarity between two adjacent storage cells sharing the same conductive line, reduce the difficulty of circuit design, and improve the consistency of multi-layer storage.

[0070] Please refer to Figure 13 and Figure 14 , Figure 13 is a schematic cross-sectional structural diagram of several memory cell groups 300 in a phase change memory 10 provided in one embodiment of the present application. Figure 14 yes Figure 13 A schematic cross-sectional view of the structure of any one of the storage unit groups 300. Figure 13 In the embodiment shown, the material of the first gating layer includes a first base material, and the material of the second gating layer includes a second base material. The first base material and the second base material have the same elemental composition but have different contents of at least one element. Different content of an element refers to different percentages of the number of atoms of the same element in the base material ( Figure 13Different filling densities are used to indicate different percentages of atoms). For example, the first matrix material and the second matrix material include Se elements. The greater the percentage of the number of atoms of Se elements in the matrix material, the greater the threshold voltage of the gating layer. By adjusting the percentage of the number of atoms of Se elements in the second matrix material, the second threshold voltage can be increased to reduce the difference between the second threshold voltage and the first threshold voltage, thereby achieving threshold voltage matching. The first matrix material and the second matrix material include compounds such as GeAsSe, GeSe, GeAsSeIn, GeAsSeSi, and GeAsSeInSi, whose general chemical formula is In a Si b -Ge x As y Se 1-(x+y)-(a+b) , where 0 <x<0.5,0<y<0.5,0<x+y<0.6,0≤a<0.15,0≤b<0.15。

[0071] exist Figure 13 In the illustrated embodiment, the critical dimension of the first memory cell 310 is the same as the critical dimension of the second memory cell 320. In other embodiments, the critical dimensions of the first memory cell 310 and the second memory cell 320 may be different.

[0072] exist Figure 13 In the illustrated embodiment, the material of the second storage layer includes a third matrix material, and the material of the second storage layer includes a fourth matrix material. The third matrix material and the fourth matrix material have the same elemental composition and the same element content. The same element content means that the atomic percentage of the same element in the matrix material is the same. In other embodiments, the third matrix material and the fourth matrix material may have the same elemental composition but differ in the content of at least one element.

[0073] Please refer to Figure 15 and Figure 16 , Figure 15 is a schematic cross-sectional structural diagram of several memory cell groups 300 in a phase change memory 10 provided in one embodiment of the present application. Figure 16 yes Figure 15 A schematic cross-sectional view of the structure of any one of the storage unit groups 300. Figure 15 In the embodiment shown, the material of the first storage layer includes a third matrix material, and the material of the second storage layer includes a fourth matrix material. The third matrix material and the fourth matrix material have the same elemental composition but differ in the content of at least one element. The different content of an element refers to the different percentage of the number of atoms of the same element in the matrix material ( Figure 15are shown with different filling densities to indicate different atomic percentage ratios). Exemplarily, the third matrix material and the fourth matrix material include the Ge element. The greater the atomic percentage ratio of the Ge element in the matrix material, the greater the resistance of the storage layer, and thus the greater the threshold voltage. By adjusting the atomic percentage ratio of the Ge element in the fourth matrix material, the second threshold voltage (especially the threshold voltage in the RTS state) can be increased to reduce the difference between the second threshold voltage and the first threshold voltage, achieving the matching of the threshold voltages. The chemical general formula of the third matrix material and the fourth matrix material is M a L b -Ge x Sb y Te 1-(x+y)-(a+b) , 0 < x < 0.6, 0 < y < 0.6. Where the M element is a metal doping element, such as In / Zn / Hf / Zr / Ta, etc., the L is a non-metal doping element, such as C / N / O / B / Si / P / , etc., 0 ≤ a < 0.1, 0 ≤ b < 0.1.

[0074] In Figure 15 the embodiment shown, the critical dimension of the first storage unit 310 is the same as that of the second storage unit 320. In some other embodiments, the critical dimensions of the first storage unit 310 and the second storage unit 320 may also be different.

[0075] Figures 9-16 The number of storage units in the storage unit group 300 shown in the embodiment is 2. In some other embodiments of the present application, the number of storage units in the storage unit group 300 may not be limited. For embodiments with 3 or more storage units in the storage unit group, it is necessary to keep each first storage unit adjacent to any second storage unit.

[0076] In the description of the present application, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, the meaning of "plurality" is two or more, unless otherwise specifically defined.

[0077] In the above embodiments, the descriptions of each embodiment have their own emphases. For parts not detailed in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0078] Among the embodiments, implementation manners and related technical features of the present application, they can be combined and replaced with each other without conflict.

[0079] The above are merely preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A phase change memory, characterized in that: include: a plurality of storage unit groups arranged at intervals, each of the storage unit groups comprising at least one first storage unit and at least one second storage unit alternately stacked along a first direction; The first memory cell includes a first gating layer and a first storage layer sequentially stacked along the first direction, and the second memory cell includes a second storage layer and a second gating layer sequentially stacked along the first direction; or, The first memory cell includes a first memory layer and a first gate layer sequentially stacked along the first direction, and the second memory cell includes a second gate layer and a second memory layer sequentially stacked along the first direction.

2. The phase change memory according to claim 1, wherein: The first gate layer has a first threshold voltage, the second gate layer has a second threshold voltage, and a difference between the first threshold voltage and the second threshold voltage is between 0V and 0.5V.

3. The phase change memory according to claim 1, wherein: The critical dimension of the first memory cell is different from the critical dimension of the second memory cell.

4. The phase change memory according to claim 1, wherein: The critical dimensions of the first memory cell and the critical dimensions of the second memory cell are both in the range of 10 nm to 30 nm, and the ratio of the critical dimensions of the first memory cell to the critical dimensions of the second memory cell is in the range of 0.8 to 1.

2.

5. The phase change memory according to claim 1, wherein: In the first direction, the thickness of the first gating layer is different from the thickness of the second gating layer; and / or the thickness of the first storage layer is different from the thickness of the second storage layer.

6. The phase change memory according to claim 5, characterized in that The ratio of the thickness of the first storage unit to the thickness of the second storage unit is in a range of 0.8 to 1.

2.

7. The phase change memory according to claim 5, wherein: The thickness of the first gating layer and the thickness of the second gating layer are both in the range of 10 nm to 30 nm.

8. The phase change memory according to claim 1, wherein: The material of the first gate layer is different from the material of the second gate layer; and / or the material of the first storage layer is different from the material of the second storage layer.

9. The memory according to claim 8, wherein: The material of the first gating layer includes a first base material, and the material of the second gating layer includes a second base material. The first base material and the second base material have the same element composition but have different contents of at least one element.

10. The memory according to claim 8, wherein The material of the first storage layer includes a third matrix material, and the material of the second storage layer includes a fourth matrix material. The third matrix material and the fourth matrix material have the same element composition but have different contents of at least one element.

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