Semiconductor device

Abstract

According to one embodiment, a semiconductor device includes a semiconductor substrate; an interlayer insulating film provided on the semiconductor substrate; a first electrode disposed on the interlayer insulating film; the second electrode is arranged under the semiconductor substrate; a plurality of gate regions extending from the interlayer insulating film in a first direction to reach the semiconductor substrate, the first direction being a thickness direction of the semiconductor substrate, the plurality of gate regions being disposed in a second direction intersecting the first direction, the first direction and the second direction intersect with each other and extend in a third direction intersecting with the first direction and the second direction; and a plurality of plugs located between the gate regions in the second direction, having a length in the second direction greater than a length in the third direction, spaced apart from each other in the third direction, and electrically connecting the first electrode to the semiconductor substrate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based upon and claims the benefit of priority from Japanese patent application No. 2024-032211 filed on March 4, 2024, and the entire contents of that application are incorporated herein by reference. Technical Field

[0003] Generally speaking, embodiments described herein relate to semiconductor devices. Background Art

[0004] A structure is known in which a plug is formed to connect an electrode and a semiconductor substrate facing each other via an insulating film. The plug is formed by embedding W (tungsten) in an opening dug by etching or the like. Summary of the Invention

[0005] Embodiments provide a semiconductor device capable of optimizing current control and improving electrical characteristics.

[0006] One embodiment provides a semiconductor device, including:

[0007] semiconductor substrates;

[0008] an interlayer insulating film provided on the semiconductor substrate;

[0009] a first electrode disposed on the interlayer insulating film;

[0010] a second electrode disposed under the semiconductor substrate;

[0011] a plurality of gate regions extending from the interlayer insulating film in a first direction to reach the semiconductor substrate, the first direction being a thickness direction of the semiconductor substrate, the plurality of gate regions being arranged in a second direction intersecting the first direction and extending in a third direction intersecting the first direction and the second direction; and

[0012] A plurality of plugs are located between the gate regions in the second direction, have a length in the second direction greater than a length in the third direction, are spaced apart from each other in the third direction, and electrically connect the first electrode to the semiconductor substrate.

[0013] One embodiment provides a semiconductor device, including:

[0014] semiconductor substrates;

[0015] an interlayer insulating film provided on the semiconductor substrate;

[0016] a first electrode disposed on the interlayer insulating film;

[0017] a second electrode disposed under the semiconductor substrate;

[0018] a plurality of gate regions extending from the interlayer insulating film in a first direction to reach the semiconductor substrate, the first direction being a thickness direction of the semiconductor substrate, the plurality of gate regions being arranged in a second direction intersecting the first direction and extending along a third direction intersecting the first direction and the second direction;

[0019] a plurality of plugs located between the gate regions in the second direction and spaced apart from each other in the third direction and electrically connecting the first electrode to the semiconductor substrate; and

[0020] The plurality of third semiconductor regions in the semiconductor substrate are disposed between the plurality of gate regions and are not aligned in the third direction.

[0021] Furthermore, one embodiment provides a semiconductor device including:

[0022] semiconductor substrates;

[0023] an interlayer insulating film provided on the semiconductor substrate;

[0024] a first electrode provided on the interlayer insulating film and connected to the semiconductor substrate;

[0025] a gate wiring provided on the interlayer insulating film so as to be spaced apart from the first electrode;

[0026] a second electrode disposed under the semiconductor substrate;

[0027] a plurality of gate regions extending from the interlayer insulating film in a first direction to reach the semiconductor substrate, the first direction being a thickness direction of the semiconductor substrate, the plurality of gate regions being arranged in a second direction intersecting the first direction and extending along a third direction intersecting the first direction and the second direction, each of the gate regions including a gate electrode embedded in the gate region and a gate insulating film covering the gate electrode; and

[0028] A plurality of plugs are spaced apart from each other in the third direction and electrically connect the gate wiring to the gate electrode in each of the gate regions. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1A is a plan view showing the semiconductor device according to the first embodiment.

[0030] Figure 1B Yes Display Figure 1A An enlarged plan view of region Ra of the semiconductor device is shown.

[0031] Figure 2A Yes Display Figure 1B A cross-sectional view of the semiconductor device taken along line AA' is shown.

[0032] Figure 2B Yes Display Figure 1B An enlarged cross-sectional view of a BB' cross section of the semiconductor device shown.

[0033] Figure 2C Yes Display Figure 1B An enlarged cross-sectional view of a CC' cross section of the semiconductor device shown.

[0034] Figure 2D Yes Display Figure 1B An enlarged cross-sectional view of a CC' cross section of another configuration of a semiconductor device is shown.

[0035] Figure 3 It is an enlarged plan view showing a first modification of the semiconductor device according to the first embodiment.

[0036] Figure 4 is an enlarged plan view showing a semiconductor device according to a first reference example.

[0037] Figure 5 Yes Display Figure 4 A cross-sectional view of the semiconductor device taken along line DD' is shown.

[0038] Figure 6 is an enlarged plan view showing a semiconductor device according to a second reference example.

[0039] Figure 7 is an enlarged plan view showing a semiconductor device according to a second embodiment.

[0040] Figure 8A Yes Display Figure 7 A cross-sectional view of the semiconductor device taken along line EE' is shown.

[0041] Figure 8B Yes Display Figure 7 A cross-sectional view of the semiconductor device taken along line FF' is shown.

[0042] Figure 9 is an enlarged plan view showing a semiconductor device according to a third embodiment.

[0043] Figure 10 Yes Display Figure 9 A cross-sectional view of the semiconductor device shown is taken along line GG'.

[0044] Figures 11-16Each of them is a cross-sectional view corresponding to the AA′ cross section of the semiconductor device shown in FIG. 1 , and illustrates the method for manufacturing the semiconductor device according to the first embodiment. DETAILED DESCRIPTION

[0045] Embodiments provide a semiconductor device capable of optimizing current control therein and improving electrical characteristics thereof.

[0046] Generally, according to one embodiment, a semiconductor device includes: a semiconductor substrate; an interlayer insulating film arranged on the semiconductor substrate; a first electrode arranged on the interlayer insulating film; a second electrode arranged under the semiconductor substrate; a plurality of gate regions extending from the interlayer insulating film in a first direction to reach the semiconductor substrate, the first direction being a thickness direction of the semiconductor substrate, the plurality of gate regions being arranged in a second direction intersecting with the first direction and extending along a third direction intersecting with the first direction and the second direction; and a plurality of plugs located between the gate regions in the second direction, being longer in the second direction than in the third direction, being spaced apart from each other in the third direction, and electrically connecting the first electrode to the semiconductor substrate.

[0047] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0048] These drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio between the sizes of each part, etc. are not necessarily the same as the actual ones. Even if the same component is shown, the size and ratio may be expressed differently depending on the drawings.

[0049] In the present specification and drawings, elements that have been described with respect to previous drawings are given the same reference numerals, and detailed description is appropriately omitted.

[0050] The direction from the first semiconductor region 21 to the second semiconductor region 22 is referred to herein as the Z direction. The Z direction is the thickness direction of the semiconductor substrate 20. Furthermore, the direction intersecting the Z direction is referred to herein as the X direction, and the direction intersecting the X and Z directions is referred to herein as the Y direction. The semiconductor device 1 shown in FIG2 is a cross-sectional view taken along the XZ plane. Although the X, Y, and Z directions are shown as being orthogonal in this embodiment, these directions are not limited to being orthogonal and may also be intersecting.

[0051] In this specification, the positive direction of the Z direction is referred to as “upper,” and the other side is referred to as “lower.” The “upper” and “lower” directions are not limited to the direction of gravity or the direction when the semiconductor device is mounted.

[0052] In this specification, orthogonal coordinate axes of X, Y, and Z may be used to describe technical issues. Orthogonal coordinate axes only specify the relative positions of components and are not intended to limit the directions stated in the claims to specific directions. For example, the Z axis is not limited to a height direction relative to the ground. The +Z axis direction and the -Z axis direction are opposite directions. When the Z axis direction is mentioned without indicating positive or negative, it means a direction parallel to the +Z axis and the -Z axis.

[0053] In addition, in the following description, the symbol n + 、n、n - 、p + , p and p - Indicates the relative level of impurity concentration of each conductivity type. In other words, n + Indicates that the n-type impurity concentration is relatively higher than the n-type, n - Indicates that the n-type impurity concentration is relatively lower than the n-type. In addition, p + Indicates the p-type impurity concentration is higher than that of p-type, p - Indicates that the p-type impurity concentration is relatively lower than that of the p-type. + Type and n - Type can be abbreviated as n type, p + Type and p - Type can be abbreviated as p-type.

[0054] (First embodiment)

[0055] Figure 1A 1 is a schematic plan view showing the internal wiring structure of the semiconductor device 1 according to the present embodiment. Figure 1B Yes Display Figure 1A An enlarged plan view of the region Ra is shown. Figure 1A and Figure 1B In FIG. 5 , the first electrode 11 and the interlayer insulating film 50 are omitted in order to show the internal wiring structure.

[0056] Figure 1A The following is a schematic top view of a semiconductor device 1 and an enlarged plan view of a portion of the top view. In the active region AR of the semiconductor device 1, for example, an insulated gate bipolar transistor (IGBT) is formed. The active region AR is a region through which current primarily flows when the semiconductor device 1 is in the on state.

[0057] exist Figure 1AIn a plan view, gate regions 30 are repeatedly arranged along the X direction on the semiconductor substrate 20, and the gate regions 30 extend in the Y direction. In the semiconductor substrate 20, a plurality of plugs 40 are arranged between the plurality of rows of gate regions 30 arranged along the X direction, and these plugs 40 are spaced apart from each other in the Y direction. Here, the plugs 40 are described as being arranged between the gate regions 30. However, if, for example, the plugs 40 are located at the outermost periphery outside the active region AR of the semiconductor device 1, not all plugs 40 need to be arranged between the gate regions 30.

[0058] Figure 1A The plan view schematically shows a portion of the active region AR, and the peripheral portion of the active region AR is not limited to Figure 1A Furthermore, for example, if an IGBT is formed in the active region AR, the portion where the emitter is formed and the portion where the gate electrode is formed may have different structures.

[0059] Figure 1B yes Figure 1A An enlarged plan view of the region Ra is shown. Figure 1B The internal wiring structure is shown. Gate region 30 includes, for example, a gate insulating film 31 and a gate electrode 32. Gate insulating film 31 covers gate electrode 32. Gate electrodes 32 do not need to be at the same potential throughout. A dummy electrode may be included in a portion of gate electrode 32 in gate region 30. Furthermore, gate region 30 does not necessarily need to include gate electrode 32. A portion of gate region 30 may be made of, for example, an insulating material alone.

[0060] The semiconductor substrate 20 includes a first semiconductor region 21 of a first conductivity type ( Figure 1B The first semiconductor region 22 is a second semiconductor region of the second conductivity type (not shown), and the first semiconductor region 23 is a third semiconductor region of the first conductivity type. The second semiconductor region 22 is, for example, a p-type base region. The third semiconductor region 23 is, for example, an n-type emitter region. The third semiconductor region 23 is selectively provided on the second semiconductor region 22.

[0061] like Figure 1BAs shown in FIG, a plurality of third semiconductor regions 23 are provided in the Y direction (for example, between the gate regions 30). For example, the length of the third semiconductor region 23 in the X direction is longer than the length of the third semiconductor region 23 in the Y direction. The second semiconductor region 22 is located between the separated third semiconductor regions 23. By providing a plurality of third semiconductor regions 23 in the Y direction, the contact area between the third semiconductor region 23 and the gate region 30 can be controlled, and the flow of current can be dispersed. As described below, when the semiconductor device 1 is in the on state, current flows through the third semiconductor region 23 near the gate region 30. By configuring the plurality of third semiconductor regions 23 formed in the Y direction, the flow of current in the on state can be controlled. The third semiconductor region 23 can be a region extending and continuously formed along the Y direction.

[0062] The plurality of plugs 40 are provided in contact with either or both of the second semiconductor region 22 or the third semiconductor region 23. The plurality of regions formed in the Y direction may be collectively referred to as plugs 40, but each of the plurality of regions may also be referred to as a plug 40.

[0063] After describing FIG2, the Figure 1B The lengths L1, L2, L3 and LG are shown in FIG.

[0064] In the following, reference will be made to Figure 2A 、 2B and Figure 2C A cross-sectional structure of the semiconductor device 1 according to the first embodiment is described.

[0065] Figure 2A 、 2B and Figure 2C Along Figure 1B Cross-sectional views taken along lines AA', BB', and CC' are shown. Figure 2A 、 2B and Figure 2C The cross-sectional view shows the first electrode 11 and the interlayer insulating film 50. Figure 1B They are omitted in Figure 2B and Figure 2C In the cross-sectional view of , the structure below the first semiconductor region 21 is omitted.

[0066] First, refer to Figure 2A A cross-sectional view taken along line AA′ of the semiconductor device 1 according to the first embodiment will be described. Figure 2AThe semiconductor device 1 according to the present embodiment shown includes a first electrode 11, a second electrode 12, a semiconductor substrate 20, a gate region 30, a plug 40, and an interlayer insulating film 50. The semiconductor substrate 20 includes a first semiconductor region 21 of a first conductivity type, a second semiconductor region 22 of a second conductivity type, a third semiconductor region 23 of a first conductivity type, a fourth semiconductor region 24 of a second conductivity type, and a fifth semiconductor region 25 of a second conductivity type. The gate region 30 includes a gate insulating film 31 and a gate electrode 32.

[0067] The first electrode 11 and the second electrode are, for example, metals including AlCu or AlSi. The first electrode 11 is, for example, an emitter of an IGBT. The second electrode 12 is, for example, a collector of the IGBT. A semiconductor substrate 20 is provided between the first electrode 11 and the second electrode 12.

[0068] The semiconductor substrate 20 is made of a semiconductor containing Si, for example. The first semiconductor region 21 is, for example, an n-type drift layer. The second semiconductor region 22 is, for example, a p-type - The third semiconductor region 23 is, for example, n + The fourth semiconductor region 24 is, for example, a p + The fifth semiconductor region 25 is, for example, a p + For example, a p-type semiconductor layer is formed by doping a Si substrate with B. For example, an n-type semiconductor layer is formed by doping a Si substrate with N or P.

[0069] The gate region 30 is, for example, a gate trench of an IGBT. The gate insulating film 31 includes silicon oxide such as SiO 2 . The gate insulating film 31 is, for example, a gate insulating film of an IGBT and is formed by oxidation. The gate electrode 32 is, for example, a gate electrode of an IGBT and includes polysilicon.

[0070] Plug 40 is preferably made of a metal containing W (tungsten). Plug 40 may also be covered with a barrier metal 41. Barrier metal 41 is formed between plug 40 and semiconductor substrate 20 and between plug 40 and the interlayer insulating film. Barrier metal 41 has a layer structure containing, for example, Ti and TiN. Barrier metal 41 has higher adhesion to interlayer insulating film 50 than plug 40, and prevents plug 40 from peeling off from interlayer insulating film 50 when stress is applied to semiconductor substrate 20 and interlayer insulating film 50 due to temperature changes, etc. Furthermore, if plug 40 is formed on the surface of barrier metal 41, for example, by CVD, the reactivity between the gas used for CVD and barrier metal 41 can be controlled by selecting the material of barrier metal 41. For example, when CVD is performed using a gas containing fluorine, a barrier metal 41 containing TiN can reduce the reactivity of fluorine.

[0071] The plug 40 may be covered with a barrier metal 41, and the barrier metal 41 may be in contact with the semiconductor substrate 20. The plug 40 and the semiconductor substrate 20 are electrically connected to each other in a contact portion where the plug 40 and the semiconductor substrate 20 are in contact with each other. In the description of this specification, the contact region between the plug 40 and the semiconductor substrate 20 is described, but the definition of "contact" also includes a case where the plug 40 and the semiconductor substrate 20 face each other with the barrier metal 41 interposed therebetween.

[0072] The plug 40 electrically connects the first electrode 11 and the semiconductor substrate 20. The plug 40 contacts the third semiconductor region 23 in the AA' cross section and reaches the second semiconductor region 22. On the bottom surface of the plug 40, the fifth semiconductor region 25 is formed.

[0073] The gate region 30 is provided below the interlayer insulating film 50 and extends in the negative Z direction to the first semiconductor region 21. The gate region 30 includes a gate electrode 32 covered with a gate insulating film 31. The gate insulating film 31 is provided between the gate electrode 32 and the semiconductor substrate 20, and at least a portion of the gate insulating film 31 is in contact with the second semiconductor region 22. The gate electrode 32 is electrically insulated from the semiconductor substrate 20 by the gate insulating film 31. By applying a voltage to the gate electrode 32, an inversion layer is formed in the second semiconductor region 22, and the semiconductor device can be set to an on state.

[0074] The interlayer insulating film 50 is made of silicon oxide such as SiO2. The interlayer insulating film 50 is formed, for example, by CVD. The interlayer insulating film 50 is formed on the semiconductor substrate 20 and is provided to cover the gate region 30. The gate electrode 32 and the first electrode 11 are electrically insulated from each other by the interlayer insulating film 50.

[0075] Figure 2B It is along Figure 1B Since the BB' cross section does not pass through the plug 40, there is no Figure 2B On the other hand, the gate region 30 is Figure 1B extends in the Y direction, so Figure 2A In the same way, Figure 2B The gate region 30 is shown in FIG.

[0076] Figure 2C It is along Figure 1B A plurality of plugs 40 are provided in the Y direction. Figure 2C The arrangement of the plugs 40 in the Y direction can be changed according to the arrangement of the third semiconductor regions 23 in the Y direction. The plugs 40 and the third semiconductor regions 23 are arranged at regular intervals in the Y direction, for example.

[0077] Some plugs 40 may be in contact with the third semiconductor regions 23, and some plugs may be located between a plurality of third semiconductor regions 23. At least one plug 40 is provided between the third semiconductor regions 23 spaced apart along the Y direction. Figure 2C As shown, the plugs 40 in contact with the third semiconductor regions 23 and the plugs 400 located between the plurality of third semiconductor regions 23 are repeated alternately in the Y direction. Figure 2D As described, the plugs 40 in contact with the third semiconductor region 23 and the plugs 40 located between the plurality of third semiconductor regions 23 do not necessarily need to be repeated alternately in the Y direction. Figure 2D Is displayed with Figure 2C Figures showing different examples of embodiments, with cross-sections directed to the Figure 2C same.

[0078] like Figure 2D As shown in FIG, among some of the plurality of plugs 40, plugs 40 adjacent to each other in the Y direction may be in contact with the third semiconductor region 23. For example, two or more plugs 40 may be in contact with one of the plurality of third semiconductor regions 23.

[0079] although Figure 2D Although not shown in the figure, the plugs 40 adjacent to each other in the Y direction may contact different third semiconductor regions 23 spaced apart from each other in the Y direction among the plurality of third semiconductor regions 23. In other words, the third semiconductor region 23, the second semiconductor region 22, and the third semiconductor region 23 may be arranged in the Y direction between the plugs 40 adjacent to each other in the Y direction.

[0080] Or, as Figure 2D As shown in , for at least some of the plurality of plugs 40, the plugs 40 adjacent to each other in the Y direction may be located between the third semiconductor regions 23 spaced apart from each other in the Y direction. Among the plurality of third semiconductor regions 23, two or more plugs 40 may be provided between the third semiconductor regions 23 adjacent to each other in the Y direction.

[0081] The following will refer to Figure 1B and Figure 2A 、 2B and Figure 2C The configuration of the plug 40 of the semiconductor device 1 according to the first embodiment will be further described.

[0082] First, refer to Figure 1B For explanation. Figure 1BAs shown, when comparing the pitch LG between the gate regions 30 in the X direction and the length L1 of the plug 40 in the X direction, L1 is shorter. By making L1 smaller than LG, the plug 40 can be formed between the gate regions 30. L1 (<LG) is not limited to any length smaller than LG, and considering the alignment error in the X direction when forming the plug 40, L1 can be set to be sufficiently smaller than LG.

[0083] In addition, the length L1 of the plug 40 in the X direction and the distance L2 in the Y direction are different from each other. L1 is, for example, the length of the long side of the plug 40 having a rectangular cross section in the XY plane, and L2 is, for example, the length of the short side of the plug 40 having a rectangular cross section in the XY plane.

[0084] The pitch L3 between the plugs 40 adjacent to each other in the Y direction can be smaller or larger than L1. As Figure 1B shown, the plugs 40 can be set at a fixed pitch L3.

[0085] In Figure 1B the shown XY plane, the plug 40 contacts the second semiconductor region 22 or the third semiconductor region 23. At least a part of the plug 40 can contact the second semiconductor region 22 and the third semiconductor region 23 in the XY plane.

[0086] Next, reference will be made to Figure 2A for description. The plug 40 has a depth D in the Z direction. The depth D is the length in the Z direction from the interface between the plug 40 and the first electrode 11 to the bottom surface of the plug 40. The shape of the bottom surface of the plug 40 is not limited to Figure 2A shown, and the bottom surface can be circular.

[0087] The ratio between the depth D and the length L1 (i.e., D / L1) is called the first aspect ratio. In addition, Figure 2C the ratio between the depth D shown and the length L2 of the plug 40 in the Y direction (i.e., D / L2) is called the second aspect ratio.

[0088] For example, the first aspect ratio D / L1 is in the range of 0 < D / L1 ≤ 2. If the first aspect ratio satisfies 0 < D / L1 ≤ 2, the embeddability when forming the plug 40 can be improved. Preferably, the first aspect ratio is in the range of 0 < D / L1 ≤ 1.

[0089] The second aspect ratio D / L2 satisfies D / L1 ≤ D / L2, for example 1 ≤ D / L2. By making the second aspect ratio D / L2 satisfy 1 ≤ D / L2, the contact area between the plug 40 and the semiconductor substrate 20 can be increased, which is beneficial for miniaturization. Since the first aspect ratio is smaller than the second aspect ratio, even if the second aspect ratio is large, a satisfactory embeddability of the plug 40 can be maintained.

[0090] For example, the plug 40 may have a structure that tapers in the negative direction of the Z direction. In this case, the lengths L1 and L2 may be defined as the maximum lengths in the X direction of a portion of the plug 40 located between the gate regions 30. For example, in the Z direction, the length in the X direction of the plug 40 at a position corresponding to the interface between the semiconductor substrate 20 and the interlayer insulating film 50 is measured and set to L1.

[0091] Next, we will refer to Figure 2A The operation of the semiconductor device 1 will be described. As an example, the operation of the IGBT will be described. - type drift region, the second semiconductor region 22 is a p-type base region, and the third semiconductor region 23 is an n-type + The fourth semiconductor region 24 is a p-type emitter layer. + Type collector layer, the fifth semiconductor region 25 is p + First, the action of turning on the IGBT will be described.

[0092] A negative voltage is applied to the first electrode 11 with reference to the second electrode 12. By applying a positive voltage equal to or greater than the threshold voltage with reference to the potential of the first electrode 11 to the gate electrode 32, an inversion layer (channel) is formed in the second semiconductor region 22 near the gate insulating film 31. That is, an inversion layer having n-type conductivity is formed in the second semiconductor region 22, which is a p-type base region.

[0093] The inversion layer formed in the second semiconductor region 22 has the same conductivity type as the first semiconductor region 21 and the third semiconductor region 23. Therefore, electrons that reach the third semiconductor region 23 from the first electrode 11 (emitter) through the plug 40 flow toward the first semiconductor region 21 through the inversion layer formed in the second semiconductor region 22.

[0094] Furthermore, holes are injected into the first semiconductor region 20 (drift layer) from the fourth semiconductor region 24 (collector layer) disposed below the first semiconductor region 21. This allows current, using electrons and holes as carriers, to flow from the second electrode 12 (collector) to the first electrode (emitter), turning the IGBT on.

[0095] Next, when the IGBT is turned off, the potential of the gate electrode 32 is set to the same potential as, for example, the first electrode 11. The inversion layer formed in the second semiconductor region 22 disappears, and the injection of electrons from the third semiconductor region 23 into the first semiconductor region 21 is suppressed. To completely turn the IGBT off, it is necessary to discharge the carriers accumulated in the first semiconductor region 21 during the on-state. Electrons are discharged to the second electrode 12, and holes are discharged to the first electrode 11 through the p-type second semiconductor region 22 and the plug 40.

[0096] For example, these holes are discharged through the following route: the holes accumulated in the first semiconductor region 21 are discharged to the plug 40 through the second semiconductor region 22 and the fifth semiconductor region 25 having the same conductivity type as the second semiconductor region. That is, the fifth semiconductor region 25 connects the plug 40 and the second semiconductor region 22, and further forms an ohmic contact with the plug 40 to serve as a hole discharge path.

[0097] That is, the plug 40 is a path for electrons to flow from the first electrode 11 to the third semiconductor region 23 when the IGBT is in the on state, and for holes to discharge from the second semiconductor region 22 to the first electrode 11 when the IGBT is off. As described above, the plug 4 electrically connects the first electrode 11 and the semiconductor substrate 20, and the semiconductor device 1 operates.

[0098] In the semiconductor device 1 of this embodiment, each of the plurality of plugs 40 arranged along the Y direction has a length L1 in the X direction and a length L2 in the Y direction that is different from L1. This prevents defects in the plugs 40 and improves the reliability of the semiconductor device. By improving the flatness of the first electrode 11 formed on the plug 40, stress concentration and cracking in a portion of the electrode are prevented.

[0099] The plug 40 and the semiconductor substrate 20 are typically made of materials with different coefficients of thermal expansion. For example, the W (tungsten) contained in the plug 40 has a greater coefficient of thermal expansion than the Si (silicon) contained in the semiconductor substrate. When heat is applied, the plug 40 and the semiconductor substrate 20 expand to different degrees, which may cause deformation and stress. The stress generated between the plug 40 and the semiconductor substrate 20 may cause wafer warpage. Generally, as the width of the plug 40 increases, the film thickness of the W (tungsten) needs to be increased, which increases the stress, leading to concerns that wafer warpage may increase. In other words, the increase in the size of the contact area between the plug 40 and the semiconductor substrate 20 may lead to increased stress applied to the wafer.

[0100] Hereinafter, as an example, a case where the plug 40 is made of W (tungsten) will be described. For example, the plug 40 is formed by embedding a conductive material in an opening, wherein the opening is formed by digging the semiconductor substrate 20 and the interlayer insulating film 50 in the Z direction. A film containing a conductive material (for example, W) is embedded in the opening by forming a film having a prescribed thickness on the bottom surface and side walls of the opening. For example, in order to form a plug 40 with a length of L2 in the Y direction, a film with a thickness of L2 / 2 is formed on the side walls. In order to fill the opening, a film with a thickness of at least L2 / 2 is formed on the side walls of the opening. In order to satisfactorily fill the opening without compromising flatness and preventing the formation of voids, the film thickness is preferably L2×(3 / 5) or greater. More preferably, the film thickness is L2×(3 / 4) or greater.

[0101] Here, length Tmax is defined. Length Tmax is the maximum thickness of the W (tungsten) film formed on the sidewalls of the opening, which is the length at which the stress on the wafer is equal to or less than a specified allowable value. The specified allowable stress value is determined so that the amount of wafer warpage caused by stress is sufficiently minimized. By setting the thickness of the W (tungsten) film formed on the sidewalls of the opening to be equal to or less than Tmax, the reliability of the semiconductor device is improved.

[0102] To prevent wafer warpage, the film formed on the sidewalls of the opening must have a thickness, L2 / 2, that satisfies L2 / 2 ≤ Tmax. In other words, L2 ≤ 2Tmax. A film with a thickness of L2 / 2 formed on the sidewalls of the opening has a film thickness of Tmax or less, thereby reducing stress on the wafer. In other words, to reduce stress on the wafer, the length, L2, of plug 40 in the Y direction must be set to 2Tmax or less.

[0103] To more satisfactorily fill the opening, L2 is preferably ≤ (5 / 3) Tmax. A film with a thickness of (3 / 5) L2 formed on the sidewall of the opening has a film thickness of Tmax or less, thereby reducing stress on the wafer. More preferably, L2 is ≤ (4 / 3) Tmax.

[0104] For example, by forming plug 40 so that L2 ≤ (4 / 3)Tmax, L1 can be increased arbitrarily without exceeding LG. This is because the W (tungsten) film is formed thinly in the Y direction to prevent wafer warpage. Furthermore, by preventing the formation of voids, the opening can be filled satisfactorily. In other words, the formation of defects in plug 40 can be prevented.

[0105] Because L1 can be determined without considering the effect of the W film thickness on wafer warpage, the length of the region where the plug 40 contacts the second semiconductor region 22 or the third semiconductor region 23 can be increased in the X direction to increase the contact area. This reduces on-resistance and facilitates the discharge of carriers from the semiconductor substrate 20 to the plug 40 during switching, thereby reducing switching losses. By reducing switching losses, power consumption is reduced, and a semiconductor device with improved switching performance can be provided.

[0106] Since L1 can be determined without considering the influence of the film thickness of W on wafer warpage, according to this embodiment, when the range of the value of the gap LG between the gate regions 30 in the X direction is wide, the plug 40 with satisfactory embedding properties can be formed. The wide range of the value of the gap LG will be described below in comparison with the first reference example and the second reference example.

[0107] Furthermore, according to this embodiment, multiple third semiconductor regions 23 are arranged in the Y direction, and plugs in contact with the third semiconductor regions 23 can be formed, or plugs 40 in contact with the second semiconductor region 22 can be formed between third semiconductor regions 23 spaced apart from each other in the Y direction. Current density in the XY plane can also be controlled by varying the layout of the third semiconductor regions 23 or the layout of the plugs 40. This increases design freedom and controls the heat generated by current flow, thereby improving the reliability of the semiconductor device.

[0108] The third semiconductor region 23 serves as a current path when the semiconductor device 1 is in the on-state. In other words, the shorter the distance between the multiple plugs 40 in contact with the third semiconductor region 23, that is, as the dispersion of the multiple plugs 40 in contact with the third semiconductor region 23 in the XY plane decreases, the higher the current density in the on-state. Conversely, by increasing the dispersion of the multiple plugs 40 in contact with the third semiconductor region 23 in the XY plane, the current density can be reduced, thereby reducing the locally generated heat.

[0109] For example, plugs 40 adjacent to each other in the Y direction may be located between third semiconductor regions 23 spaced apart from each other in the Y direction. That is, by increasing the proportion of plugs 40 in contact with the second semiconductor region 22, current density and generated heat can be reduced. Furthermore, by increasing the contact area between the second semiconductor region 22 and the plugs 40, a wide carrier discharge path can be formed, thereby reducing switching losses.

[0110] After reducing the generated heat, for example, the plugs 40 adjacent to each other in the Y direction may be allowed to contact the third semiconductor region 23 at a portion, thereby increasing the current density. In a region where heat dissipation is relatively high, the current density may be designed to be higher.

[0111] Furthermore, some plugs 40 may be arranged so as to straddle the second semiconductor region 22 and the third semiconductor region 23 in the Y direction. By varying the positional relationship between the third semiconductor region 23 and the plugs 40, the degree of dispersion of the plurality of plugs 40 in contact with the third semiconductor region 23 within the XY plane may be adjusted. In other words, by adjusting the configuration of the third semiconductor region 23 and the configuration of the plugs 40, the amount of heat generated and the current density may be optimized according to the electrical characteristics of the semiconductor device.

[0112] The degree of dispersion of the plurality of plugs 40 in contact with the third semiconductor region 23 in the XY plane can be varied. For example, the degree of dispersion can be increased at the end of the active region AR shown in FIG1 . This can reduce heat generation at the end of the active region AR and improve reliability.

[0113] According to this embodiment, the current density in the XY plane can be controlled by the layout of the plug 40 without having to change the layout of the third semiconductor region 23. This increases the design freedom for controlling the current density. Furthermore, in areas of the XY plane where it is desirable to reduce heat generation, the current density can be reduced by locally changing the positional relationship between the third semiconductor region 23 and the plug 40. Furthermore, the layout of the third semiconductor region 23 can be changed to adjust the layout of the third semiconductor region 23 and the layout of the plug 40, further increasing the design freedom.

[0114] Furthermore, for a given layout of the third semiconductor region 23, the range of options can be expanded by adjusting the configuration of the plugs 40, compared to controlling the current simply by changing the layout of the third semiconductor region 23. By appropriately selecting the configuration of the plugs 40, the electrical characteristics of the semiconductor device can be improved. In other words, in addition to adjusting the layout of the third semiconductor region 23, the current can be further controlled by arranging the plugs 40 in the X and Y directions.

[0115] (Modification of the first embodiment)

[0116] Next, we will refer to Figure 3 A semiconductor device 1 according to a modification of the first embodiment is described. Figure 3 It is an enlarged plan view of the semiconductor device 1 according to a modification of the first embodiment. Figure 3 and Figure 1B The difference between them is the cross-sectional shape of the plug 40 in the XY plane. Figure 3Shows the case where the plug 40 has an elliptical shape, which has a length L1 in the X direction and a length L2 in the Y direction. The length L1 in the X direction is the length of the major axis of the ellipse, and the length L2 in the Y direction is the length of the minor axis of the ellipse. For example, L2 < L1, L2 ≤ 2Tmax. A relationship of L2 ≤ (5 / 3)Tmax or L2 ≤ (4 / 3)Tmax can be established.

[0117] In addition, the cross-sectional shape of the plug 40 in the XY plane is not limited to Figure 1B the rectangle shown or Figure 3 the ellipse shown. For example, the cross-sectional shape can be an oblong or a polygon, or a polygon with rounded corners.

[0118] More generally, any point within the figure (e.g., a rectangle) representing the cross-sectional shape of the plug 40 in the XY plane is located within a distance of Tmax from at least one point on the outer periphery of the figure. The length of the cross-sectional shape of the plug 40 in at least one direction in the XY plane is 2Tmax or less. When forming the plug 40, W (tungsten) with a thickness of Tmax or less can be used to sufficiently fill the opening.

[0119] For example, in Figure 3 the elliptical shape shown, the length L2 of the minor axis ≤ 2Tmax. The distances between the center of the ellipse and a certain point on the ellipse circumference in two directions in the Y direction (minor axis direction) are equal to or less than Tmax. That is, the center of the ellipse can be sufficiently filled with a tungsten film with a film thickness of Tmax or less from the side walls of the opening. Figure 3 The same applies to any point within the ellipse of the cross-sectional shape of the plug 40 shown.

[0120] In addition, the cross-sectional shape of the plug 40 in the XY plane can be curved, for example, it can be an L shape. Or, the cross-sectional shape can be a cross shape.

[0121] That is, the shape of the plug 40 is not limited to an ellipse, but can be any shape that can prevent defects from forming in the plug 40. A figure with long sides and short sides (e.g., a rectangle) is preferred because this can prevent defect formation on the short sides and make the area where the plug 40 and the semiconductor substrate 20 contact each other occupy a larger length at the long sides. In this specification, a shape with long sides and short sides is defined as a "rectangle"

[0122] The present disclosure is not limited to Figure 1B the semiconductor device 1 according to the first embodiment shown, for example, by Figure 3The modified example of the first embodiment shown can prevent the formation of defects in plug 40 and improve the reliability of the semiconductor device. At the same time, by adopting a wider contact area between plug 40 and second semiconductor region 22, switching losses can be reduced and the switching performance of the semiconductor device can be improved. The modified example of the first embodiment has been described above.

[0123] (First Reference Example)

[0124] Next, we will refer to Figure 4 and Figure 5 A semiconductor device 101 according to a first reference example will be described. Differences from the first embodiment will be described in detail. Figure 4 and Figure 5 An enlarged plan view and a cross-sectional view of the semiconductor device 101 according to the first reference example are respectively shown. Figure 4 This is an enlarged plan view showing the internal wiring structure. Figure 5 Yes Display Figure 4 A cross-sectional view of the semiconductor device taken along line DD' is shown.

[0125] First, refer to Figure 4 A plan view of a first reference example is shown. In a semiconductor device 101, plugs 140 are arranged in two rows in the X direction and extend in the Y direction. Multiple plugs 140 are provided between multiple gate regions 130 arranged in the X direction and extending in the Y direction. Plugs 140 are in contact with the second semiconductor region 122 and the third semiconductor region 123 of a semiconductor substrate 120.

[0126] The gate region 130 includes a gate electrode 132 and a gate insulating film 131 covering the gate electrode 132 . The gate electrode 132 and the gate insulating film 131 extend in the Y direction. The gate electrode 132 is electrically insulated from the semiconductor substrate 120 .

[0127] The second semiconductor region 122 and the third semiconductor region 123 are semiconductor regions of different conductivity types. For example, the second semiconductor region 122 is a p-type base region, and the third semiconductor region 123 is an n-type emitter region.

[0128] The width of the plug 140 in the semiconductor device 101 according to the first reference example in the X direction is L4, and the distance between the plugs 40 arranged in two rows in the X direction is L5. Furthermore, the distance between adjacent gate regions 130 in the X direction is LG.

[0129] Next, we will refer to Figure 5 A DD' cross-sectional view of the semiconductor device 101 according to the first reference example is described. The plug 140 extends from the first electrode 111 through the interlayer insulating film 150 to the semiconductor substrate 120. Figure 5In the DD′ cross section shown, the plug 140 is in contact with the third semiconductor region 123 .

[0130] The gate region 130 is filled with a gate electrode 132 and a gate insulating film 131 covering the gate electrode 132. The gate insulating film 131 reaches the first semiconductor region 121 of the semiconductor substrate 120. The gate insulating film 131 is in contact with the second semiconductor region 122.

[0131] exist Figure 4 and Figure 5 In the embodiment, 2L4+L5≤LG, two rows of plugs 140 are provided in the X direction. If 2L4+L5>LG, two rows of plugs 140 cannot be formed between the gate regions 130. In other words, openings for embedding two rows of plugs 140 cannot be formed between the gate regions 130.

[0132] An opening is formed by digging the semiconductor substrate 120 and the interlayer insulating film 150 to embed the plug 140. The plug 140 is formed by forming a W (tungsten) film in the opening. Figure 5 The plug 140 shown needs to form two rows of openings with a width of L4 at an interval of L5 in the X direction.

[0133] Generally speaking, L4 cannot be infinitely small. L4 cannot be set to be equal to or less than Lmin. The length Lmin is determined based on the excavation accuracy of the semiconductor substrate, and L4 ≥ Lmin. When forming an opening for embedding W (tungsten), the processing accuracy of excavating the semiconductor substrate 120 and the interlayer insulating film 150 is limited. In other words, the processing accuracy during the excavation process can determine the minimum value of L4 that can be achieved. In this way, the length Lmin can be defined as the minimum value of L4 determined based on the constraints of the processing accuracy. In other words, Lmin can be defined as the minimum diameter of the opening to be set in the semiconductor substrate.

[0134] Similarly, L5 is also limited by machining accuracy, and the minimum achievable value of L5 can also be determined by machining accuracy. For example, because the machining accuracy of the excavated opening and the machining accuracy of the unexcavated area (tabletop) are essentially the same, the inequality L5 ≥ Lmin holds. The following discussion assumes that the minimum value of both L4 and L5 is Lmin.

[0135] If LG<3Lmin, then due to the limitation of machining accuracy when forming the opening, 2L4+L5(≥3Lmin)>LG holds true, so it is difficult to Figure 4 and Figure 5 As shown, two rows of plugs 140 are formed in the X direction. That is, for the semiconductor device 101 of the first reference example, if LG<3Lmin, it is difficult to form the plugs 140.

[0136] In addition, according to the first reference example, if LG is large, it may not be possible to increase the length in the X direction of the region where the plug 140 and the semiconductor substrate 120 contact each other. This is because, if L4 > 2Tmax, a film thickness of at least Tmax or greater is required for W to avoid generating voids, which increases the stress on the wafer and promotes wafer warping. To ensure the reliability of the semiconductor device, it is preferable to set the length L4 within the range of L4 ≤ 2Tmax. To ensure flatness, it is best to set the length within the range of L4 ≤ (4 / 3)Tmax. For simplicity, the case of L4 ≤ 2Tmax will be described below, but the cases of L4 ≤ (5 / 3)Tmax and L4 ≤ (4 / 3)Tmax are the same.

[0137] If two rows of plugs 140 are formed in the X direction and the reliability of the semiconductor device is ensured, the length in the X direction of the region where the plug 140 and the semiconductor substrate 120 contact each other cannot be greater than 4Tmax. That is, it is not necessarily the case that the length L4 is set proportionally larger with respect to the interval LG in the X direction between the gate region 130, and it is difficult to increase the contact area between the plug 140 and the semiconductor substrate 120 according to the value of LG.

[0138] Specifically, if the value of LG ranges from 4Tmax + Lmin < LG, it is difficult to increase the contact area between the plug 140 and the semiconductor substrate 120 in the first reference example. This is because L5 requires a minimum length Lmin, and even if the value of LG increases to more than 4Tmax + Lmin, each of the two rows of plugs 140 can only have a maximum width of 2Tmax.

[0139] To prevent an increase in stress and wafer warping when LG increases to the range of LG > 4Tmax + Lmin, L4 is restricted to a length that satisfies L4 ≤ 2Tmax, and the length of the portion where the plug 140 is not formed is increased (i.e., the length of L5 or the length in the X direction between the plug 140 and the gate region 130). Therefore, it is difficult to increase the contact area between the plug 140 and the semiconductor substrate 120 according to the value of LG. Since it is difficult to increase the contact area between the plug 140 and the semiconductor substrate 120, it is difficult to promote the discharge of carriers in the off state.

[0140] In summary, for the semiconductor device 101 of the first reference example, if LG < 3Lmin, it is difficult to form the plug 140 between the gate regions 130. In addition, if 4Tmax + Lmin < LG, as LG increases beyond 4Tmax + Lmin, it is difficult to increase the contact area between the plug 140 and the semiconductor substrate 120. That is to say, it can be said that the structure in the first reference example is only applicable to LG within the range of 3Lmin ≤ LG ≤ 4Tmax + Lmin.

[0141] On the other hand, for the semiconductor device 1 of the first embodiment, the plug 40 can be formed regardless of the interval LG in the X direction of the gate regions 30. In particular, even if (Lmin <) LG < 3Lmin, the plug 40 can be formed in the semiconductor device 1.

[0142] In addition, for the semiconductor device 1 of the first embodiment, if LG is large, L1 can also increase proportionally to LG, and the contact area between the plug 40 and the semiconductor substrate 20 can increase according to the value of LG. According to the semiconductor device 1 of the first embodiment, even in the range of LG values where it is difficult to increase the contact area between the plug 140 and the semiconductor substrate 20 in the first reference example, i.e., 4Tmax + Lmin < LG, the contact area between the plug 40 and the semiconductor substrate 20 can be increased according to LG. Therefore, the discharge of carriers in the off state can be promoted, and the switching loss can be reduced.

[0143] For the semiconductor device 1 of the first embodiment, the reliability and performance of the semiconductor device can be improved within a wider range of LG than in the first reference example. That is to say, the configuration of the gate regions ३० is more diverse.

[0144] (Second reference example)

[0145] Next, reference will be made to Figure 6 Describe the semiconductor device 102 according to the second reference example.

[0146] Figure 6 is an enlarged plan view showing the semiconductor device 102 according to the second reference example. The semiconductor device 102 according to the second reference example is different from the semiconductor device 101 according to the first reference example in that the plugs 140 are arranged in a row in the X direction and the plugs 140 extend in the Y direction. The width of the plugs 140 arranged in a row in the X direction is called L6. Similar to the first reference example, the interval of the gate regions 130 in the X direction is called LG.

[0147] For the semiconductor device 102 of the second reference example, if L6 is less than or equal to LG, the plug 140 can be formed. In other words, using the length Lmin determined according to the excavation accuracy of the length L6, if LG ≥ Lmin, the plug 140 can be formed.

[0148] On the other hand, if L6 > 2Tmax, it is difficult to prevent the formation of defects in the plug 140 while preventing wafer warping. That is, in order to ensure the reliability of the semiconductor device, it is preferable that L6 has a length satisfying L6 ≤ 2Tmax.

[0149] In the semiconductor device 102 according to the second reference example, in order not to impair the reliability of the semiconductor device, it is necessary to form the plug 140 within the range where L6 ≤ 2Tmax. As LG increases within the range of LG > 2Tmax, it becomes difficult to increase the contact area between the plug 140 and the semiconductor substrate 120 according to the increase in LG.

[0150] In summary, for the semiconductor device 102 of the second reference example, only for LG within the range of Lmin ≤ LG ≤ 2Tmax, the contact area between the plug 140 and the semiconductor substrate 120 can be increased to promote the discharge of carriers and improve the performance of the semiconductor device.

[0151] On the other hand, for the semiconductor device 1 of the first embodiment, L1 is set to be larger according to LG. Therefore, even for LG where 2Tmax < LG, the contact area between the plug 40 and the semiconductor substrate 20 can be increased to promote the discharge of carriers and improve the switching performance of the semiconductor device.

[0152] The semiconductor device 102 according to the second reference example has been described above.

[0153] Next, the semiconductor device 101 according to the first reference example and the semiconductor device 102 according to the second reference example will be described in comparison with the semiconductor device 1 according to the first embodiment. Generally speaking, if LG is within the range of LG < Lmin or 2Tmax < LG, the second reference example is not suitable, and if LG is within the range of LG < 3Lmin or 4Tmax + Lmin < LG, the first reference example is also not suitable. Combining these two inequalities, for simplicity, assuming 2Tmax < 3Lmin, if LG is set within the ranges of LG < Lmin (from the second reference example), 2Tmax < LG < 3Lmin (2Tmax < LG from the second reference example and LG < 3Lmin from the first reference example), or 4Tmax + Lmin < LG (from the first reference example), the structures in both the first reference example and the second reference example are not suitable.

[0154] On the other hand, in the semiconductor device 1 according to the first embodiment, for any LG value greater than Lmin, the contact area between the plug 140 and the semiconductor substrate 20 can be increased.

[0155] In the semiconductor device 101 according to the first reference example and the semiconductor device 102 according to the second reference example, if the interval LG of the gate regions 130 in the X direction is within a specific range, it is difficult to improve the performance.

[0156] That is, according to the value of LG, it is necessary to select which one of the semiconductor device 101 according to the first reference example or the semiconductor device 102 according to the second reference example to apply each time. In addition, there is a problem that there is an LG range (2Tmax < LG < 3Lmin or 4Tmax + Lmin < LG), within which it is impossible to efficiently form the plug 140 in either the semiconductor device 101 according to the first reference example or the semiconductor device 102 according to the second reference example.

[0157] Here, "efficiently forming the plug 140" means that as LG increases, the contact area between the plug 140 and the semiconductor substrate 20 can be increased according to LG. On the contrary, when it is difficult to increase the contact area between the plug 140 and the semiconductor substrate 20 in response to the increase of LG, it can be said that the plug 140 cannot be efficiently formed.

[0158] The length LG can be determined by the configuration of the semiconductor device. For example, based on characteristics such as the breakdown voltage required for the semiconductor device, the interval between the gate regions of the IGBT can be determined. Therefore, LG cannot be arbitrarily selected, and there may be a situation where it is necessary to form the gate region 30 such that the value of LG is within the range of 2Tmax < LG < 3Lmin or 4Tmax + Lmin < LG.

[0159] If the required LG value of the semiconductor device is within the range of 2Tmax < LG < 3Lmin or 4Tmax + Lmin < LG, neither the first reference example nor the second reference example is appropriate. That is, neither the first reference example nor the second reference example can efficiently form the plug 140.

[0160] In addition, for example, when focusing on the range of LG values for which the first reference example is suitable, that is, 3Lmin ≤ LG ≤ 4Tmax + Lmin, as the difference between 2Tmax and Lmin becomes smaller, the range of LG values satisfying the inequality is restricted. That is, if 2Tmax and Lmin become substantially the same length, the range of LG suitable for the structure in the first reference example becomes narrower. The same is true for the range of LG values suitable for the second reference example, that is, Lmin < LG < 2Tmax.

[0161] That is, for example, according to the first reference example and the second reference example, the more it is necessary to reduce the film thickness of the tungsten film by reducing the stress on the wafer, the more restricted the range of the LG value for efficiently forming the plug 140 becomes. As the range of the LG value becomes more restricted, the degree of freedom in designing the semiconductor device decreases.

[0162] The inequality of LG is as described above. On the other hand, the inequality of L1 may also need to be considered. When L1 is set to be smaller than LG by a certain value as a measure to cope with the X-direction alignment error when forming the plug 40, the inequality of L1 can be considered. That is, actually, it is not necessarily to set L1 to be equal to the length of LG (even if LG > Lmin, it is not necessarily possible to form the plug 40), and it may be appropriate to consider the inequality of the length L1.

[0163] For example, if Lmin < LG, the plug 40 as shown may not necessarily be formed. Figure 1B This is because when forming the plug 40 with L1 having a length equal to LG, due to the alignment error in the X direction, there is a concern that the plug 40 and the gate electrode 32 will be electrically connected. Therefore, it is considered that L1 is set to be smaller than LG due to the alignment error so that the plug 40 and the gate electrode 32 are not electrically connected. In this case, even if Lmin < LG, there is a problem that L1 < Lmin, which will be unachievable considering the etching accuracy.

[0164] On the other hand, if Lmin < L1, from the perspective of etching accuracy, the plug 40 as shown can be formed. Figure 1B That is, considering the alignment error, Lmin < LG and Lmin < L1 do not necessarily have the same meaning. Therefore, it is preferable to consider the inequality of LG and the inequality of L1.

[0165] In Figure 3 the semiconductor device 1 according to the first embodiment as shown, the inequality of LG can be rewritten as the inequality of L1. For example, the inequality 2Tmax < LG < 3Lmin can be rewritten as the inequality of L1 (2Tmax < L1 < 3Lmin). When the inequality of LG is rewritten as the inequality of L1, even if 2Tmax < L1 < 3Lmin or 4Tmax + Lmin < L1 (< 5Lmin), the semiconductor device 1 according to the first embodiment can form the plug 40.

[0166] Hereinafter, more generally, the case of forming n rows (n is a natural number) of plugs 140 (not shown) along the X direction between the gate regions 130 will be described. The first reference example corresponds to the case of n = 2, and the second reference example corresponds to the case of n = 1.

[0167] For example, if n = 3, three rows of plugs 140 with a width of L4 are formed in the X direction, and a semiconductor substrate 20 with a width of L5 is provided between the plugs 140. Therefore, since the relationship 3L4 + 2L5 ≤ LG must be satisfied, and Lmin ≤ L4 and Lmin ≤ L5, the relationship 5Lmin ≤ LG is required to form three rows of plugs 140. If three rows of plugs 140 are formed in the X direction, for LG within the range of LG < 5Lmin, it is difficult to form three rows of plugs 140 in the X direction.

[0168] In addition, if n = 3 and 6Tmax + 2Lmin < LG, it is difficult to proportionally increase the contact area between the plugs 140 and the semiconductor substrate 20, that is, it is difficult to efficiently form the plugs 140. In other words, if n = 3, the plugs 140 can only be efficiently formed within the range of 5Lmin ≤ LG ≤ 6Tmax + 2Lmin.

[0169] Therefore, a range of LG values (4Tmax + Lmin < LG < 5Lmin) exists between the range of LG values suitable for the second reference example (n = 2), that is, 3Lmin ≤ LG ≤ 4Tmax + Lmin, and the range of LG values suitable for the example of n = 3.

[0170] Through similar discussions, generally, if n rows of plugs 140 (n is a natural number) are formed in the X direction between the gate regions 130, the plugs 140 cannot be efficiently formed unless (2n - 1)×Lmin ≤ LG ≤ n×2Tmax + (n - 1)×Lmin.

[0171] As described above, when LG is within the range of 2Tmax < LG < 3Lmin, neither the second reference example (n = 1) nor the first reference example (n = 2) can efficiently form the plugs 140. Similarly, when LG is within the inequality range of n×2Tmax + (n - 1)×Lmin < LG < (2n + 1)×Lmin for a certain natural number n, it is difficult to efficiently form n rows of plugs 140 in the X direction.

[0172] That is, in the method of forming n rows of plugs 140 along the X direction, since the number of rows of plugs 140 formed in the X direction changes according to the value of LG, the manufacturing cost may increase.

[0173] In addition, it is obvious from the inequality (2n - 1)×Lmin < LG < n×2Tmax + (n - 1)×Lmin that for any natural number n, the more the thickness of the tungsten film must be reduced in order to reduce the stress on the wafer, the narrower the range of LG values suitable for forming n rows of plugs 14,0 will become.

[0174] On the other hand, for the semiconductor device 1 of the first embodiment, L1 can be set to a larger value according to LG regardless of the value of LG. Therefore, the contact area between the plug 40 and the semiconductor substrate 20 can be increased. That is, for a wider range of LG values, the plug 40 can be efficiently formed. Specifically, even for a certain natural number n, when LG is within the range of the inequality n×2Tmax+(n - 1)×Lmin < LG < (2n + 1)×Lmin, the plug 40 can be efficiently formed. Therefore, compared with the method of forming n rows of plugs 140 in the X direction, the degree of freedom in designing the semiconductor device is increased.

[0175] For the semiconductor device 1 of the first embodiment, the plug 40 can be efficiently formed even if the range of the LG value is wider. For example, even if the value of LG is restricted due to the electrical characteristics of the semiconductor device, the plug 40 can be efficiently formed. By increasing the selection range of the LG value, for example, when controlling the magnitude and distribution of the current flowing through the semiconductor device according to the configuration of the gate region 30, the selection range can be increased according to the optimization of current control. By appropriately selecting the value of LG, the electrical characteristics can be improved.

[0176] (Second Embodiment)

[0177] Next, reference will be made to Figure 7 and Figure 8A and Figure 8B to describe the semiconductor device 2 according to the second embodiment. The semiconductor device 2 according to the second embodiment is an example of a structure that can be realized by increasing the degrees of freedom in designing the third semiconductor region 23 and the plug 40.

[0178] Figure 7 and Figure 8A and Figure 8B are respectively an enlarged plan view and a cross-sectional view showing the semiconductor device 2 according to the second embodiment. Figure 7 is an enlarged plan view, Figure 8A showing Figure 7 the E - E' cross-section of the semiconductor device shown, Figure 8B showing Figure 7 the F - F' cross-section of the semiconductor device shown. In Figure 7 , the description of the same parts as in Figure 1B is omitted. In Figure 8A and Figure 8B 中,省略了与 Figure 2A 中相同部分的描述。

[0179] Figure 7The semiconductor device 2 according to the second embodiment shown includes third semiconductor regions 23 arranged between a plurality of gate regions 30 arranged along the X direction, with the third semiconductor regions 23 being offset from one another in the X and Y directions. That is, the plurality of third semiconductor regions 23 are arranged in the Y direction, and at least one group of the plurality of third semiconductor regions 23 is arranged offset from one another in the X direction. This means that at least one of the third semiconductor regions 23 is located between the gate regions 30 in the positive X direction, and at least one of the third semiconductor regions 23 is located between the gate regions 30 in the negative X direction. In other words, the third semiconductor regions 23 are not aligned in the Y direction.

[0180] Here, the expression “the third semiconductor region 23 is located in the positive (negative) direction of the X direction between the gate regions 30” means that the center of each of the plurality of third semiconductor regions 23 is located in the positive (negative) direction of the X direction relative to the center line MM′, wherein the center line MM′ is obtained by connecting points that are equidistant from two adjacent gate regions 30 in the X direction. Figure 7 As shown, in the third semiconductor region 23 located in the positive direction of the X direction, one end in the negative direction of the X direction can be located in the negative direction from the center line MM' to the X direction. According to this embodiment, even if the end of the third semiconductor region 23 in the negative direction of the X direction is located in the positive direction of the center line MM' in the X direction, satisfactory contact can be achieved by the plurality of plugs 40 arranged in the Y direction.

[0181] The gate region 30 includes a first gate insulating film 31a, a first gate electrode 32a, a second gate insulating film 31b, and a second gate electrode 32b. The first gate electrode 32a is covered with the first gate insulating film 31a. The second gate electrode 32b is covered with the second gate insulating film 31b. The first gate insulating film 31a and the second gate insulating film 31b are formed to be spaced apart from each other in the X direction.

[0182] The third semiconductor region 23 includes a region close to the first gate insulating film 31 a and a region close to the second gate insulating film 31 b .

[0183] That is, when comparing the distance between the third semiconductor region 23 and the first gate insulating film 31a in the X direction, and the distance between the third semiconductor region 23 and the second gate electrode 32b in the X direction, in the third semiconductor region 23, there are regions where the former is shorter than the latter, and regions where the former is longer than the latter.

[0184] In this manner, a plurality of plugs 40 are provided in the Y direction so as to be electrically connected to the third semiconductor regions 23 which are arranged offset from each other in the X direction. The positions of the plurality of third semiconductor regions are offset in the second direction (X direction). The positions of the plurality of plugs are also offset in the second direction (X direction). The length L1 of the plug 40 in the X direction is different from the length L2 in the Y direction. For example, L1 < L2 and L1 ≤ 2Tmax. In order to improve the flatness by preventing the generation of voids and more satisfactorily fill the plug 40, it is preferable that L1 ≤ (5 / 3)Tmax or less. More preferably, L1 ≤ (4 / 3)Tmax or less.

[0185] Figure 8A is a cross-sectional view taken along the line E-E' shown in Figure 7 . The third semiconductor region 23 is located in the X direction near one of the gate regions 30. In other words, the distance between the third semiconductor region 23 and the first gate insulating film 31a is shorter than the distance between the third semiconductor region 23 and the second gate insulating film 31b.

[0186] The plug 40 is provided to penetrate the interlayer insulating film 50 and electrically connect the first electrode 11 and the semiconductor substrate 20. The plug 40 may be covered with a barrier metal 41. The barrier metal 41 has, for example, a laminated structure containing Ti and TiN.

[0187] Figure 8A shows an example in which the plug 40 is formed on the third semiconductor region 23 near the center of the third semiconductor region 23. On the other hand, the plug 40 may penetrate the third semiconductor region 23 in the Z direction and reach the second semiconductor region 22. Further, the plug 40 is not limited to being formed near the center of the third semiconductor region 23 in the X direction, and the plug 40 may be formed at a position closer to or farther from the first gate insulating film 31a.

[0188] Figure 8B is a cross-sectional view taken along the line F-F' shown in Figure 7 . The third semiconductor region 23 is located near the gate region 30 in the X direction and on the opposite side in the X direction from Figure 8A . The distance between the third semiconductor region 23 and the first gate insulating film 31a is longer than the distance between the third semiconductor region 23 and the second gate insulating film 31b.

[0189] The semiconductor substrate 20 and the first electrode 11 are electrically connected to each other via the plug 40.

[0190] In the semiconductor device 2 of the present embodiment, the plug 4 is provided according to the configuration of the third semiconductor region 23, thereby improving the electrical connection between the third semiconductor region 23 and the plug 40 and the electrical connection between the semiconductor substrate 20 and the first electrode 11.

[0191] First, if Figure 6 As in the semiconductor device 102 of the second reference example shown in FIG. 1 , a description will be given by comparing with a case where an attempt is made to electrically connect to the third semiconductor region 23 using a single plug 140 extending in the Y direction. Figure 6 With the single plug 140 shown, there is a concern that the contact area between the plug 140 and the third semiconductor region 23 may be reduced when the third semiconductor region 23 is offset in the positive or negative direction of the X direction. Furthermore, there is a concern that electrical connection between the plug 140 and the third semiconductor region 23 may be at least partially impossible.

[0192] In addition, if Figure 7 As shown, when the third semiconductor region 23 includes a portion offset in the positive and negative directions of the X direction, as shown in FIG. Figure 6 As shown, there is a concern that a single plug 140 may not be able to sufficiently contact the third semiconductor region 23. That is, when the plug 140 is formed to contact the third semiconductor region 23 offset in one direction, it is difficult to contact the third semiconductor region 23 offset in another direction.

[0193] On the other hand, for Figure 7 In the semiconductor device 2 of the present embodiment shown, the arrangement of each of the plurality of plugs 40 can be adjusted in the X direction, so that the plugs 40 can be formed above each of the third semiconductor regions 23 that are offset in the X direction. Therefore, reliable contact between the plugs 40 and the third semiconductor regions 23 can be ensured.

[0194] For example, in Figure 8A In the above example, it is considered that the first semiconductor region 21 is an n-type drift layer and the second semiconductor region 22 is a p-type drift layer. - Type base layer, the third semiconductor region 23 is n + By applying a positive voltage to the gate electrode 32 relative to the first electrode 11, an n-type inversion layer is generated in the second semiconductor region 22, and the semiconductor device 2 is set to be in an on state. Figure 8A The structure shown is that the third semiconductor region 23 is located near the first gate electrode 32a among the plurality of gate electrodes 32. Therefore, the current flowing in the on state flows from the first semiconductor region 21 to the third semiconductor region 23 through the inversion layer mainly generated around the first gate insulating film 31a.

[0195] The current flowing to the third semiconductor region 23 flows to the first electrode 11 via the plug 40 electrically connected to the third semiconductor region 23, wherein the first electrode 11 is, for example, an emitter. In this embodiment, according to the configuration of the third semiconductor region 23, the plug 40 is arranged at Figure 8Aa position near a gate region 30 (first gate insulating film 31a and first gate electrode 32a) in. As compared with Figure 8A a case where the plug 40 is near the gate region 30 (second gate insulating film 31b and second gate electrode 32b) and the third semiconductor region 23 is not near this position, a more reliable electrical connection between the third semiconductor region 23 and the plug 40 can be ensured.

[0196] Figure 8B The same applies to the configuration of the third semiconductor region 23 and the plug 40 shown.

[0197] In this way, the plug 40 is set according to the configuration of the third semiconductor region 23. Therefore, with the semiconductor device 2 of the present embodiment, the electrical connection between the semiconductor substrate 20 and the first electrode 11 via the plug 40 can be improved. That is, for the semiconductor device 2 of the present embodiment, by diversifying the possible structures of the third semiconductor region 23, the degree of freedom in the design of the semiconductor device can be increased. For the specified layout of the third semiconductor region 23, the selection range can be expanded according to the optimization of current control, including the configuration of the plug 40 that is offset in the X direction between the gate regions 30. By appropriately selecting the layouts of the third semiconductor region 23 and the plug 40, the electrical characteristics can be further improved.

[0198] (Third Embodiment)

[0199] Figure 9 and Figure 10 are enlarged plan views and cross-sectional views showing a semiconductor device 3 according to the third embodiment. Figure 10 shows Figure 9 a cross-sectional view of the G - G' cross-section of the semiconductor device shown. Descriptions of the same parts as in the first embodiment will be appropriately omitted, and the differences will be described.

[0200] In the semiconductor device 3 according to this embodiment, the gate electrode 32 provided in the gate region 30 is electrically connected to the plug 40. In Figure 9 , for the gate region 30 extending in the Y direction in the Y direction, a plurality of plugs 40 are provided. In Figure 9 , the gate wiring 13 and the interlayer insulating film 50 shown in Figure 10 are omitted.

[0201] As shown in [[ID=​​​The plug 40 is electrically insulated from the semiconductor substrate 20 by the gate insulating film 31 .

[0203] Figure 10 It is along Figure 9 The cross-sectional view taken along the G-G' line. Figure 10 As shown in FIG, gate wiring 13 is electrically connected to gate electrode 32 via plug 40. Plug 40 is made of a metal such as W (tungsten). Gate electrode 32 is made of polysilicon, for example. Gate electrode 32 is, for example, the gate electrode of an IGBT, and gate wiring 13 is, for example, a gate wiring electrically connected to gate electrode 32. By applying a voltage to gate wiring 13, the potential of gate electrode 32 can be controlled.

[0204] The plug 40 may be covered with a barrier metal 41. The barrier metal 41 has a layered structure including, for example, Ti and TiN.

[0205] The semiconductor device 3 according to the present embodiment may include a first electrode 11 provided at a position adjacent to the first electrode 11. Figure 9 and Figure 10 The first electrode 11 is electrically connected to the third semiconductor region 23 of the semiconductor substrate 20 via a conductive member (not shown) provided in the interlayer insulating film 50. The third semiconductor region 23 is, for example, the emitter region of the IGBT.

[0206] In addition, the conductive member connecting the first electrode 11 and the semiconductor substrate 20 may be different from Figure 9 and Figure 10 In other words, a plug 40 different from the plug 40 shown in the drawings may electrically connect the semiconductor substrate 20 and the semiconductor substrate 20. Figure 9 The semiconductor device 3 according to this embodiment can be Figure 9 In the area not shown in FIG, there are Figure 1B and Figure 2A The structure shown.

[0207] That is, the potentials of the semiconductor substrate 20 and the gate electrode 32 can be controlled via the plurality of plugs 40. Figure 9 and Figure 10 With the structure not shown in FIG, the potential of the semiconductor substrate 20 can be controlled via the plug 40 , and the potentials of the emitter and gate electrodes of the IGBT can be individually controlled via different plugs 40 .

[0208] For the semiconductor device 3 of the present embodiment, since the plurality of plugs 40 are spaced apart from each other in the Y direction, the electrical connection between the gate wiring 13 and the gate electrode 32 can be improved regardless of the value of L7. For gate electrodes 32 of various shapes, the electrical connection can be improved by the plugs 40, and an inversion layer can be reliably formed in the semiconductor substrate 20.

[0209] In addition, by setting the shorter length of L1 and L2 to, for example, 2Tmax or less, it is possible to prevent the formation of defects in the plugs 40 while preventing wafer warping. By preventing the formation of defects, the reliability of the semiconductor device can be improved.

[0210] With the semiconductor device 3 of the present embodiment, plugs 40 having a length L1 proportional to L7 can be formed. As L7 increases, the contact area between the gate electrode 32 and the plug 40 can be increased.

[0211] In addition, for a certain natural number n, L7 may be within the range of the inequality n×2Tmax+(n - 1)×Lmin < L7 < (2n + 1)×Lmin.

[0212] By increasing the selection range of the L7 value, for example, when controlling the magnitude and distribution of the current flowing through the semiconductor device according to the configuration of the gate region 30, the selection range can be increased according to the optimization of the current control. By appropriately selecting the value of L7, the electrical characteristics can be improved.

[0213] In addition, by electrically connecting the gate electrode 32 and the gate wiring 13 via the plug 40, the potential of the gate electrode 32 can be controlled. The potentials of the plurality of gate electrodes 32 arranged in the X direction can be individually controlled by different plugs 40, and a multi-gate structure can be achieved by the plurality of plugs 40. By individually controlling the potential of the gate electrode 32, the loss during switching can be reduced, and the performance of the semiconductor device can be further improved.

[0214] In at least one of the embodiments described above, each of the plurality of plugs 40 arranged in the Y direction has a length L1 in the X direction and a length L2 in the Y direction, and at least one of L1 and L2 is formed to be shorter so as to be able to reduce the stress on the wafer. Therefore, by making the other of L1 and L2 longer, the contact area between the plug 40 and the semiconductor substrate 20 becomes larger, so that the performance of the semiconductor device can be improved within a wider value range of LG or L7. In addition, the formation of defects in the plugs 40 can be prevented, and the reliability of the semiconductor device can be improved.

[0215] Furthermore, the degree of design freedom within the value range of LG or L7 can be increased, and the degree of design freedom of the layout of the third semiconductor region 23 and the plug 40 can be increased. The range of selection of the value of LG or L7 or the layout of the third semiconductor region 23 and the plug 40 can be increased. By appropriately selecting the value of LG or L7 or the layout of the third semiconductor region 23 and the plug 40, the electrical characteristics of the semiconductor device can be improved by optimizing current control.

[0216] Hereinafter, a method of manufacturing a semiconductor device will be described.

[0217] Will refer to Figures 11 to 16 , a method for manufacturing the semiconductor device 1 according to the first embodiment is described.

[0218] In the following description, Figure 11 、 12 ,…and Figure 16 is with Figure 1B The cross-sectional view of the semiconductor device shown corresponds to the AA' cross-sectional view. That is, Figure 11 、 12 ,…and Figure 16 Shows the various manufacturing processes and Figure 1B A cross-sectional view of the semiconductor device at a position corresponding to the AA' cross section, Figure 1B This is the completed diagram.

[0219] In the description of the manufacturing method, the formation of the plug 40 will be described in detail, and since the formation of the gate region 30 , the semiconductor substrate 20 , and the second electrode 12 is not significantly different from a general manufacturing method, description of their formation will be omitted.

[0220] Figure 11 This is a cross-sectional view showing the process of providing an interlayer insulating film 50. Semiconductor device 1 includes a semiconductor substrate 20 and a gate region 30, although their manufacturing methods are not described. Semiconductor substrate 20 comprises, for example, Si, and is doped with, for example, N or P to form an n-type semiconductor layer, and doped with, for example, B to form a p-type semiconductor layer. Gate region 30 includes a gate insulating film 31 and a gate electrode 32. Gate insulating film 31 comprises, for example, silicon oxide. Gate electrode 32 is, for example, polycrystalline silicon.

[0221] like Figure 11 As shown in FIG, an interlayer insulating film 50 is provided on the semiconductor substrate 20 and the gate region 30. The interlayer insulating film 50 is, for example, an oxide film including silicon oxide formed by chemical vapor deposition (CVD).

[0222] Next, if Figure 12 As shown in FIG, a resist 60 is provided on the interlayer insulating film 50. For example, the resist 60 is selectively formed by a photolithography technique.

[0223] Next, if Figure 13 As shown in FIG, the opening 70 is provided by digging out the portion where the resist 60 is not provided. In the Y direction, a plurality of openings 70 are formed at intervals. The opening 70 is formed by, for example, reactive ion etching (RIE) or chemical dry etching (CDE). Figure 13 As shown in FIG, some of the plurality of openings 70 penetrate the third semiconductor region 23 and reach the second semiconductor region 22. Some of the openings 70 may also be located at the same Figure 13 In the cross section different from the AA′ cross section shown, the semiconductor region reaches the second semiconductor region 22 but does not contact the third semiconductor region 23 .

[0224] Next, the resist 60 is peeled off to form a conductive film 80, as shown in FIG. Figure 14 As shown. However, the barrier metal 41 may be formed before forming the conductive film 80. The barrier metal 41 has a layered structure containing, for example, Ti and TiN. For example, the barrier metal 41 is formed by CVD. The conductive film 80 contains, for example, W (tungsten). For example, the conductive film 80 is formed by CVD.

[0225] Next, if Figure 15 As shown in FIG, the conductive film 80 is partially removed by etching back, and the remaining portion is referred to as a plug 40.

[0226] Finally, if Figure 16 As shown in FIG, a first electrode 11 is provided on the plug 40 and the interlayer insulating film 50. The first electrode 11 comprises, for example, AlCu or AlSi. For example, the first electrode 11 is formed by sputtering. In this way, Figure 2A Configuration shown.

[0227] In the manufacturing method described above, in the process of embedding the conductive film 80 in the opening 70 to form the plug 40, for example, as described in the semiconductor device 1 according to the first embodiment, a plurality of plugs 40 are provided in the Y direction, so that the interval value ( Figure 1B The contact area between the plug 40 and the semiconductor substrate 20 is increased over a wider range of the LG shown in FIG. 1 . In addition, when the conductive film 80 is embedded in the opening 70 to form the plug 40, the opening 70 has, for example, a rectangular shape in the XY plane, so that the generation of voids can be prevented, thereby achieving satisfactory embedding while reducing the stress applied by the plug 40 to the semiconductor substrate 20.

[0228] The embodiments have been described above with reference to specific examples. However, the embodiments are not limited to these specific examples. That is, specific examples in which a person of ordinary skill in the art changes the design scheme are also included in the embodiments of the present invention, as long as they have the characteristics of these embodiments. The elements, their arrangement, materials, conditions, shapes, sizes, etc. in the specific examples described above are not limited to those illustrated and can be changed as appropriate.

[0229] In addition, the elements in the embodiments described above can be combined as much as technically possible, and the combined elements are also included in the protection scope of the embodiments of the present invention, as long as they have the characteristics of these embodiments. It should be understood that within the conceptual scope of these embodiments, those skilled in the art can make changes and modifications, and these changes and modifications are also included in the protection scope of these embodiments.

[0230] Although certain embodiments have been described, these embodiments have been presented by way of example only and are not intended to limit the scope of protection of the present invention. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions, and changes in form may be made to the embodiments described herein without departing from the spirit of the present invention. The appended claims and their equivalents are intended to cover such forms or modifications as fall within the scope and spirit of the present disclosure.

Claims

1. A semiconductor device comprising: semiconductor substrates; an interlayer insulating film provided on the semiconductor substrate; a first electrode provided on the interlayer insulating film; a second electrode disposed under the semiconductor substrate; a plurality of gate regions extending from the interlayer insulating film in a first direction to reach the semiconductor substrate, the first direction being a thickness direction of the semiconductor substrate, the plurality of gate regions being arranged in a second direction intersecting the first direction and extending along a third direction intersecting the first direction and the second direction; as well as A plurality of plugs are located between the gate regions in the second direction, have a length in the second direction greater than a length in the third direction, are spaced apart from each other in the third direction, and electrically connect the first electrode to the semiconductor substrate.

2. The semiconductor device according to claim 1, wherein A shape of each of the plugs in a plane including the second direction and the third direction is a rectangle or an ellipse.

3. The semiconductor device according to claim 2, wherein The semiconductor substrate comprises: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type, disposed on the first semiconductor region; The third semiconductor region of the first conductivity type is selectively provided on the second semiconductor region; and The fourth semiconductor region of the second conductivity type is provided between the second electrode and the first semiconductor region, The gate region includes: a gate electrode embedded in the gate region; and A gate insulating film covers the gate electrode.

4. The semiconductor device according to claim 3, wherein The third semiconductor region includes a plurality of sub-regions disposed between the plurality of gate regions and spaced apart from each other in the third direction.

5. The semiconductor device according to claim 4, wherein At least one of the plugs is in contact with the second semiconductor region and is provided between two of the sub-regions of the third semiconductor region. The semiconductor device according to claim 5 , wherein: At least some of the plurality of plugs arranged adjacent to each other in the third direction are in contact with the third semiconductor region.

7. The semiconductor device according to claim 5, wherein At least some of the plurality of plugs arranged adjacent to each other in the third direction are located between two of the sub-regions of the third semiconductor region.

8. The semiconductor device according to claim 1, wherein The depth D of each of the plugs in the first direction and the length L1 of each of the plugs in the second direction satisfy the following relationship: <D / L1≤2。 9. The semiconductor device according to claim 1, wherein Each of the plugs contains W.

10. The semiconductor device according to claim 9, wherein The semiconductor device further includes: A barrier metal covering each of the plugs and including Ti and TiN.

11. A semiconductor device comprising: semiconductor substrates; an interlayer insulating film provided on the semiconductor substrate; a first electrode provided on the interlayer insulating film; a second electrode disposed under the semiconductor substrate; a plurality of gate regions extending from the interlayer insulating film in a first direction to reach the semiconductor substrate, the first direction being a thickness direction of the semiconductor substrate, the plurality of gate regions being arranged in a second direction intersecting the first direction and extending along a third direction intersecting the first direction and the second direction; a plurality of plugs located between the gate regions in the second direction, spaced apart from each other in the third direction, and electrically connecting the first electrode to the semiconductor substrate; as well as The plurality of third semiconductor regions in the semiconductor substrate are disposed between the plurality of gate regions and are not aligned in the third direction.

12. The semiconductor device according to claim 11, wherein The third semiconductor regions are spaced apart from each other in the third direction.

13. The semiconductor device according to claim 11, wherein Positions of the plurality of third semiconductor regions are shifted in the second direction.

14. The semiconductor device according to claim 13, wherein Positions of the plurality of plugs are offset in the second direction.

15. The semiconductor device according to claim 11, wherein Some of the third semiconductor regions are located on a first side of a line extending along the third direction, and some of the third semiconductor regions are located on a second side of the line opposite to the first side.

16. The semiconductor device according to claim 11, wherein One of the plurality of gate regions includes a first gate insulating film and a second gate insulating film spaced apart from the first gate insulating film in the second direction; some of the third semiconductor regions are closer to the first gate insulating film than to the second gate insulating film; Some of the plurality of plugs are closer to the first gate insulating film than to the second gate insulating film.

17. The semiconductor device according to claim 11, wherein Each of the plugs contains W.

18. A semiconductor device comprising: semiconductor substrates; an interlayer insulating film provided on the semiconductor substrate; a first electrode provided on the interlayer insulating film and connected to the semiconductor substrate; a gate wiring provided on the interlayer insulating film so as to be spaced apart from the first electrode; a second electrode disposed under the semiconductor substrate; a plurality of gate regions extending from the interlayer insulating film in a first direction to reach the semiconductor substrate, the first direction being a thickness direction of the semiconductor substrate, the plurality of gate regions being arranged in a second direction intersecting the first direction and extending along a third direction intersecting the first direction and the second direction, each of the gate regions including a gate electrode embedded in the gate region and a gate insulating film covering the gate electrode; as well as A plurality of plugs are spaced apart from each other in the third direction and electrically connect the gate wiring to the gate electrode in each of the gate regions.

19. The semiconductor device according to claim 18, wherein The length of the plug in the second direction is greater than the length in the third direction.

20. The semiconductor device according to claim 18, wherein Each of the plugs contains W.

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