Semiconductor device

Abstract

The invention discloses a semiconductor device which comprises a first semiconductor body which comprises a first ohmic contact region and a second ohmic contact region which are different in conduction type and located on a first surface, and a buried layer which is the same as the second ohmic contact region in conduction type and located on the sides, close to a second surface, of the first ohmic contact region and the second ohmic contact region; the second semiconductor body is located on the first surface and comprises a first semiconductor layer, a third semiconductor layer and a second semiconductor layer which is different from the first semiconductor layer and the third semiconductor layer in conduction type and located between the first semiconductor layer and the third semiconductor layer; a first electrode electrically connected to the first ohmic contact region and the third semiconductor layer; the first grid electrode is electrically connected with the second ohmic contact region and the first semiconductor layer; a second gate electrically connected to the second semiconductor layer; a first resistive material layer in contact with the second gate and the third semiconductor layer; and the second resistive material layer is in contact with the second grid electrode and the first semiconductor layer. The problem of device short circuit caused by miller capacitor charging and discharging is solved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor technology, and in particular to a semiconductor device. Background Art

[0002] Field-Effect Transistor (FET) is a semiconductor device that uses electric field effects to control current. Its core is to modulate channel conductivity by changing the gate voltage.

[0003] In related technologies, SiC MOSFET (Metal Oxide Semiconductor Field Effect Transistor) has lower switching losses than bipolar transistors such as IGBT (Insulate-Gate Bipolar Transistor), which makes it more competitive in high-frequency application scenarios, such as being used as a switching device in a bridge circuit.

[0004] However, since the SiC material itself has a high saturation carrier migration rate, the short-circuit withstand time of the planar SiC MOSFET is extremely short, so it is difficult for the drive circuit to effectively protect it in time. Moreover, when SiC MOSFET is used at a higher switching frequency, the higher switching speed will result in an increase in dv / dt. Especially in a bridge circuit, the rapid change of the switch node voltage will cause the Miller capacitor in the power MOSFET to charge and discharge rapidly, and this charge and discharge current will form a potential difference between the gate and source of the power MOSFET through the peripheral drive circuit. When this potential difference reaches a certain magnitude, it will cause the device to be mistakenly turned on, resulting in a short circuit between the upper and lower tubes, and eventually the device will burn out. Therefore, how to improve the short-circuit problem of semiconductor devices caused by the charging and discharging of the Miller capacitor in high-frequency applications has become a technical problem that needs to be solved urgently by people in this field. Summary of the Invention

[0005] An embodiment of the present invention provides a semiconductor device to improve the device short circuit problem caused by the charging and discharging of the Miller capacitor in high-frequency applications.

[0006] According to one aspect of the present invention, there is provided a semiconductor device comprising at least one cellular structure, wherein the cellular structure comprises:

[0007] A first semiconductor body comprising a first surface and a second surface disposed opposite to each other; the first semiconductor body comprising a first ohmic contact region and a second ohmic contact region of different conductivity types, both located on the first surface; the first semiconductor body further comprising a buried layer located on a side of the first ohmic contact region and the second ohmic contact region closer to the second surface; wherein the buried layer and the second ohmic contact region have the same conductivity type;

[0008] a second semiconductor body located on a first surface of the first semiconductor body; the second semiconductor body comprising a first semiconductor layer, a third semiconductor layer, and a second semiconductor layer located between the first semiconductor layer and the third semiconductor layer; wherein the first semiconductor layer and the third semiconductor layer have the same conductivity type as the second ohmic contact region; and the second semiconductor layer has the same conductivity type as the first ohmic contact region;

[0009] a first electrode and a first gate; the first electrode is electrically connected to the first ohmic contact region and the third semiconductor layer, and the first gate is electrically connected to the second ohmic contact region and the first semiconductor layer;

[0010] A first resistive material layer, a second resistive material layer and a second gate; the second gate is located between the first resistive material layer and the second resistive material layer; wherein the second gate is electrically connected to the second semiconductor; the first resistive material layer is in contact with the second gate and the third semiconductor layer, and the second resistive material layer is in contact with the second gate and the first semiconductor layer.

[0011] Optionally, the first semiconductor body further includes a first JFET region extending along a first direction and a second JFET region extending along a second direction; the first direction and the second direction intersect each other, and the first direction is a direction from the first surface to the second surface;

[0012] The first JFET region and the second JFET region are connected, and the second JFET region is located between the buried layer and the second ohmic contact region.

[0013] Optionally, the first resistive material layer, the second resistive material layer and the second gate are all located on a side of the second semiconductor body away from the first semiconductor body;

[0014] In the second semiconductor body, the second semiconductor layer is located on the surface of the first semiconductor layer close to the first semiconductor body and the sidewall of the first semiconductor layer; the third semiconductor layer is located on the surface of the second semiconductor layer close to the first semiconductor body and the sidewall of the second semiconductor layer away from the first semiconductor layer.

[0015] Optionally, a surface of the second semiconductor body away from the first semiconductor body is a plane;

[0016] A surface of the second semiconductor body away from the first semiconductor body includes a first region surface, a third region surface, and a second region surface located between the first region surface and the third region surface;

[0017] The second region surface is the surface of the second semiconductor layer away from the first semiconductor body, the first region surface is the surface of the first semiconductor layer away from the first semiconductor body, and the third region surface is the surface of the third semiconductor layer away from the first semiconductor body; the second gate is located on the second region surface, the first resistive material layer extends from the second gate along the second region surface to the covering part of the third region surface, and the second resistive material layer extends from the second gate along the second region surface to the covering part of the first region surface.

[0018] Optionally, the first electrode and the first gate are located on opposite sides of the second semiconductor body;

[0019] The semiconductor device further includes a first insulating layer and a second insulating layer; wherein the first insulating layer is located between the first electrode and the sidewall of the second semiconductor body; and the second insulating layer is located between the first gate and the sidewall of the second semiconductor body.

[0020] Optionally, the cellular structure further includes:

[0021] a first ohmic contact layer, located on a surface of the first ohmic contact region away from the second surface, the first electrode being electrically connected to the first ohmic contact region through the first ohmic contact layer;

[0022] and / or, a second ohmic contact layer located on a surface of the second ohmic contact region away from the second surface, the first gate being electrically connected to the second ohmic contact region through the second ohmic contact layer;

[0023] and / or a third ohmic contact layer located on a portion of the surface of the third region, wherein the first electrode is electrically connected to the third semiconductor layer through the third ohmic contact layer;

[0024] and / or, a fourth ohmic contact layer is located on a portion of the surface of the first region, and the first gate is electrically connected to the first semiconductor layer through the fourth ohmic contact layer;

[0025] And / or, a fifth ohmic contact layer is located on a portion of the surface of the second region, and the second gate is electrically connected to the second semiconductor layer through the fifth ohmic contact layer.

[0026] Optionally, the cellular structure further includes:

[0027] a third insulating layer, located on a side of the first resistive material layer, the second resistive material layer, the first gate, and the second gate away from the first semiconductor body;

[0028] The first electrode is also located on a side of the third insulating layer away from the first semiconductor body, and extends toward the first ohmic contact region along sidewalls of the third insulating layer, the first resistive material layer, and the second semiconductor body.

[0029] Optionally, the material of the first semiconductor body is different from the material of the second semiconductor body;

[0030] The material of the first semiconductor body includes silicon carbide; the material of the second semiconductor body includes silicon.

[0031] Optionally, the semiconductor device includes at least two of the cellular structures, and two adjacent cellular structures are mirror-symmetric in the second direction.

[0032] The technical solution provided by the embodiment of the present invention forms a second semiconductor body on the first surface of the first semiconductor body through heterogeneous integration, and uses the second semiconductor body, the first resistive material layer and the second resistive material layer to form a Miller clamp circuit, so that when a short circuit occurs due to crosstalk, the semiconductor device can be shut down in time to avoid damage, thereby improving the device short circuit problem caused by the charging and discharging of the Miller capacitor in high-frequency applications.

[0033] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0035] Figure 1 This is a circuit diagram of a half-bridge circuit provided in the related art;

[0036] Figure 2is a structural cross-sectional view of a semiconductor device provided by an embodiment of the present invention;

[0037] Figure 3 yes Figure 2 A working principle diagram of a Miller clamp circuit formed by the second semiconductor body, the first resistive material layer and the second resistive material layer in the structure shown;

[0038] Figure 4 1 is a circuit diagram of a half-bridge circuit provided by an embodiment of the present invention;

[0039] Figure 5 It is a structural cross-sectional view of another semiconductor device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0040] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0041] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0042] As mentioned in the background technology, in a bridge circuit, the rapid change of the switch node voltage will cause the Miller capacitor in the power MOSFET to charge and discharge rapidly, and this charge and discharge current will form a potential difference between the gate and source of the power MOSFET through the peripheral drive circuit. When this potential difference reaches a certain level, it will cause the device to turn on by mistake, resulting in a short circuit between the upper and lower tubes, and eventually the device will burn out. Figure 1 , Figure 1 This is a circuit diagram of a half-bridge application where the lower bridge transistor M2 is turned off and the upper bridge transistor M1 is in the process of turning on. Flows through the load. Since the power MOSFET is used in high-frequency scenarios, the upper bridge transistor M1 turns on in a very short time. Figure 1 At the SW point shown in the figure, the voltage drop at this point changes rapidly during the opening process. This voltage change will affect the Miller capacitance of the lower bridge transistor M2. Charge and discharge are performed on the A potential difference will be formed in the peripheral drive circuit loop, causing the originally turned-off lower bridge transistor M2 to be mistakenly turned on. At this time, the upper bridge transistor M1 has already been turned on, eventually causing The device is burned out if the terminal is short-circuited to GND terminal. Among them, the peripheral drive circuit includes gate resistor and for outputting gate voltage (e.g., turn-on voltage and shutdown voltage ) driving circuit. Capacitor is the capacitance formed between the gate and the source, is the capacitance formed between the drain and source.

[0043] In view of the above problems, an embodiment of the present invention provides a semiconductor device. Figure 2 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention, with reference to Figure 2 , the semiconductor device includes at least one cellular structure, the cellular structure including:

[0044] A first semiconductor body 10 includes a first surface and a second surface disposed opposite to each other; the first semiconductor body 10 includes a first ohmic contact region 121 and a second ohmic contact region 122 of different conductivity types, both located on the first surface; the first semiconductor body 10 further includes a buried layer 123 located on a side of the first ohmic contact region 121 and the second ohmic contact region 122 closer to the second surface, the buried layer 123 and the second ohmic contact region 122 having the same conductivity type;

[0045] The second semiconductor body 20 is located on the first surface of the first semiconductor body 10. The second semiconductor body 20 includes a first semiconductor layer 21, a third semiconductor layer 23, and a second semiconductor layer 22 located between the first semiconductor layer 21 and the third semiconductor layer 23. The first semiconductor layer 21 and the third semiconductor layer 23 have the same conductivity type as the second ohmic contact region 122. The second semiconductor layer 22 has the same conductivity type as the first ohmic contact region 121.

[0046] A first electrode 1 and a first gate G1; the first electrode 1 is electrically connected to the first ohmic contact region 121 and the third semiconductor layer 23, and the first gate G1 is electrically connected to the second ohmic contact region 122 and the first semiconductor layer 21;

[0047] A first resistive material layer 31, a second resistive material layer 32 and a second gate G2; the second gate G2 is located between the first resistive material layer 31 and the second resistive material layer 32; wherein the second gate G2 is electrically connected to the second semiconductor layer 22; the first resistive material layer 31 is in contact with the second gate G2 and the third semiconductor layer 23, and the second resistive material layer 32 is in contact with the second gate G2 and the third semiconductor layer 23.

[0048] Specifically, the first semiconductor body 10 can be formed by a single epitaxial growth process or multiple epitaxial growth processes. That is, the first semiconductor body 10 can be a single first semiconductor epitaxial layer 12 or a stacked structure formed by multiple first semiconductor epitaxial layers 12. The first semiconductor body 10 can also include a substrate 11, that is, the first semiconductor body 10 includes the substrate 11 and at least one first semiconductor epitaxial layer 12 formed on one side of the substrate 11. The material of the substrate 11 is the same as that of the first semiconductor epitaxial layer 12.

[0049] When the first semiconductor body 10 includes a substrate 11 and a first semiconductor epitaxial layer 12 , the second surface is a surface of the substrate 11 away from the first semiconductor epitaxial layer 12 , and the first surface is a surface of the first semiconductor epitaxial layer 12 farthest from the substrate 11 away from the substrate 11 . Figure 2 The first semiconductor body 10 shown includes a substrate 11 and a first semiconductor epitaxial layer 12 located on one side of the substrate 11. The first surface is the surface of the first semiconductor epitaxial layer 12 away from the substrate 11, and the second surface is the surface of the substrate 11 away from the first semiconductor epitaxial layer 12.

[0050] The first semiconductor epitaxial layer 12 includes a first ohmic contact region 121 and a second ohmic contact region 122 of different conductivity types, and a buried layer 123 of the same conductivity type as the second ohmic contact region 122. The buried layer 123 is located on the side of the first ohmic contact region 121 and the second ohmic contact region 122 that is closer to the substrate 11. The conductivity type of the first ohmic contact region 121 is the same as that of the first semiconductor epitaxial layer 12, both being the first conductivity type. The doping concentration of the first conductivity type ions in the first ohmic contact region 121 is greater than the doping concentration of the first conductivity type ions in the first semiconductor epitaxial layer 12. The conductivity type of the second ohmic contact region 122 is the second conductivity type. The second ohmic contact region 122 and the buried layer 123 can be formed by implanting ions of the second conductivity type into the first semiconductor epitaxial layer 12. The doping concentration of the second conductivity type ions in the second ohmic contact region 122 can be equal to or different from the doping concentration of the second conductivity type ions in the buried layer 123. In the embodiment of the present invention, both the first ohmic contact region 121 and the second ohmic contact region 122 are heavily doped regions. The first ohmic contact region 121 extends from the edge of the first surface toward the second ohmic contact region 122. The orthographic projection of the first ohmic contact region 121 on the substrate 11 is located within the orthographic projection of the buried layer 123 on the substrate 11. A portion of the orthographic projection of the second ohmic contact region 122 on the substrate 11 overlaps with the orthographic projection of the buried layer 123 on the substrate 11, while another portion of the orthographic projection of the second ohmic contact region 122 on the substrate 11 does not overlap with the orthographic projection of the buried layer 123 on the substrate 11.

[0051] The first electrode 1 contacts the first ohmic contact region 121, and the first gate G1 contacts the second ohmic contact region 122. The second surface of the first semiconductor body 10 also includes a second electrode 2. The first semiconductor body 10 is used to form a junction field-effect transistor (JFET). The first electrode can be a source electrode and the second electrode a drain electrode; alternatively, the second electrode can be a source electrode and the first electrode a drain electrode. The first gate G1 is used to control the formation and breaking of a channel between the buried layer 123 and the second ohmic contact region 122. When a channel is formed between the buried layer 123 and the second ohmic contact region 122, electrical conduction occurs between the first electrode 1 and the second electrode 2. Figure 2 In the structure shown, the first electrode 1 is the source electrode and the second electrode 2 is the drain electrode. It should be noted that the gate voltage is input from the second gate G2 and is divided by the second resistive material layer 32 to form the voltage of the first gate G1.

[0052] The second semiconductor body 20 is disposed on one side of the first semiconductor body 10 and is located on the first surface of the first semiconductor body 10. The second semiconductor body 20 can be formed by a single epitaxial growth or by multiple epitaxial growths. That is, the second semiconductor body 20 can be a single second semiconductor epitaxial layer or a stacked structure formed by multiple second semiconductor epitaxial layers. The second semiconductor body 20 includes a first semiconductor layer 21, a third semiconductor layer 23, and a second semiconductor layer 22 located between the first semiconductor layer 21 and the third semiconductor layer 23. Because the first semiconductor layer 21 and the third semiconductor layer 23 both have the same conductivity type as the second ohmic contact region 122, the second semiconductor layer 22 has the same conductivity type as the first ohmic contact region 121, and the first ohmic contact region 121 and the second ohmic contact region 122 have different conductivity types, in the second semiconductor body 20, the second semiconductor layer 22 has a different conductivity type from the first semiconductor layer 21, and the second semiconductor layer 22 has a different conductivity type from the third semiconductor layer 23.

[0053] The first conductivity type may be N-type, and the second conductivity type may be P-type, i.e., the conductivity type of the first ohmic contact region 121 is N-type, and the conductivity type of the second ohmic contact region 122 is P-type. Alternatively, the first conductivity type may be P-type, and the second conductivity type may be N-type, i.e., the conductivity type of the first ohmic contact region 121 is P-type, and the conductivity type of the second ohmic contact region 122 is N-type. A PN junction is formed between the second semiconductor layer 22 and the first semiconductor layer 21, and a PN junction is formed between the second semiconductor layer 22 and the third semiconductor layer 23. Figure 2 In the structure shown, the conductivity type of the first ohmic contact region 121 is N-type, and the conductivity type of the second ohmic contact region 122 is P-type.

[0054] The first electrode 1 is electrically connected to the third semiconductor layer 23, the first gate G1 is electrically connected to the first semiconductor layer 21, and the second gate G2 is electrically connected to the second semiconductor layer 22, thereby forming a BJT (bipolar junction transistor) on the first semiconductor body 10. Furthermore, the second gate G2 is positioned between the first resistive material layer 31 and the second resistive material layer 32. The first resistive material layer 31 contacts the second gate G2 and the third semiconductor layer 23, while the second resistive material layer 32 contacts the second gate G2 and the third semiconductor layer 23. This allows for the formation of a resistor between the second gate G2 and the first semiconductor layer 21, and a resistor between the second gate G2 and the third semiconductor layer 23. The first resistive material layer 31 and the second resistive material layer 32 are both high-resistance dielectric layers. For example, the materials of the first resistive material layer 31 and the second resistive material layer 32 include, but are not limited to, SIPOS (semi-insulating polysilicon). In this way, two current paths can be constructed between the first gate G1 and the first electrode 1 through the second semiconductor body 20 , the first resistive material layer 31 and the second resistive material layer 32 .

[0055] Figure 3 yes Figure 2 The working principle diagram of the Miller clamp circuit formed by the second semiconductor body 20, the first resistive material layer 31 and the second resistive material layer 32 in the structure shown in FIG. The first resistor R1 formed by the second resistive material layer 32 forms a forward voltage drop between the emitter of the BJT (the first gate G1 is equivalent to the emitter of the BJT) and the second gate G2, and the second resistor R2 formed by the first resistive material layer 31 forms a forward voltage drop between the second gate G2 and the collector of the BJT (the first electrode 1 is equivalent to the collector of the BJT). When the crosstalk current is large enough, the emitter junction of the BJT is forward biased, the collector junction is reverse biased, the BJT is turned on, and the crosstalk current flows from Transformed into , crosstalk current The current flows through the inside of the BJT, the voltage of the first gate G1 is clamped to the potential of the first electrode 1, and the JFET device formed by the first semiconductor body 10 is turned off, thereby preventing the bridge arm through device in the circuit from being damaged.

[0056] If we take the half-bridge circuit and the BJT as PNP type BJT as an example, the equivalent circuit diagram is as follows Figure 4The crosstalk current in the lower bridge transistor (junction field effect transistor J2) will first be divided across the first resistor R1 and the second resistor R2 to turn on the PNP type BJT. The gate and source ends of the lower bridge transistor (junction field effect transistor J2) are short-circuited through the conductive channel provided by the PNP type BJT, thereby turning off the lower bridge transistor (junction field effect transistor J2) to prevent a short circuit.

[0057] The technical solution provided by the embodiment of the present invention forms a second semiconductor body 20 on the first surface of the first semiconductor body 10 through heterogeneous integration, and uses the second semiconductor body 20, the first resistive material layer 31 and the second resistive material layer 32 to form a Miller clamp circuit, so that when a short circuit occurs due to crosstalk, the semiconductor device can be shut down in time to avoid damage, thereby improving the device short circuit problem caused by the charging and discharging of the Miller capacitor in high-frequency applications.

[0058] Based on the above embodiments, Figure 2 Optionally, the first semiconductor body 10 further includes a first JFET region 125 extending along a first direction X and a second JFET region 124 extending along a second direction Y. The first direction X is the direction from the first surface to the second surface, and the first direction X and the second direction Y are arranged intersectingly, for example, perpendicularly. The first JFET region 125 and the second JFET region 124 are connected, and the second JFET region 124 is located between the buried layer 123 and the second ohmic contact region 122. It can be understood that the first semiconductor epitaxial layer 12 located between the buried layer 123 and the second ohmic contact region 122 is used to form the second JFET region 124, and the first semiconductor epitaxial layer 12 located on the sidewalls of the buried layer 123 is used to form the first JFET region 125. In this embodiment of the present invention, by connecting the lateral JFET region (the second JFET region 124) and the vertical JFET region (the first JFET region 125) in series, a longer JFET region is formed, thereby enhancing the negative feedback effect of the JFET region on the saturation current and ultimately improving the short-circuit withstand time of the device.

[0059] Based on the above embodiments, Figure 2 Optionally, in the second semiconductor body 20, the second semiconductor layer 22 is located on the surface of the first semiconductor layer 21 close to the first semiconductor body 10 and the sidewall of the first semiconductor layer 21; the third semiconductor layer 23 is located on the surface of the second semiconductor layer 22 close to the first semiconductor body 10 and the sidewall of the second semiconductor layer 22 away from the first semiconductor layer 21; the first resistive material layer 31, the second resistive material layer 32 and the second gate G2 are all located on the side of the second semiconductor body 20 away from the first semiconductor body 10.

[0060] Specifically, the second semiconductor layer 22 is located on the surface of the first semiconductor layer 21 on the side close to the first semiconductor body 10 and on the sidewall of the first semiconductor layer 21. The cross-section of the second semiconductor layer 22 is L-shaped. The third semiconductor layer 23 is located on the surface of the second semiconductor layer 22 on the side close to the first semiconductor body 10 and on the sidewall of the second semiconductor layer 22 on the side away from the first semiconductor layer 21. The cross-section of the third semiconductor layer 23 is L-shaped. The second semiconductor layer 22 is located on the surface of the first semiconductor layer 21 on the side close to the first semiconductor body 10 and on the sidewall of the first semiconductor layer 21, and the third semiconductor layer 23 is located on the surface of the second semiconductor layer 22 on the side close to the first semiconductor body 10 and on the sidewall of the second semiconductor layer 22 on the side away from the first semiconductor layer 21. This ensures that the second semiconductor layer 22 is located between the first semiconductor layer 21 and the third semiconductor layer 23, meeting the requirement of forming two PN junctions. It also allows the second semiconductor layer 22 and the third semiconductor layer 23 to be exposed, facilitating electrical connection with the second gate G2 and the first electrode 1, respectively, and facilitating the placement of the first resistive material layer 31 and the second resistive material layer 32.

[0061] Based on the above embodiments, Figure 2 Optionally, the surface of the second semiconductor body 20 away from the first semiconductor body 10 is a plane; the surface of the second semiconductor body 20 away from the first semiconductor body 10 includes a first region surface, a third region surface, and a second region surface located between the first region surface and the third region surface;

[0062] Among them, the second area surface is the surface of the second semiconductor layer 22 away from the first semiconductor body 10, the first area surface is the surface of the first semiconductor layer 21 away from the first semiconductor body 10, and the third area surface is the surface of the third semiconductor layer 23 away from the first semiconductor body 10; the second gate G2 is located on the second area surface, the first resistive material layer 31 extends from the second gate G2 along the second area surface to the third area surface of the covering part, and the second resistive material layer 32 extends from the second gate G2 along the second area surface to the first area surface of the covering part.

[0063] Specifically, the second semiconductor layer 22 is located on the surface of the first semiconductor layer 21 on the side close to the first semiconductor body 10 and on the entire sidewall of the first semiconductor layer 21. The second semiconductor layer 22 located on the sidewall of the first semiconductor layer 21 is relatively wide, allowing it to support the second gate G2, part of the first resistive material layer 31, and part of the second resistive material layer 32. The third semiconductor layer 23 is located on the surface of the second semiconductor layer 22 on the side close to the first semiconductor body 10 and on the entire sidewall of the second semiconductor layer 22. The third semiconductor layer 23 located on the sidewall of the second semiconductor layer 22 is relatively wide, allowing it to have an area electrically connected to the first electrode 1 while also supporting another portion of the first resistive material layer 31.

[0064] In addition, the distance between the surface of the second semiconductor layer 22 located on the side wall of the first semiconductor layer 21 away from the first semiconductor body 10 and the first semiconductor body 10, and the distance between the surface of the third semiconductor layer 23 located on the side wall of the second semiconductor layer 22 away from the first semiconductor body 10 and the first semiconductor body 10 are both equal to the distance between the surface of the first semiconductor layer 21 away from the first semiconductor body 10 and the first semiconductor body 10, so that the surface of the second semiconductor body 20 away from the first semiconductor body 10 is flat, which can further facilitate the arrangement of the second gate G2, the first resistive material layer 31 and the second resistive material layer 32.

[0065] Based on the above embodiments, Figure 2 Optionally, the first electrode 1 and the first gate G1 are located on opposite sides of the second semiconductor body 20;

[0066] The semiconductor device further includes a first insulating layer 41 and a second insulating layer 42 . The first insulating layer 41 is located between the first electrode 1 and the sidewall of the second semiconductor body 20 . The second insulating layer 42 is located between the first gate G1 and the sidewall of the second semiconductor body 20 .

[0067] Specifically, the second semiconductor body 20 covers a portion of the first surface of the first semiconductor body 10 to expose a portion of the first ohmic contact region 121 and a portion of the second ohmic contact region 122, thereby facilitating electrical connection between the first electrode 1 and the first ohmic contact region 121, and facilitating electrical connection between the first gate G1 and the second contact region. The exposed first ohmic contact region 121 and the exposed second ohmic contact region 122 are located on opposite sides of the second semiconductor body 20, and thus the first electrode 1 and the first gate G1 are located on opposite sides of the second semiconductor body 20. A first insulating layer 41 is disposed between the sidewalls of the first electrode 1 and the second semiconductor body 20 to prevent electrical connection between the first electrode 1 and the sidewalls of the second semiconductor body 20. A second insulating layer 42 is disposed between the first gate G1 and another sidewall of the second semiconductor body 20 to prevent electrical connection between the first gate G1 and the sidewalls of the second semiconductor body 20, thereby preventing direct electrical connection between the third semiconductor layer 23 and the first semiconductor layer 21. The material of the first insulating layer 41 includes, but is not limited to, silicon oxide, and the material of the second insulating layer 42 includes, but is not limited to, silicon oxide. The first insulating layer 41 and the second insulating layer 42 may be formed simultaneously.

[0068] Based on the above embodiments, Figure 2 , optionally, the cell structure also includes:

[0069] a first ohmic contact layer 51 located on a surface of the first ohmic contact region 121 away from the second surface; the first electrode 1 is electrically connected to the first ohmic contact region 121 via the first ohmic contact layer 51, thereby reducing the contact resistance between the first electrode 1 and the first ohmic contact region 121;

[0070] and / or, the second ohmic contact layer 52 is located on a surface of the second ohmic contact region 122 away from the second surface, and the first gate G1 is electrically connected to the second ohmic contact region 122 through the second ohmic contact layer 52, thereby reducing the contact resistance between the first gate G1 and the second ohmic contact region 122;

[0071] and / or, a third ohmic contact layer 53 is located on a portion of the surface of the third region, and the first electrode 1 and the first resistive material layer 31 are electrically connected to the third semiconductor layer 23 via the third ohmic contact layer 53, thereby reducing the contact resistance between the first electrode 1 and the first ohmic contact region 121, and reducing the contact resistance between the first resistive material layer 31 and the first ohmic contact region 121;

[0072] and / or, a fourth ohmic contact layer 54 is located on a portion of the surface of the first region, and the first gate G1 and the second resistive material layer 32 are electrically connected to the first semiconductor layer 21 through the fourth ohmic contact layer 54, thereby reducing the contact resistance between the first gate G1 and the second ohmic contact region 122, and reducing the contact resistance between the second resistive material layer 32 and the second ohmic contact region 122;

[0073] And / or, the fifth ohmic contact layer 55 is located on a portion of the surface of the second region, and the second gate G2 is electrically connected to the second semiconductor layer 22 through the fifth ohmic contact layer 55 , thereby reducing the contact resistance between the second gate G2 and the second semiconductor layer 22 .

[0074] Based on the above embodiments, Figure 2 Optionally, the cell structure further includes a third insulating layer 60; the third insulating layer 60 is located on a side of the first resistive material layer 31, the second resistive material layer 32, the first gate G1, and the second gate G2 away from the first semiconductor body 10; the first electrode 1 is also located on a side of the third insulating layer 60 away from the first semiconductor body 10, and extends along the sidewalls of the third insulating layer 60, the sidewalls of the first resistive material layer 31, and the sidewalls of the second semiconductor body 20 toward the first ohmic contact region 121. The third insulating layer 60 is used as an interlayer dielectric layer to electrically isolate the first electrode 1 from the first gate G1, and to electrically isolate the first electrode 1 from the second gate G2. The material of the third insulating layer 60 includes, but is not limited to, silicon oxide.

[0075] Based on the above embodiments, optionally, the material of the first semiconductor body 10 is different from the material of the second semiconductor body 20; the material of the first semiconductor body 10 includes but is not limited to silicon carbide; the material of the second semiconductor body 20 includes but is not limited to silicon.

[0076] Based on the above embodiments, Figure 5 is a cross-sectional view of another semiconductor device provided by an embodiment of the present invention, with reference to Figure 5 Optionally, the semiconductor device includes at least two cellular structures, and two adjacent cellular structures are mirror-symmetrical in the second direction Y.

[0077] The two adjacent cell structures share the same first gate G1 ; the first semiconductors of the two adjacent cell structures may share the same first electrode 1 and second electrode 2 .

[0078] Furthermore, the two adjacent cellular structures are prepared and formed synchronously, that is, the same membrane layers in the two adjacent cellular structures are prepared and formed synchronously.

[0079] refer to Figure 4 The present invention also provides a bridge circuit, comprising an upper-bridge switching device unit 01 and a lower-bridge switching device unit 02; the lower-bridge switching device unit 02 comprises at least one semiconductor device according to any embodiment of the present invention. Furthermore, the upper-bridge switching device unit 01 comprises at least one semiconductor device according to any embodiment of the present invention.

[0080] Taking a half-bridge circuit in which the BJT is a PNP-type BJT as an example, the semiconductor device in the lower-bridge switching device unit 02 includes a junction field-effect transistor J2 and a corresponding Miller clamp circuit, and the semiconductor device in the upper-bridge switching device unit 01 includes a junction field-effect transistor J1 and a corresponding Miller clamp circuit. The crosstalk current in the lower-bridge transistor (junction field-effect transistor J2) will first be divided across the first resistor R1 and the second resistor R2 to turn on the PNP-type BJT. The gate and source terminals of the lower-bridge transistor (junction field-effect transistor J2) are short-circuited through the conductive channel provided by the PNP-type BJT, thereby turning off the lower-bridge transistor (junction field-effect transistor J2) to prevent a short circuit.

[0081] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the concept of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A semiconductor device, characterized in that: comprising at least one cellular structure, the cellular structure comprising: A first semiconductor body comprising a first surface and a second surface disposed opposite to each other; the first semiconductor body comprising a first ohmic contact region and a second ohmic contact region of different conductivity types, both located on the first surface; the first semiconductor body further comprising a buried layer located on a side of the first ohmic contact region and the second ohmic contact region closer to the second surface; wherein the buried layer and the second ohmic contact region have the same conductivity type; a second semiconductor body located on a first surface of the first semiconductor body; the second semiconductor body comprising a first semiconductor layer, a third semiconductor layer, and a second semiconductor layer located between the first semiconductor layer and the third semiconductor layer; wherein the first semiconductor layer and the third semiconductor layer have the same conductivity type as the second ohmic contact region; and the second semiconductor layer has the same conductivity type as the first ohmic contact region; a first electrode and a first gate; the first electrode is electrically connected to the first ohmic contact region and the third semiconductor layer, and the first gate is electrically connected to the second ohmic contact region and the first semiconductor layer; A first resistive material layer, a second resistive material layer and a second gate; the second gate is located between the first resistive material layer and the second resistive material layer; wherein the second gate is electrically connected to the second semiconductor layer; the first resistive material layer is in contact with the second gate and the third semiconductor layer, and the second resistive material layer is in contact with the second gate and the first semiconductor layer.

2. The semiconductor device according to claim 1, wherein The first semiconductor body further includes a first JFET region extending along a first direction and a second JFET region extending along a second direction; the first direction and the second direction intersect each other, and the first direction is a direction from the first surface to the second surface; The first JFET region and the second JFET region are connected, and the second JFET region is located between the buried layer and the second ohmic contact region.

3. The semiconductor device according to claim 1, wherein The first resistive material layer, the second resistive material layer and the second gate are all located on a side of the second semiconductor body away from the first semiconductor body; In the second semiconductor body, the second semiconductor layer is located on the surface of the first semiconductor layer close to the first semiconductor body and the sidewall of the first semiconductor layer; the third semiconductor layer is located on the surface of the second semiconductor layer close to the first semiconductor body and the sidewall of the second semiconductor layer away from the first semiconductor layer.

4. The semiconductor device according to claim 3, wherein A surface of the second semiconductor body away from the first semiconductor body is a plane; A surface of the second semiconductor body away from the first semiconductor body includes a first region surface, a third region surface, and a second region surface located between the first region surface and the third region surface; The second region surface is the surface of the second semiconductor layer away from the first semiconductor body, the first region surface is the surface of the first semiconductor layer away from the first semiconductor body, and the third region surface is the surface of the third semiconductor layer away from the first semiconductor body; the second gate is located on the second region surface, the first resistive material layer extends from the second gate along the second region surface to the covering part of the third region surface, and the second resistive material layer extends from the second gate along the second region surface to the covering part of the first region surface.

5. The semiconductor device according to claim 1, wherein The first electrode and the first gate are located on opposite sides of the second semiconductor body; The semiconductor device further includes a first insulating layer and a second insulating layer; wherein the first insulating layer is located between the first electrode and the sidewall of the second semiconductor body; and the second insulating layer is located between the first gate and the sidewall of the second semiconductor body.

6. The semiconductor device according to claim 4, wherein The cellular structure further includes: a first ohmic contact layer, located on a surface of the first ohmic contact region away from the second surface, the first electrode being electrically connected to the first ohmic contact region through the first ohmic contact layer; and / or, a second ohmic contact layer located on a surface of the second ohmic contact region away from the second surface, the first gate being electrically connected to the second ohmic contact region through the second ohmic contact layer; and / or a third ohmic contact layer located on a portion of the surface of the third region, wherein the first electrode is electrically connected to the third semiconductor layer through the third ohmic contact layer; and / or, a fourth ohmic contact layer is located on a portion of the surface of the first region, and the first gate is electrically connected to the first semiconductor layer through the fourth ohmic contact layer; And / or, a fifth ohmic contact layer is located on a portion of the surface of the second region, and the second gate is electrically connected to the second semiconductor layer through the fifth ohmic contact layer.

7. The semiconductor device according to claim 3, wherein The cellular structure further includes: a third insulating layer, located on a side of the first resistive material layer, the second resistive material layer, the first gate, and the second gate away from the first semiconductor body; The first electrode is also located on a side of the third insulating layer away from the first semiconductor body, and extends toward the first ohmic contact region along sidewalls of the third insulating layer, the first resistive material layer, and the second semiconductor body.

8. The semiconductor device according to claim 1, wherein The material of the first semiconductor body is different from the material of the second semiconductor body; The material of the first semiconductor body includes silicon carbide; the material of the second semiconductor body includes silicon.

9. The semiconductor device according to claim 1, wherein It comprises at least two of the cellular structures, and the two adjacent cellular structures are mirror-symmetrical in the second direction.

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