Groove type MOSFET and manufacturing method thereof

Abstract

The invention discloses a trench type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), which is characterized in that a first well region and a source region positioned on the top surface of the first well region are formed on the first side of a trench gate, a second doped region is formed on the second side of the trench gate, and a part of the second doped region extends right below the bottom surface of a gate trench; a plane gate is formed on the top of the second doped region, a third doped region and a fourth doped region are formed on the two sides of the plane gate respectively, the third doped region is located in the top surface area of the second doped region, and the fourth doped region is located in the first epitaxial layer outside the second doped region; the source region, the first well region, the third doped region and the second gate conductive material layer of the planar gate are all connected to a source. The invention further discloses a manufacturing method of the groove type MOSFET. The gate-controlled diode can be integrated, reverse follow current can be realized, conduction voltage drop can be reduced, unipolar conduction can be realized, dynamic loss can be reduced, the reliability of the device can be improved, and Miller capacitance can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a trench MOSFET; the present invention also relates to a manufacturing method of the trench MOSFET. Background Art

[0002] Wide bandgap semiconductor material SiC is an ideal material for preparing high voltage power electronic devices. Compared with Si material, SiC material has a high breakdown electric field strength (4×10 6 V / cm), high carrier saturation drift velocity (2×10 7 cm / s), high thermal conductivity, good thermal stability, etc., so it is particularly suitable for use in high-power, high-voltage, high-temperature and radiation-resistant electronic devices.

[0003] SiC VDMOS is a commonly used SiC power device. Compared to bipolar devices, SiC VDMOS has better frequency characteristics and lower switching losses because it does not have a charge storage effect. The wide bandgap of SiC material also allows SiC VDMOS to operate at temperatures as high as 300°C.

[0004] However, planar SiC VDMOS has two problems. First, the density of the JFET region is too high, which introduces a large Miller capacitance and increases the dynamic loss of the device. Second, the parasitic SiC body diode has a too high forward voltage drop. As a bipolar device, it has a large reverse recovery current. In addition, the bipolar degradation phenomenon caused by the silicon carbide BPD defect causes the forward voltage drop of the body diode to continue to increase with the increase of usage time. Therefore, the body diode of SiC VDMOS cannot be used directly as a freewheeling diode. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a trench MOSFET that can integrate a gate-controlled diode, thereby achieving reverse freewheeling and rectification without the need for a body diode or an additional parallel diode. This reduces the on-state voltage drop and enables unipolar conduction, thereby reducing dynamic losses, improving device reliability, and reducing Miller capacitance. To this end, the present invention also provides a method for manufacturing the trench MOSFET.

[0006] In order to solve the above technical problems, the present invention provides a trench MOSFET comprising:

[0007] A first epitaxial layer doped with a first conductivity type is provided, and a drain region heavily doped with the first conductivity type is formed on the back side of the first epitaxial layer.

[0008] The trench gate comprises a bottom dielectric layer formed on the bottom surface of a gate trench, a first gate dielectric layer formed on the side of the gate trench, and a first gate conductive material layer filled in the gate trench.

[0009] A first well region of the second conductive type is formed in the first epitaxial layer at the first side surface of the gate trench, and the bottom surface of the first well region is located above the bottom surface of the gate trench; the surface of the first well region covered by the side of the first gate conductive material layer is used to form the first channel region of the MOSFET.

[0010] A source region heavily doped with the first conductivity type is formed in the surface area of ​​the first well region, the second side surface of the first well region and the second side surface of the source region are aligned with the first side surface of the gate trench, the first side surface of the source region is located on the inner side of the first side surface of the first well region, and the outer side of the first side surface of the first well region is the first epitaxial layer.

[0011] A second doped region of a second conductive type is formed in the first epitaxial layer at the second side surface of the gate trench, the bottom surface of the second doped region is located below the bottom surface of the gate trench and the second doped region also extends directly below the bottom surface of the gate trench.

[0012] A third doping region heavily doped with the first conductivity type is formed in the surface area of ​​the second doping region, the first side surface of the third doping region and the first side surface of the second doping region are aligned with the second side surface of the gate trench, and the second side surface of each third doping region is located inside the second side surface of the second doping region.

[0013] A fourth doping region doped with the first conductive type is formed on the top surface of the first epitaxial layer outside the second side surface of the second doping region.

[0014] A planar gate is formed on a top surface of the second doping region between the third doping region and the fourth doping region.

[0015] The planar gate includes a second gate dielectric layer and a second gate conductive material layer stacked in sequence.

[0016] The source region, the first well region, the third doped region and the second gate conductive material layer are all connected to a source electrode composed of a front metal layer through corresponding top through-holes.

[0017] The surface of the second doped region covered by the side surface of the second gate conductive material layer is used to form a second channel region of the gate-controlled diode.

[0018] A further improvement is that the material of the first epitaxial layer is a semiconductor material having a band gap width greater than the band gap width of silicon.

[0019] A further improvement is that the material of the first epitaxial layer includes SiC.

[0020] A further improvement is that the bottom dielectric layer, the first gate dielectric layer and the second gate dielectric layer are made of the same material, the bottom dielectric layer is thicker than the first gate dielectric layer, and the second gate dielectric layer is thinner than the first gate dielectric layer.

[0021] A further improvement is that the material of the bottom dielectric layer includes an oxide layer; and the top surface of the bottom dielectric layer is arc-shaped.

[0022] The first gate conductive material layer includes a polysilicon gate.

[0023] The second gate conductive material layer includes a polysilicon gate.

[0024] A further improvement is that the thickness of the second gate dielectric layer is 10 nm to 100 nm.

[0025] A further improvement is that the doping concentration of the first epitaxial layer is 1E15cm -3 ~1E17cm -3 ;

[0026] The doping concentration of the second doping region is 1E14 cm -3 ~1E16cm -3 ;

[0027] The doping concentration of the third doping region is less than or equal to 1E16 cm -3 .

[0028] A further improvement is that an ohmic contact alloy is formed on the bottom surfaces of the through holes corresponding to the source region, the first well region and the third doping region.

[0029] A further improvement is that the trench MOSFET is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the trench MOSFET is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0030] To solve the above technical problems, the present invention provides a method for manufacturing a trench MOSFET comprising the following steps:

[0031] A first epitaxial layer doped with a first conductivity type is formed, and a drain region heavily doped with the first conductivity type is formed on the back side of the first epitaxial layer.

[0032] A second doping region of the second conductivity type is formed in the first epitaxial layer, and a junction depth of the second doping region is greater than a depth of the gate trench.

[0033] A first well region of the second conductivity type is formed in the first epitaxial layer, wherein a junction depth of the first well region is smaller than a depth of the gate trench.

[0034] A trench gate is formed, wherein the trench gate includes a bottom dielectric layer formed on a bottom surface of a gate trench, a first gate dielectric layer formed on a side surface of the gate trench, and a first gate conductive material layer filled in the gate trench.

[0035] A source region heavily doped with the first conductivity type is formed in the surface area of ​​the first well region, the second side surface of the first well region and the second side surface of the source region are aligned with the first side surface of the gate trench, the first side surface of the source region is located inside the first side surface of the first well region, and the first epitaxial layer is outside the first side surface of the first well region.

[0036] A third doping region heavily doped with the first conductivity type is formed in the surface area of ​​the second doping region, the first side surface of the third doping region and the first side surface of the second doping region are aligned with the second side surface of the gate trench, and the second side surface of each third doping region is located inside the second side surface of the second doping region.

[0037] A fourth doping region doped with the first conductive type is formed on the top surface of the first epitaxial layer outside the second side surface of the second doping region.

[0038] A planar gate is formed on a top surface of the second doping region between the third doping region and the fourth doping region; the planar gate includes a second gate dielectric layer and a second gate conductive material layer stacked in sequence.

[0039] An interlayer film, a through hole and a front metal layer are formed, and the front metal layer is patterned and etched to form a source electrode; the source region, the first well region, the third doped region and the second gate conductive material layer are all connected to the source electrode composed of the front metal layer through corresponding through holes on the top.

[0040] The surface of the second doped region covered by the side surface of the second gate conductive material layer is used to form a second channel region of the gate-controlled diode.

[0041] A drain electrode composed of a back metal layer is formed on the back side of the drain region.

[0042] A further improvement is that the material of the first epitaxial layer is a semiconductor material having a band gap width greater than the band gap width of silicon.

[0043] A further improvement is that the material of the first epitaxial layer includes SiC.

[0044] A further improvement is that the bottom dielectric layer, the first gate dielectric layer and the second gate dielectric layer are made of the same material, the bottom dielectric layer is thicker than the first gate dielectric layer, and the second gate dielectric layer is thinner than the first gate dielectric layer.

[0045] A further improvement is that the material of the bottom dielectric layer includes an oxide layer; and the top surface of the bottom dielectric layer is arc-shaped.

[0046] The first gate conductive material layer includes a polysilicon gate.

[0047] The second gate conductive material layer includes a polysilicon gate.

[0048] The trench gate is formed after forming the second doping region, the first well region, the third doping region, and the fourth doping region, and then the planar gate is formed, including the following steps:

[0049] The first epitaxial layer is patterned and etched to form the gate trench.

[0050] The bottom dielectric layer is formed at the bottom of the gate trench by adopting an oxide layer deposition and etching process, and the top surface of the bottom dielectric layer is made into an arc shape by an etching process.

[0051] A first gate dielectric layer is formed on the side of the gate trench by using a thermal oxidation process. The first gate dielectric layer is also formed on the surface of the first epitaxial layer outside the gate trench.

[0052] Polysilicon deposition and etching are performed to form the first gate conductive material layer in the gate trench.

[0053] The first gate dielectric layer outside the gate trench is thinned by a CMP process to obtain the second gate dielectric layer.

[0054] Polysilicon deposition and etching are performed to form the second gate conductive material layer.

[0055] A further improvement is that the thickness of the second gate dielectric layer is 10 nm to 100 nm.

[0056] A further improvement is that the doping concentration of the first epitaxial layer is 1E15cm -3 ~1E17cm -3 .

[0057] The doping concentration of the second doping region is 1E14 cm -3 ~1E16cm -3 .

[0058] The doping concentration of the third doping region is less than or equal to 1E16 cm-3 .

[0059] A further improvement is that the trench MOSFET is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the trench MOSFET is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0060] The present invention forms the first channel region of the MOSFET only on one side of the gate trench, and forms a second doped region with a depth greater than the gate trench on the other side of the gate trench, forms a planar gate on the top surface of the second doped region, and forms a third doped region and a fourth doped region doped with the first conductive type on both sides of the planar gate, respectively. The third doped region and the second gate conductive material layer of the planar gate are both connected to the source through the through hole at the top, so that a gate-controlled diode can be realized, that is, a diode composed of a MOSFET with the gate and source connected together. The gate-controlled diode can be turned on in the third quadrant working state, and the conduction path is the source, the third doped region, the second channel region formed on the surface of the second doped region, the fourth doped region, the first epitaxial layer, the drain region to the drain. Therefore, the present invention can integrate the gate-controlled diode, thereby achieving reverse freewheeling without the need for a body diode or an additional parallel diode, and can greatly reduce the dynamic loss of the device.

[0061] The on-state voltage drop of the gate-controlled diode corresponds to the threshold voltage required when the second channel region is turned on. The threshold voltage required when the second channel region is turned on can be reduced by adjusting the structural parameters of the planar gate. For example, the second gate dielectric layer can use a thin gate oxide to reduce the threshold voltage required when the second channel region is turned on. Therefore, the gate-controlled diode of the present invention has the advantage of reduced on-state voltage. The gate-controlled diode of the present invention is formed by MOSFET connection, so it also has the advantage of unipolar conduction, so there is no reverse recovery current and no bipolar degeneration.

[0062] In addition, part of the second doped region of the present invention is located directly below the bottom surface of the trench gate, which can share the electric field strength of the first gate dielectric layer at the bottom of the gate trench in the off state, thereby improving the long-term reliability of the device; at the same time, after the second doped region extends to the bottom of the gate trench, it can reduce the overlapping area between the gate and the drain, thereby significantly reducing the Miller capacitance and thus reducing the switching damage of the device.

[0063] Furthermore, the bottom dielectric layer at the bottom surface of the gate trench in the trench gate of the present invention and the first gate dielectric layer on the side of the gate trench are independent structures, meaning that their materials and thicknesses can be independently set. By improving the reliability of the bottom dielectric layer, the reliability of the entire device can be improved. For example, when both the bottom dielectric layer and the first gate dielectric layer are oxide layers, increasing the thickness of the bottom dielectric layer can increase device reliability. Furthermore, the bottom surface of the gate trench of the present invention is smoother, further improving device reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0065] Figure 1 3D schematic diagram of the trench MOSFET according to an embodiment of the present invention;

[0066] Figure 2 is a cross-sectional view taken along the xy plane of a trench MOSFET according to an embodiment of the present invention;

[0067] Figure 3-Figure 12 Schematic diagram of the device structure in each step of the method for manufacturing a trench MOSFET according to an embodiment of the present invention;

[0068] Figure 13 1 is a schematic diagram of an equivalent circuit of a trench MOSFET in a forward conduction state according to an embodiment of the present invention;

[0069] Figure 14 Schematic diagram of the equivalent circuit of the trench MOSFET in the embodiment of the present invention during reverse freewheeling. DETAILED DESCRIPTION

[0070] like Figure 1 FIG. 1 is a schematic diagram of the three-dimensional structure of a trench MOSFET according to an embodiment of the present invention; FIG. Figure 2 FIG. 1 is a cross-sectional view of a trench MOSFET according to an embodiment of the present invention taken along an xy plane. The trench MOSFET according to an embodiment of the present invention includes:

[0071] The first epitaxial layer 2 is doped with the first conductivity type, and a drain region 1 heavily doped with the first conductivity type is formed on the back surface of the first epitaxial layer 2. A drain electrode composed of a back metal layer 14 is formed on the back surface of the drain region 1.

[0072] The trench gate includes a bottom dielectric layer 4 formed on the bottom surface of the gate trench 101, a first gate dielectric layer 5 formed on the side of the gate trench 101, and a first gate conductive material layer 6 filled in the gate trench 101. Figure 6 shown.

[0073] A first well region 7 of the second conductive type is formed in the first epitaxial layer 2 at the first side surface of the gate trench 101, and the bottom surface of the first well region 7 is located above the bottom surface of the gate trench 101; the surface of the first well region 7 covered by the side of the first gate conductive material layer 6 is used to form the first channel region of the MOSFET.

[0074] A source region 8 heavily doped with the first conductivity type is formed in the surface area of ​​the first well region 7. The second side surface of the first well region 7 and the second side surface of the source region 8 are aligned with the first side surface of the gate trench 101. The first side surface of the source region 8 is located on the inner side of the first side surface of the first well region 7, and the outer side of the first side surface of the first well region 7 is the first epitaxial layer 2.

[0075] A second doping region 3 of the second conductivity type is formed in the first epitaxial layer 2 at the second side surface of the gate trench 101. The bottom surface of the second doping region 3 is located below the bottom surface of the gate trench 101 and the second doping region 3 also extends directly below the bottom surface of the gate trench 101.

[0076] A third doping region 9 heavily doped with the first conductivity type is formed in the surface area of ​​the second doping region 3, and the first side surface of the third doping region 9 and the first side surface of the second doping region 3 are aligned with the second side surface of the gate trench 101, and the second side surface of each third doping region 9 is located inside the second side surface of the second doping region 3.

[0077] A fourth doping region 17 doped with the first conductivity type is formed on the top surface of the first epitaxial layer 2 outside the second side surface of the second doping region 3 .

[0078] A planar gate is formed on the top surface of the second doping region 3 between the third doping region 9 and the fourth doping region 17 .

[0079] The planar gate includes a second gate dielectric layer 15 and a second gate conductive material layer 16 stacked in sequence.

[0080] The source region 8, the first well region 7, the third doped region 9 and the second gate conductive material layer 16 are all connected to the source electrode formed by the front metal layer 13 through corresponding top vias 12. The vias 12 pass through the interlayer film 10.

[0081] Ohmic contact alloys 11 are formed on the bottom surfaces of the through holes 12 corresponding to the source region 8 , the first well region 7 and the third doping region 9 .

[0082] The first gate conductive material layer 6 is connected to the gate formed by the front metal layer 13 .

[0083] The surface of the second doped region 3 covered by the side of the second gate conductive material layer 16 is used to form the second channel region of the gate-controlled diode. Figure 2 As shown, the gate-controlled diode is formed by connecting the planar gate MOSFET formed by the third doping region 9, the planar gate, the second channel region and the fourth doping region 17 in a diode manner, that is, the third doping region 9 and the second gate conductive material layer 16 of the planar gate are electrically connected together.

[0084] In an embodiment of the present invention, the material of the first epitaxial layer 2 is a semiconductor material having a bandgap greater than that of silicon. Preferably, the material of the first epitaxial layer 2 includes SiC. In other embodiments, the first epitaxial layer 2 may also be made of other suitable semiconductor materials, which can be selected based on actual needs.

[0085] In the embodiment of the present invention, the bottom dielectric layer 4, the first gate dielectric layer 5, and the second gate dielectric layer 15 are made of the same material. The bottom dielectric layer 4 is thicker than the first gate dielectric layer 5, and the second gate dielectric layer 15 is thinner than the first gate dielectric layer 5. The second gate dielectric layer 15 is thinner to reduce the forward conduction voltage of the gate-controlled diode. In other embodiments, the materials of the bottom dielectric layer 4, the first gate dielectric layer 5, and the second gate dielectric layer 15 are also independently selected as needed.

[0086] Preferably, the material of the bottom dielectric layer 4 is an oxide layer; thus, the materials of the first gate dielectric layer 5 and the second gate dielectric layer 15 are also oxide layers.

[0087] The top surface of the bottom dielectric layer 4 is in an arc shape.

[0088] The first gate conductive material layer 6 includes a polysilicon gate.

[0089] The second gate conductive material layer 16 includes a polysilicon gate.

[0090] In some embodiments, the second gate dielectric layer 15 has a thickness of 10 nm to 100 nm.

[0091] The doping concentration of the first epitaxial layer 2 is 1E15 cm -3 ~1E17cm -3 ;

[0092] The doping concentration of the second doping region 3 is 1E14 cm -3 ~1E16cm -3 ;

[0093] The doping concentration of the third doping region 9 is less than or equal to 1E16 cm -3 .

[0094] In the embodiment of the present invention, the trench MOSFET is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the trench MOSFET can also be a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0095] In the embodiment of the present invention, the first channel region of the MOSFET is formed only on one side of the gate trench 101, and a second doping region 3 with a depth greater than the gate trench 101 is formed on the other side of the gate trench 101. A planar gate is formed on the top surface of the second doping region 3, and a third doping region 9 and a fourth doping region 17 doped with the first conductive type are formed on both sides of the planar gate. The third doping region 9 and the second gate conductive material layer 16 of the planar gate are connected to the source through the through hole 12 at the top. In this way, a gate-controlled diode can be realized, that is, a diode composed of a MOSFET with the gate and source connected together. The gate-controlled diode can be turned on in the third quadrant working state, and the conduction path is the source, the third doping region 9, the second channel region formed on the surface of the second doping region 3, the fourth doping region 17, the first epitaxial layer 2, the drain region 1 to the drain. Therefore, the embodiment of the present invention can integrate the gate-controlled diode, so that reverse freewheeling can be achieved without using a body diode or an additional parallel diode, which can greatly reduce the dynamic loss of the device.

[0096] The on-state voltage drop of the gate-controlled diode corresponds to the threshold voltage required when the second channel region is turned on. The threshold voltage required when the second channel region is turned on can be reduced by adjusting the structural parameters of the planar gate, such as adjusting the thickness of the second gate dielectric layer 15. For example, the second gate dielectric layer 15 can use a thin gate oxide to reduce the threshold voltage required when the second channel region is turned on. Therefore, the gate-controlled diode of the embodiment of the present invention has the advantage of low on-state voltage. The gate-controlled diode of the embodiment of the present invention is formed by MOSFET connection, so it also has the advantage of unipolar conduction, so there is no reverse recovery current and no bipolar degeneration.

[0097] In addition, part of the second doped region 3 of the embodiment of the present invention is located directly below the bottom surface of the trench gate, which can share the electric field strength of the first gate dielectric layer 5 at the bottom of the gate trench 101 in the off state, thereby improving the long-term reliability of the device; at the same time, after the second doped region 3 extends to the bottom of the gate trench 101, it can reduce the overlapping area between the gate and the drain, thereby significantly reducing the Miller capacitance, thereby reducing the switching damage of the device.

[0098] In addition, the bottom dielectric layer 4 on the bottom surface of the gate trench 101 in the trench gate of the embodiment of the present invention and the first gate dielectric layer 5 on the side of the gate trench 101 are independent structures, that is, the material and thickness can be set independently. By improving the reliability of the bottom dielectric layer 4, the reliability of the entire device can be improved. For example, when both the bottom dielectric layer 4 and the first gate dielectric layer 5 are oxide layers, the reliability of the device can be increased by increasing the thickness of the bottom dielectric layer 4. In addition, the bottom surface of the gate trench 101 in the embodiment of the present invention is smoother, which can further improve the reliability of the device.

[0099] like Figure 13, which is a schematic diagram of the equivalent circuit of a trench MOSFET in the forward conduction state according to an embodiment of the present invention; the trench MOSFET is integrated with a MOSFET 201 and a gate-controlled diode 202. During forward conduction, the gate is applied with a positive voltage greater than the threshold voltage of the MOSFET 201, and the drain is applied with a voltage greater than the source. This causes the first channel region of the MOSFET 201 to conduct, thereby forming a current Ids from the drain to the source, as shown by the dotted line 203, which is conducted through the first channel region of the MOSFET 201.

[0100] like Figure 14 FIG. 1 is a schematic diagram of an equivalent circuit of a trench MOSFET in a reverse freewheeling state according to an embodiment of the present invention. Figure 14 The corresponding operating state is the third quadrant operating state. When the gate voltage is less than the threshold voltage of MOSFET 201, such as 0V, MOSFET 201 is turned off, the source voltage is greater than the drain voltage, and the gate-controlled diode 202 is forward biased and turned on. This is because the source of the gate-controlled diode 202 corresponds to the drain of the entire device. Therefore, when the source voltage is greater than the drain voltage, the voltage between the gate of the gate-controlled diode 202, i.e., the second gate conductive material layer 16, and the source, i.e., the fourth doped region 17, is the gate-source voltage of the gate-controlled diode 202. When the gate-source voltage is greater than the threshold voltage of the gate-controlled diode 202, the gate-controlled diode 202 is turned on. The on-state current of the gate-controlled diode 202 corresponds to the current Isd from the source to the drain of the gate-controlled diode 202, as shown by the dotted line 204.

[0101] like Figures 3 to 12 , which is a schematic diagram of the device structure in each step of the method for manufacturing a trench MOSFET according to an embodiment of the present invention, wherein the corresponding cross section is the xy plane; the method for manufacturing a trench MOSFET according to an embodiment of the present invention comprises the following steps:

[0102] Step 1: Figure 3 As shown, a first epitaxial layer 2 doped with the first conductivity type is formed, and a drain region 1 heavily doped with the first conductivity type is formed on the back side of the first epitaxial layer 2 .

[0103] In the embodiment of the present invention, the material of the first epitaxial layer 2 is a semiconductor material having a band gap greater than that of silicon. Preferably, the material of the first epitaxial layer 2 includes SiC.

[0104] In the method of the embodiment of the present invention, the drain region 1 is composed of a semiconductor substrate, the first epitaxial layer 2 is formed on the semiconductor substrate, and the semiconductor substrate and the first epitaxial layer are made of the same material, for example, SiC.

[0105] Step 2: Figure 3 As shown, a second doping region 3 of the second conductivity type is formed in the first epitaxial layer 2 , and a junction depth of the second doping region 3 is greater than a depth of the gate trench 101 .

[0106] Figure 3 Two second doping regions 3 are shown in the figure, but in practice more can be provided as needed.

[0107] In the method of the embodiment of the present invention, the formation area of ​​the second doped region 3 is defined by photolithography. Before the photolithography process, an ion implantation mask layer is formed on the surface of the first epitaxial layer 2. The material of the ion implantation mask layer includes an oxide layer. After the photolithography process, the ion implantation mask layer needs to be patterned before ion implantation. The ion implantation mask layer is then removed and the surface is cleaned. In the method of the embodiment of the present invention, the trench MOSFET is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In this case, the second doped region 3 is P-type doped, and the implanted impurities in the second doped region 3 include Al. The implantation temperature condition is 300K to 1000K. In other embodiments, the field effect transistor can also be a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type. In this case, the second doped region 3 is an N-type buried layer.

[0108] Step 3: Figure 4 As shown, a first well region 7 of the second conductivity type is formed in the first epitaxial layer 2 , and a junction depth of the first well region 7 is smaller than a depth of the gate trench 101 .

[0109] In the method of the embodiment of the present invention, the formation area of ​​the first well region 7 is defined by photolithography. Before the photolithography process, an ion implantation mask layer is formed on the surface of the first epitaxial layer 2. The material of the ion implantation mask layer includes an oxide layer. After the photolithography process, the ion implantation mask layer needs to be patterned before ion implantation. The ion implantation mask layer is then removed and the surface is cleaned. In the method of the embodiment of the present invention, the first well region 7 is P-type doped. The implanted impurity in the first well region 7 includes Al. The implantation temperature is 300K to 1000K.

[0110] Step 4: Figure 5 As shown, a source region 8 heavily doped with the first conductivity type is formed in the surface region of the first well region 7. The second side surfaces of the first well region 7 and the source region 8 are aligned with the first side surfaces of the gate trench 101 in the subsequent process. The first side surface of the source region 8 is located inside the first side surface of the first well region 7, and the first epitaxial layer 2 is outside the first side surface of the first well region 7. The source region 8 does not directly contact the first epitaxial layer 2. The source region 8 needs to be electrically connected to the first epitaxial layer 2 through the conduction of the first channel region of the MOSFET 201.

[0111] In the method of the embodiment of the present invention, the formation area of ​​source region 8 is defined by photolithography. Before the photolithography process, an ion implantation mask layer is formed on the surface of the first epitaxial layer 2. The material of the ion implantation mask layer includes an oxide layer. After the photolithography process, the ion implantation mask layer needs to be patterned before ion implantation. The ion implantation mask layer is then removed and the surface is cleaned. In the method of the embodiment of the present invention, source region 8 is N-type doped. The impurities implanted into source region 8 include nitrogen (N) at a temperature of 300K to 1000K.

[0112] Step 5: Figure 5 As shown, a third doping region 9 heavily doped with the first conductivity type is formed in the surface area of ​​the second doping region 3, and the first side surface of the third doping region 9 and the first side surface of the second doping region 3 are aligned with the second side surface of the gate trench 101, and the second side surface of each third doping region 9 is located inside the second side surface of the second doping region 3.

[0113] In the method of the embodiment of the present invention, the formation area of ​​the third doped region 9 is defined by photolithography. Before the photolithography process, an ion implantation mask layer is formed on the surface of the first epitaxial layer 2. The material of the ion implantation mask layer includes an oxide layer. After the photolithography process, the ion implantation mask layer needs to be patterned before ion implantation. The ion implantation mask layer is then removed and the surface is cleaned. In the method of the embodiment of the present invention, the third doped region 9 is N-type doped. The implanted impurities in the third doped region 9 include phosphorus. The implantation temperature is 300K to 1000K.

[0114] In some embodiments, the doping concentration of the first epitaxial layer 2 is 1E15 cm -3 ~1E17cm -3 .

[0115] The doping concentration of the second doping region 3 is 1E14 cm -3 ~1E16cm -3 .

[0116] The doping concentration of the third doping region 9 is less than or equal to 1E16 cm -3 .

[0117] Step 6: Figure 5 As shown, a fourth doping region 17 doped with the first conductive type is formed on the top surface of the first epitaxial layer 2 outside the second side surface of the second doping region 3 .

[0118] In the method of the embodiment of the present invention, the formation area of ​​the fourth doped region 17 is defined by photolithography. Before the photolithography process, an ion implantation mask layer is formed on the surface of the first epitaxial layer 2. The material of the ion implantation mask layer includes an oxide layer. After the photolithography process, the ion implantation mask layer needs to be patterned before ion implantation. The ion implantation mask layer is then removed and the surface is cleaned. In the method of the embodiment of the present invention, the fourth doped region 17 is N-type doped. The implanted impurities in the fourth doped region 17 include phosphorus. The implantation temperature is 300K to 1000K.

[0119] Step 7: Forming a trench gate. The trench gate includes a bottom dielectric layer 4 formed on the bottom surface of the gate trench 101, a first gate dielectric layer 5 formed on the side of the gate trench 101, and a first gate conductive material layer 6 filled in the gate trench 101. The steps of forming the trench gate include:

[0120] Step 71: Figure 6 As shown, a gate trench 101 is formed in the first epitaxial layer 2, and the etched region of the gate trench 101 is located between the first well region 7 and the second doped region 3. After the gate trench 101 is formed, the remaining second doped region 3 is located in the first epitaxial layer 2 at the second side surface of the gate trench 101. The bottom surface of the second doped region 3 is located below the bottom surface of the gate trench 101 and the second doped region 3 also extends directly below the bottom surface of the gate trench 101. The second doped region 3 extending directly below the bottom surface of the gate trench 101 can be regarded as a buried layer.

[0121] In the method according to the embodiment of the present invention, the steps of forming the gate trench 101 include:

[0122] depositing an oxide layer as an etching mask layer;

[0123] Then, photolithography is performed to define the formation area of ​​the gate trench 101, and then the etching mask layer is etched;

[0124] Afterwards, the first epitaxial layer 2 is subjected to reactive ion etching using the etching mask layer as a mask to form a gate trench 101 .

[0125] Step 72: Figure 7 As shown, a bottom dielectric layer 4 is formed on the bottom surface of the gate trench 101 .

[0126] In the method of the embodiment of the present invention, the material of the bottom dielectric layer 4 includes an oxide layer. The oxide layer of the bottom dielectric layer 4 is grown by a deposition process and its thickness is controlled by an etching process. The etching process is used to make the top surface of the bottom dielectric layer 4 have an arc shape. The steps of forming the bottom dielectric layer 4 include:

[0127] like Figure 6As shown, the deposition of the bottom dielectric layer 4 material is performed.

[0128] Afterwards, etching is performed to form a bottom dielectric layer 4 a located at the bottom of the gate trench 101 . At this time, a mark 4 a is used alone to mark the bottom dielectric layer.

[0129] like Figure 7 As shown, the bottom dielectric layer 4 a is further etched so that the top surface of the bottom dielectric layer 4 a is rounded, and finally the required bottom dielectric layer 4 is formed.

[0130] Step 73: Figure 8 As shown, a first gate dielectric layer 5 is formed on the side of the gate trench 101 .

[0131] In the embodiment of the present invention, the material of the bottom dielectric layer 4 is the same as that of the first gate dielectric layer 5, and the thickness of the bottom dielectric layer 4 is greater than that of the first gate dielectric layer 5. By thickening the bottom dielectric layer 4, the reliability of the device can be enhanced.

[0132] The material of the first gate dielectric layer 5 includes an oxide layer. The oxide layer of the first gate dielectric layer 5 is formed by a thermal oxidation process. Before the thermal oxidation, a carbon capping step is performed. The thermal oxidation process is achieved by annealing at a high temperature above 1600°C. The thermal process of the thermal oxidation process also activates the injected impurities.

[0133] Step 74: Figure 9 As shown, the gate trench 101 is filled with a first gate conductive material layer 6 .

[0134] In the method of the embodiment of the present invention, the first gate conductive material layer 6 comprises a polysilicon gate, which is formed by depositing polysilicon and patterning and etching the polysilicon.

[0135] Step 8: Form a planar gate on the top surface of the second doping region 3 between the third doping region 9 and the fourth doping region 17; the planar gate includes a second gate dielectric layer 15 and a second gate conductive material layer 16 stacked in sequence. The steps of forming the planar gate include:

[0136] Step 81: Figure 9 As shown, the first gate dielectric layer 5 outside the gate trench 101 is thinned by a CMP process to obtain a second gate dielectric layer 15 .

[0137] In some embodiments, the thickness of the second gate dielectric layer 15 is 10 nm to 100 nm.

[0138] Step 82: Figure 10 As shown, polysilicon deposition is performed to obtain a polysilicon layer 16a.

[0139] like Figure 11As shown, etching is performed to form a second gate conductive material layer 16 .

[0140] After that, it also includes:

[0141] like Figure 12 As shown, an interlayer film 10 is formed.

[0142] Back to Figure 2 As shown, pattern etching is performed to form a plurality of through-hole openings passing through the interlayer film 10 .

[0143] An ohmic contact alloy 11 is formed on the bottom surfaces of the through-hole openings corresponding to the source region 8 , the first well region 7 , and the third doping region 9 .

[0144] The steps of forming the ohmic contact alloy 11 include: depositing Ni alloy, and annealing at a temperature of 900-1200° C. to form the ohmic contact alloy 11 .

[0145] A metal is filled in each through-hole opening to form a through-hole 12 .

[0146] A front metal layer 13 is formed. In some embodiments, the front metal layer 13 is formed by Al deposition. The front metal layer 13 is patterned and etched to form a source electrode. The source region 8, the first well region 7, the third doped region 9, and the second gate conductive material layer 16 are all connected to the source electrode through corresponding vias 12 at the top.

[0147] A drain electrode composed of a back metal layer 14 is formed on the back side of the drain region 1. In some embodiments, the back metal layer 14 is formed by back sputtering a Ni alloy and then annealing.

[0148] In the embodiment of the present invention, the trench MOSFET is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the trench MOSFET may be a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0149] As can be seen from the above, in the method of the embodiment of the present invention, the trench gate is formed after forming the second doping region 3, the first well region 7, the third doping region 9, and the fourth doping region 17, and then the planar gate is formed. In this way, the second gate dielectric layer 15 does not need to be formed separately, and can be obtained by performing CMP thinning on the first gate dielectric layer 5 located on the outer surface of the gate trench 101. In other embodiment methods, the trench gate formation step can also be placed before or after the corresponding formation steps of the second doping region 3, the first well region 7, the third doping region 9, and the fourth doping region 17 as needed.

[0150] The trench MOSFET of the embodiment of the present invention is a trench silicon carbide MOSFET with an integrated gate-controlled diode. When the device is operating normally, a forward bias voltage is applied to the gate of the MOSFET region, the channel is opened, and electrons flow from the source to the drain under the action of the electric field, forming a current Ids from the drain to the source, as shown in FIG. Figure 13 As shown by the arrow line corresponding to the dotted line 203; when the device is turned off and enters the third quadrant working state, the positive potential difference from the source to the drain causes the diode region to be turned on. Since the gate of the gate-controlled diode is short-circuited with the source, the gate-controlled diode is turned on, forming a current Isd from the source to the drain, as shown Figure 14 The dashed line 204 corresponds to the arrow line.

[0151] In half-bridge or full-bridge applications, for example, silicon carbide MOSFETs typically require anti-parallel silicon carbide Schottky diodes for freewheeling. The embodiments of the present invention can avoid the need for additional freewheeling diodes to be connected in parallel.

[0152] Taking an N-type device as an example, the embodiment of the present invention utilizes a trench plus P-type buried layer structure, i.e., a gate trench 101 plus a second doped region 3 extending directly below the bottom surface of the gate trench 101. This significantly reduces the Miller capacitance of the device, thereby reducing the switching losses of the device. Furthermore, the addition of the P-type buried layer weakens the electric field concentration at the bottom and corners of the trench. The gate oxide layer is formed through a two-step deposition and thermal oxidation process, making the oxide layer thickness at the bottom of the trench greater than the oxide layer thickness on the trench sidewalls. This also makes the chamfer at the bottom of the trench smoother, reducing the curvature effect and improving the long-term reliability of the device.

[0153] The embodiment of the present invention monolithically integrates a gate-controlled diode. A planar polysilicon layer, i.e., the second gate conductive material layer 16, is short-circuited with the source metal to form the gate-controlled diode. An N-type contact region, i.e., the third doped region 9, is formed above the P-type buried layer using the impurity compensation effect. The gate-controlled diode's forward voltage drop is adjusted using a thin gate oxide layer, i.e., the second gate dielectric layer 15, and planar polysilicon. The gate-controlled diode integrated in the embodiment of the present invention is a rectifier based on the MOSFET diode connection. Compared to the body diode of a conventional MOSFET, the rectifier implemented in the embodiment of the present invention has the advantages of a lower forward voltage drop and unipolar conduction (no reverse recovery current and no double-bounce degradation). This rectifier can be used as a freewheeling diode for a MOSFET, significantly reducing dynamic losses.

[0154] The present invention has been described in detail above by means of specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may make many variations and improvements, which should also be considered as the scope of protection of the present invention.

Claims

1. A trench MOSFET, characterized in that: include: a first epitaxial layer doped with a first conductivity type, with a drain region heavily doped with the first conductivity type formed on the back side of the first epitaxial layer; A trench gate, comprising a bottom dielectric layer formed on the bottom surface of a gate trench, a first gate dielectric layer formed on a side of the gate trench, and a first gate conductive material layer filled in the gate trench; a first well region of the second conductivity type, formed in the first epitaxial layer at a first side surface of the gate trench, wherein a bottom surface of the first well region is located above a bottom surface of the gate trench; a surface of the first well region covered by a side surface of the first gate conductive material layer is used to form a first channel region of the MOSFET; A source region heavily doped with a first conductivity type is formed in a surface area of ​​the first well region, a second side surface of the first well region and a second side surface of the source region are aligned with the first side surface of the gate trench, the first side surface of the source region is located inside the first side surface of the first well region, and the first epitaxial layer is outside the first side surface of the first well region; a second doped region of a second conductivity type, formed in the first epitaxial layer at a second side surface of the gate trench, wherein a bottom surface of the second doped region is located below a bottom surface of the gate trench and further extends to directly below the bottom surface of the gate trench; A third doped region heavily doped with the first conductivity type is formed in a surface area of ​​the second doped region, wherein a first side surface of the third doped region and a first side surface of the second doped region are aligned with the second side surface of the gate trench, and a second side surface of each third doped region is located inward of the second side surface of the second doped region; A fourth doping region doped with the first conductive type is formed on the top surface of the first epitaxial layer outside the second side surface of the second doping region; A planar gate is formed on a top surface of the second doping region between the third doping region and the fourth doping region; The planar gate comprises a second gate dielectric layer and a second gate conductive material layer stacked in sequence; The source region, the first well region, the third doped region and the second gate conductive material layer are all connected to the source electrode composed of the front metal layer through corresponding top through-holes; The surface of the second doped region covered by the side surface of the second gate conductive material layer is used to form a second channel region of the gate-controlled diode.

2. The trench MOSFET according to claim 1, wherein: The material of the first epitaxial layer is a semiconductor material having a band gap width greater than that of silicon.

3. The trench MOSFET according to claim 2, wherein: The material of the first epitaxial layer includes SiC.

4. The trench MOSFET according to claim 1, wherein: The bottom dielectric layer, the first gate dielectric layer and the second gate dielectric layer are made of the same material. The bottom dielectric layer is thicker than the first gate dielectric layer, and the second gate dielectric layer is thinner than the first gate dielectric layer.

5. The trench MOSFET according to claim 4, wherein: The material of the bottom dielectric layer includes an oxide layer; the top surface of the bottom dielectric layer is in an arc shape; The first gate conductive material layer includes a polysilicon gate; The second gate conductive material layer includes a polysilicon gate.

6. The trench MOSFET according to claim 5, wherein: The thickness of the second gate dielectric layer is 10 nm to 100 nm.

7. The trench MOSFET according to claim 1, wherein: The doping concentration of the first epitaxial layer is 1E15cm -3 ~1E17cm -3 ; The doping concentration of the second doping region is 1E14 cm -3 ~1E16cm -3 ; The doping concentration of the third doping region is less than or equal to 1E16 cm -3 .

8. The trench MOSFET according to claim 1, wherein: Ohmic contact alloy is formed on the bottom surfaces of the through holes corresponding to the source region, the first well region, and the third doping region.

9. The field effect transistor according to any one of claims 1 to 8, characterized in that: The trench MOSFET is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the trench MOSFET is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

10. A method for manufacturing a trench MOSFET, characterized in that: The steps include: forming a first epitaxial layer doped with a first conductivity type, and forming a drain region heavily doped with the first conductivity type on the back side of the first epitaxial layer; forming a second doping region of a second conductivity type in the first epitaxial layer, wherein a junction depth of the second doping region is greater than a depth of the gate trench; forming a first well region of the second conductivity type in the first epitaxial layer, wherein a junction depth of the first well region is smaller than a depth of the gate trench; forming a trench gate, the trench gate comprising a bottom dielectric layer formed on a bottom surface of a gate trench, a first gate dielectric layer formed on a side surface of the gate trench, and a first gate conductive material layer filled in the gate trench; forming a heavily doped source region of the first conductivity type in a surface area of ​​the first well region, wherein the second side surface of the first well region and the second side surface of the source region are aligned with the first side surface of the gate trench, the first side surface of the source region is located inside the first side surface of the first well region, and the first epitaxial layer is located outside the first side surface of the first well region; A third doped region heavily doped with the first conductivity type is formed in a surface area of ​​the second doped region, wherein a first side surface of the third doped region and a first side surface of the second doped region are aligned with the second side surface of the gate trench, and a second side surface of each third doped region is located inward of the second side surface of the second doped region; A fourth doping region doped with the first conductive type is formed on the top surface of the first epitaxial layer outside the second side surface of the second doping region; forming a planar gate on a top surface of the second doping region between the third doping region and the fourth doping region; the planar gate comprises a second gate dielectric layer and a second gate conductive material layer stacked in sequence; forming an interlayer film, a through hole and a front metal layer, and patterning and etching the front metal layer to form a source electrode; the source region, the first well region, the third doped region and the second gate conductive material layer are all connected to the source electrode composed of the front metal layer through corresponding through holes on the top; The surface of the second doped region covered by the side surface of the second gate conductive material layer is used to form a second channel region of the gate-controlled diode; A drain electrode composed of a back metal layer is formed on the back side of the drain region.

11. The method for manufacturing a trench MOSFET according to claim 10, wherein: The material of the first epitaxial layer is a semiconductor material having a band gap width greater than that of silicon.

12. The method for manufacturing a trench MOSFET according to claim 11, wherein: The material of the first epitaxial layer includes SiC.

13. The method for manufacturing a trench MOSFET according to claim 10, wherein: The bottom dielectric layer, the first gate dielectric layer and the second gate dielectric layer are made of the same material. The bottom dielectric layer is thicker than the first gate dielectric layer, and the second gate dielectric layer is thinner than the first gate dielectric layer.

14. The trench MOSFET according to claim 13, wherein: The material of the bottom dielectric layer includes an oxide layer; the top surface of the bottom dielectric layer is in an arc shape; The first gate conductive material layer includes a polysilicon gate; The second gate conductive material layer includes a polysilicon gate; The trench gate is formed after forming the second doping region, the first well region, the third doping region, and the fourth doping region, and then the planar gate is formed, including the following steps: Performing patterned etching on the first epitaxial layer to form the gate trench; The bottom dielectric layer is formed at the bottom of the gate trench by using an oxide layer deposition and etching process, and the top surface of the bottom dielectric layer is made into an arc shape by using an etching process; forming a first gate dielectric layer on the side of the gate trench by a thermal oxidation process, wherein the first gate dielectric layer is also formed on the surface of the first epitaxial layer outside the gate trench; Performing polysilicon deposition and etching to form the first gate conductive material layer in the gate trench; thinning the first gate dielectric layer outside the gate trench by using a CMP process to obtain the second gate dielectric layer; Polysilicon deposition and etching are performed to form the second gate conductive material layer.

15. The method for manufacturing a trench MOSFET according to claim 14, wherein: The thickness of the second gate dielectric layer is 10 nm to 100 nm.

16. The method for manufacturing a trench MOSFET according to claim 10, wherein: The doping concentration of the first epitaxial layer is 1E15cm -3 ~1E17cm -3 ; The doping concentration of the second doping region is 1E14 cm -3 ~1E16cm -3 ; The doping concentration of the third doping region is less than or equal to 1E16 cm -3 .

17. The field effect transistor according to any one of claims 10 to 16, characterized in that: The trench MOSFET is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the trench MOSFET is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

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