Groove type MOSFET and manufacturing method thereof
By integrating a Schottky diode into a trench MOSFET, the Miller capacitance and body diode conduction voltage drop problems of SiC VDMOS devices are solved, reverse freewheeling and reliability are improved, and dynamic losses are reduced.
Patent Information
- Application Number
- CN202510746840.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-05
- Publication Date
- 2025-09-05
AI Technical Summary
Existing SiC VDMOS devices have problems such as large Miller capacitance in the JFET region, high parasitic body diode conduction voltage drop and large reverse recovery current, and the body diode cannot be used as a freewheeling diode.
A trench MOSFET with an integrated Schottky diode is designed. Reverse freewheeling is achieved by forming a third doped region in the second doped region and the first well region of the gate trench, and forming a Schottky contact alloy on the top surface of the third doped region. At the same time, the bottom dielectric layer and gate dielectric layer structure of the gate trench are optimized to reduce the Miller capacitance.
It realizes reverse freewheeling without the need for a body diode or an additional diode, reduces the forward conduction voltage drop and dynamic loss of the device, and improves the reliability of the device and the current capability of the Schottky diode.
Smart Images
Figure CN120603314A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a trench MOSFET; the present invention also relates to a manufacturing method of the trench MOSFET. Background Art
[0002] Wide bandgap semiconductor material SiC is an ideal material for preparing high voltage power electronic devices. Compared with Si material, SiC material has a high breakdown electric field strength (4×10 6 V / cm), high carrier saturation drift velocity (2×10 7 cm / s), high thermal conductivity, good thermal stability, etc., so it is particularly suitable for use in high-power, high-voltage, high-temperature and radiation-resistant electronic devices.
[0003] SiC VDMOS is a commonly used SiC power device. Compared to bipolar devices, SiC VDMOS has better frequency characteristics and lower switching losses because it does not have a charge storage effect. The wide bandgap of SiC material also allows SiC VDMOS to operate at temperatures as high as 300°C.
[0004] However, planar SiC VDMOS has two problems. First, the density of the JFET region is too high, which introduces a large Miller capacitance and increases the dynamic loss of the device. Second, the parasitic SiC body diode has a too high forward voltage drop. As a bipolar device, it has a large reverse recovery current. In addition, the bipolar degradation phenomenon caused by the silicon carbide BPD defect causes the forward voltage drop of the body diode to continue to increase with the increase of usage time. Therefore, the body diode of SiC VDMOS cannot be used directly as a freewheeling diode. Summary of the Invention
[0005] The technical problem to be solved by the present invention is to provide a trench MOSFET that can integrate a Schottky diode, thereby achieving reverse freewheeling without the need for a body diode or an additional parallel diode. This also improves device reliability, reduces Miller capacitance, increases the current capability of the Schottky diode, and reduces the forward voltage drop and dynamic losses of the device. To this end, the present invention also provides a method for manufacturing the trench MOSFET.
[0006] In order to solve the above technical problems, the present invention provides a trench MOSFET comprising:
[0007] A first epitaxial layer doped with a first conductivity type is provided, and a drain region heavily doped with the first conductivity type is formed on the back side of the first epitaxial layer.
[0008] The trench gate comprises a bottom dielectric layer formed on the bottom surface of a gate trench, a gate dielectric layer formed on the side of the gate trench, and a gate conductive material layer filled in the gate trench.
[0009] A first well region of the second conductivity type is formed in the first epitaxial layer at a first side surface of the gate trench, with a bottom surface of the first well region located above the bottom surface of the gate trench. A surface of the first well region covered by the side surface of the gate conductive material layer is used to form a channel region of the MOSFET.
[0010] A source region heavily doped with a first conductivity type is formed in the first well region, a second side surface of the first well region and a second side surface of the source region are aligned with the first side surface of the gate trench, the first side surface of the source region is located inside the first side surface of the first well region, and the first epitaxial layer is outside the first side surface of the first well region;
[0011] A second doped region of a second conductive type is formed in the first epitaxial layer at the second side surface of the gate trench, the bottom surface of the second doped region is located below the bottom surface of the gate trench and the second doped region also extends directly below the bottom surface of the gate trench.
[0012] A third doped region doped with the first conductive type is formed in the surface area of the second doped region, the first side of the third doped region and the first side of the second doped region are aligned with the second side of the gate trench, the second side of the third doped region extends to or is aligned with the outside of the second side of the second doped region, and the outside of the second side of the second doped region is the first epitaxial layer.
[0013] The source region, the first well region and the third doped region are all connected to a source electrode composed of a front metal layer through corresponding top through-holes.
[0014] Ohmic contact alloy is formed on bottom surfaces of the source region and the through holes corresponding to the first well region.
[0015] A Schottky contact alloy is formed on the bottom surface of the through hole corresponding to the third doping region, and the Schottky contact alloy contacts the third doping region to form a Schottky diode.
[0016] A further improvement is that a fourth doping region doped with the first conductive type is formed in the surface area of the first epitaxial layer between the second doping region of each gate trench and the first well region or the second doping region corresponding to the adjacent gate trench, the side of the third doping region is in contact with the fourth doping region, and the doping concentration of the fourth doping region is greater than the doping concentration of the first epitaxial layer.
[0017] A further improvement is that the material of the first epitaxial layer is a semiconductor material having a band gap width greater than the band gap width of silicon.
[0018] A further improvement is that the material of the first epitaxial layer includes SiC.
[0019] A further improvement is that the material of the bottom dielectric layer is the same as that of the gate dielectric layer, and the thickness of the bottom dielectric layer is greater than that of the gate dielectric layer.
[0020] A further improvement is that the material of the bottom dielectric layer includes an oxide layer; the top surface of the bottom dielectric layer is arc-shaped;
[0021] The material of the gate dielectric layer includes an oxide layer;
[0022] The gate conductive material layer includes a polysilicon gate.
[0023] A further improvement is that the doping concentration of the first epitaxial layer is 1E15cm -3 ~1E17cm -3 ;
[0024] The doping concentration of the second doping region is 1E14 cm -3 ~1E16cm -3 ;
[0025] The doping concentration of the third doping region is less than or equal to 1E16 cm -3 .
[0026] A further improvement is that the trench MOSFET is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the trench MOSFET is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.
[0027] To solve the above technical problems, the present invention provides a method for manufacturing a trench MOSFET comprising the following steps:
[0028] A first epitaxial layer doped with a first conductivity type is formed, and a drain region heavily doped with the first conductivity type is formed on the back side of the first epitaxial layer.
[0029] A plurality of second doping regions of a second conductivity type are formed in the first epitaxial layer.
[0030] A plurality of gate trenches are formed in the first epitaxial layer, and the etched area of the gate trenches includes a portion of the second doped region. After the gate trenches are formed, the retained second doped region is located in the first epitaxial layer at the second side surface of the gate trench, and the bottom surface of the second doped region is located below the bottom surface of the gate trench and the second doped region also extends to directly below the bottom surface of the gate trench.
[0031] A bottom dielectric layer is formed on the bottom surface of the gate trench.
[0032] A gate dielectric layer is formed on the side of the gate trench.
[0033] A gate conductive material layer is filled in the gate trench.
[0034] A first well region of the second conductivity type is formed in the first epitaxial layer at a first side surface of the gate trench, wherein a bottom surface of the first well region is located above a bottom surface of the gate trench. A surface of the first well region covered by a side surface of the gate conductive material layer is used to form a channel region of the MOSFET.
[0035] A source region heavily doped with the first conductivity type is formed in the first well region, the second side surface of the first well region and the second side surface of the source region are aligned with the first side surface of the gate trench, the first side surface of the source region is located inside the first side surface of the first well region, and the first epitaxial layer is outside the first side surface of the first well region.
[0036] A third doped region doped with the first conductive type is formed in the surface area of the second doped region, the first side of the third doped region and the first side of the second doped region are aligned with the second side of the gate trench, the second side of the third doped region extends to or is aligned with the outside of the second side of the second doped region, and the outside of the second side of the second doped region is the first epitaxial layer.
[0037] An interlayer film is formed.
[0038] Pattern etching is performed to form a plurality of through-hole openings passing through the interlayer film.
[0039] An ohmic contact alloy is formed on bottom surfaces of the through-hole openings corresponding to the source region and the first well region.
[0040] A Schottky contact alloy is formed on the bottom surface of the through-hole opening corresponding to the third doping region, and the Schottky contact alloy contacts the third doping region to form a Schottky diode.
[0041] Metal is filled in each of the through-hole openings to form a through-hole.
[0042] A front metal layer is formed, and the front metal layer is patterned and etched to form a source electrode; the source region, the first well region, and the third doped region are all connected to the source electrode through corresponding through holes on the top.
[0043] A drain electrode composed of a back metal layer is formed on the back side of the drain region.
[0044] A further improvement is that, before forming the interlayer film, the method further comprises:
[0045] A fourth doping region doped with the first conductive type is formed in the surface area of the first epitaxial layer between the second doping region of each gate trench and the first well region or the second doping region corresponding to the adjacent gate trench, the side of the third doping region is in contact with the fourth doping region, and the doping concentration of the fourth doping region is greater than the doping concentration of the first epitaxial layer.
[0046] A further improvement is that the material of the first epitaxial layer is a semiconductor material having a band gap width greater than the band gap width of silicon.
[0047] A further improvement is that the material of the first epitaxial layer includes SiC.
[0048] A further improvement is that the material of the bottom dielectric layer is the same as that of the gate dielectric layer, and the thickness of the bottom dielectric layer is greater than that of the gate dielectric layer.
[0049] A further improvement is that the material of the bottom dielectric layer includes an oxide layer, the oxide layer of the bottom dielectric layer is grown by a deposition process and its thickness is controlled by an etching process, and the top surface of the bottom dielectric layer is arc-shaped by the etching process.
[0050] The material of the gate dielectric layer includes an oxide layer, and the oxide layer of the gate dielectric layer is formed by a thermal oxidation process;
[0051] The gate conductive material layer includes a polysilicon gate.
[0052] A further improvement is that the doping concentration of the first epitaxial layer is 1E15cm -3 ~1E17cm -3 ;
[0053] The doping concentration of the second doping region is 1E14 cm -3 ~1E16cm -3 ;
[0054] The doping concentration of the third doping region is less than or equal to 1E16 cm -3 .
[0055] A further improvement is that the trench MOSFET is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the trench MOSFET is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.
[0056] The present invention forms a MOSFET channel region only on one side of the gate trench, forms a second doped region with a depth greater than the gate trench on the other side of the gate trench, and forms a third doped region with a first type of doping with the same or greater width on the top surface of the second doped region, so that the third doped region can contact the first epitaxial layer on the outside, and a Schottky contact alloy is formed on the top surface of the third doped region and connected to the source through a through hole, so that a Schottky diode can be integrated in the trench MOSFET, and the Schottky diode can be turned on in the third quadrant working state, and the conduction path is the source, Schottky contact alloy, third doped region, first epitaxial layer, drain region to drain. Therefore, the present invention can integrate a Schottky diode, thereby achieving reverse freewheeling without using a body diode or an additional parallel diode.
[0057] In addition, part of the second doped region of the present invention is located directly below the bottom surface of the trench gate, which can share the electric field strength of the gate dielectric layer at the bottom of the gate trench in the off state, thereby improving the long-term reliability of the device; at the same time, after the second doped region extends to the bottom of the gate trench, it can reduce the overlapping area between the gate and the drain, thereby significantly reducing the Miller capacitance and thus reducing the switching damage of the device.
[0058] Furthermore, the bottom dielectric layer at the bottom surface of the gate trench in the trench gate of the present invention and the gate dielectric layer on the side of the gate trench are independent structures, meaning that their materials and thicknesses can be independently set. By improving the reliability of the bottom dielectric layer, the reliability of the entire device can be improved. For example, when both the bottom dielectric layer and the gate dielectric layer are oxide layers, increasing the thickness of the bottom dielectric layer can increase device reliability. Furthermore, the bottom surface of the gate trench of the present invention is smoother, further improving device reliability.
[0059] The Schottky diode of the present invention is formed in the surface area of the second doping region, that is, the area of the second doping region is fully utilized to achieve the integration of the Schottky diode, which can greatly reduce the unit spacing and unit cell size of the integrated Schottky diode.
[0060] In addition, the present invention can also form a fourth doped region of the first conductivity type with a higher doping concentration in the top region of the first epitaxial layer that contacts the side of the third doped region, thereby increasing the first conductivity type doping concentration in the top region of the first epitaxial layer, thereby increasing the current capacity of the Schottky diode, reducing the forward conduction voltage drop and thereby reducing dynamic loss.
[0061] In addition, the second doped region corresponding to the gate trench is adjacent to the second doped region or the first well region of the adjacent gate trench. This adjacent structure can deplete the first epitaxial layer between them during reverse cutoff, thereby greatly reducing the leakage risk of the Schottky diode. BRIEF DESCRIPTION OF THE DRAWINGS
[0062] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
[0063] Figure 1 3D schematic diagram of the trench MOSFET according to an embodiment of the present invention;
[0064] Figure 2 is a cross-sectional view taken along the xy plane of a trench MOSFET according to an embodiment of the present invention;
[0065] Figure 3-Figure 12 Schematic diagram of the device structure in each step of the method for manufacturing a trench MOSFET according to an embodiment of the present invention;
[0066] Figure 13 1 is a schematic diagram of an equivalent circuit of a trench MOSFET in a forward conduction state according to an embodiment of the present invention;
[0067] Figure 14 Schematic diagram of the equivalent circuit of the trench MOSFET in the embodiment of the present invention during reverse freewheeling. DETAILED DESCRIPTION
[0068] like Figure 1 FIG. 1 is a schematic diagram of the three-dimensional structure of a trench MOSFET according to an embodiment of the present invention; FIG. Figure 2 FIG. 1 is a cross-sectional view of a trench MOSFET according to an embodiment of the present invention taken along an xy plane. The trench MOSFET according to an embodiment of the present invention includes:
[0069] The first epitaxial layer 2 is doped with the first conductivity type, and a drain region 1 heavily doped with the first conductivity type is formed on the back surface of the first epitaxial layer 2. A drain electrode composed of a back metal layer 14 is formed on the back surface of the drain region 1.
[0070] The trench gate includes a bottom dielectric layer 4 formed on the bottom surface of the gate trench 101, a gate dielectric layer 5 formed on the side of the gate trench 101, and a gate conductive material layer 6 filled in the gate trench 101. Figure 4 shown.
[0071] A first well region 7 of the second conductivity type is formed in the first epitaxial layer 2 at a first side surface of the gate trench 101 , and a bottom surface of the first well region 7 is located above the bottom surface of the gate trench 101 .
[0072] A source region 8 heavily doped with the first conductivity type is formed in the first well region 7. The second side surface of the first well region 7 and the second side surface of the source region 8 are aligned with the first side surface of the gate trench 101. The first side surface of the source region 8 is located on the inner side of the first side surface of the first well region 7. The outer side surface of the first well region 7 is the first epitaxial layer 2.
[0073] A second doping region 3 of the second conductivity type is formed in the first epitaxial layer 2 at the second side surface of the gate trench 101. The bottom surface of the second doping region 3 is located below the bottom surface of the gate trench 101 and the second doping region 3 also extends directly below the bottom surface of the gate trench 101.
[0074] A third doping region 9 doped with the first conductive type is formed in the surface area of the second doping region 3. The first side surface of the third doping region 9 and the first side surface of the second doping region 3 are aligned with the second side surface of the gate trench 101. The second side surface of the third doping region 9 extends to or is aligned with the outside of the second side surface of the second doping region 3. The outside of the second side surface of the second doping region 3 is the first epitaxial layer 2.
[0075] The source region 8, the first well region 7 and the third doped region 9 are all connected to the source electrode composed of the front metal layer 13 through the corresponding via 12 on the top. The via 12 passes through the interlayer film 10. Figure 1 The structural diagram of the interlayer film 10, the through hole 12 and the front metal layer 13 is omitted.
[0076] Ohmic contact alloys 11 a are formed on the bottom surfaces of the through holes 12 corresponding to the source region 8 and the first well region 7 .
[0077] A Schottky contact alloy 11 b is formed on the bottom surface of the through hole 12 corresponding to the third doping region 9 . The Schottky contact alloy 11 b contacts the third doping region 9 to form a Schottky diode.
[0078] The gate conductive material layer 6 is connected to the gate formed by the front metal layer 13 .
[0079] A drain electrode composed of a back metal layer 14 is formed on the back side of the drain region 1 .
[0080] The surface of the first well region 7 covered by the gate conductive material layer 6 is used to form a channel region of the MOSFET.
[0081] In the embodiment of the present invention, a fourth doped region 15 doped with the first conductivity type is formed in the surface region of the first epitaxial layer 2 between the second doped region 3 of each gate trench 101 and the first well region 7 or second doped region 3 corresponding to the adjacent gate trench 101. The side of the third doped region 9 contacts the fourth doped region 15, and the doping concentration of the fourth doped region 15 is greater than the doping concentration of the first epitaxial layer 2. When the Schottky diode is turned on, current flows from the source through the Schottky diode into the third doped region 9, then into the first epitaxial layer 2, and finally into the drain. The fourth doped region 15 increases the top doping concentration of the first epitaxial layer 2, thereby reducing the resistance from the third doped region 9 to the fourth doped region 15. Therefore, the current capability of the Schottky diode is increased. At the same time, the fourth doped region 15 also reduces the forward voltage drop of the device and thus reduces dynamic loss.
[0082] In an embodiment of the present invention, the material of the first epitaxial layer 2 is a semiconductor material having a bandgap greater than that of silicon. Preferably, the material of the first epitaxial layer 2 includes SiC. In other embodiments, the first epitaxial layer 2 may also be made of other suitable semiconductor materials, which can be selected based on actual needs.
[0083] The material of the bottom dielectric layer 4 is the same as that of the gate dielectric layer 5 , and the thickness of the bottom dielectric layer 4 is greater than that of the gate dielectric layer 5 .
[0084] In some embodiments, the material of the bottom dielectric layer 4 includes an oxide layer; and the top surface of the bottom dielectric layer 4 is arc-shaped.
[0085] The material of the gate dielectric layer 5 includes an oxide layer.
[0086] The gate conductive material layer 6 includes a polysilicon gate.
[0087] In some embodiments, the doping concentration of the first epitaxial layer 2 is 1E15 cm -3 ~1E17cm -3 .
[0088] The doping concentration of the second doping region 3 is 1E14 cm -3 ~1E16cm -3 .
[0089] The doping concentration of the third doping region 9 is less than or equal to 1E16 cm -3 .
[0090] In the embodiment of the present invention, the trench MOSFET is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the trench MOSFET can also be a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.
[0091] In the embodiment of the present invention, the channel region of the MOSFET is formed only on one side of the gate trench 101, and a second doping region 3 with a depth greater than the gate trench 101 is formed on the other side of the gate trench 101, and a third doping region 9 of the first type doping with the same or greater width is formed on the top surface of the second doping region 3, so that the third doping region 9 can be in contact with the first epitaxial layer 2 on the outside, and a Schottky contact alloy 11b is formed on the top surface of the third doping region 9 and connected to the source through the through hole 12, so that a Schottky diode can be integrated in the trench MOSFET, and the Schottky diode can be turned on in the third quadrant working state, and the conduction path is the source, Schottky contact alloy 11b, third doping region 9, first epitaxial layer 2, drain region 1 to the drain, so the embodiment of the present invention can integrate the Schottky diode, so that reverse freewheeling can be achieved without using a body diode or an additional parallel diode.
[0092] In addition, part of the second doped region 3 of the embodiment of the present invention is located directly below the bottom surface of the trench gate, which can share the electric field strength of the gate dielectric layer 5 at the bottom of the gate trench 101 in the off state, thereby improving the long-term reliability of the device; at the same time, after the second doped region 3 extends to the bottom of the gate trench 101, it can reduce the overlapping area between the gate and the drain, thereby significantly reducing the Miller capacitance, thereby reducing the switching damage of the device.
[0093] In addition, the bottom dielectric layer 4 on the bottom surface of the gate trench 101 and the gate dielectric layer 5 on the side of the gate trench 101 in the trench gate of the embodiment of the present invention are independent structures, that is, the material and thickness can be independently set. By improving the reliability of the bottom dielectric layer 4, the reliability of the entire device can be improved. For example, when both the bottom dielectric layer 4 and the gate dielectric layer 5 are oxide layers, the reliability of the device can be increased by increasing the thickness of the bottom dielectric layer 4. In addition, the bottom surface of the gate trench 101 in the embodiment of the present invention is smoother, which can further improve the reliability of the device.
[0094] The Schottky diode of the embodiment of the present invention is formed in the surface area of the second doping region 3, that is, the area of the second doping region 3 is fully utilized to realize the integration of the Schottky diode, which can greatly reduce the unit spacing and unit cell size of the integrated Schottky diode.
[0095] In addition, the embodiment of the present invention can also form a fourth doping region 15 of the first conductive type with a higher doping concentration in the top area of the first epitaxial layer 2 that contacts the side of the third doping region 9. This can increase the first conductive type doping concentration in the top area of the first epitaxial layer 2, thereby increasing the current capability of the Schottky diode, reducing the forward conduction voltage drop and thereby reducing dynamic loss.
[0096] In addition, the second doped region 3 corresponding to the gate trench 101 is adjacent to the second doped region 3 or the first well region 7 of the adjacent gate trench 101. This adjacent structure can deplete the first epitaxial layer 2 therebetween during reverse cutoff, thereby greatly reducing the leakage risk of the Schottky diode.
[0097] like Figure 13 , which is a schematic diagram of the equivalent circuit of a trench MOSFET according to an embodiment of the present invention during forward conduction; the trench MOSFET is integrated with a MOSFET 201 and a Schottky diode 202. During forward conduction, the gate is applied with a positive voltage greater than the threshold voltage of MOSFET 201, and the drain is applied with a voltage greater than the source. This causes the channel region of MOSFET 201 to conduct, thereby forming a drain-to-source current Ids, as shown by the dotted line 203, flowing through the first channel region of MOSFET 201. MOSFET 201 itself has a body diode formed between the first well region 7 and the first epitaxial layer 2. During forward conduction, both the body diode and the Schottky diode 202 are reverse biased, thereby being cut off.
[0098] like Figure 14 FIG. 1 is a schematic diagram of an equivalent circuit of a trench MOSFET in a reverse freewheeling state according to an embodiment of the present invention. Figure 14 The corresponding operating state is the third quadrant operating state. When the gate voltage is less than the threshold voltage of MOSFET 201, such as 0V, MOSFET 201 is turned off, the source voltage is greater than the drain voltage, and Schottky diode 202 is forward biased and turned on, achieving the source-to-drain current Isd shown by the dotted line 204 through the conduction of Schottky diode 202. At the same time, because the barrier of Schottky diode 202 is lower than the barrier of the body diode, Schottky diode 202 is turned on first.
[0099] When the device is reverse cutoff, it returns to Figure 2 As shown, the first epitaxial layer 2 on the conduction path of the Schottky diode 202 is located between the first well region 7 and the adjacent second doped region 3, so the first epitaxial layer 2 on the conduction path of the Schottky diode 202 will be depleted, thereby greatly reducing the leakage risk of the Schottky diode 202.
[0100] like Figures 3 to 12 , which is a schematic diagram of the device structure in each step of the method for manufacturing a trench MOSFET according to an embodiment of the present invention, wherein the corresponding cross section is the xy plane; the method for manufacturing a trench MOSFET according to an embodiment of the present invention comprises the following steps:
[0101] Step 1: Figure 3 As shown, a first epitaxial layer 2 doped with the first conductivity type is formed, and a drain region 1 heavily doped with the first conductivity type is formed on the back side of the first epitaxial layer 2 .
[0102] In the embodiment of the present invention, the material of the first epitaxial layer 2 is a semiconductor material having a band gap greater than that of silicon. Preferably, the material of the first epitaxial layer 2 includes SiC.
[0103] In the method of the embodiment of the present invention, the drain region 1 is composed of a semiconductor substrate, the first epitaxial layer 2 is formed on the semiconductor substrate, and the semiconductor substrate and the first epitaxial layer are made of the same material, for example, SiC.
[0104] Step 2: Figure 3 As shown, a plurality of second doping regions 3 of the second conductivity type are formed in the first epitaxial layer 2 . Figure 4 Two second doping regions 3 are shown in the figure, but in practice more can be provided as needed.
[0105] In the method of the embodiment of the present invention, the formation area of the second doped region 3 is defined by photolithography. Before the photolithography process, an ion implantation mask layer is formed on the surface of the first epitaxial layer 2. The material of the ion implantation mask layer includes an oxide layer. After the photolithography process, the ion implantation mask layer needs to be patterned before ion implantation. The ion implantation mask layer is then removed and the surface is cleaned. In the method of the embodiment of the present invention, the trench MOSFET is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In this case, the second doped region 3 is P-type doped, and the implanted impurities in the second doped region 3 include Al. The implantation temperature condition is 300K to 1000K. In other embodiments, the field effect transistor can also be a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type. In this case, the second doped region 3 is an N-type buried layer.
[0106] Step 3: Figure 4 As shown, multiple gate trenches 101 are formed in the first epitaxial layer 2. The etched areas of the gate trenches 101 include portions of the second doped regions 3. After the gate trenches 101 are formed, the remaining second doped regions 3 are located in the first epitaxial layer 2 at the second side of the gate trenches 101. The bottom surfaces of the second doped regions 3 are located below the bottom surfaces of the gate trenches 101 and extend directly below the bottom surfaces of the gate trenches 101. The second doped regions 3 extending directly below the bottom surfaces of the gate trenches 101 can be considered as buried layers.
[0107] In the method according to the embodiment of the present invention, the steps of forming the gate trench 101 include:
[0108] depositing an oxide layer as an etching mask layer;
[0109] Then, photolithography is performed to define the formation area of the gate trench 101, and then the etching mask layer is etched;
[0110] Afterwards, the first epitaxial layer 2 is subjected to reactive ion etching using the etching mask layer as a mask to form a gate trench 101 .
[0111] Step 4: forming a bottom dielectric layer 4 on the bottom surface of the gate trench 101 .
[0112] In the method of the embodiment of the present invention, the material of the bottom dielectric layer 4 includes an oxide layer. The oxide layer of the bottom dielectric layer 4 is grown by a deposition process and its thickness is controlled by an etching process. The etching process is used to make the top surface of the bottom dielectric layer 4 have an arc shape. The steps of forming the bottom dielectric layer 4 include:
[0113] like Figure 5 As shown, the deposition of the bottom dielectric layer 4 material is performed.
[0114] Afterwards, etching is performed to form a bottom dielectric layer 4 a located at the bottom of the gate trench 101 . At this time, a mark 4 a is used alone to mark the bottom dielectric layer.
[0115] like Figure 6 As shown, the bottom dielectric layer 4 a is further etched so that the top surface of the bottom dielectric layer 4 a is rounded, and finally the required bottom dielectric layer 4 is formed.
[0116] Step 5: Figure 7 As shown, a gate dielectric layer 5 is formed on the side of the gate trench 101 .
[0117] In the embodiment of the present invention, the material of the bottom dielectric layer 4 is the same as that of the gate dielectric layer 5, and the thickness of the bottom dielectric layer 4 is greater than that of the gate dielectric layer 5. By thickening the bottom dielectric layer 4, the reliability of the device can be enhanced.
[0118] The material of the gate dielectric layer 5 includes an oxide layer. The oxide layer of the gate dielectric layer 5 is formed by a thermal oxidation process. Before the thermal oxidation process, a carbon capping step is performed. The thermal oxidation process is achieved by annealing at a high temperature above 1600°C. The thermal process of the thermal oxidation process also activates the injected impurities.
[0119] Step 6: Figure 7 As shown, the gate trench 101 is filled with a gate conductive material layer 6 .
[0120] In the method of the embodiment of the present invention, the gate conductive material layer 6 comprises a polysilicon gate, which is formed by depositing polysilicon and patterning and etching the polysilicon.
[0121] Step 7: Figure 8 As shown, a first well region 7 of the second conductivity type is formed in the first epitaxial layer 2 at a first side surface of the gate trench 101 , and a bottom surface of the first well region 7 is located above the bottom surface of the gate trench 101 .
[0122] In the method of the embodiment of the present invention, the formation area of the first well region 7 is defined by photolithography. Before the photolithography process, an ion implantation mask layer is formed on the surface of the first epitaxial layer 2. The material of the ion implantation mask layer includes an oxide layer. After the photolithography process, the ion implantation mask layer needs to be patterned before ion implantation. The ion implantation mask layer is then removed and the surface is cleaned. In the method of the embodiment of the present invention, the first well region 7 is P-type doped. The implanted impurity in the first well region 7 includes Al. The implantation temperature is 300K to 1000K.
[0123] Step 8: Figure 9 As shown, a heavily doped source region 8 of the first conductivity type is formed in the first well region 7. The second side surface of the first well region 7 and the second side surface of the source region 8 are aligned with the first side surface of the gate trench 101. The first side surface of the source region 8 is located inside the first side surface of the first well region 7. The first epitaxial layer 2 is located outside the first side surface of the first well region 7. Figure 8 As shown, the source region 8 does not directly contact the first epitaxial layer 2 , and the source region 8 needs to be electrically connected to the first epitaxial layer 2 through the conduction of the first channel region of the MOSFET 201 .
[0124] In the method of the embodiment of the present invention, the formation area of source region 8 is defined by photolithography. Before the photolithography process, an ion implantation mask layer is formed on the surface of the first epitaxial layer 2. The material of the ion implantation mask layer includes an oxide layer. After the photolithography process, the ion implantation mask layer needs to be patterned before ion implantation. The ion implantation mask layer is then removed and the surface is cleaned. In the method of the embodiment of the present invention, source region 8 is N-type doped. The impurities implanted into source region 8 include phosphorus (P) at a temperature of 300K to 1000K.
[0125] Step 9: Figure 10 As shown, a third doping region 9 doped with the first conductive type is formed in the surface area of the second doping region 3, the first side of the third doping region 9 and the first side of the second doping region 3 are aligned with the second side of the gate trench 101, the second side of the third doping region 9 extends to the outside of the second side of the second doping region 3 or is aligned, and the outside of the second side of the second doping region 3 is the first epitaxial layer 2.
[0126] In the method of the embodiment of the present invention, the formation area of the third doped region 9 is defined by photolithography. Before the photolithography process, an ion implantation mask layer is formed on the surface of the first epitaxial layer 2. The material of the ion implantation mask layer includes an oxide layer. After the photolithography process, the ion implantation mask layer needs to be patterned before ion implantation. The ion implantation mask layer is then removed and the surface is cleaned. In the method of the embodiment of the present invention, the third doped region 9 is N-type doped. The implanted impurities in the third doped region 9 include phosphorus. The implantation temperature is 300K to 1000K.
[0127] In some embodiments, the doping concentration of the first epitaxial layer 2 is 1E15 cm -3 ~1E17cm -3 .
[0128] The doping concentration of the second doping region 3 is 1E14 cm -3 ~1E16cm -3 .
[0129] The doping concentration of the third doping region 9 is less than or equal to 1E16 cm -3 .
[0130] Afterwards, it also includes: forming a fourth doping region 15 doped with the first conductive type in the surface area of the first epitaxial layer 2 between the second doping region 3 of each gate trench 101 and the first well region 7 or the second doping region 3 corresponding to the adjacent gate trench 101, the side of the third doping region 9 is in contact with the fourth doping region 15, and the doping concentration of the fourth doping region 15 is greater than the doping concentration of the first epitaxial layer 2.
[0131] In the method of the embodiment of the present invention, the formation area of the fourth doped region 15 is defined by photolithography. Before the photolithography process, an ion implantation mask layer is formed on the surface of the first epitaxial layer 2. The material of the ion implantation mask layer includes an oxide layer. After the photolithography process, the ion implantation mask layer needs to be patterned before ion implantation. The ion implantation mask layer is then removed and the surface is cleaned. In the method of the embodiment of the present invention, the fourth doped region 15 is N-type doped. The implanted impurities in the fourth doped region 15 include phosphorus. The implantation temperature is 300K to 1000K.
[0132] Step 10: Figure 11 As shown, an interlayer film is formed.
[0133] Step 11: Figure 11 As shown, pattern etching is performed to form a plurality of through-hole openings passing through the interlayer film.
[0134] Step 12: Figure 11 As shown, an ohmic contact alloy 11 a is formed on the bottom surfaces of the through-hole openings corresponding to the source region 8 and the first well region 7 .
[0135] The steps of forming the ohmic contact alloy 11 include: depositing Ni alloy, and annealing at a temperature of 900-1200° C. to form the ohmic contact alloy 11 .
[0136] Step 13: Figure 11 As shown, a Schottky contact alloy 11 b is formed on the bottom surface of the through-hole opening corresponding to the third doping region 9 , and the Schottky contact alloy 11 b contacts the third doping region 9 to form a Schottky diode.
[0137] The Schottky contact alloy 11b needs to be annealed at 500-600°C after the Schottky contact metal is deposited.
[0138] Step 14: Figure 2 As shown, metal is filled in each through-hole opening to form a through-hole 12 .
[0139] Step 15: Figure 2 As shown, a front metal layer 13 is formed, and the front metal layer 13 is patterned and etched to form a source electrode; the source region 8, the first well region 7 and the third doped region 9 are all connected to the source electrode through corresponding through holes 12 on the top.
[0140] Step 11: Return Figure 2 As shown, a drain electrode composed of a back metal layer 14 is formed on the back side of the drain region 1 .
[0141] In some embodiments, the back metal layer 14 is formed by back-sputtering a Ni alloy followed by annealing.
[0142] In the embodiment of the present invention, the trench MOSFET is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the trench MOSFET may be a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.
[0143] The trench MOSFET of the embodiment of the present invention can be well applied to the trench silicon carbide MOSFET to meet the high-frequency switching application requirements of silicon carbide power semiconductors, and finally realize the trench silicon carbide MOSFET with integrated Schottky diode. The trench silicon carbide MOSFET with integrated Schottky diode of the embodiment of the present invention, when the device is working normally, the gate of the MOSFET area is applied with a forward bias voltage, the channel is opened, and electrons flow from the source to the drain under the action of the electric field, forming Figure 13 The current Ids from the drain to the source is shown by the arrow line 203 in the middle. When the device is turned off and enters the third quadrant working state, the positive potential difference from the source to the drain causes the diode area to turn on. Since the Schottky barrier is lower than the body diode of the MOSFET, the integrated Schottky diode turns on first, forming Figure 14The current Isd from the source to the drain is shown by the arrow line 204. In applications such as half-bridge or full-bridge, conventional silicon carbide MOSFETs typically require an anti-parallel silicon carbide Schottky diode for freewheeling. The device according to the present invention can avoid the need for an additional freewheeling diode in parallel.
[0144] Taking an N-type device as an example, the trench MOSFET of the present invention employs a trench structure, namely a gate trench plus a P-type buried layer. The P-type buried layer is the portion of the second doped region 3 extending directly below the bottom surface of the gate trench 101. The P-type buried layer substantially reduces the Miller capacitance of the device, thereby reducing the switching loss of the device. Furthermore, the addition of the P-type buried layer weakens the electric field concentration at the bottom and corners of the trench. The gate oxide layer is formed through a two-step deposition and thermal oxidation process, making the oxide layer thickness at the bottom of the trench greater than the oxide layer thickness on the trench sidewalls. This also makes the chamfer at the bottom of the trench smoother, reducing the curvature effect and improving the long-term reliability of the device.
[0145] The embodiment of the present invention monolithically integrates a Schottky diode, forms a lightly doped N-type region, namely the third doped region 9, above the P-type buried layer by utilizing the impurity compensation effect, and forms a Schottky contact above the lightly doped N-type region, thereby integrating the Schottky diode. The area above the second doped region 3 is fully utilized to integrate the Schottky diode, greatly reducing the unit pitch and cell size of the integrated Schottky diode. In addition, the fourth doped region 15 is provided near the third doped region 9, which can improve the current capability of the Schottky diode, reduce the forward conduction voltage drop, and thus reduce dynamic loss. Moreover, the second doped region 3 is adjacent to the first well region 7, which can greatly reduce the leakage risk of the Schottky diode.
[0146] Compared with the body diode of the existing traditional MOSFET, the embodiment of the present invention uses Schottky diode rectification, which has the advantages of low on-state voltage and unipolar conduction (no reverse recovery current and no double-bounce degradation). This enables the Schottky diode to be used as a freewheeling diode of the MOSFET, greatly reducing dynamic losses.
[0147] The present invention has been described in detail above by means of specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may make many variations and improvements, which should also be considered as the scope of protection of the present invention.
Claims
1. A trench MOSFET, characterized in that: include: a first epitaxial layer doped with a first conductivity type, with a drain region heavily doped with the first conductivity type formed on the back side of the first epitaxial layer; A trench gate, comprising a bottom dielectric layer formed on the bottom surface of a gate trench, a gate dielectric layer formed on the side of the gate trench, and a gate conductive material layer filled in the gate trench; A first well region of the second conductivity type is formed in the first epitaxial layer at a first side surface of the gate trench, wherein a bottom surface of the first well region is located above a bottom surface of the gate trench; The surface of the first well region covered by the side surface of the gate conductive material layer is used to form a channel region of the MOSFET; A source region heavily doped with a first conductivity type is formed in the first well region, a second side surface of the first well region and a second side surface of the source region are aligned with the first side surface of the gate trench, the first side surface of the source region is located inside the first side surface of the first well region, and the first epitaxial layer is outside the first side surface of the first well region; a second doped region of a second conductivity type, formed in the first epitaxial layer at a second side surface of the gate trench, wherein a bottom surface of the second doped region is located below a bottom surface of the gate trench and further extends to directly below the bottom surface of the gate trench; A third doped region doped with the first conductivity type is formed in a surface area of the second doped region, a first side surface of the third doped region and a first side surface of the second doped region are aligned with the second side surface of the gate trench, a second side surface of the third doped region extends to or is aligned with the outside of the second side surface of the second doped region, and an outside of the second side surface of the second doped region is the first epitaxial layer; The source region, the first well region and the third doped region are all connected to a source electrode composed of a front metal layer through corresponding top through-holes; An ohmic contact alloy is formed on the bottom surfaces of the through holes corresponding to the source region and the first well region; A Schottky contact alloy is formed on the bottom surface of the through hole corresponding to the third doping region, and the Schottky contact alloy contacts the third doping region to form a Schottky diode.
2. The trench MOSFET according to claim 1, wherein: A fourth doping region doped with the first conductive type is formed in the surface area of the first epitaxial layer between the second doping region of each gate trench and the first well region or the second doping region corresponding to the adjacent gate trench, the side of the third doping region is in contact with the fourth doping region, and the doping concentration of the fourth doping region is greater than the doping concentration of the first epitaxial layer.
3. The trench MOSFET according to claim 1, wherein: The material of the first epitaxial layer is a semiconductor material having a band gap width greater than that of silicon.
4. The trench MOSFET according to claim 3, wherein: The material of the first epitaxial layer includes SiC.
5. The trench MOSFET according to claim 1, wherein: The material of the bottom dielectric layer is the same as that of the gate dielectric layer, and the thickness of the bottom dielectric layer is greater than that of the gate dielectric layer.
6. The trench MOSFET according to claim 5, wherein: The material of the bottom dielectric layer includes an oxide layer; the top surface of the bottom dielectric layer is in an arc shape; The material of the gate dielectric layer includes an oxide layer; The gate conductive material layer includes a polysilicon gate.
7. The trench MOSFET according to claim 1, wherein: The doping concentration of the first epitaxial layer is 1E15cm -3 ~1E17cm -3 ; The doping concentration of the second doping region is 1E14 cm -3 ~1E16cm -3 ; The doping concentration of the third doping region is less than or equal to 1E16 cm -3 .
8. The field effect transistor according to any one of claims 1 to 7, characterized in that: The trench MOSFET is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the trench MOSFET is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.
9. A method for manufacturing a trench MOSFET, characterized in that: The steps include: forming a first epitaxial layer doped with a first conductivity type, and forming a drain region heavily doped with the first conductivity type on the back side of the first epitaxial layer; forming a plurality of second doped regions of a second conductivity type in the first epitaxial layer; forming a plurality of gate trenches in the first epitaxial layer, wherein the etched regions of the gate trenches include portions of the second doped regions, and after the gate trenches are formed, the remaining second doped regions are located in the first epitaxial layer at second side surfaces of the gate trenches, and the bottom surfaces of the second doped regions are located below the bottom surfaces of the gate trenches and further extend directly below the bottom surfaces of the gate trenches; forming a bottom dielectric layer on the bottom surface of the gate trench; forming a gate dielectric layer on a side of the gate trench; filling a gate conductive material layer in the gate trench; forming a first well region of a second conductivity type in the first epitaxial layer at a first side surface of the gate trench, wherein a bottom surface of the first well region is located above a bottom surface of the gate trench; The surface of the first well region covered by the side surface of the gate conductive material layer is used to form a channel region of the MOSFET; forming a heavily doped source region of the first conductivity type in the first well region, wherein the second side surface of the first well region and the second side surface of the source region are aligned with the first side surface of the gate trench, the first side surface of the source region is located inside the first side surface of the first well region, and the first epitaxial layer is outside the first side surface of the first well region; forming a third doped region doped with the first conductivity type in a surface area of the second doped region, wherein a first side surface of the third doped region and a first side surface of the second doped region are aligned with the second side surface of the gate trench, a second side surface of the third doped region extends outside or is aligned with the second side surface of the second doped region, and an outer side surface of the second doped region is the first epitaxial layer; Formation of interlayer membrane; Performing patterned etching to form a plurality of through-hole openings passing through the interlayer film; forming an ohmic contact alloy on bottom surfaces of the through-hole openings corresponding to the source region and the first well region; forming a Schottky contact alloy on a bottom surface of the through-hole opening corresponding to the third doping region, wherein the Schottky contact alloy contacts the third doping region to form a Schottky diode; Filling metal in each of the through-hole openings to form a through-hole; forming a front metal layer, and pattern-etching the front metal layer to form a source electrode; the source region, the first well region, and the third doped region are all connected to the source electrode through corresponding through holes on the top; A drain electrode composed of a back metal layer is formed on the back side of the drain region.
10. The method for manufacturing a trench MOSFET according to claim 9, wherein: Before forming the interlayer film, the method further includes: A fourth doping region doped with the first conductive type is formed in the surface area of the first epitaxial layer between the second doping region of each gate trench and the first well region or the second doping region corresponding to the adjacent gate trench, the side of the third doping region is in contact with the fourth doping region, and the doping concentration of the fourth doping region is greater than the doping concentration of the first epitaxial layer.
11. The method for manufacturing a trench MOSFET according to claim 9, wherein: The material of the first epitaxial layer is a semiconductor material having a band gap width greater than that of silicon.
12. The method for manufacturing a trench MOSFET according to claim 11, wherein: The material of the first epitaxial layer includes SiC.
13. The method for manufacturing a trench MOSFET according to claim 9, wherein: The material of the bottom dielectric layer is the same as that of the gate dielectric layer, and the thickness of the bottom dielectric layer is greater than that of the gate dielectric layer.
14. The method for manufacturing a trench MOSFET according to claim 13, wherein: The material of the bottom dielectric layer includes an oxide layer, the oxide layer of the bottom dielectric layer is grown by a deposition process and the thickness is controlled by an etching process, and the top surface of the bottom dielectric layer is arc-shaped by the etching process; The material of the gate dielectric layer includes an oxide layer, and the oxide layer of the gate dielectric layer is formed by a thermal oxidation process; The gate conductive material layer includes a polysilicon gate.
15. The method for manufacturing a trench MOSFET according to claim 9, wherein: The doping concentration of the first epitaxial layer is 1E15cm -3 ~1E17cm -3 ; The doping concentration of the second doping region is 1E14 cm -3 ~1E16cm -3 ; The doping concentration of the third doping region is less than or equal to 1E16 cm -3 .
16. The field effect transistor according to any one of claims 9 to 15, characterized in that: The trench MOSFET is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the trench MOSFET is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.