Groove type MOSFET and manufacturing method thereof

Abstract

The invention discloses a trench-type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), which is characterized in that a first well region of a second conduction type, which is used as a first channel region of the MOSFET, is formed at a first side surface of a gate trench, and a second doped region of the second conduction type is formed at a second side surface of the gate trench and can also extend to a position right below the bottom surface of the gate trench; third doped regions of the first conductivity type are formed on the top surface of the second doped region and are arranged at intervals along the length direction of the gate trench, and the second side surfaces of the third doped regions extend to the outer side of the second side surface of the second doped region or are aligned with the second side surface of the second doped region. The second doped region and the adjacent first well region between two adjacent gate trenches or the second doped region is used as a gate region of the JFET, and the first epitaxial layer and the third doped region between the gate regions form a channel region of the JFET. The invention further discloses a manufacturing method of the groove type MOSFET. According to the invention, the JCR can be integrated, the conduction voltage drop is reduced, the unipolar conduction is realized, the Miller capacitance can be reduced, and the reliability of the device can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a trench MOSFET; the present invention also relates to a manufacturing method of the trench MOSFET. Background Art

[0002] Wide bandgap semiconductor material SiC is an ideal material for preparing high voltage power electronic devices. Compared with Si material, SiC material has a high breakdown electric field strength (4×10 6 V / cm), high carrier saturation drift velocity (2×10 7 cm / s), high thermal conductivity, good thermal stability, etc., so it is particularly suitable for use in high-power, high-voltage, high-temperature and radiation-resistant electronic devices.

[0003] SiC VDMOS is a commonly used SiC power device. Compared to bipolar devices, SiC VDMOS has better frequency characteristics and lower switching losses because it does not have a charge storage effect. The wide bandgap of SiC material also allows SiC VDMOS to operate at temperatures as high as 300°C.

[0004] However, planar SiC VDMOS has two problems. First, the density of the JFET region is too high, which introduces a large Miller capacitance and increases the dynamic loss of the device. Second, the parasitic SiC body diode has a too high forward voltage drop. As a bipolar device, it has a large reverse recovery current. In addition, the bipolar degradation phenomenon caused by the silicon carbide BPD defect causes the forward voltage drop of the body diode to continue to increase with the increase of usage time. Therefore, the body diode of SiC VDMOS cannot be used directly as a freewheeling diode. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a trench MOSFET that can achieve reverse freewheeling and thus rectification without using a body diode or an additional parallel diode. The resulting rectifier has the advantages of low forward voltage drop and unipolar conduction. To this end, the present invention also provides a method for manufacturing the trench MOSFET.

[0006] In order to solve the above technical problems, the present invention provides a trench MOSFET comprising:

[0007] A first epitaxial layer doped with a first conductivity type is provided, and a drain region heavily doped with the first conductivity type is formed on the back side of the first epitaxial layer.

[0008] The trench gate comprises a bottom dielectric layer formed on the bottom surface of a gate trench, a gate dielectric layer formed on the side of the gate trench, and a gate conductive material layer filled in the gate trench.

[0009] A first well region of the second conductivity type is formed in the first epitaxial layer at a first side surface of the gate trench, and a bottom surface of the first well region is located above a bottom surface of the gate trench.

[0010] A source region heavily doped with the first conductivity type is formed in the first well region, the second side surface of the first well region and the second side surface of the source region are aligned with the first side surface of the gate trench, the first side surface of the source region is located inside the first side surface of the first well region, and the first epitaxial layer is outside the first side surface of the first well region.

[0011] A second doped region of a second conductivity type is formed in the first epitaxial layer at the second side surface of the gate trench, the bottom surface of the second doped region is located below the bottom surface of the gate trench and the second doped region also extends directly below the bottom surface of the gate trench.

[0012] A plurality of third doping regions doped with the first conductive type are formed in the surface area of ​​the second doping region, and the third doping regions are arranged at intervals along the length direction of the second side of the gate trench; the first side of each of the third doping regions and the first side of the second doping region are aligned with the second side of the gate trench, and the second side of each of the third doping regions extends to or is aligned with the outside of the second side of the second doping region, and the outside of the second side of the second doping region is the first epitaxial layer.

[0013] The source region, the first well region, the second doping region and the third doping region are all connected to a source electrode composed of a front metal layer through corresponding top through-holes.

[0014] The surface of the first well region covered by the side surface of the gate conductive material layer is used to form a first channel region of the MOSFET.

[0015] The second doped region and the adjacent first well region or the second doped region located between two adjacent gate trenches serve as the gate region of the JFET, the first epitaxial layer between the gate regions forms the longitudinal channel region of the JFET, and the third doped region forms the lateral channel region of the JFET.

[0016] A further improvement is that the material of the first epitaxial layer is a semiconductor material having a band gap width greater than the band gap width of silicon.

[0017] A further improvement is that the material of the first epitaxial layer includes SiC.

[0018] A further improvement is that the material of the bottom dielectric layer and the material form of the gate dielectric layer are different, and the thickness of the bottom dielectric layer is greater than the thickness of the gate dielectric layer.

[0019] A further improvement is that the material of the bottom dielectric layer includes an oxide layer; and the top surface of the bottom dielectric layer is in an arc shape.

[0020] The material of the gate dielectric layer includes an oxide layer.

[0021] The gate conductive material layer includes a polysilicon gate.

[0022] A further improvement is that an ohmic contact alloy is formed on the bottom surfaces of the through holes corresponding to the source region, the first well region, the second doping region, and the third doping region.

[0023] A further improvement is that the doping concentration of the first epitaxial layer is 1E15cm -3 ~1E17cm -3 ;

[0024] The doping concentration of the second doping region is 1E14 cm -3 ~1E16cm -3 ;

[0025] The doping concentration of the third doping region is less than or equal to 1E16 cm -3 .

[0026] A further improvement is that the trench MOSFET is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the trench MOSFET is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0027] To solve the above technical problems, the present invention provides a method for manufacturing a trench MOSFET comprising the following steps:

[0028] A first epitaxial layer doped with a first conductivity type is formed, and a drain region heavily doped with the first conductivity type is formed on the back side of the first epitaxial layer.

[0029] A plurality of second doping regions of a second conductivity type are formed in the first epitaxial layer.

[0030] A plurality of gate trenches are formed in the first epitaxial layer, and the etched area of ​​the gate trenches includes a portion of the second doped region. After the gate trenches are formed, the retained second doped region is located in the first epitaxial layer at the second side surface of the gate trench, and the bottom surface of the second doped region is located below the bottom surface of the gate trench and the second doped region also extends to directly below the bottom surface of the gate trench.

[0031] A bottom dielectric layer is formed on the bottom surface of the gate trench.

[0032] A gate dielectric layer is formed on the side of the gate trench.

[0033] A gate conductive material layer is filled in the gate trench.

[0034] A first well region of the second conductivity type is formed in the first epitaxial layer at a first side surface of the gate trench, and a bottom surface of the first well region is located above a bottom surface of the gate trench.

[0035] A source region heavily doped with the first conductivity type is formed in the first well region, the second side surface of the first well region and the second side surface of the source region are aligned with the first side surface of the gate trench, the first side surface of the source region is located inside the first side surface of the first well region, and the first epitaxial layer is outside the first side surface of the first well region.

[0036] A plurality of third doping regions doped with the first conductive type are formed in the surface area of ​​the second doping region, and the third doping regions are arranged at intervals along the length direction of the second side of the gate trench; the first side of each of the third doping regions and the first side of the second doping region are aligned with the second side of the gate trench, and the second side of each of the third doping regions extends to or is aligned with the outside of the second side of the second doping region, and the outside of the second side of the second doping region is the first epitaxial layer.

[0037] An interlayer film, a through hole and a front metal layer are formed, and the front metal layer is patterned and etched to form a source electrode; the source region, the first well region, the second doped region and the third doped region are all connected to the source electrode composed of the front metal layer through the through hole corresponding to the top.

[0038] A drain electrode composed of a back metal layer is formed on the back side of the drain region.

[0039] A further improvement is that the material of the first epitaxial layer is a semiconductor material having a band gap width greater than the band gap width of silicon.

[0040] A further improvement is that the material of the first epitaxial layer includes SiC.

[0041] A further improvement is that the material of the bottom dielectric layer and the material form of the gate dielectric layer are different, and the thickness of the bottom dielectric layer is greater than the thickness of the gate dielectric layer.

[0042] A further improvement is that the material of the bottom dielectric layer includes an oxide layer, the oxide layer of the bottom dielectric layer is grown by a deposition process and its thickness is controlled by an etching process, and the top surface of the bottom dielectric layer is arc-shaped by the etching process.

[0043] The material of the gate dielectric layer includes an oxide layer, and the oxide layer of the gate dielectric layer is formed by a thermal oxidation process.

[0044] The gate conductive material layer includes a polysilicon gate.

[0045] A further improvement is that an ohmic contact alloy is formed on the bottom surfaces of the through holes corresponding to the source region, the first well region, the second doping region, and the third doping region.

[0046] A further improvement is that the doping concentration of the first epitaxial layer is 1E15cm -3 ~1E17cm -3 ;

[0047] The doping concentration of the second doping region is 1E14 cm -3 ~1E16cm -3 ;

[0048] The doping concentration of the third doping region is less than or equal to 1E16 cm -3 .

[0049] A further improvement is that the trench MOSFET is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the trench MOSFET is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0050] The present invention forms a first well region and a corresponding source region for forming a first channel region of a MOSFET only on the first side of the trench gate, and forms a second doped region of the second conductivity type on the second side of the trench gate that does not form the first trench region of the MOSFET, the bottom portion of the second doped region extends to just below the bottom surface of the trench gate, and the top area of ​​the second doped region is formed with a plurality of third doped regions of the first conductivity type that are arranged at intervals along the length direction of the trench gate, the second doped region and the adjacent second doped region or the first well region will form the gate region of the JFET, the first epitaxial layer and the third doped region between the gate region of the JFET will serve as the channel region of the JFET, wherein the first epitaxial layer serves as the longitudinal channel region of the JFET and the third doped region serves as the longitudinal channel region of the JFET. The lateral channel region of the JFET, so that the JFET can turn on the channel region of the JFET in the third quadrant working state and thereby realize reverse freewheeling; the JFET can also pinch off the channel region of the JFET when the device is turned off to reduce leakage, so the present invention can realize rectification through JFET control, that is, the present invention can realize a JFET-controlled rectifier (JCR), so the present invention can realize reverse freewheeling and thereby realize rectification without using a body diode or an additional parallel diode, and the realized rectifier has the advantages of low conduction voltage drop and unipolar conduction, the unipolar conduction rectifier has no reverse recovery current and no bipolar degradation, and finally can greatly reduce the dynamic loss of the device.

[0051] In addition, part of the second doped region of the present invention is located directly below the bottom surface of the trench gate, which can share the electric field strength of the gate dielectric layer at the bottom of the gate trench in the off state, thereby improving the long-term reliability of the device; at the same time, since the second doped region is connected to the source, the second doped region extends to the bottom of the gate trench, which can reduce the overlapping area between the gate and the drain, thereby significantly reducing the Miller capacitance and thus reducing the switching damage of the device.

[0052] Furthermore, the bottom dielectric layer at the bottom surface of the gate trench in the trench gate of the present invention and the gate dielectric layer on the side of the gate trench are independent structures, meaning that their materials and thicknesses can be independently set. By improving the reliability of the bottom dielectric layer, the reliability of the entire device can be improved. For example, when both the bottom dielectric layer and the gate dielectric layer are oxide layers, increasing the thickness of the bottom dielectric layer can increase device reliability. Furthermore, the bottom surface of the gate trench of the present invention is smoother, further improving device reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0054] Figure 1 3D schematic diagram of the trench MOSFET according to an embodiment of the present invention;

[0055] Figure 2 It is along Figure 1 The cross-sectional view at the dotted line AA in FIG;

[0056] Figure 3 It is along Figure 1 The cross-sectional view at the dotted line AA in FIG;

[0057] Figure 4-13 Schematic diagram of the device structure in each step of the method for manufacturing a trench MOSFET according to an embodiment of the present invention;

[0058] Figure 14 1 is a schematic diagram of an equivalent circuit of a trench MOSFET in a forward conduction state according to an embodiment of the present invention;

[0059] Figure 15 Schematic diagram of the equivalent circuit of the trench MOSFET in the embodiment of the present invention during reverse freewheeling. DETAILED DESCRIPTION

[0060] like Figure 1 FIG. 1 is a schematic diagram of the three-dimensional structure of a trench MOSFET according to an embodiment of the present invention; FIG. Figure 2 As shown, it is along Figure 1 The cross-sectional view at the dotted line AA in FIG; Figure 3 As shown, it is along Figure 1 The cross-sectional view at the dotted line AA in FIG;

[0061] Figure 1 The corresponding coordinate system is also shown. Figure 2 and Figure 3 The corresponding cross sections are all in the xy plane; the trench MOSFET of the embodiment of the present invention includes:

[0062] The first epitaxial layer 2 is doped with the first conductivity type, and a drain region 1 heavily doped with the first conductivity type is formed on the back surface of the first epitaxial layer 2. A drain electrode composed of a back metal layer 14 is formed on the back surface of the drain region 1.

[0063] The trench gate includes a bottom dielectric layer 4 formed on the bottom surface of the gate trench 101, a gate dielectric layer 5 formed on the side of the gate trench 101, and a gate conductive material layer 6 filled in the gate trench 101. Figure 5 shown.

[0064] A first well region 7 of the second conductivity type is formed in the first epitaxial layer 2 at a first side surface of the gate trench 101 , and a bottom surface of the first well region 7 is located above the bottom surface of the gate trench 101 .

[0065] A source region 8 heavily doped with the first conductivity type is formed in the first well region 7. The second side surface of the first well region 7 and the second side surface of the source region 8 are aligned with the first side surface of the gate trench 101. The first side surface of the source region 8 is located on the inner side of the first side surface of the first well region 7. The outer side surface of the first well region 7 is the first epitaxial layer 2.

[0066] A second doping region 3 of the second conductivity type is formed in the first epitaxial layer 2 at the second side surface of the gate trench 101. The bottom surface of the second doping region 3 is located below the bottom surface of the gate trench 101 and the second doping region 3 also extends directly below the bottom surface of the gate trench 101.

[0067] A plurality of third doping regions 9 doped with the first conductive type are formed in the surface area of ​​the second doping region 3. The third doping regions 9 are arranged at intervals along the length direction of the second side surface of the gate trench 101. Figure 1 As shown, the length direction of the second side of the gate trench 101 is along the z-direction. The first side of each third doping region 9 and the first side of the second doping region 3 are aligned with the second side of the gate trench 101. The second side of each third doping region 9 extends outside the second side of the second doping region 3 or is aligned. The first epitaxial layer 2 is outside the second side of the second doping region 3, and the second side of the third doping region 9 will contact the first epitaxial layer 2.

[0068] like Figure 2As shown, the source region 8, the first well region 7, the second doping region 3 and the third doping region 9 are all connected to the source electrode composed of the front metal layer 13 through the corresponding through hole 12 on the top. The through hole 12 will pass through the interlayer film 10, Figure 1 The structural diagram of the interlayer film 10, the through hole 12 and the front metal layer 13 is omitted.

[0069] The gate conductive material layer 6 is connected to the gate formed by the front metal layer.

[0070] The surface of the first well region 7 covered by the gate conductive material layer 6 is used to form a first channel region of the MOSFET.

[0071] The second doped region 3 and the adjacent first well region 7 or second doped region 3 between two adjacent gate trenches 101 serve as the gate region of the JFET. The first epitaxial layer 2 between the gate regions forms the longitudinal channel region of the JFET, and the third doped region 9 forms the lateral channel region of the JFET. Figure 2 , two gate trenches 101 are shown, wherein the second doped region 3 at the second side of the left gate trench 101 and the first well region 7 at the first side of the right gate trench 101 are adjacent, and the first epitaxial layer 2 between the two gate trenches 101 serves as the longitudinal channel region of the JFET. In other implementations, the second sides of the two gate trenches 101 may be adjacent, so that the two second doped regions 3 are adjacent, and the first epitaxial layer 2 between the two second doped regions 3 serves as the longitudinal channel region of the JFET.

[0072] Also, please refer to Figure 1 As shown, along the length of the gate trench 101, both sides of the third doped region 9 are second doped regions 3, so the third doped region 9 serves as the lateral channel region of the JFET. The lateral channel region and the longitudinal channel region of the JFET together form the JFET channel region. In the third quadrant operating state, the JFET channel region will be turned on, thereby achieving reverse freewheeling. When the device is reverse cutoff, the JFET channel region will also be depleted and cut off, thereby reducing leakage.

[0073] In an embodiment of the present invention, the material of the first epitaxial layer 2 is a semiconductor material having a bandgap greater than that of silicon. Preferably, the material of the first epitaxial layer 2 includes SiC. In other embodiments, the first epitaxial layer 2 may also be made of other suitable semiconductor materials, which can be selected based on actual needs.

[0074] The material of the bottom dielectric layer 4 is the same as that of the gate dielectric layer 5 , and the thickness of the bottom dielectric layer 4 is greater than that of the gate dielectric layer 5 .

[0075] In some embodiments, the material of the bottom dielectric layer 4 includes an oxide layer; and the top surface of the bottom dielectric layer 4 is arc-shaped.

[0076] The material of the gate dielectric layer 5 includes an oxide layer.

[0077] The gate conductive material layer 6 includes a polysilicon gate.

[0078] Ohmic contact alloys 11 are formed on the bottom surfaces of the through holes 12 corresponding to the source region 8 , the first well region 7 , the second doping region 3 and the third doping region 9 .

[0079] In some embodiments, the doping concentration of the first epitaxial layer 2 is 1E15 cm -3 ~1E17cm -3 .

[0080] The doping concentration of the second doping region 3 is 1E14 cm -3 ~1E16cm -3 .

[0081] The doping concentration of the third doping region 9 is less than or equal to 1E16 cm -3 .

[0082] In the embodiment of the present invention, the trench MOSFET is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the trench MOSFET can also be a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0083] In the embodiment of the present invention, a first well region 7 and a corresponding source region 8 for forming a first channel region of a MOSFET are formed only on the first side of the trench gate, and a second doping region 3 of the second conductivity type that does not form the first trench region of the MOSFET is formed on the second side of the trench gate. The bottom portion of the second doping region 3 extends to just below the bottom surface of the trench gate, and a plurality of third doping regions 9 of the first conductivity type are formed in the top area of ​​the second doping region 3 and are arranged at intervals along the length direction of the trench gate. The second doping region 3 and the adjacent second doping region 3 or the first well region 7 will form the gate region of the JFET. The first epitaxial layer 2 and the third doping region 9 between the gate region of the JFET will serve as the channel region of the JFET, wherein the first epitaxial layer 2 As the longitudinal channel region of the JFET and the third doped region 9 as the lateral channel region of the JFET, the JFET can turn on the channel region of the JFET and thereby realize reverse freewheeling when the device is in the third quadrant working state; the JFET can also pinch off the channel region of the JFET when the device is turned off to reduce leakage, so the present invention can realize rectification through JFET control, that is, the embodiment of the present invention can realize JCR, so the embodiment of the present invention can realize reverse freewheeling and thereby realize rectification without using a body diode or an additional parallel diode, and the realized rectifier has the advantages of low conduction voltage drop and unipolar conduction, the unipolar conduction rectifier has no reverse recovery current and no bipolar degradation, and finally can greatly reduce the dynamic loss of the device.

[0084] In addition, part of the second doped region 3 of the embodiment of the present invention is located directly below the bottom surface of the trench gate, which can share the electric field strength of the gate dielectric layer 5 at the bottom of the gate trench 101 in the off state, thereby improving the long-term reliability of the device; at the same time, since the second doped region 3 is connected to the source, the second doped region 3 extends to the bottom of the gate trench 101, which can reduce the overlapping area between the gate and the drain, thereby significantly reducing the Miller capacitance, thereby reducing the switching damage of the device.

[0085] In addition, the bottom dielectric layer 4 on the bottom surface of the gate trench 101 and the gate dielectric layer 5 on the side of the gate trench 101 in the trench gate of the embodiment of the present invention are independent structures, that is, the material and thickness can be independently set. By improving the reliability of the bottom dielectric layer 4, the reliability of the entire device can be improved. For example, when both the bottom dielectric layer 4 and the gate dielectric layer 5 are oxide layers, the reliability of the device can be increased by increasing the thickness of the bottom dielectric layer 4. In addition, the bottom surface of the gate trench 101 in the embodiment of the present invention is smoother, which can further improve the reliability of the device.

[0086] like Figure 14 , which is a schematic diagram of the equivalent circuit of a trench MOSFET in the forward conduction state according to an embodiment of the present invention; the trench MOSFET is integrated with a MOSFET 201 and a JFET 202. Since the first epitaxial layer 2 is made of SiC, MOSFET 201 is also represented by a SiC MOSFET, and JFET 202 is also represented by a SiC JFET. During forward conduction, the gate is applied with a positive voltage greater than the threshold voltage of MOSFET 201, and the drain is applied with a voltage greater than the source voltage. This causes the first channel region to conduct, thereby forming a drain-to-source current Ids, as shown by the dotted line 203, flowing through the first channel region of MOSFET 201.

[0087] like Figure 15 FIG. 1 is a schematic diagram of an equivalent circuit of a trench MOSFET in a reverse freewheeling state according to an embodiment of the present invention. Figure 15 The corresponding working state is the third quadrant working state. When the gate voltage is less than the threshold voltage of MOSFET201, such as 0V, MOSFET201 is turned off, the gate region of the JFET is connected to the source, and the source voltage is greater than the drain voltage. In this way, the channel region of JFET202 will be turned on, realizing the current Isd from the source to the drain shown by the dotted line 204 through the channel region of JFET202.

[0088] When the device is reverse-blocked, the channel region of JFET 202 will be depleted, thereby reducing leakage.

[0089] like Figures 4 to 13FIG. 1 is a schematic diagram of the device structure in each step of the method for manufacturing a trench MOSFET according to an embodiment of the present invention; wherein, Figures 4 to 8 They are all cross-sections, and the surfaces corresponding to the cross-sections are Figure 1 The corresponding xy plane; Figure 9 This is a three-dimensional diagram after the second doping region 9 is formed. Figure 10 and Figure 12 Corresponding to the Figure 9 The cross-section at the dotted line AA, Figure 11 and Figure 13 Corresponding to the Figure 9 The cross-sectional view at the dotted line BB shows that the method for manufacturing a trench MOSFET according to an embodiment of the present invention includes the following steps:

[0090] Step 1: Figure 4 As shown, a first epitaxial layer 2 doped with the first conductivity type is formed, and a drain region 1 heavily doped with the first conductivity type is formed on the back side of the first epitaxial layer 2 .

[0091] In the embodiment of the present invention, the material of the first epitaxial layer 2 is a semiconductor material having a band gap greater than that of silicon. Preferably, the material of the first epitaxial layer 2 includes SiC.

[0092] In the method of the embodiment of the present invention, the drain region 1 is composed of a semiconductor substrate, the first epitaxial layer 2 is formed on the semiconductor substrate, and the semiconductor substrate and the first epitaxial layer are made of the same material, for example, SiC.

[0093] Step 2: Figure 4 As shown, a plurality of second doping regions 3 of the second conductivity type are formed in the first epitaxial layer 2 . Figure 4 Two second doping regions 3 are shown in the figure, but in practice more can be provided as needed.

[0094] In the method of the embodiment of the present invention, the formation area of ​​the second doped region 3 is defined by photolithography. Before the photolithography process, an ion implantation mask layer is formed on the surface of the first epitaxial layer 2. The material of the ion implantation mask layer includes an oxide layer. After the photolithography process, the ion implantation mask layer needs to be patterned before ion implantation. The ion implantation mask layer is then removed and the surface is cleaned. In the method of the embodiment of the present invention, the trench MOSFET is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In this case, the second doped region 3 is P-type doped, and the implanted impurities in the second doped region 3 include Al. The implantation temperature condition is 300K to 1000K. In other embodiments, the field effect transistor can also be a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type. In this case, the second doped region 3 is an N-type buried layer.

[0095] Step 3: Figure 5As shown, multiple gate trenches 101 are formed in the first epitaxial layer 2. The etched areas of the gate trenches 101 include portions of the second doped regions 3. After the gate trenches 101 are formed, the remaining second doped regions 3 are located in the first epitaxial layer 2 at the second side of the gate trenches 101. The bottom surfaces of the second doped regions 3 are located below the bottom surfaces of the gate trenches 101 and extend directly below the bottom surfaces of the gate trenches 101. The second doped regions 3 extending directly below the bottom surfaces of the gate trenches 101 can be considered as buried layers.

[0096] In the method according to the embodiment of the present invention, the steps of forming the gate trench 101 include:

[0097] depositing an oxide layer as an etching mask layer;

[0098] Then, photolithography is performed to define the formation area of ​​the gate trench 101, and then the etching mask layer is etched;

[0099] Afterwards, the first epitaxial layer 2 is subjected to reactive ion etching using the etching mask layer as a mask to form a gate trench 101 .

[0100] Step 4: forming a bottom dielectric layer 4 on the bottom surface of the gate trench 101 .

[0101] In the method of the embodiment of the present invention, the material of the bottom dielectric layer 4 includes an oxide layer. The oxide layer of the bottom dielectric layer 4 is grown by a deposition process and its thickness is controlled by an etching process. The etching process is used to make the top surface of the bottom dielectric layer 4 have an arc shape. The steps of forming the bottom dielectric layer 4 include:

[0102] like Figure 5 As shown, the deposition of the bottom dielectric layer 4 material is performed.

[0103] Afterwards, etching is performed to form a bottom dielectric layer 4 a located at the bottom of the gate trench 101 . At this time, a mark 4 a is used alone to mark the bottom dielectric layer.

[0104] like Figure 6 As shown, the bottom dielectric layer 4 a is further etched so that the top surface of the bottom dielectric layer 4 a is rounded, and finally the required bottom dielectric layer 4 is formed.

[0105] Step 5: Figure 7 As shown, a gate dielectric layer 5 is formed on the side of the gate trench 101 .

[0106] In the embodiment of the present invention, the material of the bottom dielectric layer 4 is the same as that of the gate dielectric layer 5, and the thickness of the bottom dielectric layer 4 is greater than that of the gate dielectric layer 5. By thickening the bottom dielectric layer 4, the reliability of the device can be enhanced.

[0107] The material of the gate dielectric layer 5 includes an oxide layer. The oxide layer of the gate dielectric layer 5 is formed by a thermal oxidation process. Before the thermal oxidation process, a carbon capping step is performed. The thermal oxidation process is achieved by annealing at a high temperature above 1600°C. The thermal process of the thermal oxidation process also activates the injected impurities.

[0108] Step 6: Figure 7 As shown, the gate trench 101 is filled with a gate conductive material layer 6 .

[0109] In the method of the embodiment of the present invention, the gate conductive material layer 6 comprises a polysilicon gate, which is formed by depositing polysilicon and patterning and etching the polysilicon.

[0110] Step 7: Figure 8 As shown, a first well region 7 of the second conductivity type is formed in the first epitaxial layer 2 at a first side surface of the gate trench 101 , and a bottom surface of the first well region 7 is located above the bottom surface of the gate trench 101 .

[0111] In the method of the embodiment of the present invention, the formation area of ​​the first well region 7 is defined by photolithography. Before the photolithography process, an ion implantation mask layer is formed on the surface of the first epitaxial layer 2. The material of the ion implantation mask layer includes an oxide layer. After the photolithography process, the ion implantation mask layer needs to be patterned before ion implantation. The ion implantation mask layer is then removed and the surface is cleaned. In the method of the embodiment of the present invention, the first well region 7 is P-type doped. The implanted impurity in the first well region 7 includes Al. The implantation temperature is 300K to 1000K.

[0112] Step 8: Figure 8 As shown, a heavily doped source region 8 of the first conductivity type is formed in the first well region 7. The second side surface of the first well region 7 and the second side surface of the source region 8 are aligned with the first side surface of the gate trench 101. The first side surface of the source region 8 is located inside the first side surface of the first well region 7. The first epitaxial layer 2 is located outside the first side surface of the first well region 7. Figure 8 As shown, the source region 8 does not directly contact the first epitaxial layer 2 , and the source region 8 needs to be electrically connected to the first epitaxial layer 2 through the conduction of the first channel region of the MOSFET 201 .

[0113] In the method of the embodiment of the present invention, the formation area of ​​source region 8 is defined by photolithography. Before the photolithography process, an ion implantation mask layer is formed on the surface of the first epitaxial layer 2. The material of the ion implantation mask layer includes an oxide layer. After the photolithography process, the ion implantation mask layer needs to be patterned before ion implantation. The ion implantation mask layer is then removed and the surface is cleaned. In the method of the embodiment of the present invention, source region 8 is N-type doped. The impurities implanted into source region 8 include phosphorus (P) at a temperature of 300K to 1000K.

[0114] Step 9: Figure 9 As shown, a plurality of third doping regions 9 doped with the first conductive type are formed in the surface area of ​​the second doping region 3, and the third doping regions 9 are arranged at intervals along the length direction of the second side of the gate trench 101; the first side of each third doping region 9 and the first side of the second doping region 3 are aligned with the second side of the gate trench 101, and the second side of each third doping region 9 extends to the outside of the second side of the second doping region 3 or is aligned, and the outside of the second side of the second doping region 3 is the first epitaxial layer 2. Figure 10 and Figure 11 They also correspond to the cross-sectional views when the third doping region 9 is formed. Figure 11 Since the position is located at the dotted line BB, which corresponds to the spacer area of ​​the third doping region 9 , the third doping region 9 is not shown.

[0115] In the method of the embodiment of the present invention, the formation area of ​​the third doped region 9 is defined by photolithography. Before the photolithography process, an ion implantation mask layer is formed on the surface of the first epitaxial layer 2. The material of the ion implantation mask layer includes an oxide layer. After the photolithography process, the ion implantation mask layer needs to be patterned before ion implantation. The ion implantation mask layer is then removed and the surface is cleaned. In the method of the embodiment of the present invention, the third doped region 9 is N-type doped. The implanted impurities in the third doped region 9 include phosphorus. The implantation temperature is 300K to 1000K.

[0116] After the third doping region 9 is formed, the second doping region 3 and the first well region 7 formed in the first epitaxial layer 2 will serve as the gate region of the JFET, and the area surrounded by the gate region of the JFET will serve as the channel region of the JFET. The channel region of the JFET is further divided into a longitudinal channel region and a lateral channel region, wherein the first epitaxial layer 2 located between the second doping region 3 and the adjacent first well region 7 or the second doping region 3 serves as the longitudinal channel region of the JFET, and the third doping region 9 serves as the lateral channel region. Thus, the integration of the JFET is achieved. In the embodiment method of the present invention, the integrated JFET can control rectification, so it is also called integrated JCR.

[0117] In some embodiments, the doping concentration of the first epitaxial layer 2 is 1E15 cm -3 ~1E17cm -3 .

[0118] The doping concentration of the second doping region 3 is 1E14 cm -3 ~1E16cm -3 .

[0119] The doping concentration of the third doping region 9 is less than or equal to 1E16 cm -3 .

[0120] Step 10: Figure 12 As shown, an interlayer film 10, a through hole 12 and a front metal layer 13 are formed. Figure 2 As shown, the front metal layer 13 is patterned and etched to form a source; the source region 8, the first well region 7, the second doping region 3 and the third doping region 9 are all connected to the source composed of the front metal layer 13 through the corresponding through holes 12 on the top.

[0121] In the method of the embodiment of the present invention, the steps of forming the through hole 12 include:

[0122] like Figure 12 As shown, photolithography definition and etching are performed to form the opening of the through hole 12;

[0123] The process then includes forming an ohmic contact alloy 11 on the bottom surfaces of the openings of the through holes 12 corresponding to the source region 8 , the first well region 7 , the second doping region 3 and the third doping region 9 .

[0124] The steps of forming the ohmic contact alloy 11 include: depositing Ni alloy, and annealing at a temperature of 900-1200° C. to form the ohmic contact alloy 11 .

[0125] Afterwards, if Figure 2 As shown, a metal layer is filled in the opening of the through hole 12 to form the through hole 12 .

[0126] Step 11: Return Figure 2 As shown, a drain electrode composed of a back metal layer 14 is formed on the back side of the drain region 1 .

[0127] In the embodiment of the present invention, the trench MOSFET is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the trench MOSFET may be a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0128] The MOSFET of the present invention embodiment has a trench structure. The gate oxide layer (bottom gate dielectric layer 4) at the bottom of the polysilicon (gate conductive material layer 6) of the trench MOSFET is thicker than the gate oxide layer (gate dielectric layer 5) on the sidewalls of the gate trench, resulting in a smoother bottom of the gate trench. Taking an N-type device as an example, the present invention embodiment also adds a P-type doped buried layer (the portion of the second doped region 3 extending to the bottom of the gate trench) at the bottom of the gate trench. This layer can share the electric field strength of the gate oxide (bottom gate dielectric layer 4) at the bottom of the gate trench in the off state, thereby improving the long-term reliability of the device and significantly reducing the Miller capacitance and switching losses compared to a planar VDMOS. Furthermore, the present invention embodiment forms a lateral JFET region by providing a second N-type doped contact region (third doped region 9) above the second doped region 3 using the impurity compensation effect. Ohmic contacts are provided above the second N-type doped contact region and above the second doped region 3, and are short-circuited to the first N-type doped contact region (source region 2) using metal through-hole technology. Thus, a JCR lateral JFET region and a vertical JFET region are formed between the second doped region 3, the third doped region 9, and the first well region 7. When the device is in reverse cutoff, the JCR's lateral and vertical JFET regions are pinched off by the P / N junction depletion region of the second doped region 3 and the first well region 7, reducing leakage. Compared to the body diode of a conventional MOSFET, the JCR diode integrated in this embodiment of the present invention offers the advantages of lower forward voltage and unipolar conduction (no reverse recovery current and no double-blink degradation). This rectifier can be used as a freewheeling diode for a MOSFET, significantly reducing dynamic losses.

[0129] The embodiment of the present invention realizes a trench silicon carbide MOSFET with integrated JCR. When the device is working normally, the gate of the MOSFET region is applied with a forward bias voltage, the channel is opened, and electrons flow from the source to the drain under the action of the electric field, forming a current Ids from the drain to the source, as shown in FIG. Figure 14 As shown; when the device is turned off and enters the third quadrant working state, the P-type doped first well region 7 and the second doped region 3 and their ohmic contacts serve as the gate region of the SiC JFET region, and the source region 21 and its ohmic contacts serve as the source region of the SiC JFET region. The gate and source of the SiC JFET region are short-circuited through the metal through-hole, and electrons are conducted through the channel region of the JFET corresponding to the third doped region 9 to form a current Isd from the source to the drain, as shown Figure 15 As shown,

[0130] In applications such as half-bridge or full-bridge, existing silicon carbide MOSFETs typically require anti-parallel silicon carbide Schottky diodes for freewheeling. The device according to the present invention can avoid the need for additional freewheeling diodes to be connected in parallel.

[0131] The present invention has been described in detail above by means of specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may make many variations and improvements, which should also be considered as the scope of protection of the present invention.

Claims

1. A trench MOSFET, characterized in that: include: a first epitaxial layer doped with a first conductivity type, with a drain region heavily doped with the first conductivity type formed on the back side of the first epitaxial layer; A trench gate, comprising a bottom dielectric layer formed on the bottom surface of a gate trench, a gate dielectric layer formed on the side of the gate trench, and a gate conductive material layer filled in the gate trench; A first well region of the second conductivity type is formed in the first epitaxial layer at a first side surface of the gate trench, wherein a bottom surface of the first well region is located above a bottom surface of the gate trench; A source region heavily doped with a first conductivity type is formed in the first well region, a second side surface of the first well region and a second side surface of the source region are aligned with the first side surface of the gate trench, the first side surface of the source region is located inside the first side surface of the first well region, and the first epitaxial layer is outside the first side surface of the first well region; a second doped region of a second conductivity type, formed in the first epitaxial layer at a second side surface of the gate trench, wherein a bottom surface of the second doped region is located below a bottom surface of the gate trench and further extends to directly below the bottom surface of the gate trench; A plurality of third doped regions doped with the first conductivity type are formed in a surface area of ​​the second doped region, and the third doped regions are arranged at intervals along the length direction of the second side of the gate trench; the first side of each of the third doped regions and the first side of the second doped region are aligned with the second side of the gate trench, and the second side of each of the third doped regions extends to or is aligned with the second side of the second doped region, and the first epitaxial layer is located outside the second side of the second doped region; The source region, the first well region, the second doping region and the third doping region are all connected to the source electrode composed of the front metal layer through corresponding top through-holes; The surface of the first well region covered by the side surface of the gate conductive material layer is used to form a first channel region of the MOSFET; The second doped region and the adjacent first well region or the second doped region located between two adjacent gate trenches serve as the gate region of the JFET, the first epitaxial layer between the gate regions forms the longitudinal channel region of the JFET, and the third doped region forms the lateral channel region of the JFET.

2. The trench MOSFET according to claim 1, wherein: The material of the first epitaxial layer is a semiconductor material having a band gap width greater than that of silicon.

3. The trench MOSFET according to claim 2, wherein: The material of the first epitaxial layer includes SiC.

4. The trench MOSFET according to claim 1, wherein: The material of the bottom dielectric layer and the material form of the gate dielectric layer, the thickness of the bottom dielectric layer is greater than the thickness of the gate dielectric layer.

5. The trench MOSFET according to claim 4, wherein: The material of the bottom dielectric layer includes an oxide layer; the top surface of the bottom dielectric layer is in an arc shape; The material of the gate dielectric layer includes an oxide layer; The gate conductive material layer includes a polysilicon gate.

6. The trench MOSFET according to claim 1, wherein: Ohmic contact alloy is formed on the bottom surfaces of the through holes corresponding to the source region, the first well region, the second doping region, and the third doping region.

7. The trench MOSFET according to claim 1, wherein: The doping concentration of the first epitaxial layer is 1E15cm -3 ~1E17cm -3 ; The doping concentration of the second doping region is 1E14 cm -3 ~1E16cm -3 ; The doping concentration of the third doping region is less than or equal to 1E16 cm -3 .

8. The field effect transistor according to any one of claims 1 to 7, characterized in that: The trench MOSFET is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the trench MOSFET is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

9. A method for manufacturing a trench MOSFET, characterized in that: The steps include: forming a first epitaxial layer doped with a first conductivity type, and forming a drain region heavily doped with the first conductivity type on the back side of the first epitaxial layer; forming a plurality of second doped regions of a second conductivity type in the first epitaxial layer; forming a plurality of gate trenches in the first epitaxial layer, wherein the etched regions of the gate trenches include portions of the second doped regions, and after the gate trenches are formed, the remaining second doped regions are located in the first epitaxial layer at second side surfaces of the gate trenches, and the bottom surfaces of the second doped regions are located below the bottom surfaces of the gate trenches and further extend directly below the bottom surfaces of the gate trenches; forming a bottom dielectric layer on the bottom surface of the gate trench; forming a gate dielectric layer on a side of the gate trench; filling a gate conductive material layer in the gate trench; forming a first well region of a second conductivity type in the first epitaxial layer at a first side surface of the gate trench, wherein a bottom surface of the first well region is located above a bottom surface of the gate trench; forming a heavily doped source region of the first conductivity type in the first well region, wherein the second side surface of the first well region and the second side surface of the source region are aligned with the first side surface of the gate trench, the first side surface of the source region is located inside the first side surface of the first well region, and the first epitaxial layer is outside the first side surface of the first well region; forming a plurality of third doped regions doped with the first conductivity type in a surface region of the second doped region, the third doped regions being arranged at intervals along a length direction of the second side of the gate trench; the first side of each of the third doped regions and the first side of the second doped region being aligned with the second side of the gate trench, the second side of each of the third doped regions extending to or aligned with the second side of the second doped region, the first epitaxial layer being located outside the second side of the second doped region; forming an interlayer film, a through hole and a front metal layer, and patterning and etching the front metal layer to form a source electrode; the source region, the first well region, the second doped region and the third doped region are all connected to the source electrode composed of the front metal layer through the corresponding through holes on the top; A drain electrode composed of a back metal layer is formed on the back side of the drain region.

10. The method for manufacturing a trench MOSFET according to claim 9, wherein: The material of the first epitaxial layer is a semiconductor material having a band gap width greater than that of silicon.

11. The method for manufacturing a trench MOSFET according to claim 10, wherein: The material of the first epitaxial layer includes SiC.

12. The method for manufacturing a trench MOSFET according to claim 9, wherein: The material of the bottom dielectric layer and the material form of the gate dielectric layer, the thickness of the bottom dielectric layer is greater than the thickness of the gate dielectric layer.

13. The method for manufacturing a trench MOSFET according to claim 12, wherein: The material of the bottom dielectric layer includes an oxide layer, the oxide layer of the bottom dielectric layer is grown by a deposition process and the thickness is controlled by an etching process, and the top surface of the bottom dielectric layer is arc-shaped by the etching process; The material of the gate dielectric layer includes an oxide layer, and the oxide layer of the gate dielectric layer is formed by a thermal oxidation process; The gate conductive material layer includes a polysilicon gate.

14. The method for manufacturing a trench MOSFET according to claim 9, wherein: Ohmic contact alloy is formed on the bottom surfaces of the through holes corresponding to the source region, the first well region, the second doping region, and the third doping region.

15. The method for manufacturing a trench MOSFET according to claim 9, wherein: The doping concentration of the first epitaxial layer is 1E15cm -3 ~1E17cm -3 ; The doping concentration of the second doping region is 1E14 cm -3 ~1E16cm -3 ; The doping concentration of the third doping region is less than or equal to 1E16 cm -3 .

16. The field effect transistor according to any one of claims 9 to 15, characterized in that: The trench MOSFET is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the trench MOSFET is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

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