A solar cell, a photovoltaic module and a method for manufacturing a solar cell

Abstract

The application discloses a solar cell, a photovoltaic module and a manufacturing method of the solar cell, and relates to the technical field of solar cells, and aims to solve the problem of how to make the photoelectric efficiency of the solar cell reach a high level. The solar cell comprises a semiconductor substrate, a first doped layer and a second doped layer. The semiconductor substrate comprises opposite first and second surfaces; the first surface comprises a first electrode area and a first non-electrode area; the surface of the first electrode area has a first texture structure, and the first non-electrode area has a second texture structure; the second surface comprises a second electrode area and a second non-electrode area; the second non-electrode area has a third texture structure, and the size consistency of the second texture structure is greater than that of the third texture structure; the first doped layer is arranged on the first electrode area; the second doped layer is arranged on the first non-electrode area; and the doping concentration of the first doped layer is greater than that of the second doped layer.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, and more particularly to a solar cell, a photovoltaic module, and a method for manufacturing a solar cell. Background Technology

[0002] A solar cell is a device that utilizes solar energy to directly convert light energy into electrical energy through the photoelectric effect or photochemical effect.

[0003] Current bifacial solar cells mainly include TOPCon (Tunnel Oxide Passivated Contact) cells, PERC cells (Passivated emitter and real cell) cells, and heterojunction cells.

[0004] Bifacial solar cells have a promising market due to their relatively simple manufacturing process and low cost. However, achieving high photoelectric efficiency remains a pressing technical challenge for the industry. Summary of the Invention

[0005] The purpose of this invention is to provide a solar cell, a photovoltaic module, and a method for manufacturing a solar cell, so as to improve the efficiency of solar cells.

[0006] To achieve the above objectives, in a first aspect, the present invention provides a solar cell. The solar cell includes: a semiconductor substrate, a first doped layer, and a second doped layer. The semiconductor substrate includes a first surface and a second surface opposite to each other; the first surface includes a first electrode region and a first non-electrode region; the surface of the first electrode region has a first textured structure, and the first non-electrode region has a second textured structure; the second surface includes a second electrode region and a second non-electrode region; the second non-electrode region has a third textured structure, the dimensional uniformity of the second textured structure being greater than the dimensional uniformity of the third textured structure; the first doped layer is disposed in the first electrode region; the second doped layer is disposed in the first non-electrode region; the doping concentration of the first doped layer is greater than the doping concentration of the second doped layer.

[0007] In the solar cell provided by this invention, the second non-electrode region has a third textured structure. Compared to a second non-electrode region without a textured structure, the reflectivity of the second non-electrode region is significantly reduced. Combined with passivation process optimization, the cell efficiency remains unaffected, improving the bifaciality of the cell. Furthermore, the dimensional consistency of the second textured structure is greater than that of the third textured structure. Dimensional consistency refers to the consistency of the one-dimensional dimension of the bottom surface and / or the height of the textured structure. Dimensional consistency is the difference between the size of the textured structure within a certain area and the average size of the textured structures within that area. For example, the one-dimensional dimension of the bottom surface of the second textured structure within a unit area on the first non-electrode region and the one-dimensional dimension of the bottom surface of the third textured structure in the second non-electrode region can be statistically analyzed, and the variance or range of these dimensions of the textured structures in the first and second non-electrode regions can be calculated respectively. Using the variance or range of the textured structures in the first and second non-electrode regions as a reference for consistency, the consistency of different textured structures can be compared by comparing the magnitude of the variance or range. The smaller the variance or range, the better the dimensional consistency.

[0008] When the first surface is the light-receiving surface, the second textured structure is located on it. Compared to the third textured structure, it has higher requirements for light-trapping and passivation performance. The textured structure has higher dimensional consistency, ensuring good light-trapping effects at different locations in the first non-electrode region, reducing the probability of incident light being reflected. Simultaneously, the better dimensional consistency of the textured structure provides a relatively regular surface undulation, which is more beneficial for the uniformity of the subsequent passivation layer thickness. This improves the passivation performance of the first non-electrode region surface, reduces the possibility of incident light recombination on the surface of the first non-electrode region, and ensures that incident light has a high probability of entering the semiconductor substrate at different locations within the first non-electrode region without being recombinated by surface defects. The second textured structure is designed to have greater dimensional consistency than the third textured structure. The fabricated second and third textured structures can respectively meet the requirements for light-trapping and passivation of the solar cell's light-receiving surface, and the requirement for improved light-trapping performance on the back surface. By combining the fabrication process with the size differentiation of the second and third textured structures, the etching degree of the second non-electrode region of the battery can be reduced while meeting the battery performance requirements, reducing the loss in the thickness direction of the semiconductor substrate, ensuring the thickness of the battery cell, increasing the utilization of absorbed incident light, and ensuring the mechanical strength of the battery cell.

[0009] Furthermore, the doping concentration of the first doped layer disposed in the first electrode region is greater than the doping concentration of the second doped layer disposed in the first non-electrode region. By reducing the doping concentration in the first non-electrode region, the high-concentration area on the first surface of the solar cell is reduced, mitigating recombination problems on the semiconductor substrate surface caused by high doping concentration and increasing the open-circuit voltage of the cell. Simultaneously, retaining the first doped layer in the first electrode region ensures a smaller contact resistance between the electrode and the first doped layer, reducing the cell's series resistance, improving the fill factor, and thus increasing the efficiency of the solar cell. Since the first non-electrode region lacks the obstruction of grid lines, it focuses on the light-trapping effect and passivation performance of the first surface of the cell, while the first electrode region focuses on contact performance and passivation performance. Based on the functional differences between the first electrode region and the first non-electrode region, the first non-electrode region needs to balance the light-trapping effect and the passivation performance of the passivation layer coating.

[0010] In one implementation, the size consistency of the first texture structure is greater than that of the third texture structure.

[0011] In one implementation, the first texture structure, the second texture structure, or the third texture structure is a pyramid-shaped structure.

[0012] Using the above technical solution is beneficial to increasing the surface area of ​​the semiconductor substrate, improving the light trapping effect of the semiconductor substrate, and allowing more light to be refracted into the semiconductor substrate through the area where the first texture structure, the second texture structure, or the third texture structure is located, and then utilized by the semiconductor substrate, so that the solar cell has a higher photoelectric conversion efficiency.

[0013] In one implementation, along the thickness direction of the semiconductor substrate, the first electrode region is higher than the first non-electrode region. The distance between the first electrode region and the first non-electrode region along the thickness direction of the semiconductor substrate is greater than or equal to 2 μm and less than or equal to 7 μm.

[0014] When the above technical solution is adopted, the first non-electrode region is recessed relative to the first electrode region, so that light can be reflected and absorbed in the groove, thereby reducing the reflectivity of the second texture structure.

[0015] In one implementation, the reflectivity of the first electrode region where the first texture structure is located is greater than the reflectivity of the first non-electrode region where the second texture structure is located.

[0016] With the above technical solution, the surface of the first non-electrode region where the second texture structure is located is not blocked by grid lines. Combined with the velvet structure with low reflectivity, it can better utilize incident light, improve light absorption and utilization, and thus improve the photoelectric conversion efficiency of the solar cell.

[0017] In one implementation, the first electrode region and / or the second electrode region includes a collector electrode region and a bus electrode region, wherein the extension direction of the collector electrode region and the extension direction of the bus electrode region are not the same; the width of the bus electrode region is greater than the width of the collector electrode region.

[0018] In the above technical solution, the busbar electrode region includes continuously arranged busbar electrodes or intermittently arranged busbar electrodes and end-line structures at the edge of the cell, used for welding interconnects such as solder ribbons in the module. Because the contact performance between the busbar electrode and the solar cell is lower than that of the current collector electrode, or because the busbar electrode needs to be welded to interconnects such as solder ribbons, the contact area with the solar cell surface or interconnects is usually increased by increasing the width of the busbar electrode to improve its contact and welding performance. Therefore, the width of the busbar electrode region in the first electrode region and the second electrode region is set to be greater than the width of the current collector electrode region, thus reducing the area of ​​the first electrode region and the second electrode region while ensuring the contact and welding performance between the busbar electrode and the solar cell.

[0019] In one implementation, along the thickness direction of the semiconductor substrate, the projection of the first non-electrode region on the second surface at least partially overlaps with the projection of the second non-electrode region on the second surface.

[0020] When the above technical solution is adopted, if both the second non-electrode region and the first non-electrode region are recessed into the semiconductor substrate, and if the second non-electrode region and the first non-electrode region completely correspond along the thickness direction of the semiconductor substrate, then the thickness of the semiconductor substrate located in the second non-electrode region and the first non-electrode region is smaller than the thickness of the semiconductor substrate located in the second electrode region and the first electrode region. That is, the thickness of the semiconductor substrate in the non-electrode region is smaller than the thickness of the semiconductor substrate in the electrode region, resulting in a significant reduction in the mechanical strength of the semiconductor substrate in the non-electrode region. Therefore, compared to the situation where the projections of the first non-electrode region and the second non-electrode region on the second surface completely overlap, in this application, the projections of the first non-electrode region and the second non-electrode region on the second surface at least partially overlap, which can meet the mechanical strength requirements of the semiconductor substrate and reduce or eliminate the probability of semiconductor substrate breakage.

[0021] In one implementation, the second non-electrode region is higher than the second electrode region along the thickness direction of the semiconductor substrate; the distance between the second electrode region and the second non-electrode region is greater than or equal to 2 μm and less than or equal to 6 μm along the thickness direction of the semiconductor substrate.

[0022] With the above technical solution, if the distance between the second electrode region and the second non-electrode region is greater than 6 μm along the thickness direction of the semiconductor substrate, and the second non-electrode region is deeper, then a significant portion of the second surface of the semiconductor substrate is removed, which reduces the overall mechanical strength of the solar cell. Furthermore, solar cells generate electricity by separating electrons and holes from light illuminating the semiconductor substrate. If too much of the semiconductor substrate is removed, the light transmission path on the semiconductor substrate will be reduced, and the light absorption rate on the semiconductor substrate will decrease. This leads to a reduction in the number of photogenerated carriers (holes and electrons) generated on the semiconductor substrate, resulting in a decrease in the photoelectric conversion efficiency of the solar cell. This application sets the distance between the second electrode region and the second non-electrode region within the aforementioned range along the thickness direction of the semiconductor substrate, ensuring a high light absorption rate of the semiconductor substrate, maintaining the photoelectric conversion efficiency of the solar cell, and ensuring sufficient mechanical strength of the solar cell.

[0023] Secondly, the present invention also provides a photovoltaic module. The photovoltaic module includes a cell string and an encapsulation layer. The cell string includes multiple interconnecting elements and multiple solar cells as described in the above technical solutions. The interconnecting elements are used to connect the multiple solar cells in series to form the cell string, and the encapsulation layer is used to cover the surface of the cell string.

[0024] The beneficial effects of the photovoltaic module provided by this invention are the same as those of the solar cell described in the above technical solution, and will not be repeated here.

[0025] Thirdly, the present invention also provides a method for manufacturing a solar cell. The method for manufacturing the solar cell includes:

[0026] First, a semiconductor substrate is provided; the semiconductor substrate has a first side and a second side opposite to each other; the first side and the second side are texturized to form a first textured structure; the first side includes a first electrode region and a first non-electrode region, and the second side includes a second electrode region and a second non-electrode region;

[0027] Next, a diffusion process is performed on the first surface of the semiconductor substrate to form a first doped layer and a first doped oxide layer formed on the first doped layer;

[0028] Next, a tunneling layer and a doped conductive layer are deposited on the edge region of the first surface and on the second surface; a second doped oxide layer is formed on the doped conductive layer.

[0029] Next, the first laser is used to irradiate the first doped oxide layer and the first doped layer located on the first non-electrode region, and to irradiate the second doped oxide layer, the doped conductive layer and the tunneling layer located on the edge region of the first non-electrode region.

[0030] Next, the second laser is used to irradiate the second doped oxide layer, the doped conductive layer and the tunneling layer located on the second non-electrode region.

[0031] Next, after the first and second laser irradiation processes, a secondary texturing process is performed to form a second texture structure on the first non-electrode region, while simultaneously forming a third texture structure in the second non-electrode region; the size uniformity of the second texture structure is greater than that of the third texture structure.

[0032] In the method for manufacturing a solar cell provided by this invention, a first laser is used to irradiate the first doped oxide layer and the first doped layer located on the first non-electrode region. At this point, only the first doped layer in the first electrode region is retained, and the doping concentration at the corresponding position in the first electrode region is greater than the doping concentration at the corresponding position in the first non-electrode region. By reducing the doping concentration in the first non-electrode region, the high-concentration area on the first surface of the solar cell is reduced, mitigating recombination problems on the semiconductor substrate surface caused by high doping concentration and increasing the open-circuit voltage of the cell. Simultaneously, retaining the first doped layer in the first electrode region ensures a smaller contact resistance between the electrode and the first doped layer, reducing the cell's series resistance, improving the fill factor, and thus increasing the efficiency of the solar cell. Since the first non-electrode region is not obstructed by grid lines, it focuses on the light-trapping effect and passivation performance of the first surface of the cell, while the first electrode region focuses on contact performance and passivation performance. Based on the functional differences between the first electrode region and the first non-electrode region, the first non-electrode region needs to balance the light-trapping effect and the passivation performance of the passivation layer coating. Furthermore, the aforementioned "secondary texturing process to form a second textured structure on the first non-electrode region" is performed after the steps of "depositing a tunneling layer and a doped conductive layer on the edge region of the first surface and the second surface; forming a second doped oxide layer on the doped conductive layer." This reduces the surface difference between the edge region near the semiconductor substrate and the middle region of the first non-electrode region before texturing, thereby reducing the difference in the second textured structure formed on the first non-electrode region after texturing. In addition, the chemical passivation of the tunneling layer and the field passivation of the doped conductive layer can significantly reduce the recombination degree on the semiconductor substrate surface. Simultaneously, the tunneling layer ensures effective tunneling of majority carriers, and the doped conductive layer significantly improves the conduction performance of photogenerated carriers, thereby increasing the open-circuit voltage and fill factor of the solar cell. When a tunneling layer and a doped conductive layer are stacked on the second electrode region, they form a passivated contact structure. The tunneling layer allows majority carrier electrons to tunnel into the doped conductive layer while blocking minority carrier hole recombination. This allows electrons to be collected by the metal during lateral transport in the doped conductive layer, greatly reducing the metal-to-metal recombination current and increasing the open-circuit voltage and short-circuit current of the battery, thereby improving battery efficiency.

[0033] In one implementation, the power of the first laser is 1W to 50W, and the scanning speed of the first laser is 5m / s to 40m / s; the power of the second laser is 1W to 50W, and the scanning speed of the second laser is 5m / s to 40m / s; the power and scanning speed of the first laser and the second laser are different.

[0034] In one implementation, the secondary texturing process includes: placing a semiconductor substrate, after undergoing a first laser and a second laser irradiation process, into a first etching tank for secondary texturing; the first etching tank contains an alkaline solution and a texturing additive, the temperature of the first etching tank is 60°C to 85°C, the concentration of the alkaline solution is 0.2% to 6%, and the duration of the secondary texturing process is 2 min to 8 min.

[0035] In one implementation, after the first and second laser irradiation processes, a secondary texturing process is performed to form a second textured structure on the first non-electrode region. After forming a third textured structure in the second non-electrode region, the method for manufacturing a solar cell further includes:

[0036] A passivation layer is formed on the doped conductive layer and on the first and second surfaces of the semiconductor substrate;

[0037] Electrodes are formed on the passivation layer, with the electrodes located in the first electrode region and the second electrode region, respectively.

[0038] The aforementioned passivation layer can passivate the surface of a semiconductor substrate, reduce surface recombination, and improve open-circuit voltage and fill factor. Attached Figure Description

[0039] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0040] Figure 1 This is a cross-sectional view of the solar cell in an embodiment of the present invention;

[0041] Figure 2 This is an enlarged schematic diagram of a portion of the structure of the first surface of the solar cell in an embodiment of the present invention. Figure 1 ;

[0042] Figure 3 This is an enlarged schematic diagram of a portion of the structure of the first surface of the solar cell in an embodiment of the present invention. Figure 2 ;

[0043] Figure 4 This is an enlarged schematic diagram of a portion of the structure of the second surface of the solar cell in an embodiment of the present invention.

[0044] Figure label:

[0045] 1-Semiconductor substrate, 10-First side, 100-First electrode region, 101-First non-electrode region, 102-First textured structure, 103-Second textured structure; 11-Second side, 110-Second electrode region, 111-Second non-electrode region, 112-Third textured structure; 12-Side surface, 3-Tunneling layer, 4-Doped conductive layer, 5-Passivation layer, 50-Aluminum oxide passivation layer, 51-Silicon nitride passivation layer; 6-First electrode, 7-Second electrode. Detailed Implementation

[0046] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0047] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0048] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0049] In the description of this invention, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0050] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0051] In a first aspect, embodiments of the present invention provide a solar cell. See [link to previous section]. Figure 1 The solar cell includes: a semiconductor substrate 1, a first doped layer, and a second doped layer ( Figures 1 to 4 (Not shown in the image). The semiconductor substrate 1 includes a first surface 10 and a second surface 11 facing each other; the first surface 10 includes a first electrode region 100 and a first non-electrode region 101; since the first non-electrode region 101 is not blocked by the gate line, the first non-electrode region 101 focuses on the light trapping effect and passivation performance of the front side of the cell, while the first electrode region 100 focuses on the contact performance and passivation performance. Based on the functional differences between the first electrode region 100 and the first non-electrode region 101, the first non-electrode region 101 needs to take into account both the light trapping effect and the passivation performance of the passivation layer coating.

[0052] In terms of shape, the first surface 10 and the second surface 11 of the semiconductor substrate 1 may have the same shape or different shapes. In this embodiment of the invention, the first surface 10 and the second surface 11 have the same shape. For example, the shape of the first surface 10 or the second surface 11 may be a square, a rectangle, a rounded square, a circle, etc.

[0053] In terms of materials, the semiconductor substrate 1 can be any semiconductor material such as silicon substrate, germanium silicon substrate, germanium substrate or gallium arsenide substrate.

[0054] In terms of conductivity type, the semiconductor substrate 1 can be an intrinsically conductive substrate, an N-type conductive substrate, or a P-type conductive substrate. Preferably, the semiconductor substrate 1 is a P-type conductive substrate or an N-type conductive substrate. Compared with an intrinsically conductive substrate, a P-type conductive substrate or an N-type conductive substrate has better conductivity, resulting in a lower bulk resistivity in the final solar cell and thus improving the efficiency of the solar cell. For example, the semiconductor substrate 1 is an N-type silicon substrate. Compared with a P-type conductive substrate, an N-type silicon substrate has advantages such as higher minority carrier lifetime, no light decay, and better performance in low-light conditions.

[0055] In terms of light reception, when the first side 10 is the light-receiving side, the second side 11 is the backlight side.

[0056] In some embodiments, a first doped layer is disposed in a first electrode region 100; a second doped layer is disposed in a first non-electrode region 101; and the doping concentration of the first doped layer is greater than the doping concentration of the second doped layer.

[0057] See Figures 1 to 4The doping concentration of the first doped layer in the first electrode region 100 is greater than that of the second doped layer in the first non-electrode region 101. Retaining the first doped layer in the first electrode region 100 ensures a smaller contact resistance between the electrode and the first doped layer, reducing the cell series resistance, increasing the fill factor, and thus improving the efficiency of the solar cell. Simultaneously, by reducing the doping concentration in the first non-electrode region 101, the influence of dopant ions in the doped layer on the field effect of the passivation layer is reduced without affecting contact performance, improving the passivation performance of the light-receiving surface. Furthermore, reducing the high-concentration area on the front side of the solar cell reduces recombination problems on the semiconductor substrate 1 surface caused by high doping concentration, increasing the open-circuit voltage of the cell.

[0058] As one possible implementation, regarding "the doping concentration of the first doped layer is greater than the doping concentration of the second doped layer", the doping concentration of the second doped layer is greater than or equal to zero.

[0059] See Figures 1 to 4 When the doping concentration of the second doped layer is zero, a PN junction is formed between the semiconductor substrate 1 and the first doped layer located in the first electrode region 100, and no PN junction exists in the first non-electrode region 101 of the semiconductor substrate 1; that is, the first surface 10 of the solar cell includes a heavily doped region and an undoped region. At this time, the recombination level in the first non-electrode region 101 of the first surface 10 is effectively reduced, increasing the open-circuit voltage of the cell. Simultaneously, high doping can be performed in the first electrode region 100, improving the contact resistance between the electrode and the first doped layer, reducing the series resistance of the cell, and increasing the fill factor, thereby improving the efficiency of the solar cell.

[0060] Furthermore, the "doping concentration of the first doped layer" mentioned above may refer to the doping concentration on the surface of the first doped layer, or the average concentration at different locations along the thickness direction of the first doped layer.

[0061] "Doping concentration of the second doped layer" can refer to the doping concentration on the surface of the second doped layer, or the average concentration at different locations along the thickness direction of the second doped layer.

[0062] "The doping concentration of the first doped layer is greater than the doping concentration of the second doped layer" can mean that the doping concentration at the surface of the first doped layer is greater than the doping concentration at the surface of the second doped layer. Alternatively, it can mean that the average concentration of the first doped layer at different locations along its thickness is greater than the average concentration of the second doped layer at different locations along its thickness.

[0063] In some embodiments, see Figures 1 to 4The first doped layer may be an additional film layer formed on the semiconductor substrate 1; or, the first doped layer may be formed by diffusion treatment of the first surface 10 of the semiconductor substrate 1, in which case the top surface of the first doped layer is coplanar with the first surface 10 of the semiconductor substrate 1.

[0064] In some embodiments, see Figures 1 to 4 The second doped layer may be an additional film layer formed on the semiconductor substrate 1; or, the second doped layer may be formed by diffusion treatment of the first surface 10 of the semiconductor substrate 1, in which case the top surface of the second doped layer is coplanar with the first surface 10 of the semiconductor substrate 1.

[0065] As one possible implementation, see Figures 1 to 4 Semiconductor substrate 1 is an N-type silicon substrate, with a first p-type doped layer and a second p-type doped layer, both of which are diffusion layers on the surface of semiconductor substrate 1. In this case, the surfaces of the first and second doped layers are monocrystalline silicon surfaces. Setting the doping concentration of the second doped layer to be lower than that of the first doped layer is more important than adding additional doped layers to enhance the passivation effect of the subsequent passivation layer on the surface of semiconductor substrate 1.

[0066] In some embodiments, see Figures 1 to 4 The surface of the first electrode region 100 has a first texture structure 102, and the first non-electrode region 101 has a second texture structure 103; the second surface 11 includes a second electrode region 110 and a second non-electrode region 111; the second non-electrode region 111 has a third texture structure 112, and the size uniformity of the second texture structure 103 is greater than the size uniformity of the third texture structure 112.

[0067] See Figures 1 to 4The first non-electrode region 101 is located on the light-receiving surface of the bifacial cell. Compared with the second non-electrode region 111, most of the incident light enters from the light-receiving surface. Therefore, better light trapping effect and passivation performance are required to ensure that the incident light enters the semiconductor substrate 1 from the light-receiving surface instead of being reflected or incident on the surface of the light-receiving surface and recombinated by recombination centers on the light-receiving surface. This increases the possibility of the incident light being transmitted to the semiconductor substrate 1 to generate laser photocarriers, thereby increasing the utilization rate of the solar cell for the incident light. The second textured structure 103 on the light-receiving surface has higher dimensional uniformity than the third textured structure 112 on the backlighting surface. This ensures better light-trapping performance at different locations in the first non-electrode region 101, reducing the probability of incident light reflecting off the solar cell. Furthermore, the better dimensional uniformity of the textured structure provides a relatively regular surface texture, which is more beneficial for the uniformity of the subsequent passivation layer thickness. This improves the passivation performance of the first non-electrode region 101 surface, reduces the possibility of incident light recombination on the surface of the first non-electrode region 101, and ensures that incident light has a high probability of entering the semiconductor substrate 1 at different locations in the first non-electrode region 101 without being recombinated by surface defects. The second textured structure 103 is designed to have greater dimensional uniformity than the third textured structure 112. The fabricated second textured structure 103 and third textured structure 112 can respectively meet the requirements of light trapping and passivation on the light-receiving surface of the solar cell, as well as the requirement for improved light trapping performance on the backlighting surface. By combining the fabrication process, the size difference between the second texture structure 103 and the third texture structure 112 can reduce the etching degree of the second non-electrode region 111 of the battery while meeting the battery performance requirements, reduce the loss in the thickness direction of the semiconductor substrate 1, ensure the thickness of the battery cell, increase the utilization of absorbed incident light, and ensure the mechanical strength of the battery cell.

[0068] As one possible implementation, see Figures 1 to 4 The size uniformity of the first texture structure 102 in the first electrode region 100 is greater than the size uniformity of the third texture structure 112 in the second non-electrode region 111. The size uniformity of the texture structure on the light-receiving surface needs to be greater than that on the backlight surface to meet the requirements of the texture structure on the light-receiving surface of the solar cell for reflectivity uniformity and passivation performance.

[0069] The third texture structure 112 in the second non-electrode region 111 exhibits good dimensional consistency, enhancing the light-trapping effect on its surface. This not only improves the light-trapping effect on the back of the solar cell but also reduces the probability of light transmitted from inside the solar cell to the back being reflected back. Simultaneously, the first texture structure 102 in the first electrode region 100 and the second texture structure 103 in the first non-electrode region 101 show even better dimensional consistency. This enhances the reflection on the front of the solar cell, improving its light-trapping effect, while also increasing the uniformity of passivation layer thickness at different locations during passivation layer deposition, thus improving passivation performance and reducing the probability of incident light recombination on the light-receiving surface. By matching the structures of the electrode and non-electrode regions on the light-receiving and back-light-receiving surfaces, as well as the texture structures in different areas, light utilization is improved by enhancing both the light-trapping effect and reducing the probability of incident light recombination, thereby increasing the efficiency of the solar cell.

[0070] Size consistency refers to the consistency of the bottom one-dimensional dimension and / or height of a texture structure. Size consistency is the difference between the size of a texture structure within a certain region and the average size of texture structures within that region. For example, the bottom one-dimensional dimension of the second texture structure 103 within a unit area on the first non-electrode region 101 and the bottom one-dimensional dimension of the third texture structure 112 in the second non-electrode region 111 can be statistically analyzed, and the variance or range of these texture structures in the first non-electrode region 101 and the second non-electrode region 111 can be calculated respectively. Using the variance or range of the texture structures in the first non-electrode region 101 and the second non-electrode region 111 as a reference for consistency, different texture structures can be compared to determine the quality of their consistency. The smaller the variance or range, the better the size consistency.

[0071] As one possible implementation, see Figure 1 The first texture structure 102, the second texture structure 103, or the third texture structure 112 are pyramid-shaped structures. In this case, it is beneficial to increase the surface area of ​​the semiconductor substrate 1, improve the light trapping effect of the semiconductor substrate 1, and allow more light to be refracted into the semiconductor substrate 1 through the area where the first texture structure 102, the second texture structure 103, or the third texture structure 112 is located and utilized by the semiconductor substrate 1, so that the solar cell has a high photoelectric conversion efficiency.

[0072] In one alternative approach, see Figure 1When the first texture structure 102 is a pyramid-shaped structure, the height of the first texture structure 102 is greater than or equal to 1 μm and less than or equal to 4 μm; the base dimension of the first texture structure 102 is greater than or equal to 1 μm and less than or equal to 5 μm. The base of the first texture structure 102 can be square, rhomboid, rectangular, parallelogram, approximately rhomboid, or approximately rectangular. The base dimension of the first texture structure 102 can be the long side, short side, diagonal, or the farthest distance between the two endpoints of the base shape. The height and base dimension of the first texture structure 102 can be the height or base dimension of a single texture structure, or it can be the average value of the height or base dimension of the first texture structure 102 within a certain area. For example, within a range of 1 μm × 1 μm, the height of the first texture structure 102 can be 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, or 4 μm, etc. The bottom surface size of the first texture structure 102 can be 1μm, 1.5μm, 2μm, 2.5μm, 3μm, 3.5μm, 4μm, 4.5μm or 5μm, etc.

[0073] In one alternative approach, see Figure 1 When the second texture structure 103 is a pyramid-shaped structure, the height of the second texture structure 103 is greater than or equal to 1 μm and less than or equal to 4 μm; the base dimension of the second texture structure 103 is greater than or equal to 1 μm and less than or equal to 5 μm. The base of the second texture structure 103 can be square, rhomboid, rectangular, parallelogram, approximately rhomboid, or approximately rectangular. The base dimension of the second texture structure 103 can be the long side, short side, diagonal, or the farthest distance between the two endpoints of the base shape. The height and base dimension of the second texture structure 103 can be the height or base dimension of a single texture structure, or it can be the average value of the height or base dimension of the second texture structure 103 within a certain area. For example, within a range of 1 μm × 1 μm, the height of the second texture structure 103 can be 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, or 4 μm, etc. The bottom surface size of the second texture structure 103 can be 1μm, 1.5μm, 2μm, 2.5μm, 3μm, 3.5μm, 4μm, 4.5μm or 5μm, etc.

[0074] See Figure 1 The tower height or base dimensions of the first texture structure 102 and the second texture structure 103 may be equal or unequal.

[0075] As one possible implementation, see Figure 1 , Figure 2 and Figure 3Along the thickness direction A of the semiconductor substrate 1, the first electrode region 100 is higher than the first non-electrode region 101. Along the thickness direction of the semiconductor substrate 1, the distance between the first electrode region 100 and the first non-electrode region 101 is greater than or equal to 2 μm and less than or equal to 7 μm. In this case, the first non-electrode region 101 is recessed relative to the first electrode region 100, allowing light to be reflected and absorbed within the recess, thereby reducing the reflectivity of the second texture structure 103.

[0076] See Figures 1 to 3 The distance L1 between the first electrode region 100 and the first non-electrode region 101 can be the distance between the top surface of the first electrode region 100 and the top surface of the first non-electrode region 101, or the distance between the bottom surface of the first electrode region 100 and the bottom surface of the first non-electrode region 101, or the distance between the bottom surface of the first electrode region 100 and the top surface of the first non-electrode region 101, or the distance between the top surface of the first electrode region 100 and the bottom surface of the first non-electrode region 101. For example, the distance L1 between the top surface of the first electrode region 100 and the top surface of the first non-electrode region 101 can be 2μm, 2.5μm, 3μm, 3.5μm, 4μm, 4.5μm, 5μm, 5.5μm, 6μm, 6.5μm, or 7μm, etc.

[0077] It is worth noting that, see Figures 1 to 3 The top surface of the first electrode region 100 is composed of the vertices of multiple first texture structures 102. Since the sizes of different first texture structures 102 vary, this top surface is a plane formed by the vertices of most of the first texture structures 102 on the first electrode region 100. The proportion of most of the first texture structures 102 in the first electrode region 100 can be flexibly selected according to actual conditions. Similarly, the top surface of the first non-electrode region 101 is composed of the vertices of multiple second texture structures 103.

[0078] As one possible implementation, see Figures 1 to 3 The reflectivity of the first electrode region 100, where the first textured structure 102 is located, is greater than the reflectivity of the first non-electrode region 101, where the second textured structure 103 is located. The surface of the first non-electrode region 101, where the second textured structure 103 is located, is free from grid lines. Combined with the low-reflectivity textured surface, it can better utilize incident light, improving light absorption and utilization, thereby increasing the photoelectric conversion efficiency of the solar cell.

[0079] As one possible implementation, see Figures 1 to 3 The first electrode region 100 and / or the second electrode region 110 include a collector electrode region and a bus electrode region, and the extension direction of the collector electrode region and the extension direction of the bus electrode region are not the same; the width of the bus electrode region is greater than the width of the collector electrode region.

[0080] The busbar electrode region includes continuously or intermittently arranged busbar electrodes and end-line structures at the edge of the solar cell, used for welding interconnects such as solder ribbons in the module. Because the contact performance between the busbar electrode and the solar cell is lower than that of the current collector electrode, or because the busbar electrode needs to be welded to interconnects such as solder ribbons, the width of the busbar electrode is usually increased to increase the contact area with the solar cell surface or interconnects, thereby improving the contact and welding performance of the busbar electrode. Therefore, the width of the busbar electrode region in the first electrode region and the second electrode region is set to be greater than the width of the current collector electrode region, thus reducing the area of ​​the first electrode region and the second electrode region while ensuring the contact and welding performance between the busbar electrode and the solar cell.

[0081] As one possible implementation, see Figure 1 Along the thickness direction of the semiconductor substrate 1, the projection of the first non-electrode region 101 on the second surface 11 at least partially overlaps with the projection of the second non-electrode region 111 on the second surface 11.

[0082] As one possible implementation, see Figure 1 The overlap between the projection width of the first non-electrode region 101 on the second surface 11 and the projection width of the second non-electrode region 111 on the second surface 11 is 50% to 95% of the projection width of either the first non-electrode region 101 or the second non-electrode region 111 on the second surface 11. For example, the percentage can be 50%, 55%, 60%, 65%, 70%, 75%, 80%, 86%, 90%, or 95%, etc.

[0083] See Figure 1In actual solar cell fabrication, the second non-electrode region 111 is the laser-affected area. When the laser acts on the second surface 11 of the semiconductor substrate 1, it affects the first surface 10 of the semiconductor substrate 1, causing changes to the surface of the corresponding laser-affected area on the first surface 10. Based on this, when the second non-electrode region 111 and the first non-electrode region 101 are completely overlapped along the thickness direction of the semiconductor substrate 1, the laser-affected area (i.e., the first non-electrode region 101) on the other side affected by the laser-affected area (i.e., the second non-electrode region 111) can be etched away during the process, reducing the area affected by the laser on the first surface 10 and the second surface 11 of the semiconductor substrate 1, providing a good surface foundation for subsequent coating and electrode printing; and it can also reduce the transport path of charge carriers to the positive and negative electrode regions to a certain extent. When both the second non-electrode region 111 and the first non-electrode region 101 are recessed into the semiconductor substrate 1, if the second non-electrode region 111 and the first non-electrode region 101 completely correspond along the thickness direction of the semiconductor substrate 1, the thickness of the semiconductor substrate 1 located in the second non-electrode region 111 and the first non-electrode region 101 is smaller than the thickness of the semiconductor substrate 1 located in the second electrode region 110 and the first electrode region 100. That is, the thickness of the semiconductor substrate 1 in the non-electrode region is smaller than the thickness of the semiconductor substrate 1 in the electrode region, resulting in a significant reduction in the mechanical strength of the semiconductor substrate 1 in the non-electrode region. Therefore, compared to the situation where the projection of the first non-electrode region 101 on the second surface 11 completely overlaps with the projection of the second non-electrode region 111 on the second surface 11, in this application, the projection of the first non-electrode region 101 on the second surface 11 at least partially overlaps with the projection of the second non-electrode region 111 on the second surface 11, which can meet the mechanical strength requirements of the semiconductor substrate 1 and reduce or eliminate the probability of the semiconductor substrate 1 breaking.

[0084] As one possible implementation, see Figure 1 The second electrode region 110 and the second non-electrode region 111 are alternately arranged on the second surface 11. A tunneling layer 3 is disposed on the surface of the second electrode region 110, and a doped conductive layer 4 is disposed on the second electrode region 110, located on the side of the tunneling layer 3 away from the semiconductor substrate 1. The surface of the second electrode region 110 includes a tower-based structure, the undulation of which is less than that of the pyramid-shaped structure, and the reflectivity of the surface of the region where the tower-based structure is located is greater than that of the surface of the region where the pyramid-shaped structure is located.

[0085] See Figure 1The second non-electrode region 111 does not have a tunneling layer 3 and a doped conductive layer 4, which reduces the area of ​​the tunneling layer 3 and the doped conductive layer 4 on the second surface 11, reduces parasitic absorption on the second surface 11, and improves the utilization rate of incident light on the second surface 11 of the solar cell. During the fabrication of the tunneling layer 3 and the doped conductive layer 4, they are typically deposited as a whole layer on the second surface 11, and then removed from the second non-electrode region 111 using laser etching, wet etching, or other methods. Therefore, setting the second electrode region 110 higher than the second non-electrode region 111 ensures that while removing the tunneling layer 3 and the doped conductive layer 4 from the second non-electrode region 111, the inner extension layer on the surface of the semiconductor substrate 1 in the second non-electrode region 111 is also removed, reducing Auger recombination caused by dopants in the second non-electrode region 111, reducing the probability of carrier recombination in the second non-electrode region 111, and improving cell efficiency.

[0086] In some embodiments, see Figure 1 The doping type of the aforementioned doped conductive layer 4 is opposite to that of the first doped layer.

[0087] See Figure 1 Regarding the material and thickness of the tunneling layer 3, these can be set according to actual conditions and are not specifically limited here. For example, the material of the tunneling layer 3 may include one or more of silicon oxide, aluminum oxide, titanium oxide, hafnium dioxide, gallium oxide, tantalum pentoxide, niobium pentoxide, silicon nitride, silicon carbonitride, aluminum nitride, titanium nitride, and titanium nitride carbonitride. The thickness of the tunneling layer 3 is greater than or equal to 1 nm and less than or equal to 2 nm; for example, the thickness of the tunneling layer 3 may be 1 nm, 1.2 nm, 1.5 nm, 1.7 nm, 1.8 nm, or 2 nm. Furthermore, the doped conductive layer 4 may be a doped polycrystalline silicon layer, which may be a phosphorus-doped polycrystalline silicon layer, or it may be doped with other substances; no specific limitations are made here.

[0088] In some embodiments, see Figure 1 and Figure 4 Along the thickness direction A of the semiconductor substrate 1, the second non-electrode region 111 is higher than the second electrode region 110. Along the thickness direction A of the semiconductor substrate 1, the distance L2 between the second electrode region 110 and the second non-electrode region 111 is greater than or equal to 2 μm and less than or equal to 6 μm.

[0089] See Figure 1 and Figure 4The distance L2 between the second electrode region 110 and the second non-electrode region 111 can be the distance between the top surface of the second electrode region 110 and the top surface of the second non-electrode region 111, or the distance between the bottom surface of the second electrode region 110 and the bottom surface of the second non-electrode region 111, or the distance between the bottom surface of the second electrode region 110 and the top surface of the second non-electrode region 111, or the distance between the top surface of the second electrode region 110 and the bottom surface of the second non-electrode region 111. For example, the distance L2 between the second electrode region 110 and the second non-electrode region 111 can be 2μm, 2.5μm, 3μm, 3.5μm, 4μm, 4.5μm, 5μm, 5.5μm, or 6μm, etc.

[0090] See Figures 1 to 4 If the distance between the second electrode region 110 and the second non-electrode region 111 along the thickness direction of the semiconductor substrate 1 is greater than 6 μm, and the second non-electrode region 111 is deeper, then a significant portion of the second surface 11 of the semiconductor substrate 1 will be removed, reducing the overall mechanical strength of the solar cell. Furthermore, solar cells generate electricity by separating electrons and holes from light illuminating the semiconductor substrate 1. If too much of the semiconductor substrate 1 is removed, the light transmission path on the semiconductor substrate 1 will be reduced, decreasing the light absorption rate. This leads to a decrease in the number of photogenerated carriers (holes and electrons) generated on the semiconductor substrate 1, resulting in a lower photoelectric conversion efficiency of the solar cell. This application sets the distance between the second electrode region 110 and the second non-electrode region 111 along the thickness direction of the semiconductor substrate 1 within the aforementioned range, ensuring a high light absorption rate of the semiconductor substrate 1, maintaining the photoelectric conversion efficiency of the solar cell, and ensuring sufficient mechanical strength of the solar cell.

[0091] In some embodiments, see Figure 1 During the texturing process of the second non-electrode region 111 of the second surface 11 to form the third texture structure 112, a portion of the semiconductor substrate 1 located in the second non-electrode region 111 is etched away. Therefore, along the thickness direction A of the semiconductor substrate 1, the top surface of the second non-electrode region 111 is higher than the top surface of the second electrode region 110.

[0092] At this time, the top surface of the second non-electrode region 111 is composed of the vertices of multiple third texture structures 112. Since the sizes of different third texture structures 112 are different, the top surface of the second non-electrode region 111 here is a plane composed of the vertices of most of the third texture structures 112 on the second non-electrode region 111. The proportion of most of the third texture structures 112 in the second non-electrode region 111 can be flexibly selected according to the actual situation.

[0093] Secondly, embodiments of the present invention also provide a photovoltaic module. The photovoltaic module includes a cell string and an encapsulation layer. The cell string includes multiple interconnecting elements and multiple solar cells as described in the above technical solutions. The interconnecting elements are used to connect the multiple solar cells in series to form the cell string, and the encapsulation layer is used to cover the surface of the cell string.

[0094] The beneficial effects of the photovoltaic modules provided in the embodiments of the present invention are the same as those of the solar cells described in the above technical solutions, and will not be repeated here.

[0095] In some embodiments, the solar cell described above is a TOPCon cell.

[0096] Thirdly, the present invention also provides a method for manufacturing a solar cell. (Combined with...) Figures 1 to 4 The method for manufacturing this solar cell includes:

[0097] First, a semiconductor substrate 1 is provided; the semiconductor substrate 1 has a first surface 10 and a second surface 11 opposite to each other, and a plurality of side surfaces 12 located between the first surface 10 and the second surface 11; the first surface 10 and the second surface 11 are texturized to form a first textured structure 102; the first surface 10 includes a first electrode region 100 and a first non-electrode region 101, and the second surface 11 includes a second electrode region 110 and a second non-electrode region 111;

[0098] The aforementioned first texture structure 102 can trap light, reducing the reflection of sunlight by the solar cell and thus improving the performance of the solar cell.

[0099] For example, when the first surface 10 is the light-receiving surface, the second surface 11 is the backlight surface. Alternatively, when the first surface 10 is the front surface, the second surface 11 is the back surface.

[0100] For example, the semiconductor substrate 1 is cleaned, and then the first surface 10 and the second surface 11 are texturized using an alkaline texturing solution. Specific cleaning steps and texturing methods can be found in the prior art and are not specifically limited here. The shape, material, conductivity type, and light-receiving properties of the semiconductor substrate 1 are described above and will not be repeated here.

[0101] Next, the first surface 10 of the semiconductor substrate 1 is subjected to diffusion treatment to form a first doped layer and a first doped oxide layer formed on the first doped layer; wherein the semiconductor substrate 1 and the first doped layer located in the first electrode region 100 have opposite conductivity types, and at this time, the semiconductor substrate 1 and the first doped layer located in the first electrode region 100 form a PN junction.

[0102] For example, the doping source used in the diffusion process includes a group III source, such as a boron source, a gallium source, an indium source, etc.

[0103] In one alternative approach, the aforementioned Group III source is a boron source, and the first doped oxide layer is a borosilicate glass layer. During subsequent processing of the solar cell, the borosilicate glass layer can provide protection, reducing the risk of etching the first electrode region 100 and ensuring the quality of the solar cell.

[0104] In some embodiments, the first surface 10 of the semiconductor substrate 1 is subjected to a diffusion treatment to form a first doped layer and a first doped oxide layer formed on the first doped layer. This can be achieved by placing the semiconductor substrate 1 in a tube diffusion furnace and diffusing a boron source, BCl3 or BBr3, in a nitrogen and oxygen atmosphere. The diffusion time and temperature can be set according to actual needs. At this time, a first doped layer (e.g., a doped P+ layer) and a first doped oxide layer (e.g., a borosilicate glass layer) are formed. It should be noted that during the diffusion treatment of the first surface 10 of the semiconductor substrate 1, the first doped layer and the first doped oxide layer will inevitably form on at least a portion of the side surface 12 and the second surface 11. At least a portion of the second surface 11 can be understood as the edge region of the second surface 11 near the side surface 12, or the entire second surface 11.

[0105] As one possible implementation, the above-mentioned method for manufacturing solar cells further includes the following steps: removing the first doped layer formed on the second surface 11 and the side surface 12 to remove the PN junction on the second surface 11 and the side surface 12.

[0106] For example, a chain polisher and a tank polisher are used to polish the second surface 11 (backlight surface) and the side surface 12 on which the first doped layer is formed, in order to remove the PN junctions on the second surface 11 and the side surface 12 of the semiconductor substrate 1 and eliminate leakage current caused by the PN junctions on the side. As for the specific processing procedure, the reagents used can refer to the prior art and are not specifically limited here. It should be noted that the first doped oxide layer formed on the second surface 11 and the side surface 12 is also removed at this time. While cleaning the PN junctions on the second surface 11 and the side surface 12, the borosilicate glass layer remaining in the first non-electrode region 101 of the first surface 10 is also cleaned to facilitate the subsequent secondary texturing process.

[0107] Next, a tunneling layer 3 and a doped conductive layer 4 are deposited on the edge region of the first surface 10 and the second surface 11; a second doped oxide layer is formed on the doped conductive layer 4; wherein the semiconductor substrate 1 and the doped conductive layer 4 located in the first electrode region 100 have the same conductivity type. For the first surface 10 of the semiconductor substrate 1, the tunneling layer 3 and the doped conductive layer 4 are disposed on the first doped layer or the first non-electrode region 101 located in the edge region.

[0108] For example, a tunneling layer 3 and a doped conductive layer 4 are sequentially grown on the second surface 11, and the tunneling layer 3 and the doped conductive layer 4 are deposited around the edge region of the first surface 10. Alternatively, the tunneling layer 3 and the doped conductive layer 4 are sequentially grown on the edge region of the first surface 10 and on the second surface 11. Simultaneously, a second doped oxide layer is grown on the doped conductive layer 4. During subsequent processing of the solar cell, the second doped oxide layer provides protection, reducing the risk of etching the second electrode region 110 and ensuring the quality of the solar cell.

[0109] As one possible implementation method, there are three possible implementation methods for depositing the doped conductive layer 4: LPCVD (Low Pressure Chemical Vapor Deposition) double-sided deposition of the doped conductive layer, LPCVD single-sided deposition of the doped conductive layer, and PECVD (Plasma Enhanced Chemical Vapor Deposition) deposition of the doped conductive layer 4. Among them, LPCVD double-sided deposition of the doped conductive layer 4 and PECVD deposition of the doped conductive layer 4 can ensure that the doped conductive layers 4 formed on the first side 10 and the second side 11 are consistent, and a uniform texture structure can be formed in the first non-electrode region 101 and the second non-electrode region 111 during subsequent texturing. When the doped conductive layer 4 is deposited on the second surface 11 using LPCVD, the first surface 10 has a wrap-around plating situation, which results in wrap-around plating area and non-wrap-around plating area on the first surface 10. This leads to inconsistent reaction times for subsequent secondary texturing in the wrap-around plating area and non-wrap-around plating area of ​​the first surface 10. By optimizing the additives and formulation, it is possible to ensure that both the wrap-around plating area and non-wrap-around plating area can form a good texture structure, achieving the expected light trapping and passivation effects.

[0110] The material and thickness of the tunneling layer 3 can be set according to actual conditions and are not specifically limited here. For example, the material of the tunneling layer 3 may include one or more of silicon oxide, aluminum oxide, titanium oxide, hafnium dioxide, gallium oxide, tantalum pentoxide, niobium pentoxide, silicon nitride, silicon carbonitride, aluminum nitride, titanium nitride, and titanium carbonitride. The doped conductive layer 4 may be a doped polycrystalline silicon layer, which may be a phosphorus-doped polycrystalline silicon layer, or it may be doped with other substances; no specific limitation is made here. The second doped oxide layer is a phosphorus-silicon glass layer.

[0111] At this point, the aforementioned solar cell fabrication method can be used to fabricate tunneling oxide layer passivated contact cells to meet practical needs. Furthermore, the chemical passivation of the tunneling layer 3 and the field passivation of the doped conductive layer 4 can significantly reduce the recombination degree on the surface of the semiconductor substrate 1. Simultaneously, the tunneling layer 3 can ensure effective tunneling of majority carriers, and the doped conductive layer 4 can significantly improve the conduction performance of photogenerated carriers, thereby increasing the open-circuit voltage and fill factor of the solar cell. When the second surface 11 is stacked with the tunneling layer 3 and the doped conductive layer 4, the tunneling layer 3 and the doped conductive layer 4 form a passivated contact structure. The tunneling layer 3 allows majority carrier electrons to tunnel into the doped conductive layer 4 while blocking minority carrier hole recombination, thus allowing electrons to be collected by the metal during lateral transport in the doped conductive layer 4. This greatly reduces the metal contact recombination current, increases the open-circuit voltage and short-circuit current of the cell, and thus improves the cell efficiency. When a tunneling layer 3 and a doped conductive layer 4 are stacked on the edge region of the first surface 10, the tunneling layer 3 and the doped conductive layer 4 can further passivate the edge region of the first surface 10 and improve the passivation performance of the cell edge.

[0112] Next, the first doped oxide layer and the first doped layer located on the first non-electrode region 101 are irradiated with the first laser, and the second doped oxide layer, the doped conductive layer 4 and the tunneling layer 3 located on the edge region of the first non-electrode region 101 are irradiated with the first laser.

[0113] Specifically, when the first non-electrode region 101 includes an edge region and a middle region, irradiating the first doped oxide layer and the first doped layer located on the first non-electrode region 101 with the first laser includes irradiating the first doped oxide layer and the first doped layer located on the edge region and the middle region of the first non-electrode region 101 with the first laser.

[0114] The following describes one possible approach: using a first laser to irradiate the first doped oxide layer and the first doped layer located on the first non-electrode region 101, and using the first laser to irradiate the second doped oxide layer, the doped conductive layer 4, and the tunneling layer 3 located on the edge region of the first non-electrode region 101. It should be noted that the following description is for understanding purposes only and is not intended to be specific.

[0115] A first laser process is used to irradiate the first doped oxide layer located in the first non-electrode region 101, and the first laser process is also used to irradiate the second doped oxide layer located in the edge region of the first non-electrode region 101. The first laser treatment is deep enough to ensure that the first doped oxide layer and the first doped layer in the middle region of the first non-electrode region 101, as well as the second doped oxide layer, the doped conductive layer, the tunneling layer, the first doped oxide layer, and the first doped layer in the edge region of the first non-electrode region 101, can be completely removed during the subsequent cleaning process. For example, the first laser irradiation damages the doped silicon glass layer located in the first non-electrode region 101, including the borosilicate glass layer and / or the phosphosilicate glass layer, reducing the protective effect of the doped silicon glass layer on the first non-electrode region 101. The laser used in the first laser process can be any of red, green, or violet light. A high-energy laser beam of a specific wavelength emitted by the laser acts on the doped silicon glass layer. The doped silicon glass layer absorbs the high-energy laser, causing the atoms within it to gain energy and undergo vibrations, migrations, and other movements. This breaks the chemical bonds between the atoms, thereby disrupting the internal structure of the doped silicon glass layer and making it porous. Alternatively, at very high laser energies, the doped silicon glass layer may melt and vaporize within a short time, eventually evaporating and being removed. Regardless of whether the doped silicon glass layer is removed or becomes porous, its protective effect on the first non-electrode region 101 is significantly reduced. During subsequent alkaline cleaning, due to insufficient protection of the doped silicon glass layer, the alkali can corrode to the semiconductor substrate 1.

[0116] For example, after irradiating the first doped oxide layer on the first non-electrode region 101 and the second doped oxide layer on the edge region of the first non-electrode region 101 with a first laser, the first doped layer on the first non-electrode region 101 is removed using an alkaline texturing formula. At this time, only the first doped layer of the first electrode region 100 is retained, and the doping concentration at the corresponding position of the first electrode region 100 is greater than the doping concentration at the corresponding position of the first non-electrode region 101. Since the second doped oxide layer in the edge region and the first doped oxide layer in the middle region of the first non-electrode region 101 are both irradiated by the first laser, they can be removed during the cleaning process, and the surface of the semiconductor substrate 1 corresponding to the first non-electrode region 101 is exposed after processing, increasing the dimensional consistency of the texture structure of the edge region and the middle region of the first non-electrode region 101 in the subsequent texturing process.

[0117] By reducing the doping concentration of the first non-electrode region 101, the high-concentration area on the front side of the solar cell is reduced, mitigating recombination issues on the semiconductor substrate 1 surface caused by high doping concentration and increasing the open-circuit voltage of the cell. Simultaneously, the first doped layer of the first electrode region 100 is retained to ensure a low contact resistance between the electrode and the first doped layer, reducing the cell's series resistance and improving the fill factor, thereby increasing the efficiency of the solar cell. Since the first non-electrode region 101 is not obstructed by grid lines, it focuses on light-trapping and passivation performance on the front side of the cell, while the first electrode region 100 focuses on contact and passivation performance. Based on the functional differences between the first electrode region 100 and the first non-electrode region 101, the first non-electrode region 101 needs to balance light-trapping performance and the passivation performance of the passivation layer coating. In other words, after removing the first doped oxide layer on the first non-electrode region 101, the doping concentration within the first non-electrode region 101 is zero. That is, the PN junction in the first non-electrode region 101 is removed, which on the one hand effectively reduces the recombination level in the first non-electrode region 101 in the first surface 10 and improves the open-circuit voltage of the cell. At the same time, the first electrode region 100 can be highly doped, which improves the contact resistance between the electrode and the first doped layer in the first electrode region 100, reduces the series resistance of the cell, and improves the fill factor. On the other hand, the surface with a lower doping concentration in the first non-electrode region 101 can reduce the impact on the passivation of the passivation layer field effect, improve the passivation performance of the solar cell surface, and comprehensively improve the efficiency of the solar cell.

[0118] In some embodiments, see Figure 1 The width W1 of the first non-electrode region 101 is greater than or equal to 200 μm and less than or equal to 800 μm. For example, the width W1 of the first non-electrode region 101 can be 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, 500 μm, 550 μm, 600 μm, 650 μm, 700 μm, 750 μm or 800 μm, etc.

[0119] In some embodiments, the depth of corrosion of the first non-electrode region 101 is greater than or equal to 1 μm and less than or equal to 5 μm. For example, the depth can be 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, or 5 μm, etc.

[0120] It should be noted that, since the film structure of the edge region and the middle region of the first non-electrode region 101 are different, the laser action time in the edge region and the middle region can be different, so that the film depth in the edge region is larger, ensuring that the film on the surface of the first non-electrode region 101 can be completely removed in the subsequent wet process.

[0121] Next, the second laser is used to irradiate the second doped oxide layer, the doped conductive layer 4 and the tunneling layer 3 located on the second non-electrode region 111.

[0122] For example, a second laser process is used to irradiate the second doped oxide layer located in the second non-electrode region 111, that is, to perform laser patterning on the second doped oxide layer, with the second laser irradiating the second non-electrode region 111. Through high-energy laser irradiation, the laser acts on the phosphosilicate glass layer for a short time, causing the phosphosilicate glass layer to be modified, loosened, or vaporized, reducing the protective capability of the phosphosilicate glass layer located in the second non-electrode region 111. This ensures that a reaction rate gradient is formed during subsequent alkaline etching, allowing the second non-electrode region 111 to be etched as required, while the second electrode region 110 remains unaffected due to the protection of the phosphosilicate glass layer. In subsequent processing, the doped conductive layer 4 located in the second electrode region 110 is protected by the phosphosilicate glass layer and will not be etched by the alkaline agent; however, because the phosphosilicate glass layer located in the second non-electrode region 111 is damaged, the doped conductive layer 4 located in the second non-electrode region 111 is etched by the alkaline agent, and the alkaline agent further etches downwards into the tunneling layer 3 and the semiconductor substrate 1. At this point, the tunneling layer 3 and the doped conductive layer 4 located in the second electrode region 110 form a conductive contact layer, which corresponds one-to-one with the electrode. The doped conductive layer 4 located in the second non-electrode region 111 on the second surface 11 is removed, effectively reducing parasitic absorption and increasing the battery current, while the doped conductive layer 4 in the second electrode region 110 is retained to prevent the slurry from corroding the semiconductor substrate 1 during metallization, thereby improving the battery fill factor.

[0123] For example, the laser wavelengths in the first laser process and the second laser process are greater than or equal to 300 nm and less than or equal to 1200 nm. For instance, the laser wavelength can be 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1000 nm, 1100 nm, or 1200 nm, etc. The wavelengths of the first laser in the first laser process and the second laser in the second laser process can be the same or different.

[0124] The width W2 of the second non-electrode region 111 is greater than or equal to 250 μm and less than or equal to 800 μm. For example, the width W2 of the second non-electrode region 111 can be 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, 500 μm, 550 μm, 600 μm, 650 μm, 700 μm, 750 μm or 800 μm, etc.

[0125] In some embodiments, the laser power of the first laser and the second laser ranges from 1W to 50W. For example, the laser power can be 1W, 5W, 10W, 15W, 20W, 25W, 30W, 35W, 40W, 45W, or 50W. The scanning speed of the first laser and the second laser ranges from 5m / s to 40m / s. For example, the scanning speed range of the first laser and the second laser is 5m / s, 10m / s, 15m / s, 20m / s, 25m / s, 30m / s, 35m / s, or 40m / s. The first laser and the second laser represent two process steps. The specific laser power and scanning speed can be the same or different and should be adjusted according to the actual process conditions. No special limitations are made here.

[0126] Next, see Figure 1 After the first laser and second laser irradiation processes, a secondary texturing process is performed to form a second texture structure 103 on the first non-electrode region 101, and at the same time, a third texture structure 112 is formed in the second non-electrode region 111; the size uniformity of the second texture structure 103 is greater than the size uniformity of the third texture structure 112.

[0127] Based on the preceding description, see [link / reference]. Figure 1 Since the first doped oxide layer and the first doped layer in the middle region of the first non-electrode region 101, and the first doped oxide layer, the first doped layer, the second doped oxide layer, the doped conductive layer 4 and the tunneling layer 3 in the edge region are removed, the semiconductor substrate 1 located in the first non-electrode region 101 is treated with a texturing solution (e.g., a mixed solution of sodium hydroxide solution and texturing additive) to form a second textured structure 103 on the first non-electrode region 101.

[0128] See Figure 1 As described above, the destruction of the phosphosilicate glass layer in the second non-electrode region 111 leads to the corrosion of the doped conductive layer 4 in the second non-electrode region 111 by the alkaline agent. The alkaline agent further corrodes the tunneling layer 3 and the semiconductor substrate 1 downwards. When the alkaline agent corrodes the semiconductor substrate 1 within the second non-electrode region 111, a third textured structure 112 is formed in the second non-electrode region 111. Compared to the second non-electrode region 111 without a textured structure, the reflectivity of the second non-electrode region 111 is significantly reduced. Combined with optimized passivation processes, the battery efficiency remains unaffected, thus improving the battery's bifaciality.

[0129] In the process of achieving a lower doping concentration in the first doped layer than in the second doped layer, a textured structure is first prepared, and then the doping concentration in the first non-electrode region 101 is reduced by etching the first doped layer. This process destroys the textured structure of the first non-electrode region 101. However, for the light-trapping requirements of solar cells, the first non-electrode region 101 on the light-receiving surface still needs to have a textured structure that meets the structural requirements. Therefore, a second textured structure 103 and a third textured structure 112 are prepared in a secondary texturing process. The second textured structure 103 and the third textured structure 112 can be prepared in the same process step, simplifying the cell manufacturing process, increasing production capacity, and saving production costs. In addition, the differentiated setting of the above-mentioned textured structure can reduce the degree of etching in the second non-electrode region 111 during the preparation process, reduce the weight loss of the solar cell caused by etching during the preparation process, and ensure the mechanical strength of the solar cell.

[0130] The above-mentioned "secondary texturing process to form a second texture structure 103 on the first non-electrode region 101" is performed after the step of "depositing a tunneling layer 3 and a doped conductive layer 4 on the edge region of the first surface 10 and the second surface 11; and forming a second doped oxide layer on the doped conductive layer 4". At this time, the surface difference between the edge region near the semiconductor substrate 1 and the middle region of the first non-electrode region 101 before texturing can be reduced, thereby reducing the difference of the second texture structure 103 formed on the first non-electrode region 101 after texturing.

[0131] As one possible implementation, see Figure 1 As the alkaline agent corrodes downwards the semiconductor substrate 1 located in the second non-electrode region 111, a portion of the semiconductor substrate 1 located in the second non-electrode region 111 is corroded away. At this time, along the thickness direction A of the semiconductor substrate, the top surface of the second non-electrode region 111 is higher than the top surface of the second electrode region 110.

[0132] In some embodiments, along the thickness direction of the semiconductor substrate 1, the distance L2 between the top surface of the second electrode region 110 and the top surface of the second non-electrode region 111 is greater than or equal to 2 μm and less than or equal to 6 μm. For example, the distance L2 between the top surface of the second electrode region 110 and the top surface of the second non-electrode region 111 can be 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, 5.5 μm, or 6 μm, etc.

[0133] It should be noted that the top surface of the second non-electrode region 111 is composed of the vertices of multiple third texture structures 112. Since the sizes of different third texture structures 112 are different, the top surface of the second non-electrode region 111 here is a plane composed of the vertices of most of the third texture structures 112 on the second non-electrode region 111. The proportion of most of the third texture structures 112 in the second non-electrode region 111 can be flexibly selected according to the actual situation.

[0134] As one possible implementation, the secondary texturing process includes: placing the semiconductor substrate 1, after undergoing the first laser and second laser irradiation processes, into a first etching tank for secondary texturing. The first etching tank contains an alkaline solution and a texturing additive. The temperature of the first etching tank is 60°C to 85°C, the concentration of the alkaline solution is 0.2% to 6%, and the secondary texturing time is 2 min to 8 min. For example, the temperature of the first etching tank can be 60°C, 65°C, 70°C, 75°C, 80°C, 82°C, or 85°C, etc. The concentration of the alkaline solution can be 0.2%, 1%, 1.2%, 2%, 2.5%, 3%, 3.5%, 4%, 4.5%, 5%, 5.5%, or 6%, etc. The secondary texturing time can be 2 min, 2.5 min, 3 min, 3.5 min, 4 min, 4.5 min, 5 min, 5.5 min, 6 min, 6.5 min, 7 min, 7.5 min, or 8 min, etc. It should be noted that the time for the above-mentioned secondary texturing process includes the cleaning time for the semiconductor substrate 1 and the etching time for the semiconductor substrate 1.

[0135] In one alternative approach, see Figure 1 The first texture structure 102, the second texture structure 103, or the third texture structure 112 is a pyramid-shaped structure. For a description of the dimensions of the first texture structure 102 and the second texture structure 103, please refer to the first aspect; it will not be repeated here.

[0136] As one possible implementation, see Figure 1 When forming the second texture structure 103, the alkaline texturing formula is used to etch the semiconductor substrate 1 located in the first non-electrode region 101 downwards. At this time, along the thickness direction A of the semiconductor substrate 1, the first electrode region 100 is higher than the first non-electrode region 101.

[0137] In some embodiments, along the thickness direction of the semiconductor substrate 1, the distance between the first electrode region 100 and the first non-electrode region 101 is greater than or equal to 2 μm and less than or equal to 7 μm. See also Figure 1The distance L1 between the first electrode region 100 and the first non-electrode region 101 can be the distance between the top surface of the first electrode region 100 and the top surface of the first non-electrode region 101, or the distance between the bottom surface of the first electrode region 100 and the bottom surface of the first non-electrode region 101, or the distance between the bottom surface of the first electrode region 100 and the top surface of the first non-electrode region 101, or the distance between the top surface of the first electrode region 100 and the bottom surface of the first non-electrode region 101. For example, the distance L1 between the top surface of the first electrode region 100 and the top surface of the first non-electrode region 101 can be 2μm, 2.5μm, 3μm, 3.5μm, 4μm, 4.5μm, 5μm, 5.5μm, 6μm, 6.5μm, or 7μm, etc.

[0138] It is worth noting that the top surface of the first electrode region 100 is composed of the vertices of multiple first texture structures 102. Since the sizes of different first texture structures 102 vary, this top surface is a plane formed by the vertices of most of the first texture structures 102 on the first electrode region 100. The proportion of most of the first texture structures 102 in the first electrode region 100 can be flexibly selected according to the actual situation. Similarly, the top surface of the first non-electrode region 101 is composed of the vertices of multiple second texture structures 103.

[0139] Next, see Figure 1 A passivation layer 5 is formed on the doped conductive layer 4 and on the first surface 10 and the second surface 11 of the semiconductor substrate 1.

[0140] As for the material and thickness of the passivation layer 5, these can be set according to actual conditions and are not specifically limited here. For example, the material of the passivation layer 5 may include one or more of silicon nitride, hydrogen-containing silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, zinc oxide, and hafnium dioxide.

[0141] As one possible implementation, the passivation layer 5 can be a stack of multiple films, such as a stack of aluminum oxide and silicon nitride layers.

[0142] In some embodiments, an aluminum oxide passivation layer 50 is grown on the doped conductive layer 4 and on the first surface 10 and the second surface 11 of the semiconductor substrate 1 using atomic layer deposition. Then, a silicon nitride passivation layer 51 is deposited on the aluminum oxide passivation layer 50 located on the doped conductive layer 4 and on the first surface 10 and the second surface 11 using plasma enhanced chemical vapor deposition (PECVD).

[0143] The aforementioned passivation layer 5 can passivate the surface of the semiconductor substrate 1, reduce surface recombination, and improve the open-circuit voltage and fill factor. At the same time, the silicon nitride passivation layer 51 can protect the semiconductor substrate 1 and reduce contamination and mechanical damage.

[0144] Next, electrodes are formed on the passivation layer 5, with the electrodes located in the first electrode region 100 and the second electrode region 110, respectively. That is, the first electrode 6 is fabricated in the first electrode region 100 of the first surface 10 of the semiconductor substrate 1 using a printing apparatus, and the second electrode 7 is fabricated in the second electrode region 110 of the second surface 11 of the semiconductor substrate 1.

[0145] For example, the semiconductor substrate 1 is metallized, and electrodes are formed by methods such as screen printing or electroplating. The paste used to fabricate the first electrode 6 and the second electrode 7 can be a silver alloy, a silver-copper alloy, a copper alloy, a nickel alloy, etc. The paste is solidified by a low-temperature sintering process, and then the hydrogen passivation effect is enhanced by light injection. Finally, a good ohmic contact is formed using laser-assisted sintering contact technology (LECO), thus completing the production of the solar cell.

[0146] In summary, compared with existing technologies, the solar cell manufacturing method provided in this application has a shorter process flow, achieves the same effect, and improves the feasibility of mass production.

[0147] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0148] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A solar cell, characterized by, Comprising: a semiconductor substrate comprising a first surface and a second surface opposite to the first surface; the first surface comprises a first electrode region and a first non-electrode region; the first surface is a light-receiving surface, and the second surface is a back surface; a first doped layer disposed on the first electrode region; a second doped layer disposed on the first non-electrode region; the first doped layer has a higher doping concentration than the second doped layer; a surface of the first electrode region has a first texture structure, and the first non-electrode region has a second texture structure; the second surface comprises a second electrode region and a second non-electrode region; the second non-electrode region has a third texture structure, and the second texture structure has a higher dimensional consistency than the third texture structure; a surface of the second electrode region comprises a tower base structure; the first texture structure has a higher dimensional consistency than the third texture structure; the first texture structure, the second texture structure, or the third texture structure is a pyramid structure; in a thickness direction of the semiconductor substrate, the first electrode region is higher than the first non-electrode region; a distance between the first electrode region and the first non-electrode region ranges from 2 μm to 7 μm; in the thickness direction of the semiconductor substrate, the second non-electrode region is higher than the second electrode region; a distance between the second electrode region and the second non-electrode region ranges from 2 μm to 6 μm.

2. The solar cell according to claim 1, characterized in that, when the first texture structure is a pyramid structure, a tower height of the first texture structure ranges from 1 μm to 4 μm.

3. The solar cell of claim 1, wherein when the first texture structure is a pyramid structure, a base size of the first texture structure ranges from 1 μm to 5 μm.

4. The solar cell of claim 1, wherein when the second texture structure is a pyramid structure, a tower height of the second texture structure ranges from 1 μm to 4 μm.

5. The solar cell of claim 1, wherein when the second texture structure is a pyramid structure, a base size of the second texture structure ranges from 1 μm to 5 μm.

6. The solar cell of claim 1, wherein a reflectivity of the first electrode region where the first texture structure is located is higher than a reflectivity of the first non-electrode region where the second texture structure is located.

7. The solar cell of claim 1, wherein the first electrode region and / or the second electrode region comprises a current collecting electrode region and a busbar electrode region; an extension direction of the current collecting electrode region is inconsistent with an extension direction of the busbar electrode region; a width of the busbar electrode region is larger than a width of the current collecting electrode region.

8. The solar cell of claim 1, wherein, in the thickness direction of the semiconductor substrate, a projection of the first non-electrode region on the second surface at least partially overlaps with a projection of the second non-electrode region on the second surface.

9. A photovoltaic module, characterized by The photovoltaic module comprises: a cell string comprising a plurality of interconnects and a plurality of solar cells according to any one of claims 1 to 8; the interconnects are used to connect the plurality of solar cells together to form the cell string; an encapsulation layer used to cover a surface of the cell string.

10. A method for manufacturing a solar cell, characterized in that, A method for manufacturing the solar cell according to any one of claims 1 to 8; the method for manufacturing the solar cell comprises: A semiconductor substrate is provided; the semiconductor substrate has opposite first and second surfaces; the first surface is a light-receiving surface, and the second surface is a back surface; the first and second surfaces are subjected to a texturing process to form a first texture structure; the first surface includes a first electrode region and a first non-electrode region, and the second surface includes a second electrode region and a second non-electrode region; The first surface of the semiconductor substrate is subjected to a diffusion process to form a first doped layer and a first doped oxide layer formed on the first doped layer; A tunneling layer and a doped conductive layer are deposited on the edge region of the first surface and the second surface; the doped conductive layer has a second doped oxide layer formed thereon; The first doped oxide layer and the first doped layer located on the first non-electrode region are irradiated with a first laser, and the second doped oxide layer, the doped conductive layer, and the tunneling layer located on the edge region of the first non-electrode region are irradiated with the first laser; The second doped oxide layer, the doped conductive layer, and the tunneling layer located on the second non-electrode region are irradiated with a second laser; After the first and second laser irradiation processes, a secondary texturing process is performed to form a second texture structure on the first non-electrode region and a third texture structure on the second non-electrode region; the size consistency of the second texture structure is greater than that of the third texture structure; and the surface of the second electrode region includes a tower base structure.

11. The method of claim 10, wherein: the first laser has a power of 1 W to 50 W and a scanning speed of 5 m / s to 40 m / s; the second laser has a power of 1 W to 50 W and a scanning speed of 5 m / s to 40 m / s; the power and scanning speed of the first and second lasers are different.

12. The method of producing a solar cell according to claim 10, wherein The secondary texturing process includes: the semiconductor substrate after the first and second laser irradiation processes is placed in a first etching tank for the secondary texturing process; the first etching tank contains an alkaline solution and a texturing additive, has a temperature of 60°C to 85°C, and the alkaline solution has a concentration of 0.2% to 6%; and the secondary texturing process has a time of 2 min to 8 min.

13. The method of producing a solar cell according to claim 10, wherein After the first and second laser irradiation processes, a secondary texturing process is performed to form a second texture structure on the first non-electrode region and a third texture structure on the second non-electrode region, and the method further includes: forming a passivation layer on the doped conductive layer and on the first and second surfaces of the semiconductor substrate; forming an electrode on the passivation layer, the electrode being located in the first and second electrode regions, respectively.

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