Display substrate, manufacturing method thereof and display device

Abstract

The invention provides a display substrate, a manufacturing method thereof and a display device, the display substrate comprises a substrate, the substrate comprises a display area and a peripheral area located on the periphery of the display area, and the peripheral side of the display area comprises a binding side and at least two non-binding sides except the binding side; the packaging layer is positioned on the substrate; at least on the binding side, the packaging layer has a first thickness H1 in a direction perpendicular to the substrate; at least on one non-binding side, the packaging layer has a second thickness H2 in the direction perpendicular to the substrate; wherein H2 is greater than H1. According to the display substrate, the manufacturing method of the display substrate and the display device, the packaging reliability can be improved, and the color cast problem can be solved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a manufacturing method thereof, and a display device. Background Art

[0002] Taking OLED (Organic Light Emitting Diode) display products as an example, in some special application scenarios, the product size is relatively small. However, if the display area of ​​the display product is too small, the encapsulation layer film properties may be abnormal, affecting product quality. Summary of the Invention

[0003] In order to solve at least one technical problem in the above-mentioned prior art, embodiments of the present disclosure provide a display substrate, a manufacturing method thereof, and a display device.

[0004] The technical solutions provided by the embodiments of the present disclosure are as follows:

[0005] In a first aspect, an embodiment of the present disclosure provides a display substrate, comprising:

[0006] A base substrate, comprising a display area and a peripheral area located outside the display area, wherein the peripheral sides of the display area include a binding side and at least two non-binding sides except the binding side; and

[0007] A packaging layer located on the substrate; wherein,

[0008] At least on the binding side, the encapsulation layer has a first thickness H1 in a direction perpendicular to the substrate; at least on one of the non-binding sides, the encapsulation layer has a second thickness H2 in a direction perpendicular to the substrate; wherein H2 is greater than H1.

[0009] Exemplarily, the difference between H2 and H1 is 0.85±0.1 mm.

[0010] Exemplarily, at least two of the non-binding sides include a first side located opposite the binding side, and a second side and a third side located between the binding side and the first side and opposite to each other, the second side includes a first area close to the first side and a second area close to the binding side, and the third side includes a third area close to the first side and a fourth area close to the binding side; wherein, the difference between the thickness of the encapsulation layer in the second area and the fourth area and the first thickness H1 is within a threshold, and the thickness in the first area and the third area is greater than the first thickness H1 and less than or equal to the second thickness H2.

[0011] Exemplarily, there is a first junction position between the first region and the second region, and a second junction position between the third region and the fourth region, wherein the thickness of the encapsulation layer perpendicular to the base substrate is configured to gradually increase from the first junction position to the first side, and gradually increase from the second junction position to the first side.

[0012] Exemplarily, on the binding side, the edge of the encapsulation layer has a smoothly transitioned arc structure; at least on the non-binding side, the first region and the third region, the edge of the encapsulation layer has an undercut structure.

[0013] Exemplarily, the encapsulation layer includes a first sub-encapsulation layer and a second sub-encapsulation layer covering a side of the first sub-encapsulation layer facing away from the substrate; wherein,

[0014] At least on one of the non-binding sides, the first sub-packaging layer has a first packaging boundary line, the second sub-packaging layer has a second packaging boundary line, and the distance from the first packaging boundary line to the boundary of the display substrate is a first distance; the distance from the second packaging boundary line to the boundary of the display substrate is a second distance, and the first distance is greater than the second distance.

[0015] Exemplarily, the difference between the first distance and the second distance is 5±1 microns.

[0016] Exemplarily, the edge of the first sub-package layer includes a first sloped portion; the edge of the second sub-package layer includes a second sloped portion, and the edge of the second sub-package layer has a groove in the second portion at a position close to the first portion to form the undercut structure.

[0017] Exemplarily, the slope angle of the first portion is greater than the slope angle of the second portion.

[0018] Exemplarily, the encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer stacked in sequence along a direction away from the base substrate; wherein the encapsulation layer at least partially covers the peripheral area, and in the peripheral area, the encapsulation layer only includes the first inorganic encapsulation layer and the second inorganic encapsulation layer.

[0019] In a second aspect, an embodiment of the present disclosure provides a display device comprising the display substrate as described above.

[0020] In a third aspect, an embodiment of the present disclosure provides a method for manufacturing a display substrate, for manufacturing the display substrate as described above, the method comprising:

[0021] Providing a motherboard not covered with an encapsulation layer, the motherboard having multiple display screen areas, the display screen area including a display region and a peripheral region located outside the display region, the four sides of the display region including a binding side and at least two non-binding sides other than the binding side, the display screen area also including a target encapsulation area, the target encapsulation area covering the display area of ​​the display screen area, and the target encapsulation area having a target encapsulation boundary line around the peripheral contour of the display region;

[0022] forming a patterned encapsulation layer on the motherboard, wherein the pattern of the encapsulation layer includes a plurality of encapsulation units corresponding to and covering the respective display screen areas, wherein, on at least one of the non-binding sides, at least a portion of each of the encapsulation units exceeds a target encapsulation boundary line of the corresponding display screen area, and at least another portion does not exceed the target encapsulation boundary line of the corresponding display screen area, and at least on the binding side, a boundary of the encapsulation unit coincides with the target encapsulation boundary line, so that the encapsulation unit includes a reserved area and a removed area, wherein a contour of the reserved area matches a contour shape of the target encapsulation area;

[0023] The packaging unit is patterned to remove the removal area.

[0024] Exemplarily, the step of forming a patterned encapsulation layer on the motherboard includes:

[0025] A patterned packaging layer is formed on the motherboard by using a first mask through vapor deposition.

[0026] Exemplarily, at least two of the non-binding sides include a first side located opposite the binding side, and a second side and a third side located between the binding side and the first side and arranged opposite to each other, wherein the packaging unit exceeds the target packaging boundary line of the corresponding display screen area at least on the first side.

[0027] Exemplarily, the second side includes a first area close to the first side and a second area close to the binding side, and the third side includes a third area close to the first side and a fourth area close to the binding side, wherein, on the first side, the first area and the third area, the packaging unit at least partially exceeds the target packaging boundary line of the corresponding display screen area, and on the binding side, the third area and the fourth area, the boundary of the packaging unit coincides with the target packaging boundary line.

[0028] Exemplarily, the first region includes a first arc-shaped region in the second side that smoothly transitions to the first side, and the third region may include a third arc-shaped region in the third side that smoothly transitions to the first side, wherein in the first arc-shaped region, the third arc-shaped region and the first side, the boundaries of the packaging unit all exceed the target packaging boundary line.

[0029] Exemplarily, patterning the packaging unit to remove the removal area includes: patterning the packaging unit to remove the removal area by etching.

[0030] Exemplarily, the encapsulation layer includes a first sub-encapsulation layer and a second sub-encapsulation layer covering a side of the first sub-encapsulation layer facing away from the motherboard, and the reserved area includes a first reserved pattern located on the first sub-encapsulation layer and a second reserved pattern located on the second sub-encapsulation layer;

[0031] The patterning process of the packaging unit by etching specifically includes:

[0032] Through a first etching process, the second sub-encapsulation layer is etched using a second mask to remove only the removal area in the second sub-encapsulation layer to obtain a second retained pattern;

[0033] The first sub-encapsulation layer is etched using a third mask through a second etching process to remove only the removal area in the first sub-encapsulation layer, thereby obtaining the first retained pattern.

[0034] Exemplarily, the patterning of the packaging unit to remove the removal area further includes:

[0035] On a side of the packaging unit that extends beyond the target packaging boundary line, the first retention pattern includes a first packaging boundary line that extends outward by a third distance relative to the target packaging boundary line in a direction deviating from the target packaging area, and the second retention pattern includes a second packaging boundary line that extends outward by a fourth distance relative to the first packaging boundary line in a direction deviating from the target packaging area.

[0036] Exemplarily, on the side of the packaging unit that extends beyond the target packaging boundary line, the edge of the first retention pattern includes a first sloped portion; the edge of the second retention pattern includes a second sloped portion, and the edge of the second sub-packaging layer has a groove at a position of the second portion close to the first retention pattern to form an undercut structure.

[0037] Exemplarily, the motherboard further has a target cutting line surrounding the peripheral contour of the display screen area;

[0038] The patterning of the packaging unit to remove the removal area specifically includes:

[0039] On the side of the packaging unit that exceeds the target packaging boundary line, the removal area includes an inner edge that intersects with the first retained pattern, and an outer edge that expands outward relative to the inner edge and relative to the target packaging boundary line in a direction deviating from the target packaging area, wherein the outer edge expands outward relative to the target cutting line in a direction deviating from the target packaging area.

[0040] Exemplarily, the outer edge includes a first outer edge line located on the first sub-packaging layer and a second outer edge line located on the second sub-packaging layer, the first outer edge line extends outward by a fifth distance relative to the target cutting line, the second outer edge line extends outward by a sixth distance relative to the target cutting line, the fifth distance is greater than or equal to 10 microns, and the sixth distance is greater than or equal to 20 microns.

[0041] Illustratively, on the side where the boundary of the packaging unit coincides with the target packaging boundary line, the edge of the first retention pattern expands outward relative to the edge of the second retention pattern in a direction deviating from the target packaging area, and the edges of the first retention pattern and the second retention pattern cooperate with each other to make the edge of the packaging unit present a smoothly transitioned arc structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 Indicates the test results of TEG test on the display substrate in the related art;

[0043] Figure 2 A schematic diagram showing the structure of a motherboard in step S01 of the method for manufacturing a display substrate provided by an embodiment of the present disclosure;

[0044] Figure 3 A schematic diagram showing the division of the areas surrounding the display area of ​​a display substrate in some embodiments of the present disclosure;

[0045] Figure 4 One of the schematic diagrams of the motherboard structure in step S02 of the method for manufacturing a display substrate provided in an embodiment of the present disclosure;

[0046] Figure 5 A schematic diagram showing the structure of a motherboard in step S03 of the method for manufacturing a display substrate provided by an embodiment of the present disclosure;

[0047] Figure 6 Indicates a layout method of the display screen area on a motherboard;

[0048] Figure 7 One of the structural schematic diagrams of the display substrate finally obtained in the method for manufacturing the display substrate provided in the embodiment of the present disclosure;

[0049] Figure 8 Indicates that the encapsulation layer is Figure 7 Cross-sectional view along the F-F' direction;

[0050] Figure 9 Indicates that the encapsulation layer is Figure 7 A-A' sectional view;

[0051] Figure 10 A second schematic diagram showing the motherboard structure of step S02 in the method for manufacturing a display substrate provided by an embodiment of the present disclosure;

[0052] Figure 11 express Figure 10 The position indicated by the center line frame G is a schematic diagram of the local structure in step S03;

[0053] Figure 12 The second structural schematic diagram shows the display substrate finally obtained in the method for manufacturing the display substrate provided in the embodiment of the present disclosure. DETAILED DESCRIPTION

[0054] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0055] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0056] As used in the embodiments of the present disclosure, the terms "parallel," "perpendicular," and "identical" include the strict sense of "parallel," "perpendicular," and "identical," as well as "approximately parallel," "approximately perpendicular," and "approximately identical" with respect to a certain tolerance, which, taking into account the tolerances associated with the measurement of a particular quantity (e.g., limitations of the measurement system), means within an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within 3% or 5% of the stated value.

[0057] In addition, in this document, unless otherwise defined, the terms "substantially," "essentially," "approximately," and "about" are used to describe and explain small variations. When used in connection with an event or circumstance, these terms can encompass situations where the event or circumstance occurs exactly, as well as situations where the event or circumstance occurs approximately. For example, when used in connection with a numerical value, these terms can include a range of variation of less than or equal to 10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, less than or equal to ±0.05%. The term "substantially coplanar" can refer to two surfaces being aligned along the same plane within the micrometer range, for example, within 40 μm, 30 μm, 20 μm, 10 μm, or 1 μm.

[0058] It should be understood that in the exemplary embodiments of the present disclosure, when a layer or element is referred to as being on another layer or substrate, the layer or element may be directly on the other layer or substrate, or an intervening layer may exist between the layer or element and the other layer or substrate. "A and B are disposed on the same layer" means that A and B are formed using the same film-forming process to form a film layer for forming a specific pattern, and then the layer structure is formed using the same mask through a single patterning process.

[0059] Before describing in detail the display substrate, the manufacturing method thereof, and the display device provided by the embodiments of the present disclosure, the following description of related technologies is given.

[0060] In related technologies, such as OLED (Organic Light Emitting Diode) display products, small product sizes are often used in some special applications. However, if the display area of ​​a display product is too small, abnormal film properties of the encapsulation layer may occur, affecting product quality.

[0061] The inventors of the present disclosure have found through research that one of the reasons for the above problems is:

[0062] During the display substrate manufacturing process, the encapsulation layer is patterned using openings in a CVD mask. Generally speaking, the size of the openings on the mask determines the size of the encapsulation layer ultimately formed on the display substrate. If the openings on the mask are too small, the film thickness and quality near the edges of the openings will be abnormal.

[0063] The inventors of the present disclosure have found through research that one of the reasons for the above problems is:

[0064] Figure 1 The following is the TEG (Thermoelectric Generator) test result of a display substrate with a size of 8*10mm. Figure 1 The horizontal axis represents the position coordinate point of the display substrate from one edge of the display screen to the other edge of the display screen, and the vertical axis represents the film thickness of the encapsulation layer. Figure 1 As shown, within a certain range (e.g., 1.5mm) from the edge of the mask's opening pattern, the encapsulation layer will have an encapsulation ramp region T. This region gradually decreases in thickness as it moves away from the center of the display panel, resulting in insufficient encapsulation thickness in this region. For example, the actual film thickness in some areas of this region is less than 90% of the designed film thickness, affecting encapsulation reliability. Furthermore, if this insufficient encapsulation thickness extends into the display area (AA), it will cause a more pronounced color shift at the edges of the display area, thus affecting product quality.

[0065] Based on this, the embodiments of the present disclosure provide a display substrate and a manufacturing method thereof, and a display device, which can improve packaging reliability and enhance the quality of display products.

[0066] The present disclosure provides a method for manufacturing a display substrate, comprising the following steps:

[0067] Step S01: Figure 2 As shown, a motherboard 100 not covered with an encapsulation layer is provided. The motherboard 100 has multiple display screen areas 110. The display screen area 110 includes a display area AA and a peripheral area B located outside the display area AA. The four sides of the display area AA include a binding side B1 and at least two non-binding sides B2 other than the binding side B1. The display screen area 110 also includes a target encapsulation area 120. The target encapsulation area 120 covers the display area AA of the display screen area 110. The target encapsulation area 120 has a target encapsulation boundary line 121 around the peripheral side of the display area AA.

[0068] Step S02: Figure 4 and Figure 5As shown, a patterned encapsulation layer 200 is formed on the motherboard 100. The pattern of the encapsulation layer 200 includes a plurality of encapsulation units 210 corresponding to and covering each display screen area 110. On at least one non-bonding side B2, at least a portion of each encapsulation unit 210 extends beyond a target encapsulation boundary line 121 of the corresponding display screen area 110, while at least another portion does not extend beyond the target encapsulation boundary line 121 of the corresponding display screen area 110. Furthermore, on at least the bonding side B1, the boundary of the encapsulation unit 210 coincides with the target encapsulation boundary line 121, such that the encapsulation unit 210 includes a reserved area C and a removed area D, and the outline of the reserved area C matches the outline of the target encapsulation area 120.

[0069] Step S03: Figure 5 and Figure 7 As shown, the encapsulation unit 210 is patterned and the removal area D is removed.

[0070] In the above solution, the target package area 120 may refer to the area on the motherboard 100 that needs to be packaged and covered in theory or in existing designs; similarly, the target package boundary line 121 may refer to the package boundary line on the motherboard 100 in theory or in existing designs. Figure 2 As shown in FIG, the target encapsulation area 120 expands outward relative to the display area AA.

[0071] In the manufacturing method of the display substrate provided in the embodiment of the present disclosure, a first mask plate can be used to form a patterned packaging layer 200 on the motherboard 100. One packaging unit 210 can correspond to one display screen area 110. The opening pattern on the first mask plate can form the pattern of the packaging unit 210. Moreover, on at least one non-binding side B2, at least a portion of each packaging unit 210 exceeds the target packaging boundary line 121 of the corresponding display screen area 110, and at least another portion does not exceed the target packaging boundary line 121 of the corresponding display screen area 110. At least on the binding side B1, the boundary of the packaging unit 210 coincides with the target packaging boundary line 121.

[0072] In this way, for each display area, at least on one non-binding side B2, the corresponding packaging unit 210 will exceed the boundary of the target packaging area 120, and at least on the binding side B1, the boundary of the corresponding packaging unit 210 coincides with the boundary of the target packaging area 120. Compared with the method in the related art where the boundary of the packaging unit and the target packaging area completely coincides on both the packaging side and the non-packaging side, the opening pattern size of the first mask is enlarged. Although the packaging unit 210 formed by the first mask 1 still has a packaging climbing area within a certain range from the opening pattern boundary, However, since the package climbing area is farther away from the display area AA on at least one non-bonding side B2, the risk of insufficient package thickness in the package climbing area entering the display area AA is reduced. Furthermore, since the bonding area exists on the bonding side B1, the package unit 210 generally does not overlap the package area. If the package unit 210 extends beyond the boundary of the target package area 120 on the bonding side B1, the bonding area would be adversely affected during patterning of the package unit 210. Therefore, at least on the bonding side B1, the package unit 210 can overlap with the boundary of the target package area 120. Since the package unit 210 can overlap with the boundary of the target package area 120, while at least a portion of the package unit 210 extends beyond the boundary of the target package area 120 on at least one non-bonding side B2, the package thickness of the package unit 210 on at least one non-bonding side B2 is greater than the package thickness on the bonding side.

[0073] Specifically, Figure 7 FIG. 1 is a schematic diagram showing the structure of a display substrate obtained by using the display substrate manufacturing method provided by an embodiment of the present disclosure. Figure 7 As shown, the display substrate includes a base substrate 100 ′ and an encapsulation layer 200 ′ located on the base substrate 100 ′.

[0074] The display substrate may refer to a single screen obtained by cutting the motherboard 100 along a predetermined cutting line. The base substrate 100' may refer to the motherboard 100 corresponding to the single screen after cutting. The encapsulation layer 200' may refer to the encapsulation unit 210 on the single screen obtained after cutting.

[0075] The base substrate 100' includes a display area AA and a peripheral area B located outside the display area AA. The four sides of the display area AA include a binding side B1 and at least two non-binding sides B2 other than the binding side B1. At least on the binding side B1, the encapsulation layer 200' has a first thickness H1 in a direction perpendicular to the base substrate 100'. At least on one non-binding side B2, the encapsulation layer 200' has a second thickness H2 in a direction perpendicular to the base substrate 100'. H2 is greater than H1.

[0076] In some embodiments, the difference in film thickness between H2 and H1 is less than 10% of the total thickness of the encapsulation layer. For example, the difference between H2 and H1 can be 0.85±0.1 mm, but is not limited thereto.

[0077] Furthermore, it should be noted that in the above solution, the packaging unit 210 processed in step S02 includes a reserved area C that matches the pattern of the target packaging area 120, and also includes a portion that extends beyond the target packaging area 120. At least a portion of this portion that extends beyond the target packaging area 120 constitutes the removal area D. Then, in step S03, the patterned packaging unit 210 is further patterned to remove the removal area D, while the reserved area C remains and forms the packaging pattern of the encapsulated display area AA.

[0078] In this way, by increasing the size of the opening pattern on the first mask when depositing the encapsulation layer 200, so that the encapsulation unit 210 exceeds the boundary of the target encapsulation area 120 on at least one non-binding side B2, and further removing the excess part on the encapsulation layer 200, the encapsulation pattern in each display screen area 110 is obtained. At least on one non-binding side B2, the encapsulation climbing area with insufficient encapsulation thickness at the edge of the encapsulation layer 200 can be prevented from entering the display area AA, thereby improving the encapsulation reliability and improving the color deviation problem.

[0079] It should be noted that in the above step S02, the patterned encapsulation layer 200 can be formed on the motherboard 100 by chemical vapor deposition (CVD) using a first mask. By designing the opening pattern of the first mask, the deposition area can be precisely controlled. However, this is not limited to this.

[0080] by Figures 2 to 4 As shown in the example, in some embodiments, the at least two non-bonding sides B2 include: a first side B21 located opposite the bonding side B1; and a second side B22 and a third side B23 located between the bonding side B1 and the first side B21 and opposite to each other. The packaging unit 210 extends beyond the target packaging boundary line 121 of the corresponding display screen area 110 on at least the first side B21. The first side B21 is the opposite side of the bonding side B1, and the packaging unit 210 can extend beyond the target packaging boundary line 121 on at least the opposite side of the bonding side B1.

[0081] The display area AA of the display screen area 110 may be a regular or irregular shape such as a rectangle, a circle, an ellipse, or a racetrack. Correspondingly, the target packaging area 120 may be a regular or irregular shape such as a rectangle, a circle, an ellipse, or a racetrack.

[0082] In some exemplary embodiments, Figure 4As shown, the packaging unit 210 at least partially extends beyond the target packaging boundary line 121 of the corresponding display screen area 110 on the first side B21, the second side B22, and the third side B23. In other words, the packaging unit 210 is designed to extend beyond the target packaging boundary line 121 on all sides except the bonding side B1.

[0083] In some embodiments, as Figure 6 As shown, since the layout of a single screen on the motherboard 100 is such that there is sufficient space between two adjacent display screen areas 110 in the first direction Y from the binding side B1 to the first side B21, the distance by which the packaging unit 210 extends beyond the target packaging boundary line 121 on the first side B21 can be greater than the coverage range of the packaging climbing area, thereby ensuring that the packaging climbing area does not enter the display area AA as much as possible; and in the second direction X from the second side B22 to the third side B23, the space between two adjacent display screen areas 110 in the second direction X is limited. Therefore, on the second side B22 and the third side B23, the packaging unit 210 can only partially extend beyond the boundary of the target packaging boundary line 121.

[0084] For example, Figure 4 As shown, the second side B22 includes a first area E1 close to the first side B21 and a second area E2 close to the binding side, and the third side B23 includes a third area E3 close to the first side B21 and a fourth area E4 close to the binding side B1, wherein the packaging unit 210 at least partially exceeds the target packaging boundary line 121 of the corresponding display screen area 110 in the first side B21, the first area E1, and the third area E3, while in the second area E2 and the fourth area E4, the packaging unit 210 may overlap with the target packaging boundary line 121.

[0085] In this way, in the display substrate manufactured based on the above scheme, the packaging unit 210 in the second area E2, the fourth area E4, and the binding side B1 all coincide with the target packaging boundary line 121. Therefore, in the second area E2, the fourth area E4, and the binding side B1, the difference between the thickness of the packaging unit 210 and the thickness of the binding side B1 (i.e., the first thickness H1) is within the threshold, and the packaging unit 210 in the first area E1, the third area E3, and the first side B21 all exceed the target packaging boundary line 121. Therefore, the thickness of the packaging unit 210 in the first area E1, the third area E3, and the first side B21 is greater than the first thickness H1 and less than or equal to the second thickness H2.

[0086] It should be noted that the threshold value can be substantially equal to 0. In other words, the package thickness of the package unit 210 in the second region E2 and the fourth region E4 is substantially the same as the first thickness H1. "Substantially equal to 0" means a range of less than or equal to 10% of 0, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%.

[0087] Specifically, the structure of a single display substrate obtained based on the above solution is as follows: Figure 4 、 Figures 7 to 9 See Figure 4 、 Figures 7 to 9 As shown, in a single display substrate, at least two non-binding sides B2 include a first side B21 located opposite to the binding side B1, and a second side B22 and a third side B23 located between the binding side B1 and the first side B21 and opposite to each other, the second side B22 includes a first area E1 close to the first side B21 and a second area E2 close to the binding side B1, and the third side B23 includes a third area E3 close to the first side B21 and a fourth area E4 close to the binding side B1; wherein, the difference between the thickness of the encapsulation layer 200 in the second area E2 and the fourth area E4 and the first thickness H1 is within a threshold, and the thickness in the first area E1 and the third area E3 is greater than the first thickness H1 and less than or equal to the second thickness H2.

[0088] Furthermore, since there is enough space to extend the package unit 210 on the first side B21, and the package unit 210 only extends beyond the target package boundary lines of the first area E1 and the third area E3 on the second side B22 and the third side B23, the thickness of the package unit 210 perpendicular to the base substrate 100' is:

[0089] At a first boundary position a between the first region E1 and the second region E2, there is a second boundary position b between the third region E3 and the fourth region 34, and the thickness of the encapsulation unit 210 (encapsulation layer 200) in a direction perpendicular to the motherboard 100 (base substrate 100') gradually increases from the first boundary position a to the first side B21, and gradually increases from the second boundary position b to the first side B21.

[0090] For example, Figures 7 to 9As an example, the film thickness H3 of the encapsulation layer 200 at position a on the second side B22 is equal to the film thickness at position b on the bonding side B1 (i.e., first thickness H1), and is less than the film thickness at position c in the first area E1 (i.e., second thickness H2). For example, the film thickness of the encapsulation unit 210 at positions a and b can be 1.7±0.1 mm, and the film thickness at position c can be 0.85±0.1 mm. However, this is not a limitation.

[0091] Furthermore, in step S02, when depositing the encapsulation layer 200, if the opening pattern of the first mask has sharp, right-angled edges, which may cause stress concentration during processing and use, circular arc transitions can effectively disperse the stress. Therefore, in some embodiments, the adjacent two sides of the four sides of the display area 110 are formed into circular arc transitions.

[0092] In some embodiments, Figure 3 and Figure 4 As shown in the example, the first area E1 may include a first arc-shaped area E1' in the second side B22 that smoothly transitions to the first side B21, and the third area E3 may include a third arc-shaped area E3' in the third side B23 that smoothly transitions to the first side B21, wherein in the first arc-shaped area E1', the third arc-shaped area E3' and the first side B21, the boundaries of the packaging unit 210 all exceed the target packaging boundary line 121.

[0093] For example, taking the display screen area 110 as a rectangular shape, as shown in FIG. Figure 4 As shown, the first area E1 may include a first arc-shaped area E1' in the second side B22 that smoothly transitions to the first side B21, the second area E2 may include a second arc-shaped area E2' in the second side B22 that smoothly transitions to the binding side B1, and a first straight area E5 other than the first arc-shaped area E1' and the second arc-shaped area E2'; the third area E3 may include a third arc-shaped area E3' in the third side B23 that smoothly transitions to the first side B21, the second area E2 may include a fourth arc-shaped area E4' in the third side B23 that smoothly transitions to the binding side B1, and a second straight area E6 other than the third arc-shaped area E3' and the fourth arc-shaped area E4'.

[0094] like Figure 4 As shown, in the first curved area E1', the third curved area E3', and the first side B21, the boundaries of the package unit 210 all exceed the target package boundary line 121. In the second curved area E2', the first straight area E5, the fourth curved area E4', the second straight area E6, and the bonding side B1, the boundaries of the package unit 210 are all flush with the target package boundary line 121.

[0095] For example, taking the display screen area 110 as a runway shape, as shown in FIG. Figure 10 As shown, since the display screen area 110 has no right-angled edges, the binding side B1 and the first side B21 opposite to the binding side B1 can be straight lines, and the second side B22 and the third side B23 can be arc-shaped.

[0096] Among them, such as Figure 10 As shown, the first arcuate area E1' may include a portion of the second side B22 extending in a smooth transition to the first side B21, the second arcuate area E2' may include a portion of the second side B22 extending in a smooth transition to the binding side B1, the third arcuate area E3' may include a portion of the third side B23 extending in a smooth transition to the first side B21, and the fourth arcuate area E4' may include a portion of the third side B23 extending in a smooth transition to the binding side B1. Figure 12 It is a schematic structural diagram of the encapsulation layer 200 ′ on a single display substrate obtained after the above step S03 in the racetrack-shaped display screen area 110 .

[0097] It should be noted that the above is merely an exemplary description of the pattern shape of the packaging unit 210. In other embodiments, the pattern of the packaging unit 210 is not limited thereto. It is only necessary to extend at least one side of the packaging unit 210 beyond the target packaging boundary line 121 of the corresponding display area AA to expand the opening pattern size of the first mask.

[0098] In addition, in some exemplary embodiments, the above step S03 specifically includes:

[0099] The encapsulation unit 210 is patterned by etching to remove the removal area D. Unnecessary materials are removed by etching to form the desired encapsulation pattern that ultimately covers the display area AA.

[0100] In some exemplary embodiments, Figure 4 、 Figure 5 、 Figure 6 As shown, the encapsulation layer 200 includes a first sub-encapsulation layer CVD1, and a second sub-encapsulation layer CVD2 covering the side of the first sub-encapsulation layer CVD1 facing away from the motherboard 100. The reserved area C is the encapsulation pattern that ultimately needs to be covered on the display area AA. The reserved area C may include a first retained pattern C1 located on the first sub-encapsulation layer CVD1 and a second retained pattern C2 located on the second sub-encapsulation layer CVD2.

[0101] Exemplarily, the above step S03 specifically includes:

[0102] Step S031: etching the second sub-encapsulation layer CVD2 using a second mask through a first etching process to remove only a removal area D in the second sub-encapsulation layer CVD2 to obtain a second retained pattern C2;

[0103] Step S032 : etching the first sub-encapsulation layer CVD1 using a third mask through a second etching process to remove only the removal area D in the first sub-encapsulation layer CVD1 , thereby obtaining a first retained pattern C1 .

[0104] By adopting the above solution, the second sub-encapsulation layer CVD2 and the first sub-encapsulation layer CVD1 can be etched in sequence to remove the redundant portion of the encapsulation unit 210 , leaving the encapsulation pattern that is ultimately required to cover the display area AA.

[0105] Specifically, the entire display substrate manufacturing process also includes the production processes of other film layers besides the encapsulation layer 200, such as the production process of the touch layer. The process of removing the excess portion of the encapsulation unit 210 in step S03 can be performed before the start of the touch layer production process, between the production processes of the various film layers within the touch layer production process, or after the touch layer production process is completed.

[0106] For example, in the above step S03, on the side of the packaging unit 210 that exceeds the target packaging boundary line 121 (eg, the binding side B1, the first area E1 and the third area E3), as shown in FIG. Figure 10 and Figure 11 As shown, the first reserved pattern C1 includes a first package boundary line C11 that expands outward relative to the target package boundary line 121 toward the direction deviating from the target package area 120 , and the second reserved pattern C2 includes a second package boundary line C21 that expands outward relative to the first package boundary line C11 toward the direction deviating from the target package area 120 .

[0107] In the above solution, in order to ensure that the uneven thickness of the encapsulation layer 200 does not enter the display area AA, when etching the encapsulation unit 210, the etching boundaries of the first sub-encapsulation layer CVD1 and the second sub-encapsulation layer CVD2 can be designed to be expanded relative to the target encapsulation boundary line 121, and as shown in FIG. Figure 10 and Figure 11 As shown, the distance from the first encapsulation boundary line C11 to the boundary of the display substrate is a first distance d1; the distance from the second encapsulation boundary line C21 to the boundary of the display substrate is a second distance d2, and the first distance d1 is greater than the second distance d2. In other words, the etching boundary of the second sub-encapsulation layer CVD2 (i.e., the second encapsulation boundary line C21) overlying the first sub-encapsulation layer CVD1 is expanded outward relative to the etching boundary of the first sub-encapsulation layer CVD1 (i.e., the first encapsulation boundary line C11).

[0108] In this way, the etching boundaries of the first sub-encapsulation layer CVD1 and the second sub-encapsulation layer CVD2 are staggered, which can improve the step height of the etching boundary, reduce the stress of the etching edge of the encapsulation layer, reduce the risk of cracks in mechanical testing, and thus improve the reliability of the encapsulation layer 200.

[0109] Moreover, the larger the outward extension of the second package boundary line C21 relative to the first package boundary line C11, the better the stress reduction effect, but the farther the outermost etching boundary (i.e., the second package boundary line C21) is from the target cutting line of the display area, the better (for example, according to experience, the safe distance is about 10 microns). Therefore, when the frame is limited, the difference between the first distance d1 and the second distance d2 is 5±1 microns.

[0110] For example, the first package boundary line C11 extends outward from the target package boundary line 121 by a third distance d3, which may be 5±1 microns. The second package boundary line C21 extends outward from the target package boundary line 121 by a fourth distance d4, which may be 10±1 microns, to meet the above requirements. It should be understood that the values ​​of the first distance d1, the second distance d2, the third distance d3, and the fourth distance d4 are not limited to these values.

[0111] Furthermore, it is understandable that in other embodiments, the first package boundary line C11 and the second package boundary line C21 may also coincide with each other.

[0112] In addition, based on the process of sequentially etching the second sub-encapsulation layer CVD2 and the first sub-encapsulation layer CVD1, in the above step S03, on the side of the encapsulation unit 210 that exceeds the target encapsulation boundary line 121 (for example, the binding side B1, the first area E1 and the third area E3), as shown in FIG. Figure 8 As shown, the edge of the first remaining pattern C1 includes a sloped first portion C10, the edge of the second remaining pattern C2 includes a sloped second portion C20, and the edge of the second sub-encapsulation layer CVD2 includes a groove S20 at a position where the second portion C20 is close to the first portion C10, thereby forming an undercut structure S. For example, the slope angle of the first portion C10 is greater than the slope angle of the second portion C20.

[0113] In some embodiments, such as Figure 8As shown, the encapsulation unit 210 may include a first inorganic encapsulation layer 21, an organic encapsulation layer 22, and a second inorganic encapsulation layer 23 stacked in sequence along a direction away from the motherboard 100. The encapsulation unit 210 at least partially covers the peripheral region B, and in the peripheral region B, the encapsulation unit 210 includes only the first inorganic encapsulation layer 21 and the second inorganic encapsulation layer 23. In other words, the orthographic projections of the organic encapsulation layer 22 and the peripheral region B on the motherboard 100 at least partially do not overlap, while the orthographic projections of the first inorganic encapsulation layer 21 and the second inorganic encapsulation layer 23 in the peripheral region B on the motherboard 100 at least partially overlap.

[0114] In this way, the first inorganic encapsulation layer 21 is formed into the first sub-encapsulation layer CVD1, and the second inorganic encapsulation layer 23 is formed into the second sub-encapsulation layer CVD2. The first inorganic encapsulation layer 21, the organic encapsulation layer 22, and the second inorganic encapsulation layer 23 achieve multi-layer encapsulation, further improving encapsulation performance and enhancing the reliability of the display panel. The stacked inorganic and organic layers provide protection for the display panel.

[0115] The first inorganic encapsulation layer 21 and the second inorganic encapsulation layer 23 can be made of inorganic materials, such as silicon oxide, silicon nitride, silicon oxynitride, etc. The organic encapsulation layer can be made of organic materials, such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene resin, polyphenylene sulfide resin, benzocyclobutene, etc. Inorganic materials have good density and can isolate water vapor and oxygen. Organic materials have the characteristic of flexibility. Organic materials can buffer stress from the outside world, prevent the display panel from being affected by external stress and affect the display effect. At the same time, it can reduce the risk of inorganic layer fracture leading to encapsulation failure. However, this is not limited to this.

[0116] Furthermore, in some exemplary embodiments, Figure 11 As shown, the motherboard 100 further has a target cutting line L surrounding the peripheral contour of the display screen area 110 .

[0117] In step S03, on the side of the package unit 210 that extends beyond the target package boundary line 121 (e.g., the bonding side B1, the first region E1, and the third region E3), the removal area D may include an inner edge D1 that intersects with the first retained pattern C1, and an outer edge D2 that expands outward from the target package boundary line 121 relative to the inner edge D1 in a direction away from the target package area 120. The inner edge D1 corresponds to the first package boundary line C11 and the second package boundary line C21, and the outer edge D2 expands outward from the target cutting line L in a direction away from the target package area 120.

[0118] For example, Figure 8As shown, the outer edge D2 includes a first outer edge line D21 located on the first sub-packaging layer CVD1 and a second outer edge line D22 located on the second sub-packaging layer CVD2. The first outer edge line D21 expands outward by a fifth distance d5 relative to the target cutting line L, and the second outer edge line D22 expands outward by a sixth distance d6 relative to the target cutting line L. The fifth distance d5 is greater than or equal to 10 microns, and the sixth distance d6 is greater than or equal to 20 microns.

[0119] By adopting the above solution, by staggering the etching boundaries of the first sub-encapsulation layer CVD1 and the second sub-encapsulation layer CVD2, the step height of the etching boundaries of the two sub-encapsulation layers can be improved, thereby reducing stress at the etching edge of the encapsulation layer and lowering the risk of cracks during mechanical testing, thereby improving the reliability of the encapsulation layer 200. Furthermore, the larger the outward extension of the second outer edge line D22 relative to the target cutting line L, the better the stress reduction effect. However, the farther the outermost etching boundary (i.e., the second encapsulation boundary line C21) is from the target cutting line of the display area, the better (for example, a safe distance of approximately 10 microns is empirically established). Therefore, when the frame is limited, the fifth distance d5 is greater than or equal to 10 microns, and the sixth distance d6 is greater than or equal to 20 microns, to meet the above requirements. However, this is not a limitation.

[0120] In addition, illustratively, on the side where the boundary of the packaging unit 210 coincides with the target packaging boundary line 121 (eg, the binding side B1, the second area E2, and the fourth area E4), as shown in FIG. Figure 8 As shown, the edge of the first retaining pattern C1 expands outward relative to the edge of the second retaining pattern C2 in a direction away from the target packaging area 120, and the edges of the first retaining pattern C1 and the second retaining pattern C2 cooperate with each other to make the edge of the packaging unit 210 a smoothly transitioned arc structure.

[0121] In addition, an embodiment of the present disclosure further provides a display substrate. For example, the display substrate can be manufactured using the manufacturing method of the display substrate provided by the embodiment of the present disclosure.

[0122] It should be noted that the display substrate in the embodiment of the present disclosure may be the motherboard 100 covered with the encapsulation layer 200 and before being cut, or may be a display screen obtained by cutting the motherboard 100 .

[0123] like Figure 5 As shown, the display substrate may include a base substrate 100 ′ and an encapsulation layer 200 disposed on the base substrate 100 ′. The base substrate 100 ′ includes a display area AA and a peripheral area B located outside the display area AA.

[0124] For example, Figures 4 to 7As shown, when the display substrate is a motherboard 100 covered with an encapsulation layer 200 and before being cut, the base substrate 100' may refer to the entire above-mentioned motherboard 100, and a plurality of display screen areas 110 may be provided on the base substrate 100', each display screen area 110 having a corresponding display area AA and a peripheral area B; the encapsulation layer 20 may include a plurality of encapsulation units 210, and one encapsulation unit 210 corresponds to one display screen area 110.

[0125] For example, when the display substrate is a display screen obtained by cutting a motherboard 100 covered with an encapsulation layer 200, the motherboard 100 includes multiple display screen areas 110, and the base substrate 100' can be a substrate corresponding to one display screen area 110; the encapsulation layer 200' can be an encapsulation unit 210 on a single display substrate obtained by using the display substrate manufacturing method provided by the embodiment of the present disclosure.

[0126] In some exemplary embodiments, Figure 7 and Figure 8 As shown, the four sides of the display area AA include a binding side B1 and at least two non-binding sides B2 other than the binding side B1; wherein, at least on the binding side B1, the encapsulation layer 20 has a first thickness H1 in a direction perpendicular to the base substrate 100'; and at least on one non-binding side B2, the encapsulation layer 20 has a second thickness H2 in a direction perpendicular to the base substrate 100'; wherein H2 is greater than H1.

[0127] For example, in some embodiments, the difference between H2 and H1 is 0.85±0.1 mm. For example, H2 may be 1.7±0.1 mm, and H1 may be 0.85±0.1 mm. However, this is not limiting.

[0128] In some embodiments, at least two non-binding sides B2 include: a first side B21 located opposite the binding side B1; and a second side B22 and a third side B23 located between the binding side B1 and the first side B21 and opposite to each other; the second side B22 includes a first area E1 close to the first side B21 and a second area E2 close to the binding side B1, and the third side B23 includes a third area E3 close to the first side B21 and a fourth area E4 close to the binding side B1; wherein, the difference between the thickness of the encapsulation layer 20 in the second area E2 and the first thickness H1 is within a threshold, and the thickness of the encapsulation unit 210 in the first area E1, the third area E3 and the first side B21 are all greater than the first thickness H1.

[0129] For example, the threshold value may be substantially equal to 0, in which case the thickness of the encapsulation layer in the second region E2 is substantially the same as the first thickness. It should be noted that "substantially equal to 0" herein includes a range of variation of less than or equal to 10% of 0, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%.

[0130] In some embodiments, as Figures 7 to 9 As shown, at a first junction position a between the first region E1 and the second region E2, there is a second junction position b between the third region E3 and the fourth region E4, and the thickness of the encapsulation unit 210 (encapsulation layer 200) in a direction perpendicular to the motherboard 100 (base substrate 100') gradually increases from the first junction position a to the first side B21, and gradually increases from the second junction position b to the first side B21.

[0131] For example, Figure 7 and Figure 9 As an example, the thickness of the encapsulation layer 200 at position a on the second side B22 is equal to the thickness at position b on the bonding side B1, and is less than the thickness at position c in the first area E1. For example, the thickness of the encapsulation unit 210 at positions a and b can be 1.7 ± 0.1 mm, and the thickness at position c can be 0.85 ± 0.1 mm. However, this is not a limitation.

[0132] In some embodiments, the base substrate 100' has a target packaging area 120 covering the display area AA, and the target packaging area 120 has a target packaging boundary line 121 around the circumference of the display area; wherein, at least on the binding side B1, the boundary of the packaging unit 210 coincides with the target packaging boundary line 121, and the edge of the packaging unit 210 presents a smoothly transitioned arc structure; at least on one non-binding side B2, the boundary of the packaging unit 210 expands outward relative to the target packaging boundary line 121.

[0133] In some embodiments, as Figure 3 and Figure 4 As shown, the first area E1 may include a first arc-shaped area E1' in the second side B22 that smoothly transitions to the first side B21, and the third area E3 may include a third arc-shaped area E3' in the third side B23 that smoothly transitions to the first side B21, wherein in the first arc-shaped area E1', the third arc-shaped area E3' and the first side B21, the boundaries of the packaging unit 210 all exceed the target packaging boundary line 121.

[0134] Furthermore, in some embodiments, Figure 8As shown, at the binding side B1 , the edge of the encapsulation layer 20 is in a smoothly transitioned arc structure; at least at the first side B21 , the first area E1 and the third area E3 , the edge of the encapsulation layer 20 has an undercut structure S.

[0135] Furthermore, in some embodiments, Figure 8 、 Figure 10 and Figure 11 As shown, the packaging unit 210 includes a first sub-packaging layer CVD1 and a second sub-packaging layer CVD2 covering the side of the first sub-packaging layer CVD1 facing away from the motherboard 100. In at least one non-bonding side B2, the first sub-packaging layer CVD1 has a first packaging boundary line C11, and the second sub-packaging layer CVD2 has a second packaging boundary line C21. The distance from the first packaging boundary line C11 to the boundary of the display substrate is a first distance d1; the distance from the second packaging boundary line C21 to the boundary of the display substrate is a second distance d2, and the first distance d1 is greater than the second distance d2. Exemplarily, the difference between the first distance d1 and the second distance d2 is 5±1 microns.

[0136] In addition, for example, Figure 8 As shown, the edge of the first sub-encapsulation layer CVD1 includes a sloped first portion C10; the edge of the second sub-encapsulation layer CVD2 includes a sloped second portion C20. The edge of the second sub-encapsulation layer CVD2 has a groove S20 at a position where the second portion C20 is close to the first portion C10 to form an undercut structure S. For example, the slope angle of the first portion C10 is greater than the slope angle of the second portion C20.

[0137] Furthermore, in some embodiments, Figure 8 As shown, the encapsulation layer 200 includes a first inorganic encapsulation layer 21, an organic encapsulation layer 22, and a second inorganic encapsulation layer 23 stacked in sequence along a direction away from the base substrate 100'. The encapsulation layer 200 at least partially covers the peripheral region B. In the peripheral region B, the encapsulation layer 20 only includes the first inorganic encapsulation layer 21 and the second inorganic encapsulation layer 23. In other words, the orthographic projections of the organic encapsulation layer 22 and the peripheral region B on the base substrate 100' at least partially do not overlap, while the orthographic projections of the first inorganic encapsulation layer 21 and the second inorganic encapsulation layer 23 and the peripheral region B on the base substrate 100' at least partially overlap.

[0138] In this way, the first inorganic encapsulation layer 21 is formed into the first sub-encapsulation layer CVD1, and the second inorganic encapsulation layer 23 is formed into the second sub-encapsulation layer CVD2. The first inorganic encapsulation layer 21, the first organic encapsulation layer 22, and the second inorganic encapsulation layer 23 achieve multi-layer encapsulation, further improving encapsulation performance and enhancing the reliability of the display panel. The stacked inorganic and organic layers provide protection for the display panel.

[0139] The first inorganic encapsulation layer 21 and the second inorganic encapsulation layer 23 can be made of inorganic materials, such as silicon oxide, silicon nitride, silicon oxynitride, etc. The organic encapsulation layer can be made of organic materials, such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene resin, polyphenylene sulfide resin, benzocyclobutene, etc. Inorganic materials have good density and can isolate water vapor and oxygen. Organic materials have the characteristic of flexibility. Organic materials can buffer stress from the outside world, prevent the display panel from being affected by external stress and affect the display effect. At the same time, it can reduce the risk of inorganic layer fracture leading to encapsulation failure. However, this is not limited to this.

[0140] In addition, embodiments of the present disclosure further provide a display device, including the display substrate provided by embodiments of the present disclosure. Such display devices include, but are not limited to, devices with display functions, such as smartphones, monitors, laptop computers, tablet computers, electronic photo frames, driving recorders, and smart wearable devices. Other essential components of the display device (e.g., driver chips) are well understood by those skilled in the art and are not detailed here, nor should they be construed as limitations of the present disclosure.

[0141] Since the principles of solving problems by the display substrate and display device disclosed herein are similar to the principles of solving problems by the method for manufacturing the display substrate disclosed herein, the embodiments of the display substrate and display device provided in the embodiments of the present disclosure can refer to the embodiments of the method for manufacturing the display substrate provided in the embodiments of the present disclosure, and will not be repeated here.

[0142] There are a few points to note:

[0143] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0144] (2) For the sake of clarity, the thickness of layers or regions in the drawings used to describe the embodiments of the present disclosure are exaggerated or reduced, i.e., these drawings are not drawn to scale. It is understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element or intervening elements may be present.

[0145] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0146] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A display substrate, characterized in that: include: A base substrate, comprising a display area and a peripheral area located outside the display area, wherein the peripheral sides of the display area include a binding side and at least two non-binding sides except the binding side; and A packaging layer located on the substrate; wherein, At least on the binding side, the encapsulation layer has a first thickness H1 in a direction perpendicular to the substrate; at least on one of the non-binding sides, the encapsulation layer has a second thickness H2 in a direction perpendicular to the substrate; Among them, H2 is greater than H1.

2. The display substrate according to claim 1, wherein: The difference between H2 and H1 is 0.85±0.1mm.

3. The display substrate according to claim 1, wherein At least two of the non-binding sides include a first side located opposite the binding side, and a second side and a third side located between the binding side and the first side and opposite to each other, the second side includes a first area close to the first side and a second area close to the binding side, and the third side includes a third area close to the first side and a fourth area close to the binding side; wherein, the difference between the thickness of the encapsulation layer in the second area and the fourth area and the first thickness H1 is within a threshold, and the thickness in the first area and the third area is greater than the first thickness H1 and less than or equal to the second thickness H2.

4. The display substrate according to claim 3, wherein: There is a first junction position between the first region and the second region, and a second junction position between the third region and the fourth region, wherein the thickness of the encapsulation layer perpendicular to the base substrate is configured to gradually increase from the first junction position to the first side, and gradually increase from the second junction position to the first side.

5. The display substrate according to claim 3, wherein: On the binding side, the edge of the encapsulation layer has a smoothly transitioned arc structure; at least on the non-binding side, the first region and the third region, the edge of the encapsulation layer has an undercut structure.

6. The display substrate according to claim 5, wherein: The encapsulation layer includes a first sub-encapsulation layer and a second sub-encapsulation layer covering a side of the first sub-encapsulation layer facing away from the base substrate; wherein, At least on one of the non-binding sides, the first sub-packaging layer has a first packaging boundary line, the second sub-packaging layer has a second packaging boundary line, and the distance from the first packaging boundary line to the boundary of the display substrate is a first distance; the distance from the second packaging boundary line to the boundary of the display substrate is a second distance, and the first distance is greater than the second distance.

7. The display substrate according to claim 6, wherein: The difference between the first distance and the second distance is 5±1 micrometers.

8. The display substrate according to claim 6, wherein: The edge of the first sub-package layer includes a first sloped portion; the edge of the second sub-package layer includes a second sloped portion, and the edge of the second sub-package layer has a groove at a position close to the first portion to form the undercut structure.

9. The display substrate according to claim 8, wherein: The slope angle of the first portion is greater than the slope angle of the second portion.

10. The display substrate according to claim 1, wherein The encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer stacked in sequence along a direction away from the base substrate; wherein, the encapsulation layer at least partially covers the peripheral area, and in the peripheral area, the encapsulation layer only includes the first inorganic encapsulation layer and the second inorganic encapsulation layer.

11. A display device, characterized in that: The display substrate comprises the display substrate according to any one of claims 1 to 10.

12. A method for manufacturing a display substrate, characterized in that: For manufacturing the display substrate according to any one of claims 1 to 10, the method comprises: Providing a motherboard not covered with an encapsulation layer, the motherboard having multiple display screen areas, the display screen area including a display region and a peripheral region located outside the display region, the four sides of the display region including a binding side and at least two non-binding sides other than the binding side, the display screen area also including a target encapsulation area, the target encapsulation area covering the display area of ​​the display screen area, and the target encapsulation area having a target encapsulation boundary line around the peripheral contour of the display region; forming a patterned encapsulation layer on the motherboard, wherein the pattern of the encapsulation layer includes a plurality of encapsulation units corresponding to and covering the respective display screen areas, wherein, on at least one of the non-binding sides, at least a portion of each of the encapsulation units exceeds a target encapsulation boundary line of the corresponding display screen area, and at least another portion does not exceed the target encapsulation boundary line of the corresponding display screen area, and at least on the binding side, a boundary of the encapsulation unit coincides with the target encapsulation boundary line, so that the encapsulation unit includes a reserved area and a removed area, wherein a contour of the reserved area matches a contour shape of the target encapsulation area; The packaging unit is patterned to remove the removal area.

13. The method for manufacturing a display substrate according to claim 12, wherein: The step of forming a patterned packaging layer on the motherboard includes: A patterned packaging layer is formed on the motherboard by using a first mask through vapor deposition.

14. The method for manufacturing a display substrate according to claim 13, wherein: At least two of the non-binding sides include a first side located opposite the binding side, and a second side and a third side located between the binding side and the first side and opposite to each other, wherein the packaging unit exceeds the target packaging boundary line of the corresponding display screen area at least on the first side.

15. The method for manufacturing a display substrate according to claim 14, wherein: The second side includes a first area close to the first side and a second area close to the binding side, and the third side includes a third area close to the first side and a fourth area close to the binding side, wherein, on the first side, the first area, and the third area, the encapsulation unit at least partially exceeds the target encapsulation boundary line of the corresponding display screen area, and on the binding side, the third area, and the fourth area, the boundary of the encapsulation unit coincides with the target encapsulation boundary line.

16. The method for manufacturing a display substrate according to claim 15, wherein: The first region includes a first arc-shaped region in the second side that smoothly transitions to the first side, and the third region may include a third arc-shaped region in the third side that smoothly transitions to the first side, wherein in the first arc-shaped region, the third arc-shaped region and the first side, the boundaries of the packaging unit all exceed the target packaging boundary line.

17. The method for manufacturing a display substrate according to claim 12, wherein: The patterning of the packaging unit to remove the removal area includes: patterning the packaging unit to remove the removal area by etching.

18. The method for manufacturing a display substrate according to claim 17, wherein: The encapsulation layer includes a first sub-encapsulation layer and a second sub-encapsulation layer covering a side of the first sub-encapsulation layer facing away from the motherboard, and the reserved area includes a first reserved pattern located on the first sub-encapsulation layer and a second reserved pattern located on the second sub-encapsulation layer; The patterning process of the packaging unit by etching specifically includes: Through a first etching process, the second sub-encapsulation layer is etched using a second mask to remove only the removal area in the second sub-encapsulation layer to obtain a second retained pattern; The first sub-encapsulation layer is etched using a third mask through a second etching process to remove only the removal area in the first sub-encapsulation layer, thereby obtaining the first retained pattern.

19. The method for manufacturing a display substrate according to claim 18, wherein: The patterning of the packaging unit to remove the removal area specifically includes: On a side of the packaging unit that extends beyond the target packaging boundary line, the first retention pattern includes a first packaging boundary line that extends outward by a third distance relative to the target packaging boundary line in a direction deviating from the target packaging area, and the second retention pattern includes a second packaging boundary line that extends outward by a fourth distance relative to the first packaging boundary line in a direction deviating from the target packaging area.

20. The method for manufacturing a display substrate according to claim 19, wherein: On the side of the packaging unit that exceeds the target packaging boundary line, the edge of the first retaining pattern includes a first sloped portion; the edge of the second retaining pattern includes a second sloped portion, and the edge of the second sub-packaging layer has a groove at a position of the second portion close to the first retaining pattern to form an undercut structure.

21. The method for manufacturing a display substrate according to claim 18, wherein: The motherboard also has a target cutting line surrounding the peripheral contour of the display screen area; The patterning of the packaging unit to remove the removal area specifically includes: On the side of the packaging unit that exceeds the target packaging boundary line, the removal area includes an inner edge that intersects with the first retained pattern, and an outer edge that expands outward relative to the inner edge and relative to the target packaging boundary line in a direction deviating from the target packaging area, wherein the outer edge expands outward relative to the target cutting line in a direction deviating from the target packaging area.

22. The method for manufacturing a display substrate according to claim 21, wherein: The outer edge includes a first outer edge line located on the first sub-packaging layer and a second outer edge line located on the second sub-packaging layer, the first outer edge line extends outward by a fifth distance relative to the target cutting line, and the second outer edge line extends outward by a sixth distance relative to the target cutting line, the fifth distance is greater than or equal to 10 microns, and the sixth distance is greater than or equal to 20 microns.

23. The method for manufacturing a display substrate according to claim 19, wherein: On the side where the boundary of the packaging unit coincides with the target packaging boundary line, the edge of the first retaining pattern expands outward relative to the edge of the second retaining pattern in a direction deviating from the target packaging area, and the edges of the first retaining pattern and the second retaining pattern cooperate with each other to make the edge of the packaging unit present a smoothly transitioned arc structure.

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