Direct digital detection channel

Abstract

A charged particle detector includes a plurality of sensing elements, each sensing element having a sensing element stage circuit for processing a detection signal. The sense element circuit includes a threshold circuit for preventing noise at the sense element from passing to a detection unit in the sense element stage circuit. The threshold circuit may be a thyristor or other solid state current control device, which may be turned on to conduct the current when a threshold voltage or current is reached, and which may be turned off when the current falls below a holding current. The detection unit may be a direct digitized unit capable of producing measurements in discrete programmable units.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. application 63 / 441,759, filed on January 27, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] The description herein relates to detectors, and more particularly to detectors that may be suitable for charged particle detection. Background Art

[0004] Detectors can be used to sense physically observable phenomena. For example, some charged particle beam tools (such as electron microscopes) include a detector that receives charged particles projected from a sample and outputs a detection signal. The detection signal can be used to reconstruct an image of the structure of the sample being inspected, and can be used to reveal defects in the sample, for example. In the manufacture of semiconductor devices that may include a large number of densely packed, miniaturized integrated circuit (IC) components, detecting defects in the sample becomes increasingly important. To this end, an inspection system can be provided. For example, a charged particle (e.g., electron) beam microscope (such as a scanning electron microscope (SEM) or a transmission electron microscope (TEM), which has a resolution as low as less than 1 nanometer) is used as a practical tool for inspecting IC components with sub-100 nanometer feature sizes. The working principle of an electron microscope is to irradiate a sample with an electron beam and then detect secondary or backscattered electrons (or other types of secondary particles) on a detector. Secondary particles can form one or more beam spots on the detector surface.

[0005] Some detectors include a pixelated array of multiple sensing elements. The pixelated array can be useful because it allows the detector configuration to adapt to the size and shape of the beam spot formed on the detector. When multiple primary beams are used and multiple secondary beams are incident on the detector, the pixelated array can be separated into different regions of the detector, which are associated with different beam spots. Each region can form its own set of sensing elements (pixels) that are used to detect individual beam spots.

[0006] Some detectors include charged particle counting capabilities. With the continued miniaturization of semiconductor devices, inspection systems can use lower and lower beam currents in charged particle beam tools. Existing detection systems can be limited by signal-to-noise ratio (SNR) and system throughput, particularly as beam currents decrease to, for example, the picoampere range. Electron counting has been proposed to improve the SNR and increase throughput of electron beam inspection systems, where the intensity of the incident electron beam is obtained by counting the number of electrons arriving at the detector and then analyzing the frequency of electron arrival events. Summary of the Invention

[0007] Some embodiments of the present disclosure provide a sensing element-level circuit for a charged particle detector. The sensing element-level circuit may include: a threshold circuit configured to enter an on-state or an off-state in response to an output of a sensing element of the charged particle detector; and a first digitizing unit. The on-state may allow the threshold circuit to conduct current from the sensing element to the first digitizing unit of the sensing element-level circuit. The off-state may prevent the threshold circuit from conducting current from the sensing element to the first digitizing unit of the sensing element-level circuit.

[0008] Some embodiments of the present disclosure provide a method for reducing noise in a charged particle detector. The method may include: causing a threshold circuit of the charged particle detector to enter an on-state or an off-state in response to an output of a sensing element of the charged particle detector; and generating an image based on charge received at a sensing element-level readout circuit of the charged particle detector. The on-state may allow the threshold circuit to conduct current from the sensing element to a first digitizing unit of the sensing element-level readout circuit. The off-state may prevent the threshold circuit from conducting current from the sensing element to the first digitizing unit of the sensing element-level readout circuit.

[0009] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosed embodiments, as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a schematic diagram illustrating an exemplary charged particle beam inspection system consistent with embodiments of the present disclosure.

[0011] Figure 2 is a schematic diagram illustrating an exemplary multi-beam tool consistent with embodiments of the present disclosure, which may be Figure 1 A portion of an exemplary charged particle beam inspection system.

[0012] Figure 3A-3C is a graph illustrating a signal at an output of a sensing element according to a comparative embodiment.

[0013] Figure 4 is a diagram illustrating a charged particle counting detector according to a comparative embodiment.

[0014] Figure 5 is a diagram illustrating a sense element level circuit consistent with an embodiment of the present disclosure.

[0015] Figure 6 is a diagram illustrating a sense element array and sense element level readout circuitry consistent with an embodiment of the present disclosure.

[0016] Figure 7 is a diagram illustrating an example digitizing unit consistent with embodiments of the present disclosure.

[0017] Figure 8 is a diagram illustrating an example digitizing unit consistent with embodiments of the present disclosure.

[0018] Figure 9 is a flow chart illustrating a method that may be used for charged particle beam measurements consistent with embodiments of the present disclosure.

[0019] Figure 10 is a flow chart illustrating a method that may be used for charged particle beam measurements consistent with embodiments of the present disclosure. DETAILED DESCRIPTION

[0020] Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings in which the same numbers in different figures represent the same or similar elements, unless otherwise stated. The implementations set forth in the following description of exemplary embodiments do not represent all implementations consistent with the present disclosure. On the contrary, they are merely examples of apparatus and methods consistent with aspects related to the subject matter described in the appended claims. For example, although some embodiments are described in the context of utilizing a charged particle beam (e.g., an electron beam), the present disclosure is not limited thereto. Other types of charged particle beams may also be applied similarly. In addition, other imaging systems such as optical imaging, photoelectric detection, x-ray detection, etc. may be used.

[0021] Electronic devices consist of circuits formed on a semiconductor material called a substrate. The semiconductor material can include, for example, silicon, gallium arsenide, indium phosphide, or silicon germanium. Many circuits can be formed together on the same piece of silicon and are called integrated circuits, or ICs. The size of these circuits has decreased dramatically, allowing more circuits to be mounted on a substrate. For example, the IC chip in a smartphone can be as small as a thumb but can include more than 2 billion transistors, each less than 1 / 1000 the size of a human hair.

[0022] Manufacturing these ICs from extremely small structures or components is a complex, time-consuming, and expensive process, generally involving hundreds of individual steps. Even a mistake in one step can cause a defect in the finished IC, rendering it unusable. Therefore, one goal of the manufacturing process is to avoid such defects in order to maximize the number of functional ICs produced in the process; that is, to improve the overall yield of the process.

[0023] An integral part of improving yield is monitoring the chip manufacturing process to ensure that it is producing a sufficient number of functional integrated circuits. One way to monitor this process is to inspect the chip circuit structures as they are formed at the individual stages. This inspection can be performed using a scanning charged particle microscope ("SCPM"). For example, the SCPM can be a scanning electron microscope (SEM). The SCPM can be used to image these extremely small structures, in effect taking a "picture" of the wafer structure. This image can be used to determine whether the structure was correctly formed in the appropriate location. If the structure is defective, the process can be adjusted to make the defect less likely to occur again.

[0024] The working principle of the SEM is similar to that of a camera. A camera takes pictures by receiving and recording the intensity of light reflected or emitted from a person or object. The SEM takes "pictures" by receiving and recording the energy or number of electrons reflected or emitted from a wafer structure. Before taking such a "picture", an electron beam can be projected onto the structure, and when electrons are reflected or emitted ("emitted") from the structure (e.g., from the wafer surface, from a structure below the wafer surface, or both), the detector of the SEM can receive and record the energy or number of these electrons to generate an inspection image. In order to take such a "picture", the electron beam can scan the wafer (e.g., in a line-by-line or zigzag manner), and the detector can receive the emitted electrons from the area where the electron beam is projected (called a "beam spot"). The detector can initially receive and record the emitted electrons from each beam spot, and merge the information recorded for all beam spots to generate an inspection image. Some SEMs use a single electron beam (called "single-beam SEMs") to take a single "picture" to generate an inspection image, while some SEMs use multiple electron beams (also called "multi-beam SEMs") to take multiple "sub-pictures" of the wafer in parallel and stitch them together to generate an inspection image. By using multiple electron beams, the SEM can provide more electron beams to the structure to obtain these multiple "sub-pictures", thereby causing more electrons to be emitted from the structure. Therefore, the detector can receive more emitted electrons simultaneously and generate inspection images of the wafer structure with higher efficiency and faster speed.

[0025] Electrons emitted from an object (such as a wafer) and then received by a detector of the SEM can cause the detector to generate an electrical signal (e.g., a current signal or a voltage signal) commensurate with the energy of the emitted electrons and the intensity of the electron beam. For example, the amplitude of the electrical signal can be commensurate with the charge or energy of the received emitted electrons. The detector can output the electrical signal to an image processor, and the image processor can process the electrical signal to form an image of the wafer structure. A multi-beam SEM system uses multiple electron beams for inspection, and the detector of the multi-beam SEM can have multiple sections to receive them. Each section can have multiple sensing elements and can be used to form a "picture" of a sub-area of ​​the wafer. The "pictures" generated based on the signals from each section of the detector can be combined to form a complete picture of the inspected wafer.

[0026] Another challenge faced by detectors, particularly charged particle counting detectors, is high signal-to-noise ratio (SNR) in low beam current systems. For example, charged particle counting detectors may have a complex signal readout architecture at the level of each individual sensing element. Each sensing element in a charged particle counting detector may be coupled to its own array of signal detection cells, each of which may be configured to record individual electron arrival events. Because they are configured to detect such fine signals, the signal detection cells may be negatively impacted even if the noise level in the detection channel is low.

[0027] Furthermore, the design required to achieve this fine detection hinders the use of counting detectors in conventional applications with higher beam currents. Conventional detectors present a similar problem, as they may not be suitable for very low beam current applications, such as charged particle counting. Consequently, both conventional and counting detectors may suffer from low dynamic range, which prevents their use over a wide range of beam currents.

[0028] Embodiments of the present disclosure provide a charged particle detector with an improved sensing element level readout circuit design. Each sensing element level circuit in the detector may include an array of digitizing units. The digitizing units may be similar to the signal detection units in a charged particle counting detector. However, instead of counting the arrival events of individual charged particles, the digitizing units may measure the overall energy flow introduced into the detection channel by multiple arrival events. The digitizing units may directly generate a digital value of the energy flow, which may be read out by a control unit of the sensing element level circuit. The digitizing units may achieve a high dynamic range, allowing them to be used in both high beam current applications and low beam current applications.

[0029] The sensing element level readout circuit can include a threshold circuit that is configured to prevent low-level noise from reaching the digitizing unit. For example, the threshold circuit can include a solid-state current control device (SSCCD), such as a silicon-controlled rectifier (SCR). The SSCCD can be configured to turn on and conduct current when a signal above a threshold is received. Once turned on, when the current drops below the holding current threshold of the SSCCD, the SSCCD can be turned off again to stop conducting current. In this way, low-level noise can be prevented from reaching the digitizing unit between individual arrival events.

[0030] The objects and advantages of the present disclosure can be achieved by the elements and combinations set forth in the embodiments discussed herein. However, the embodiments of the present disclosure are not necessarily required to achieve these exemplary objects or advantages, and some embodiments may not achieve any of the objects or advantages.

[0031] Without limiting the scope of the present disclosure, some embodiments may be described in the context of providing detection systems and detection methods in a system utilizing an electron beam ("e-beam"). However, the present disclosure is not limited thereto. Other types of charged particle beams may also be similarly applied. In addition, the systems and methods for detection may be used in other imaging systems, such as optical imaging, photon detection, x-ray detection, ion detection, and the like.

[0032] As used herein, unless otherwise specifically stated, the term "or" includes all possible combinations unless they are not feasible. For example, if it is stated that a component can include A or B,

[0033] Then, unless otherwise specifically stated or not feasible, the component may include A or B or A and B. As a second example, if it is specified that a component may include A, B, or C, then, unless otherwise specifically stated or not feasible, the component may include A, or B, or C, or A and B, or A and C, or B and C, or A, B, and C.

[0034] For the sake of clarity, the relative sizes of components in the drawings may be exaggerated. In the following description of the drawings, identical or similar reference numerals refer to identical or similar components or entities, and only the differences from individual embodiments are described.

[0035] Figure 1 An example electron beam inspection (EBI) system 100 consistent with embodiments of the present disclosure is illustrated. The EBI system 100 can be used for imaging. Figure 1As shown, the EBI system 100 includes a main chamber 101, a load / lock chamber 102, a beam tool 104, and an equipment front end module (EFEM) 106. The beam tool 104 is located within the main chamber 101. The EFEM 106 includes a first load port 106a and a second load port 106b. The EFEM 106 may include (one or more) additional load ports. The first load port 106a and the second load port 106b receive wafer front opening pods (FOUPs), which contain wafers (e.g., semiconductor wafers or wafers made of other materials) or samples to be inspected (wafers and samples may be used interchangeably). A "batch" refers to a plurality of wafers that can be loaded as a batch for processing.

[0036] One or more robotic arms (not shown) in the EFEM 106 can transport the wafer to the load / lock chamber 102. The load / lock chamber 102 is connected to a load / lock vacuum pump system (not shown), which removes gas molecules from the load / lock chamber 102 to reach a first pressure below atmospheric pressure. After reaching the first pressure, the one or more robotic arms (not shown) can transport the wafer from the load / lock chamber 102 to the main chamber 101. The main chamber 101 is connected to a main chamber vacuum pump system (not shown), which removes gas molecules from the main chamber 101 to reach a second pressure below the first pressure. After reaching the second pressure, the wafer undergoes inspection by the beam tool 104. The beam tool 104 can be a single-beam system or a multi-beam system.

[0037] The controller 109 is electrically connected to the beam tool 104. The controller 109 may be a computer configured to perform various controls of the EBI system 100. Figure 1 106, but it will be appreciated that the controller 109 may be part of the structure.

[0038] In some embodiments, the controller 109 may include one or more processors (not shown). A processor may be a general or specialized electronic device capable of manipulating or processing information. For example, the processor may include any number of central processing units (or "CPUs"), graphics processing units (or "GPUs"), optical processors, programmable logic controllers, microcontrollers, microprocessors, digital signal processors, intellectual property (IP) cores, programmable controller arrays (PLAs), programmable array logic (PALs), general array logic (GALs), complex programmable logic devices (CPLDs), field programmable gate arrays (FPGAs), systems on chips (SoCs), application specific integrated circuits (ASICs), and any combination of any type of circuit capable of performing data processing. A processor may also be a virtual processor, which includes one or more processors distributed across multiple machines or devices coupled via a network.

[0039] In some embodiments, the controller 109 may also include one or more memories (not shown). The memory may be a general or specific electronic device capable of storing processor-accessible code and data (e.g., via a bus). For example, the memory may include any number of random access memories (RAM), read-only memories (ROM), optical disks, magnetic disks, hard disks, solid-state drives, flash drives, secure digital (SD) cards, memory sticks, compact flash (CF) cards, or any combination of any type of storage device. The code and data may include an operating system (OS) and one or more application programs (or "apps") for specific tasks. The memory may also be virtual memory, which includes one or more memories distributed across multiple machines or devices coupled via a network.

[0040] Figure 2 104 and an image processing system 290 that may be configured for use with the EBI system 100 ( Figure 1 )middle.

[0041] The beam tool 104 includes a charged particle source 202, a gun aperture 204, a focusing lens 206, a primary charged particle beam 210 emitted from the charged particle source 202, a source conversion unit 212, a plurality of beamlets 214, 216, and 218 of the primary charged particle beam 210, a primary projection optical system 220, a motorized wafer stage 280, a wafer holder 282, a plurality of secondary charged particle beams 236, 238, and 240, a secondary optical system 242, and a charged particle detection device 244. The primary projection optical system 220 may include a beam splitter 222, a deflection scanning unit 226, and an objective lens 228. The charged particle detection device 244 may include detection sub-areas 246, 248, and 250.

[0042] Charged particle source 202, gun aperture 204, condenser lens 206, source conversion unit 212, beam splitter 222, deflection scanning unit 226, and objective lens 228 may be aligned with a primary optical axis 260 of device 104. Secondary optical system 242 and charged particle detection device 244 may be aligned with a secondary optical axis 252 of device 104.

[0043] The charged particle source 202 can emit one or more charged particles, such as electrons, protons, ions, muons, or any other particles carrying an electric charge. In some embodiments, the charged particle source 202 can be an electron source. For example, the charged particle source 202 can include a cathode, an extractor, or an anode, wherein primary electrons can be emitted from the cathode and extracted or accelerated to form a primary charged particle beam 210 (in this case, a primary electron beam) having an intersection (virtual or real) 208. For ease of explanation and without ambiguity, electrons are used as examples in some descriptions herein. However, it should be noted that any charged particle can be used in any embodiment of the present disclosure, and is not limited to electrons. The primary charged particle beam 210 can be visualized as being emitted from the intersection 208. The gun aperture 204 can block the peripheral charged particles of the primary charged particle beam 210 to reduce the Coulomb effect. The Coulomb effect may result in an increase in the detection spot size.

[0044] The source conversion unit 212 may include an imaging element array and a beam limiting aperture array. The imaging element array may include a micro deflector array or a micro lens array. The imaging element array may form multiple parallel images (virtual or real) of the intersection 208 with the multiple beam waves 214, 216, and 218 of the primary charged particle beam 210. The beam limiting aperture array may limit the multiple beam waves 214, 216, and 218. Although Figure 2 , three beams 214, 216, and 218 are shown, but embodiments of the present disclosure are not limited thereto. For example, in some embodiments, device 104 may be configured to generate a first number of beams. In some embodiments, the first number of beams may be in the range of 1 to 1000. In some embodiments, the first number of beams may be in the range of 200-500. In an exemplary embodiment, device 104 may generate 400 beams.

[0045] The condenser lens 206 can focus the primary charged particle beam 210. The current of the beams 214, 216, and 218 downstream of the source conversion unit 212 can be changed by adjusting the focusing power of the condenser lens 206 or by changing the radial size of the corresponding beam limiting apertures in the beam limiting aperture array. The objective lens 228 can focus the beams 214, 216, and 218 onto the wafer 230 for imaging and form a plurality of detection spots 270, 272, and 274 on the surface of the wafer 230.

[0046] The beam splitter 222 can be a Wien filter type beam splitter that generates an electrostatic dipole field and a magnetic dipole field. In some embodiments, if the electrostatic dipole field and the magnetic dipole field are applied, the force exerted by the electrostatic dipole field on the charged particles (e.g., electrons) of the beams 214, 216, and 218 can be substantially equal in magnitude and opposite in direction to the force exerted by the magnetic dipole field on the charged particles. Therefore, the beams 214, 216, and 218 can pass directly through the beam splitter 222 with a zero deflection angle. However, the total dispersion of the beams 214, 216, and 218 generated by the beam splitter 222 can also be non-zero. The beam splitter 222 can separate the secondary charged particle beams 236, 238, and 240 from the beams 214, 216, and 218 and direct the secondary charged particle beams 236, 238, and 240 to the secondary optical system 242.

[0047] The deflection scanning unit 226 can deflect the beams 214, 216, and 218 to scan the detection spots 270, 272, and 274 over the surface area of ​​the wafer 230. In response to the incidence of the beams 214, 216, and 218 at the detection spots 270, 272, and 274, secondary charged particle beams 236, 238, and 240 can be emitted from the wafer 230. The secondary charged particle beams 236, 238, and 240 can include charged particles (e.g., electrons) having an energy distribution. For example, the secondary charged particle beams 236, 238, and 240 can be secondary electron beams including secondary electrons (with energy ≤ 50 eV) and backscattered electrons (with energy between 50 eV and the landing energy of the beams 214, 216, and 218). The secondary optical system 242 can focus the secondary charged particle beams 236, 238, and 240 onto detection sub-regions 246, 248, and 250 of the charged particle detection device 244. The detection sub-regions 246, 248, and 250 can be configured to detect the corresponding secondary charged particle beams 236, 238, and 240 and generate corresponding signals (e.g., voltage, current, etc.) for reconstructing an SCPM image of structures on or below the surface area of ​​the wafer 230.

[0048] The generated signals may represent the intensities of the secondary charged particle beams 236, 238, and 240 and may be provided to an image processing system 290 that is in communication with the charged particle detection device 244, the primary projection optical system 220, and the motorized wafer stage 280. The movement speed of the motorized wafer stage 280 may be synchronized and coordinated with the beam deflection controlled by the deflection scanning unit 226 so that the movement of the scanning probe spots (e.g., scanning probe spots 270, 272, and 274) may orderly cover the region of interest on the wafer 230. The parameters of this synchronization and coordination may be adjusted to accommodate different materials of the wafer 230. For example, different materials of the wafer 230 may have different resistance and capacitance characteristics, which may result in different signal sensitivities to the movement of the scanning probe spots.

[0049] The intensities of the secondary charged particle beams 236, 238, and 240 can vary depending on the external or internal structure of the wafer 230 and, therefore, can indicate whether the wafer 230 includes defects. Furthermore, as described above, the beams 214, 216, and 218 can be projected onto different locations on the top surface of the wafer 230 or onto different sides of a local structure of the wafer 230 to generate secondary charged particle beams 236, 238, and 240 that can have different intensities. Therefore, by mapping the intensities of the secondary charged particle beams 236, 238, and 240 to regions of the wafer 230, the image processing system 290 can reconstruct an image reflecting characteristics of the internal or external structure of the wafer 230.

[0050] In some embodiments, the image processing system 290 may include an image acquirer 292, a storage device 294, and a controller 296. The image acquirer 292 may include one or more processors. For example, the image acquirer 292 may include a computer, a server, a mainframe, a terminal, a personal computer, any type of mobile computing device, or a combination thereof. The image acquirer 292 may be communicatively coupled to the charged particle detection device 244 of the beam tool 104 via a medium such as an electrical conductor, a fiber optic cable, a portable storage medium, IR, Bluetooth, the Internet, a wireless network, wireless radio, or a combination thereof. In some embodiments, the image acquirer 292 may receive signals from the charged particle detection device 244 and may construct an image. Thus, the image acquirer 292 may acquire an SCPM image of the wafer 230. The image acquirer 292 may also perform various post-processing functions, such as generating outlines, overlaying indicators on the acquired image, and the like. The image acquirer 292 may be configured to adjust the brightness and contrast of the acquired image. In some embodiments, the storage device 294 may be a storage medium such as a hard drive, flash memory, cloud storage, random access memory (RAM), or other types of computer-readable memory. A storage device 294 may be coupled to the image acquirer 292 and may be used to store the scanned raw image data as a raw image and a post-processed image. The image acquirer 292 and the storage device 294 may be connected to a controller 296. In some embodiments, the image acquirer 292, the storage device 294, and the controller 296 may be integrated together as a control unit.

[0051] In some embodiments, the image acquirer 292 may acquire one or more SCPM images of the wafer based on the imaging signal received from the charged particle detection device 244. The imaging signal may correspond to a scanning operation for performing charged particle imaging. The acquired image may be a single image including multiple imaging regions. The single image may be stored in the storage device 294. The single image may be an original image that may be divided into multiple regions. Each region may include an imaging region that includes a feature of the wafer 230. The acquired image may include multiple images of a single imaging region of the wafer 230 sampled multiple times in a time series. The multiple images may be stored in the storage device 294. In some embodiments, the image processing system 290 may be configured to perform image processing steps on multiple images of the same position of the wafer 230.

[0052] In some embodiments, the image processing system 290 may include measurement circuitry (e.g., an analog-to-digital converter) to obtain a distribution of detected secondary charged particles (e.g., secondary electrons). The charged particle distribution data collected during the detection time window, combined with the corresponding scan path data of the beams 214, 216, and 218 incident on the wafer surface, can be used to reconstruct an image of the inspected wafer structure. The reconstructed image can be used to reveal various features of the internal or external structure of the wafer 230, and thus can be used to reveal any defects that may be present in the wafer.

[0053] In some embodiments, the charged particles may be electrons. When the electrons of the primary charged particle beam 210 are projected onto the surface of the wafer 230 (e.g., detection spots 270, 272, and 274), the electrons of the primary charged particle beam 210 may penetrate the surface of the wafer 230 to a certain depth, interacting with particles on the wafer 230. Some electrons of the primary charged particle beam 210 may elastically interact with the material of the wafer 230 (e.g., in the form of elastic scattering or collisions) and may be reflected or recoiled away from the surface of the wafer 230. Elastic interactions conserve the total kinetic energy of the interacting objects (e.g., electrons of the primary charged particle beam 210), wherein the kinetic energy of the interacting objects is not converted into other forms of energy (e.g., heat, electromagnetic energy, etc.). These reflected electrons generated by elastic interactions may be referred to as backscattered electrons (BSEs). Some electrons of the primary charged particle beam 210 may inelastically interact with the material of the wafer 230 (e.g., in the form of inelastic scattering or collisions). Inelastic interactions do not conserve the total kinetic energy of the interacting objects, wherein some or all of the kinetic energy of the interacting objects is converted into other forms of energy. For example, through inelastic interaction forces, the kinetic energy of some electrons of the primary charged particle beam 210 may cause electron excitation and transition of material atoms. This inelastic interaction may also generate electrons emitted from the surface of the wafer 230, which may be referred to as secondary electrons (SE). The yield or emission rate of BSE and SE depends on, for example, the material being inspected and the landing energy of the electrons of the primary charged particle beam 210 on the material surface. The energy of the electrons of the primary charged particle beam 210 may be determined in part by its accelerating voltage (e.g., Figure 2 The number of BSEs and SEs may be greater or lesser (or even the same as) than the number of injected electrons of the primary charged particle beam 210.

[0054] The images generated by the SEM can be used for defect inspection. For example, a generated image for capturing a test device area of ​​a wafer can be compared with a reference image for capturing the same test device area. The reference image can be predetermined (for example, by simulation) and does not include known defects. If the difference between the generated image and the reference image exceeds the tolerance level, a potential defect can be identified. For another example, the SEM can scan multiple areas of a wafer, each area including a test device area designed to be the same, and generate multiple images to capture these test device areas of manufacture. Multiple images can be compared with each other. If the difference between the multiple images exceeds the tolerance level, a potential defect can be identified.

[0055] For ease of explanation and without ambiguity, electrons are used as examples in some descriptions herein. However, it should be noted that any charged particles can be used in any embodiment of the present disclosure, and are not limited to electrons. For example, the source in a charged particle beam tool can emit one or more charged particles, such as electrons, protons, ions, muons, or any other particles that carry an electric charge. In addition, some embodiments of the present disclosure may use photons instead of charged particles, such as visible light, UV, DUV, EUV, x-rays, or light in any other wavelength range. For example, in a photon embodiment, the secondary beam spot may refer to light that is reflected, refracted, diffracted, or scattered from a sample (on which the primary beam is incident). Therefore, although the detector in the present disclosure may be disclosed for electron detection, some embodiments of the present disclosure may be directed to detecting other charged particles or photons.

[0056] Figure 3A and Figure 3B The figure shows the relationship between the signal value s(t) generated by electrons when they reach the output of the sensing element and the corresponding value s(t) in the detection channel for two different beam current levels of a conventional charged particle detector. Figure 3A At high beam currents, the signal at the output of the sensing element shows a series of sharp peaks of individual arrival events. However, the corresponding signal in the detection channel is less distinct. Overlapping peaks can be smoothed as an integrated or weighted average signal, and the detection channel adds a noise component due to, for example, thermal noise in transistors, amplifiers, resistors, etc. Figure 3B In the case of very low beam currents, such as in the pA range, the noise from the detection channel can become the dominant factor in the overall noise in the final image. At very low beam currents, the frequency of charged particle arrival events can be much lower than in high beam current applications. Smoothing out the few high, sharp peaks in the sensing element output can result in a broadening and flattening of the signal in the detection channel. At the same time, the noise component can be Figure 3AThe situation remains essentially the same, so the few arrival events may be difficult to distinguish from the noise. Since the magnitude of the signal and noise are very similar, increasing the gain in the detection channel does not help to distinguish the two.

[0057] Figure 3C The diagram shows the detection of charged particle counting detectors. Figure 3B The signal value s(t) in the detection channel of the extremely low beam current is s(t). In a counting type detector, such as Figure 3C As shown in the figure above, individual peaks can be detected individually rather than as an average signal. This can greatly improve the SNR at each local event. In addition, as shown in the figure below, the threshold circuit can be configured to prevent the signal from passing unless it exceeds a predetermined threshold (shown as a dashed line in the figure). This prevents noise components from being passed to the readout circuitry at the sensing element level, thereby achieving essentially noise-free detection of individual charged particle arrivals.

[0058] Figure 4 The diagram illustrates a circuit 400 for charged particle counting in a comparative embodiment. Circuit 400 may be one of a plurality of circuits, each of which is provided for a corresponding sensing element in an array detector. Circuit 400 may be configured to process a signal generated from sensing element 411. Sensing element 411 may be configured to generate a response to a charged particle event. A charged particle event may include an electron arrival event. For example, in response to an incident electron arriving at sensing element 411, sensing element 411 may be configured to generate a charge or current due to the energy of the incident electron. The charge or current may be generated within the sensing element and may be fed to a circuit device connected to the sensing element. In some cases, the circuit device may be integrated with the sensing element.

[0059] like Figure 4 As shown, circuit 400 includes an input stage 410, a threshold detector 420, a memory cell multiplexer 430, a memory cell array 440, a converter 450, and a control unit 490. Array 440 may include a plurality of memory cells, including a first memory cell 441, a second memory cell 442, and so on, up to, for example, an Nth memory cell 449. Memory cells 441 to 449 may include charge storage cells.

[0060] Input stage 410 can be configured to extract substantially all of the charge from sensing element 411 quickly after charge generation. Threshold detector 420 can be configured to detect the signal level of the incoming current from sensing element 411 and determine that a charged particle arrival event has occurred. Threshold detector 420 can be configured to detect the start or stop of a charged particle arrival event and trigger the recording of information from sensing element 411.

[0061] The circuit 400 may also include a memory cell multiplexer 430 configured to selectively connect the output of the input stage 410 to a plurality of memory cells 441-449 of the memory cell array 440. Each memory cell may be configured to integrate the signal from the output of the input stage 410. Integration may refer to the process of obtaining the cumulative value of charge or current over time (e.g., the area under a curve). Integration may begin when the threshold detector 420 indicates that an arrival event has begun, and may end when the threshold detector 420 indicates that an arrival event has ended. The output of the individual memory cells may be connected to a converter 450, such as an analog-to-digital converter (ADC).

[0062] The circuit 400 can be configured to interrogate the memory cells of the array 440 after the integration in the memory cells is completed. Interrogation can refer to obtaining information from the memory cells, such as obtaining a voltage value used to determine, for example, the energy level of an electron arrival event. When the detector is operating, integration and interrogation can be ongoing. The integration results stored in the memory cells can be interrogated, and the counting results can be sent to the control unit 490. Such operations can occur at the sensing element level. Therefore, separate integration and interrogation processes can be performed for all sensing elements of the detector. The data can be processed and sent to the upper control unit of the detector. The upper control unit can be configured to determine the electron count based on data from the lower control unit (e.g., the control unit 490 at the sensing element level of the detector).

[0063] The control unit 490 may be configured to perform various functions associated with the circuit 400. For example, the control unit 490 may be configured to: (i) control the operation of the sense element level circuitry, (ii) generate data based on the detection results of electron arrival events, (iii) communicate with an upper-level control unit (not shown), and (iv) communicate with adjacent control units in adjacent sense element level circuits that are similar to or the same as, for example, the circuit 400.

[0064] Further discussion of electronic counting circuitry can be found in International Application No. PCT / EP2021 / 068676 (incorporated herein by reference in its entirety) and U.S. Provisional Application No. 63 / 408,755 (incorporated herein by reference in its entirety).

[0065] Figure 4 The analog pipeline and memory cell array architecture can be complex and expensive to manufacture. This increased complexity introduces an increased risk of failure. In addition to the cost and risk of failure, this architecture can have undesirably high power consumption within each sensing element-level readout circuit. Furthermore, circuit 400 may only be suitable for very low beam currents and may not be able to handle the high beam currents of conventional inspection operations.

[0066] Figure 5 FIG2 shows a simplified block diagram of a readout design of a sensing element level circuit 500 and its corresponding sensing element 511 consistent with an embodiment of the present disclosure. The sensing element 511 may be similar to, for example, Figure 3A-3C Any of the sensing elements 311-314 can be included. Sensing element 511 can be a charged particle sensing element configured to generate an electrical signal in response to a charged particle arrival event. The electrical signal can be, for example, charge, current, or voltage. In some embodiments, sensing element 511 can be a photon sensing element. In addition to various switches, transistors, and other circuit components, sensing element level circuit 500 can also include: a threshold circuit 519, a digitizing unit array 540, and a sensing element level control unit 590.

[0067] The threshold circuit 519 may be configured to conduct current from the sensing element 511 to the digitizing unit array 540. The threshold circuit 519 may include, for example, a switch K 01 and solid-state current control device SSCCD. When the switch K is closed by, for example 01 When enabled, the solid-state current control device SSCCD can be enabled to turn on and conduct current from the sensing element 511 when the signal output from the sensing element 511 exceeds a predetermined trigger threshold. The trigger threshold can be, for example, a voltage, current, or other signal value. The solid-state current control device SSCCD can be configured to turn off again when the conducted current level drops below a predetermined holding current value. Both the trigger threshold and the holding current can be programmable. For example, the trigger threshold can be set to a value higher than the noise component in the circuit 500, or can be set to a value indicating that a charged particle arrival event has occurred at the sensing element 511. The holding current can be set to a value indicating that substantially all of the charge generated by the charged particle arrival event at the sensing element 511 has been passed to the digitizing unit array 540 by the threshold circuit 519. In some embodiments, the holding current can be a value corresponding to the trigger threshold. The holding current can be selected to substantially avoid the situation where it only passes the noise component in the detection signal.

[0068] The solid-state current control device (SSCCD) can be, for example, a silicon-controlled rectifier (SCR), a thyristor (thyristor), or another solid-state component configured to conduct current in one direction. For example, the solid-state current control device (SSCCD) can include four layers of alternating p-type and n-type materials. The solid-state current control device (SSCCD) can include, for example, a combination of a pnp bipolar transistor and an npn bipolar transistor. The solid-state current control device (SSCCD) can include a control gate (CG) configured to turn the solid-state control device on or off in response to a charged particle arrival event. For example, when charge is generated at an electrode of a sensing element due to, for example, a charged particle arrival event, the charge can generate a signal that produces a voltage value at the control gate (CG). If the voltage value at the control gate (CG) reaches or exceeds a trigger threshold, the control gate (CG) can trigger the solid-state current control device to an "on" state, in which current can flow through it. The solid-state current control device (SSCCD) can remain in this on state until the majority of the charge from the sensing element has been extracted and passed through the threshold circuit (519). When the current drops below the holding current value, the solid-state current control device SSCCD can be configured to switch from the on state to the off state, and further conduction can be prevented. Thus, the solid-state current control device SSCCD can be configured to self-deactivate after the current pulse drops below the holding current.

[0069] The solid-state current control device (SSCCD) can be configured to quickly and efficiently extract charge from the sensing element 511 when charged particles arrive. For example, the solid-state current control device (SSCCD) can be configured as a thyristor. When triggered to the on state, the thyristor can advantageously exhibit negative resistance, allowing current to increase at low voltages. This can enable rapid charge extraction from the sensing element 511, thereby increasing the speed of the detection process.

[0070] The on / off function of a thyristor or other SSCCD can be made simpler than existing configurations such as Figure 4 The threshold detector 420 and related control circuit device of the present invention are greatly improved. For example, the control gate of the thyristor can advantageously require a short response time (e.g., on the order of nanoseconds) to trigger the thyristor to the on state and begin conducting current. In this way, the charge extraction process can be initiated quickly after the charged particle arrival event occurs. Similarly, when the holding current threshold is met, the thyristor can be automatically turned off. Therefore, the thyristor can be configured to operate quickly with low power consumption and a simplified control architecture. In addition to thyristors or silicon-controlled rectifiers, other solid-state current control devices can also be configured to achieve these advantages.

[0071] The circuit 500 may include a transistor M 01 、M 02 and M03 The transistor may be, for example, a MOSFET or other transistor and may be configured as, for example, a common-gate amplifier. The common-gate amplifier arrangement may be used to stabilize the voltage value in the circuit 500 and its associated sensing element 511. In some embodiments, the transistor M may be omitted. 01 、M 02 or M 03 .

[0072] Transistor M 01 It can be arranged between the sensing element 511 and the threshold circuit 519. Transistor M 01 It can be configured to have a reference voltage V ref1 Common-gate amplifier MOSFET. Transistor M 01 The voltage at the anode of the sensing element 511 can be stabilized. As a result, the bias voltage across the sensing element can be stabilized. By introducing the transistor M 01 , which can minimize the speed and parasitic capacitance changes caused by bias voltage fluctuations during normal operation. Transistor M 01 It can also minimize the presence of residual charge in the sensing element during operation. 01 The resulting common-gate amplifier can also perform the function of a charge extractor. During the detection of charged particles, unwanted electrical effects such as parasitic capacitance can cause fluctuations in the charge extraction current. 01 It can have a low input impedance. This can help to better extract charge from the sensing element 511 and reduce the influence of parasitic capacitance in the sensing element on the detection result. 01 Similarly, transistor M 02 It can be configured to have a reference voltage V ref2 Common-gate amplifier MOSFET. Transistor M 02 The fluctuation on the cathode side of the solid-state current control device SSCCD can be stabilized.

[0073] Transistor M 03 and switch K 02 A charge release path from the sensing element 511 may be formed. For example, the switch K 02 The circuit element M may be, for example, an analog switch configured to selectively pass or block the flow of charge based on a control signal from the control unit 590. 03 M may optionally be included, for example as a current or voltage buffer. 03 It can be configured to have a reference voltage V ref1 When the sensing element 511 is not used, the switch K 02It can be closed to drain any charges generated at the sensing element 511 so that they do not accumulate.

[0074] Threshold circuit 519 can pass current to input bus 512. Input bus 512 can be coupled to storage capacitor C 01 and each analog input I of the digitizing units 541-549 in the digitizing unit array 540 in . Storage capacitor C 01 Together, the array 540 of digitizers can be configured to store and process charged particle detection events as digitally readable information. For example, as described below, the digitizers of the array 540 can be configured to continuously receive and process charge associated with one or more charged particle arrival events. When a currently operating digitizer reaches a predetermined storage capacity, it can activate the next digitizer to continue storing and processing charge from one or more charged particle arrival events.

[0075] During this process, the storage capacitor C 01 Can act as a storage buffer to provide continuous and uninterrupted processing of charged particle detection events. Any signal charge extracted from the sensing element 511 that is not immediately moved to the signal digitization unit can first be stored in the storage capacitor C 01 When the storage capacitor in the digitizing unit becomes available, the charge can be transferred from the storage capacitor C 01 The data is then transferred to the digitizing unit. In this way, signal loss can be minimized and detector accuracy can be improved.

[0076] In addition, the storage capacitor C can be monitored 01 , and adjust its capacitance as needed. For example, a reference voltage generator ( Figure 5 A voltage comparator (not shown) is provided to detect the voltage across the storage capacitor C during normal detection operation. 01 Whether the voltage at the terminal of exceeds the upper threshold. If the threshold is exceeded, an overflow flag or other alarm can be generated to indicate that the sensing element stage circuit 500 is not configured to process the complete input signal it is receiving under the current setting. This can indicate that the detection result contains an error. For example, the overflow flag can indicate that not all currents from the output of the sensor 511 are successfully processed by the digitizing unit array 540. The overflow information can include, for example, the first type, the second type, or other categories of overflow information disclosed in U.S. Publication No. 2019 / 0379682 (which is incorporated herein by reference in its entirety).

[0077] Storage capacitor C 01 There may be an adjustable capacitance to correct this error. If overflow occurs, the sensing element stage control unit 590 may add a capacitor to the storage capacitor C01 Send a control signal to increase its capacitance. Storage capacitor C 01 A storage capacitor array may also be included. The storage capacitor arrays may be coupled to each other via, for example, an interconnect switch matrix. In this configuration, capacitance adjustment may be achieved by selectively adding and removing capacitors via the switch matrix. A second voltage comparator and a second reference voltage generator having a second predefined value may also be provided. The second voltage comparator and the second reference voltage generator may be used to detect a voltage across the storage capacitor C. 01 If, within a predefined interval after the sensing element stage circuit 500 is enabled, the voltage across the capacitor C 01 If the voltage of the storage capacitor C 01 The capacitance of the storage capacitor C may be reduced. 01 A control signal is sent to reduce its capacitance. Thus, the capacitance can be increased or decreased to optimize the performance of each individual sensing element-level circuit. This adjustment can also be controlled at other levels of the control architecture, such as the detector-level control unit.

[0078] The digitizing unit array 540 may include a plurality of digitizing units, such as digitizing units 541, 542, etc., up to 549. The digitizing unit 549 may be the Nth digitizing unit in the array. In other words, the array 540 may generally include any number of digitizing units, where the digitizing unit 549 represents the final digitizing unit in the array 540. Each digitizing unit may include a plurality of inputs and outputs. For example, each digitizing unit may include: an analog signal input I in , enable signal input EN I ; Enable signal output EN O ; Bypass input BP; operating state output OP; first reset signal input R1; second reset signal input R2; and reset signal output R O .

[0079] Analog signal input I of the digitizing unit in The device may be configured to receive an electrical signal from the sensing element 511 via the threshold circuit 519 and the input bus 512 and pass the electrical signal to an internal circuit device ( Figure 51). For example, the internal circuit arrangement may include a storage capacitor. The operating status output OP may be configured to output a detection result signal from the digitizing unit to the control unit 590. The operating status output OP may include information about the energy stored in the storage capacitor. For example, the signal at the operating status output OP may indicate that the digitizing unit has been charged to its predetermined capacity by the incoming detection signal. Alternatively, the operating status output OP may be used by the control unit 590 to read the residual energy level stored in the digitizing unit, as discussed further below.

[0080] Enable signal input EN I Can be configured to receive an enable signal. Enable signal input EN I Enable signal can be passed to internal circuit devices ( Figure 5 (not shown), the internal circuit device enables the digitization unit to start receiving and processing charge. For example, in the enabled state, the internal circuit device of the digitization unit can be configured to receive and store the signal from the sensing element 511. The enable signal output EN O A further enable signal input EN may be configured to pass a further enable signal to the next digitizing unit in the array I For example, the enable signal output EN of the digitization unit 541 O The enable signal may be passed to the enable signal input EN of the next digitizing unit 542 I When the digitizing unit is to be activated for signal detection, the digitizing unit can be activated via the enable signal input EN I Receive the enable signal. When the next digitization unit needs to be activated, the digitization unit can also output EN via the enable signal. O For example, after the digitizing unit 541 is charged to a predetermined level by the detection signal from the sensing element 511, the digitizing unit 541 may output an EN via the enable signal. O Send an enable signal to the digitizing unit 542. The enable signal input EN of each digitizing unit I Can be coupled to the enable signal output EN of the immediately preceding digitizing unit O This arrangement forms a ring structure of digitizing units so that they can continuously activate each other in successive signal processing cycles. The enable signal input EN of the first digitizing unit 541 I The enable signal output EN of the Nth digitizing unit 549 can be coupled to the enable signal output EN of the Nth digitizing unit 549 through the intermediate logic gate XOR O , thus completing the ring structure.

[0081] The enable signal EN is output OAfter sending an enable signal to activate the next digitizing unit, the digitizing unit may be in an inactive state. In the inactive state, the digitizing unit may not be configured to receive additional charge from the sensing element 511. However, in the inactive state, the digitizing unit may perform other functions, such as storing charge or generating an output signal.

[0082] The reset circuit may include a first reset input R1, a second reset input R2 and a reset output R O The reset circuit can enable the internal circuit device (not shown) to reset the digitizing unit to an initial state. For example, the initial state can be an inactive state in which the digitizing unit is ready to be activated by the enable signal input EN. I For example, resetting the digitizing unit to the initial state may include releasing any charge stored in the digitizing unit, such as the charge in the storage capacitor, and stopping its enable signal output EN. O When the digitizing unit receives a first reset signal at the first reset input R1 or a second reset signal at the second reset input R2, a reset operation may occur. The first reset signal may be received from the reset output R O Output. For example, the digitizing unit 541 can send the enable signal to the digitizing unit 542 in the “forward direction” while sending the reset output signal to the digitizing unit 549 in the “reverse direction”. The digitizing unit 542 will not be able to detect the digitizing unit until the digitizing unit it enables completes its own detection period and outputs the reset output signal from its own reset output R. O This arrangement ensures that the digitizing unit currently used for signal detection will not be reset before its enable signal input EN I The enable signal continues to be received until the enable signal is no longer needed.

[0083] The digitizing unit bypass input BP may be configured to receive a bypass signal and activate the bypass circuitry of its digitizing unit ( Figure 5 (not shown in FIG. 3 ). For example, when the bypass circuit device is activated, the digitization unit can be placed in a bypass state. In the bypass state, the digitization unit may not be configured for signal detection. For example, the digitization unit may not be configured to receive or store charge from the sensing element 511 in the bypass state. The digitization unit can be configured to forward any enable signal to the next digitization unit instead of using the enable signal to activate its own circuit device. Similarly, the bypassed digitization unit can be configured to pass the first reset signal back to the previous digitization unit instead of using the reset signal to reset its own circuit device.

[0084] A digitizer unit can be bypassed, for example, if it is not functioning properly or if fewer digitizer units are needed. For example, when the frequency of charged particle arrival events is low enough that not all digitizer units are needed, it may be necessary to bypass unnecessary digitizer units to isolate their circuitry, minimize parasitics, and reduce power consumption. Furthermore, the bypass function can be used when a digitizer unit has detected and stored a signal from a charged particle arrival event, but that signal has not yet been processed by the signal processing circuitry. In this case, the digitizer unit can remain inactive until its signal has been processed and the digitizer unit is reset to its initial state, in which it is ready to be enabled again by another enable signal.

[0085] The logic gate XOR can be configured as, for example, an XOR or other logic gate device. The logic gate XOR can be configured to output EN based on the left input from the control unit 590 or the enable signal from the final digitizing unit 549 in the array 540. O The right input of the first digitizing unit 541 in the array 540 is activated. For example, the logic gate XOR can be configured to Figure 5 The left and right inputs shown receive binary signals represented by either 0 or 1. The logic gate XOR can be configured to output a signal value of 1 only when its inputs are different. For example, when both the left and right inputs are 1 or both are 0, the logic gate XOR may not output a signal value of 1. However, when the first input is 1 and the other input is 0, the logic gate XOR can be configured to output a signal value of 1. The logic gate XOR can be used to initiate and repeat a cycle of signal detection in the array 540, as discussed further below. The logic gate XOR can be part of the control unit 590.

[0086] The control unit 590 may be configured for bidirectional data flow. The control unit 590 may be configured for various functions and may be similar to, for example, Figure 1 The control unit 109 or Figure 2The control unit 290 of the embodiment of the present invention is a control unit 290. The control unit 590 can be configured to control the sensing element 511 and the digitizing units 541-549. The control unit 590 can be configured to receive and process inputs from the outputs of the digitizing units. For example, the control unit 590 can be configured to receive an operating status signal from the operating status output OP. The control unit 590 can be configured to generate an output signal and send it to the input of the digitizing unit. For example, the control unit 590 can be configured to send a digitizing unit bypass signal to the bypass input BP and a second reset signal to the second reset input R2. The control unit 590 may include additional inputs and outputs not shown here. For example, the additional inputs and outputs can functionally couple the control unit 590 to the sensing element 511, the detector-level data and control circuitry, and other sensing element-level readout circuitry of adjacent sensing elements.

[0087] The above-mentioned input, output and other components are now used to describe the embodiments consistent with the present disclosure. Figure 5 The detection operation of the circuit 500 can be performed in a detector such as Figure 2 The electron detection device 244 of the electron beam tool 104. The detector can be, for example Figure 1 1. Alternatively, the operation may be performed on another electronic detector or another type of detector, such as a proton, photon, or other detector. Thus, while the embodiments may discuss the operation and elements from an electronic perspective, it should be understood that other embodiments are possible.

[0088] When the sensing element 511 is enabled to detect a signal, the control unit 590 may place the sensing element 511 in a sensing state. For example, the control unit 590 may turn off the switch K 02 To disconnect the sensing element 511 from the charge release path. The control unit can also close the switch K 01 , so that the threshold circuit 519 can conduct the current from the sensing element 511. For example, the switch K 01 Closing the control gate CG can short the control gate CG to the anode of the solid-state current control device SSCCD, thereby changing the way it responds to the signal it receives at its anode. This allows the solid-state current control device SSCCD to be triggered when the signal (such as a voltage value) from its associated sensing element exceeds a predetermined trigger threshold. When the solid-state current control device SSCCD is triggered, it can act as a switch to quickly conduct charge from the anode to the cathode. The SSCCD can remain in the on state until most of the charge from the sensing element is extracted and simultaneously transferred to the storage capacitor C 01, signal digitizing units 541 - 549 , or both. When the current flowing through the SSCCD drops below the holding current, it can self-deactivate by switching from the on state to the off state.

[0089] The control unit 590 can also output a signal value 1 to the left input of the logic gate XOR as a start signal. Because the digitizing unit 549 is in the initial state, it is not currently output by the enable signal EN. O The signal value 1 is output to the right input of the logic gate XOR. Therefore, the enable signal output EN of the digitizing unit 549 is O Resulting in an output of a signal value of 0 (wherein a signal value of 0 may represent no signal or a binary signal value other than 1). Because the left and right inputs of the logic gate XOR are different, the logic gate XOR may input the enable signal EN to the digitizing unit 541. I The output signal value 1 is used as the enable signal. Later, when the digitizing unit 541 outputs the enable signal from the enable signal output EN O The enable signal input EN transmitted to the next digitizing unit (such as digitizing unit 542) I , the control unit 590 may stop outputting the signal value 1 to the left input of the logic gate XOR so that the left input receives the signal value 0. For example, the control unit 590 may determine that the digitizing unit 541 has output the enable signal based on the operation status output signal OP from the digitizing unit 541.

[0090] When the enable signal input EN of the digitizing unit 541 I Upon receiving an enable signal from logic gate XOR, the digitizing unit is enabled to receive and store charge from sensing element 511. For example, the enable signal may close an internal switch within digitizing unit 541 to allow current to pass to an internal storage capacitor. All other digitizing units in array 540 may remain in an inactive state, such as an initial state or a bypass state.

[0091] When even a charged particle landing occurs at the sensing element 511, an analog signal may be generated and transmitted to the analog signal input I of the currently enabled digitizing unit (such as the digitizing unit 541). in The digitizing unit 541 may remain enabled, for example, until it completes a charge measurement event. For example, the charge measurement event may be completed when the storage capacitor of the digitizing unit is charged to a predetermined level by the signal from the sensing element 511. The completion of the charge measurement event may trigger the enable signal output EN of the digitizing unit 541. O The operation state signal may be changed from 1 to 0 in some embodiments.

[0092] The operational status signal can indicate to the control unit 590, for example, that a charge measurement event in the digitization unit 541 has completed. The control unit 590 can use this signal to determine whether a predetermined amount of charge has been stored in the digitization unit 541. The predetermined amount of charge can correspond to the amount of charge stored in the storage capacitor when the voltage of the storage capacitor reaches a predetermined reference voltage. Thus, the operational status output signal OP from each digitization unit can represent a digitized signal indicating a charged particle beam measurement (e.g., a predetermined unit measurement of charged particle beam intensity, a predetermined unit measurement of charged particle arrival at the sensing element 511, etc.) in predetermined increments. The predetermined increments can be the same for all digitization units in the array 540, or different for some or all of the digitization units. The predetermined increments can be summed, for example, by the control unit 590, a detector stage control unit, or other signal processing circuitry. This sum can indicate the total charged particle beam measurement at the sensing element 511 during the measurement period. This sum can be expressed, for example, as a total beam intensity, or can indicate an estimated or actual charged particle count at the sensing element 511.

[0093] Along with the generation of the operating status signal, the completion of the charge measurement event can trigger another signal in the digitizing unit 541. For example, the enable signal output EN of the digitizing unit 541 can be O A signal is generated at the digitizing unit 542, which is used to input the enable signal EN I The enable signal is transmitted to activate the next digitizing unit 542. Alternatively, if the digitizing unit 542 is in the bypass state, the enable signal can pass directly through the digitizing unit 542 and reach the next digitizing unit until the enable signal reaches a digitizing unit that is not in the bypass state. In addition, a signal can be generated to prohibit the digitizing unit 541 from receiving additional charge. For example, the signal can turn off the internal switch within the digitizing unit 541 to prevent additional current from flowing to the internal storage capacitor. Finally, the reset output R O A reset signal is generated at . The reset signal can be passed to the first reset input R1 of the previous digitizing unit (such as the Nth digitizing unit 549). Alternatively, if the Nth digitizing unit 549 is in the bypass state, the reset signal can pass directly through the Nth digitizing unit 549 and reach, for example, the first reset input R1 of another digitizing unit until the reset signal reaches a digitizing unit that is not in the bypass state. In this way, when a charge measurement event is completed at the first digitizing unit, the first digitizing unit can be automatically disabled, the next digitizing unit can be automatically enabled, and the previous digitizing unit can be automatically reset to an initial state.

[0094] Disabled digitizing units can also be reset to their initial state directly from the controller. For example, the control unit 590 can output a reset signal to the second reset input R2. Direct reset can be used when, for example, a measurement process has ended and one or more digitizing units have not yet been reset.

[0095] This process can cycle through the digitizing units in the array 540 until it reaches the final digitizing unit 549. When the final digitizing unit 549 outputs EN from its enable signal O When the enable signal is output, it can be transmitted to the right input of the logic gate XOR as a signal value 1. Because the control unit has stopped delivering the value 1 signal as described above, the left input receives the signal value 0, and the logic gate XOR sends the enable signal input EN to the first digitizing unit 541. I A new enable signal is output. In this way, the array 540 of digitizing units 541-549 may be repeatedly cycled through the detection process as the control unit 590 repeatedly collects measurements from the operating state output OP.

[0096] In some embodiments, the process of obtaining measurement results can be further simplified. For example, the control unit 590 can measure the charged particle beam process by counting the complete cycles of the digitizing unit array 540, rather than processing the operating status output OP at each digitizing unit. For example, the operating status output OP from, for example, the Nth digitizing unit 549 can indicate that the charge measurement event at each non-bypassed unit in the array has been completed. Alternatively, the control unit 590 can be configured to output an enable signal EN from, for example, a logic gate XOR or an enable signal of the Nth digitizing unit 549. O To this end, the logic gate XOR or enable signal output EN of the Nth digitizing unit 549 is O Can comprise the other output (not shown) being coupled to control unit 590.In this way, control unit can count the number of cycles of array 540 when receiving any operating state signal from operating state output OP, until need residual (residual) count (as follows).When the number of cycles of array 540 is known, can realize the complete charged particle beam measurement of sensing element 511.For example, control unit (such as control unit 590) can multiply the number of complete array cycles by the number of digitization units that are not bypassed in array 540, and add residual (for example, the number of residual detections remaining in the final partial cycle of array 540).In order to obtain residual, control unit 590 can obtain the operating state of all non-bypassed units.Use this cycle counting system, only final residual cycle needs to count the measurement of each digitization unit.

[0097] Furthermore, the cycle length can be modified as required by bypassing a certain number of digitisation units. This allows the cycle length to be adjusted depending on operating conditions such as the beam current. For example, when the beam current is high, the frequency at which charged particles arrive at the sensing element may be higher, which may result in a higher frequency of complete detection cycles. In order to reduce the cycle frequency, more signal detection units may be put into operation to increase the cycle length. However, when the frequency of charged particle arrival events is low (e.g. due to a lower beam current), not so many signal detection units may be needed. In this case, the cycle length can be shortened by bypassing some of the signal detection units to reduce power consumption. In addition to the cycle length, the capacitance of each digitisation unit may also be adjusted. For example, increasing the capacitance of the storage capacitor or stopping the stored voltage reference value within the digitisation unit may reduce the frequency of complete detection cycles for a given beam current value.

[0098] The sensor-level readout circuit design 500 can provide a simple and cost-effective architecture configured to passively trigger the sequential activation of a series of digitizing cells without requiring complex control circuitry to manage the process. The architecture of circuit 500 can achieve high processing speeds with low cost, low power consumption, and low risk of failure. Furthermore, circuit 500 can have a sufficiently high dynamic range. For example, circuit 500 can be used in the extremely low beam current range using electron counting detectors, as well as in high beam current applications using conventional detectors.

[0099] Figure 6 Another advantage of a sense element level readout circuit design consistent with embodiments of the present disclosure is illustrated. Figure 6 A simplified example diagram of an array of sensing elements 611 is depicted, each coupled to a sensing element level readout circuit 600. The sensing elements 611 may be similar to, for example, Figure 5 The sensing element 511 of FIG. 611 may be similar to, for example, Figure 3A-3C Each sensing element level readout circuit 600 may be similar to, for example, Figure 5 The sensing element level readout circuit 500 is shown.

[0100] Each of the sensing element level readout circuits 600 may be directly coupled to a high speed processing and control unit, such as a detector level processing and control module or other signal processing and control circuitry. The high speed processing and control unit may in turn be coupled to a high speed interface that may be operatively coupled to a system control unit, such as Figure 1 Controller 109 or Figure 2Image processing system 290. Unlike comparable systems such as electronic counting detectors or conventional detectors, there can be no switch matrix or other interconnections between adjacent sensing elements, either analog or digital. Each sensing element can operate independently, and the data from each sensing unit can be individually accessible to the detector-level processing and control unit. This is achieved through the greatly simplified signal processing and control architecture described above.

[0101] In addition to the advantages described above, it may also allow the size of each sensing element 511 or 611 to be larger than in, for example, a pixelated electron counting detector. This is because the size of the sensing element is no longer limited by the need to isolate individual charged particle arrival events to prevent temporal overlap between two or more events in a single processing channel. Instead, the charge can be measured in predefined increments based on the digitizing units within each sensing element level circuit 600. Therefore, for a given active area size on a charged particle detector, embodiments of the present disclosure allow the total number of sensing elements and corresponding sensing element level circuits to be reduced. This, as well as the other advantages described above, can reduce the design complexity of the charged particle readout circuitry, thereby reducing development risk, shortening development cycles, and reducing development costs.

[0102] Figure 7 A simplified diagram illustrating an example of the internal circuitry of the digitizing unit 741 consistent with some embodiments of the present disclosure is shown. For example, the digitizing unit 741 may be Figure 5

[0066] One possible implementation of the digitizing units 541-549 of FIG. The various circuit elements and other components of the digitizing unit 741 will be discussed in turn.

[0103] The digitizing unit 741 may further include an enabling circuit and a bypass circuit, which are configured to convert the digitizing unit 741 from an initial state to, for example, an enabling state or a bypass state based on an enabling or bypass signal. For example, in the initial state, the switch K 11 Can be set in Figure 7 shown in the higher position, and switch K 12 Can be set to a lower position. Switch K 13 and K 14 Each can be set to the off state. In addition, the digitizing unit 741 may have previously received a reset signal so that when the switch K 14 Before being placed in the off state, switch K 14 Close to draw power from the storage capacitor C 11 Finally, the reset switch K 15 and K 16 Each can be set in Figure 7 Lower position shown.

[0104] In the enabled state, the digitizing unit 741 may be activated for detection. In the enabled state, the digitizing unit 741 may be ready to transfer charge from its associated sensing element (such as Figure 5 The sensing unit 511 in the embodiment is transferred to the storage capacitor C 11 The enabling circuit may include: an enabling signal input EN I ; Enable signal output EN O ; and switch K 11 and K 12 The bypass circuit may include a bypass signal input BP and a switch K 11 and K 12 In some embodiments, the bypass circuit can be omitted.

[0105] The enabling circuit can be configured to put the digitizing unit 741 into the enabling state from the initial state. 11 In the initial configuration, the enable signal can be input from the enable signal EN I Transmitted to AND gate G 12 The enable signal may be, for example, a high level voltage, or a digital value "1". For example, if the digitizing unit 741 is an array (such as Figure 5 The first digitizing unit in the array 540) can be the enable signal from a logic gate (such as a logic gate XOR or Figure 5 ) has a signal value of 1. Alternatively, the enable signal may come from a previous digitizing unit in the digitizing unit array (such as Figure 5 The enable signal output EN of the Nth digitizing unit 549) O In the initial state, the voltage comparator A 11 Can be configured as an AND gate G 12 The lower input of the AND gate G outputs another signal value 1, making the AND gate G 12 The AND gate G receives a signal value of 1 from both its upper and lower inputs. 12 Then a signal can be output to close another switch K 13 , to activate the charge detection circuit to put the digitizing unit 741 into an enabled state. For example, switch K 13 The closing of the analog input I in Passed to transistor M 11 and storage capacitor C 11 .

[0106] Alternatively, the bypass circuit of the digitizing unit 741 may receive the bypass signal at the bypass signal input BP. For example, the bypass signal may be provided by a control unit such as Figure 5 The bypass signal can make the switch K 11 and K12 from Figure 7 The position shown is reversed so that switch K 11 is in the lower position and switch K 12 In this case, the enable signal will not be fed from the enable signal input EN I Passed to AND gate G 12 Instead, the enable signal will pass through switch K 12 Passed to the enable signal output EN O And leaves the digitizing unit 741. In addition, the AND gate G 12 The upper input can be switched via switch K 11 The new position of is connected to signal ground or logic 0, so that the upper input receives, for example, a signal value of 0. Thus, it is possible to prevent switch K 13 Closed, and the charge detection circuit can be disabled. The bypass signal can further enable switch K 15 and K 16 from Figure 7 In this state, the switch K 15 Then the OR gate G 13 The right input of the switch is coupled to signal ground or logic 0. 16 The reset output R O Passes any incoming reset signal back to the previous digitizing unit.

[0107] The digitizing unit 741 may further include a charge detection circuit configured to receive current and store up to a predetermined amount of charge. The charge detection circuit may include: an analog switch K 13 ; Transistor M 11 (such as a common-gate amplifier as described above); a storage capacitor C 11 ; Voltage comparator A 11 ; NOT door G 11 ; and AND gate G 12 .

[0108] When the switch K 13 The digitizing unit 741 is enabled, and the sensing element (such as Figure 5 The charged particle arrival event at the sensing element 511 of the trigger threshold circuit (such as Figure 5 When the 519) in the circuit is turned on, the charge can be in Delivered to the storage capacitor C 11 And store. Storage capacitor C 11 The signal at can be output to the voltage comparator A 11 In some embodiments, the storage capacitor C 11 Can form an amplifier or buffer A11 In some embodiments, the storage capacitor C 11 Can be a separate component. If the storage capacitor C 11 When the signal at the input reaches a predetermined level, the voltage comparator A 11 Can be configured to output a low-level voltage (or 0 as digital data).

[0109] Then, the 0 value signal can be input to the AND gate G 12 , operation status output OP and NOT gate G 11 When the signal value 0 is output to AND gate G 11 When the lower input is 13 Switching from the closed state to the open state may make the digitizing unit 741 unable to store the capacitor C 11 At the same time, the signal value 0 can be passed as an operating state signal to the operating state output OP to be sent to the control unit, for example Figure 5 This may indicate to the control unit that the digitizing unit 741 has completed the charge measurement event. For example, the operating status signal may indicate that the digitizing unit 741 has completed the charge measurement event according to the storage capacitor C. 11 The control unit can assign a time stamp to the indicated charge measurement event based on the signal from the operating status output OP. Finally, the signal value 0 can be detected at the NOT gate G 11 The value 1 signal can be converted to value 1 via switch K 12 Passed to the enable signal output EN O and reset output R O . Enable signal output EN O The signal at can be passed to the next enable signal input EN of the next digitizing unit in the array I , to activate the next digital unit to continue detecting current. Reset output R O The signal at may be passed to a previous first reset input R1 of a previous digitizing unit in the array to reset the previous digitizing unit.

[0110] Alternatively, the next digitizer unit in the array can be bypassed, in which case the enable signal can be passed through the next digitizer unit via the bypass circuit. This process can be repeated until the enable signal reaches a digitizer unit that is in an initial state and ready to be enabled. Similarly, the previous digitizer unit in the array can be bypassed, in which case the reset signal can be passed through the previous digitizer unit via the bypass circuit.

[0111] In this way, digitization units can be automatically selected and enabled quickly and continuously during the detection process. The sensing element level architecture according to the embodiments of the present disclosure can perform digitization unit selection and switching in a fast, simplified, and robust design. In addition, unneeded digitization units can be disabled to reduce power consumption in the system. For example, in a bypass digitization unit, the enable circuit, bypass circuit, or transistor M 11 Nonessential components can be powered down.

[0112] The digitizing unit 741 may further include a reset circuit configured to reset the digitizing unit to an initial state. The reset circuit may include: a first reset input R1; a second reset input R2; an OR gate G 13 , switch K 14 ; and reset output R O . The signal detection circuit can be reset to an initial state, for example, after its enable signal no longer needs to be input to the next digitizing unit, or when a disabled or bypassed digitizing unit is put back into operation. Alternatively, a reset signal can simply be sent to ensure that the digitizing unit is ready to be enabled. In some embodiments, the control unit can send a reset signal when the digitizing unit is a predetermined number of digitizing units downstream from the currently enabled digitizing unit. For example, when the downstream digitizing unit is five non-bypassed digitizing units away from the currently enabled digitizing unit, the control unit can send a reset signal to ensure that the signal detection is ready to be enabled. In some embodiments, the reset signal can be sent automatically by another digitizing unit.

[0113] When the reset signal is input to the first reset input R1 or the second reset input R2, the OR gate G 13 Can output a signal to close switch K 14 This can be provided for the storage capacitor C 11 Clear the path of charge. When the charge is removed from the storage capacitor C 11 is cleared, the voltage comparator A 11 The voltage at the lower input can drop to the reference voltage Vref 11 Then, the result value 1 outputted at the voltage comparator can make the NOT gate G 11 The enable signal output EN O This stops the enable signal input EN to the next digitizing unit. I At the same time, when the digital unit 741 is at its own enable signal input EN I When the enable signal is received at the AND gate G 12 The 1 output of the digitizing unit 741 can make it ready to be enabled again. After the reset is completed, the digitizing unit 741 is in the initial state again and is ready to be enabled when the enable signal input ENI Receive an enable signal.

[0114] The above circuits and components are provided as examples only to illustrate the signal detection circuit (such as Figure 5 In some embodiments, the same or similar functions can be implemented by other combinations of switches, logic components, amplifiers and other circuit elements. For example, in some embodiments, the AND gate G 12 Another logic gate may be included, such as OR, XOR, NOT, NAND, NOR, XNOR, etc. In such an embodiment, other circuit devices may be configured to provide logic gate G 12 Provide appropriate input so that it switches K in the desired manner 13 Or with switch K 13 Generally, in some embodiments of the present disclosure, a variety of different configurations may be employed to perform functions such as an enable circuit, a bypass circuit, a charge detection circuit, a readout circuit, and a reset circuit.

[0115] Figure 8 A diagram illustrating an example of an internal circuit arrangement of a digitizing unit 841 consistent with some embodiments of the present disclosure. For example, the digitizing unit 841 may be Figure 5 One possible implementation of the digitizing units 541-549 of FIG. The digitizing unit 841 may be similar to the digitizing unit 741 except for the following discussion.

[0116] The digitizing unit 841 can be used in the voltage comparator A 11 The output of the flip-flop circuit F 11 . Trigger F 11 It can be, for example, a D-type flip-flop circuit. In some embodiments, the flip-flop F 11 It can be another type of flip-flop, latch or other logic circuit. In the initial state, the flip-flop F 11 can be configured to output from the inverting Toward AND gate G 12 The lower input of the voltage comparator A outputs a signal value of 1. 11 Can be configured to trigger F 11 The clock input CLK outputs a 0 signal. The data input D can be configured to receive a constant signal value of 1. Therefore, in the initial state, the AND gate G 12 can be ready at the slave enable signal input EN O When the upper input receives another signal value 1 in the form of an enable signal, the switch K is closed. 13 And activate the charge detection circuit. The operation status output OP can also be output from the reverse The receiving signal value is 1. At the same time, the enable signal output EN O A 0 signal can be received from output Q.

[0117] When a charge measurement event occurs in the digitizing unit 841, the charge from the storage capacitor C 11 The signal exceeds the reference voltage Vref 11 When the voltage comparator A 11 You can send a trigger F 11 The clock input CLK outputs a signal value of 1. The rising signal edge at the clock input CLK in the process of changing from signal 0 to signal 1 can trigger the flip-flop F 11 Passes a constant signal value of 1 from the data input D to its output Q, and inverts the output becomes a signal value of 0. Therefore, the output from the inverted The signal value 0 can make the AND gate G 12 Disconnect switch K 13 to prevent additional charge from being transferred to the storage capacitor C 11 A signal value of 0 may additionally be passed to the operating status output OP to indicate completion of the charge measurement event at the digitizing unit 841. A signal value of 1 from the output Q may be passed as an enable signal to the enable signal output EN O , to activate the next non-bypassed digitizing unit.

[0118] The first reset input R1 of the digitizing unit 841 can be coupled to the OR gate G 13 Input of OR gate G 13 The output can not only be coupled to Figure 7 Switch K shown 14 , can also be coupled to the trigger F 11 When the OR gate outputs a signal value 1 based on the reset signal from the first reset input R1 to clear the input CLR, the flip-flop F 11 Can be configured to restore to an initial state. Similarly, from, for example, a control unit such as Figure 5 The same function can be achieved by sending a reset signal from the control unit 590) to the second reset input R2.

[0119] Set the trigger F 11 Adding the digitizing unit 841 can give a storage capacitor C 11 For example, since the clock input CLK is configured to react only to rising edges rather than signal values ​​1 or 0, the voltage comparator A 11 The output change from 1 to 0 does not change Q and Therefore, the storage capacitor C 11The pressure at the position reaches the predefined reference voltage Vref 11 Thereafter, subsequent fluctuations will not invert the output, causing errors in the operation of the digitizing unit 841.

[0120] Figure 9 is a flow chart illustrating a method 900 for charged particle detection consistent with an embodiment of the present disclosure. The method 900 may be implemented by, for example, a sensing element level circuit (such as a Figure 5 or Figure 6 The sensing element level circuit 500 or 600 may be executed by the sensing element level circuit. The sensing element level circuit may include circuit devices (eg, memory and processor) programmed to implement the method 900. A digitizing unit (such as Figure 7 or Figure 8 The digitizing unit 741 or 841 in the embodiment of the present invention can be operated according to the method 900. Processing consistent with the method 900 can be performed on a sensing element by sensing element basis. In the illustrated steps of the method 900, the ordered items outside the brackets (previous, first, next, additional) indicate the first loop of the method 900, while the ordered items inside the brackets indicate the second loop of the method 900.

[0121] At step 901, a sensing element circuit can be enabled to receive charge from a sensing element. For example, enabling the sensing element circuit can include enabling a threshold circuit to conduct current from the sensing element when the sensing element reaches a predetermined threshold. The threshold circuit can include a silicon controlled rectifier (SSCCD). The SSCCD can be, for example, a silicon controlled rectifier (SCR) or other thyristor. For example, a circuit enable signal can cause a switch to close, thereby shorting the control gate of the SSCCD to the anode of the SSCCD.

[0122] At step 902, a first digitizing unit may be activated from an initial state, such as by a unit enable signal. The first digitizing unit may be an array of digitizing units (such as Figure 5 The first non-bypassed digitizing unit in the array 540 of method 900 may be configured to receive a unit enable signal from, for example, a logic gate based on an initiation signal from a control unit. For example, the enable signal may close a switch to allow current to flow to a storage capacitor of the first digitizing unit. Alternatively, the first digitizing unit of method 900 may receive the unit enable signal from an enable signal output of a previous digitizing unit.

[0123] At step 903, the first digitizing unit may receive a detection signal from the sensing element. For example, when the detection signal from the sensing element reaches a predetermined trigger threshold, the SSCCD of the threshold circuit may be configured to turn on and begin conducting current to the digitizing unit. In some embodiments, method 900 may continue until the current passing through the SSCCD of the threshold circuit falls below a holding current value, causing the threshold circuit to turn off and stop conducting current.

[0124] The sensing element can be coupled to the analog signal input of the first digitizing unit via, for example, an input bus. The input bus can be coupled to each digitizing unit in the array and, for example, a storage buffer. Current from the sensing element can pass through the threshold circuit and the input bus to the storage capacitor of the first digitizing unit. The storage capacitor can continue to receive charge until the signal at the storage capacitor reaches a predefined value. When the signal at the storage capacitor reaches the predefined value, a voltage comparator (such as Figure 7 or Figure 8 A 11 ) or other circuit components can re-open the switch in step 902 so that no further current flows to the storage capacitor of the first digitizing unit. In some embodiments, the output of the voltage comparator can be coupled to, for example, a trigger circuit. The voltage comparator can also generate a plurality of signals discussed in steps 904-906 below.

[0125] At step 904, the output of the voltage comparator may include an operating state output signal. The operating state output signal may indicate to the control unit that a charge measurement event has occurred. For example, the control unit may generate a timestamp for counting charge measurement events based on the operating state output signal. The operating state output signal may represent a digitized signal that indicates a charged particle beam measurement in predetermined increments (e.g., a predetermined unit measurement of charged particle beam intensity, a predetermined unit measurement of charged particles arriving at the sensing element 511, etc.). The predetermined increment may correspond to when the voltage of the storage capacitor reaches a reference voltage (such as Figure 7 and Figure 8 Vref in 11 ) is the amount of charge stored in the storage capacitor when

[0126] At step 905, the output of the voltage comparator may include a cell enable signal for activating the next digitizing cell in the array. The cell enable signal may be generated substantially simultaneously with the generation of the operating state output signal. The cell enable signal may continue from the enable signal output of the first digitizing cell to the enable signal input of the next digitizing cell. At this point, the process may return to step 902 and repeat for the next digitizing cell, as shown in parentheses.

[0127] On the other hand, if the next digitizing unit is in the bypass state, the unit enable signal can be passed directly through the next digitizing unit along the bypass circuit to its own enable signal output. The unit enable signal can then be passed to another enable signal input of another digitizing unit. This can continue until the unit enable signal reaches a non-bypassed digitizing unit, at which point the non-bypassed digitizing unit can be enabled.

[0128] At step 906, the output of the voltage comparator may include a reset signal for resetting a previous digitizing unit in the array. For example, the previous digitizing unit may be a unit that provides a unit enable signal to the first digitizing unit. After the charge measurement event is completed at step 903, the unit enable signal from the previous digitizing unit is no longer needed. The reset signal may be input to a first reset input of the previous digitizing unit to reset the previous digitizing unit to an initial state. Alternatively, the previous digitizing unit may be reset by inputting a reset signal from the control unit to a second reset input of the previous digitizing unit.

[0129] As described above, the second loop of method 900 is illustrated by the language in brackets. In the second iteration of step 902, the next digitization unit may receive the unit enable signal sent by the first digitization unit in the first iteration of step 905. After the next digitization unit receives and processes the charge measurement event in the second iteration of step 903, the next digitization unit may generate additional enable signals in the second iteration of step 905 to activate additional digitization units in the array.

[0130] The timestamps or other data corresponding to the operational status output signals can be summed to determine a measurement value for the sensing element. For example, the sum can indicate the total charged particle beam measurement at the sensing element 511 during the measurement period. The sum can be expressed as, for example, a total beam intensity, or it can indicate an estimated or actual charged particle count at the sensing element 511 during the measurement period.

[0131] As an alternative to summing the individual charge measurement events, Figure 10 The method 1000 illustrates a cycle counting method consistent with an embodiment of the present disclosure. The method 1000 can be used, for example, in combination with the method 900. The method 1000 can be used for a cycle counting method by, for example, a control unit such as Figure 5 The detection cycles within the sampling period set by the control unit 590, the detector stage control unit or another control unit are counted.

[0132] In step 1001, the control unit may determine an operating status output (such as Figure 9The control unit 1000 may determine whether the digitizing unit generating the operating status output is a counting unit. The counting unit may be, for example, a digitizing unit that is used to determine whether a complete signal detection cycle has occurred in the digitizing unit array. For example, the first non-bypassed digitizing unit in the array, the last non-bypassed digitizing unit in the array, or both may be used as the counting unit. In general, any digitizing unit may be used as the counting unit. Alternatively, the method 1000 may include a logic gate XOR or a final enable signal output EN from, for example, the final digitizing unit in the array. O Receive individual cycle output signals. Furthermore, full or partial cycles can be determined by other detection units in the array. For example, if any digitizing unit other than the first or last digitizing unit acting as a counting unit has a low value, such as 0, at its operating status output OP, it can be determined that the cycle is not a full cycle. In this way, the control unit can count the number of cycles of the array without summing each operating status signal from the operating status output OP, unless a residual count is required.

[0133] If the detection does represent a complete cycle, the method 1000 may continue to step 1002 where a complete detection cycle timestamp is generated at the control unit. If the detection does not represent a complete cycle, the method may continue to step 1003.

[0134] At step 1003, the control unit may determine whether a sampling period has ended. The sampling period may be based on a predetermined timing setting, for example, set by the control unit. In some embodiments, the sampling period may correspond to a normal operating period of the charged particle beam device. In some embodiments, the sampling period may correspond to another timed interval. If the sampling period has not yet ended, the process continues as shown in step 1004. If the sampling period has ended, the method may continue to step 1005.

[0135] At step 1005, a residual can be counted and added to the complete detection cycle. The residual can include a timestamp from the operating status signal retained by the control unit from the last partial cycle of the digitization unit. For example, if the digitization unit array includes ten active units, each complete cycle represents ten charge measurement events. However, as described above, the sampling period may end midway through a complete detection cycle, for example, when only five digitization units have recorded a charge measurement event. In this case, the control unit can count the individual operating status output signals from the digitization units to produce an accurate count of charge measurement events. The complete cycles can be added to the residual to determine a complete count of charge measurement events. For example, in the example of ten units described above, the control unit can multiply the number of complete cycle counts by the number of active units in the array (ten) and then add the residual (five in the example described above). The sum of the complete cycles with the residual can represent the total number of charge measurement events during the sampling period. Method 1000 can be used to produce an accurate count of charge measurement events while minimizing the actual counting performed by the signal processing circuitry.

[0136] The data from all sensing element level circuits within the charged particle detector can be summed on a sampling period by sampling period basis. In this way, a detection result similar to or the same as the counting method described above can be generated.

[0137] Furthermore, by selecting the optimal number of digitizing cells in the array, method 1000 can be customized for the detection operation. Unnecessary digitizing cells can be powered down and bypassed using signal bypass circuitry. Furthermore, the value of each charge measurement event can be customized by varying the amount of charge stored within each digitizing cell during a single charge measurement event. This can be achieved, for example, by adjusting the capacitance of a storage capacitor or the voltage reference value of a voltage comparator.

[0138] As an alternative to counting method 1000, a higher-level control unit (such as a detector-level control unit) can obtain complete cycle timestamps for each sensing element-level circuit, for example, as they are generated. Thus, the detector can sum all complete cycle counts from each sensing element in the detector. Based on the sum of the cycle counts, a detection signal can be generated to produce a charged particle beam image.

[0139] A non-transitory computer readable medium consistent with embodiments of the present disclosure may be provided for storing instructions for a controller processor (e.g., Figure 1 Controller 109, Figure 2 Image processing system 290 or Figure 9The processor of the controller 904 in the embodiment of the present invention detects the charged particle beam according to the exemplary flow charts of Figures 13, 20, and 21 described above. For example, instructions stored in a non-transitory computer-readable medium can be executed by the circuitry of the controller to partially or fully perform methods 1300, 900, or 1000. Common forms of non-transitory media include, for example, a floppy disk, a flexible disk, a hard disk, a solid-state drive, a magnetic tape, or any other magnetic data storage medium, a compact disk read-only memory (CD-ROM), any other optical data storage medium, any physical medium having a pattern of holes, a random access memory (RAM), a programmable read-only memory (PROM), and an erasable programmable read-only memory (EPROM), a FLASH-EPROM or any other flash memory, a non-volatile random access memory (NVRAM), a cache, a register, any other memory chip or cartridge, and network versions thereof.

[0140] The embodiments of the present disclosure may also be described by the following terms:

[0141] 1. A method for reducing noise in a charged particle detector, comprising:

[0142] causing a threshold circuit of the charged particle detector to enter an on-state or an off-state in response to an output of a sensing element of the charged particle detector; and

[0143] An image is generated based on the charge received at the sensing element level readout circuitry of the charged particle detector, wherein

[0144] The on-state allows the threshold circuit to conduct current from the sense element to a first digitizing unit of the sense element-level readout circuit; and

[0145] The off state prevents the threshold circuit from conducting current from the sense element to the first digitizing unit of the sense element-level readout circuitry.

[0146] 2. The method of clause 1, wherein the threshold circuit comprises a solid-state current controlled device (SSCCD).

[0147] 3. The method of clause 2, wherein the solid-state current control device comprises a thyristor.

[0148] 4. The method of clause 2, wherein causing the threshold circuit to enter an on-state or an off-state comprises closing an enable switch to couple a control gate of the SSCCD to an anode of the SSCCD in response to receiving a circuit enable signal at the threshold circuit.

[0149] 5. The method of clause 1, further comprising placing the threshold circuit in an on state in response to a voltage or current from the sensing element exceeding a predetermined trigger voltage or current of the threshold circuit.

[0150] 6. The method of clause 5, wherein the value of the predetermined trigger voltage is determined based on preventing noise from being transmitted to the first digitizing unit.

[0151] 7. The method of clause 1, further comprising placing the threshold circuit in the off state in response to current from the sensing element falling below a predetermined holding current of the threshold circuit.

[0152] 8. The method of clause 1, further comprising:

[0153] storing charge from the sensing element in a buffer storage device of the sensing element level readout circuit; and

[0154] The charge is transferred from the buffer storage device to the digitizing unit of the sense element level readout circuitry.

[0155] 9. The method according to clause 8, further comprising:

[0156] An overflow signal is generated in response to the buffer store exceeding a buffer store threshold.

[0157] 10. The method of clause 9, further comprising:

[0158] A capacitance of the buffer storage element is adjusted in response to the overflow signal.

[0159] 11. The method of clause 1, further comprising:

[0160] storing the charge from the sensing element in a storage element of the first digitizing unit, and

[0161] An operating status output signal is generated at an operating status output of the first digitizing unit in response to the stored charge reaching a predetermined amount, the operating status signal indicating completion of a charge measurement event at the first digitizing unit.

[0162] 12. The method according to clause 11, further comprising:

[0163] In response to the stored charge at the first digitizing unit reaching the predetermined amount, a first unit enable signal is generated from the first digitizing unit to a next digitizing unit of the sensing element stage circuit to enable the next digitizing unit to store charge from the sensing element.

[0164] 13. The method according to clause 11, further comprising:

[0165] In response to the stored charge at the first digitizing unit reaching the predetermined amount, a switch in the first digitizing unit is opened to prevent additional charge from being transferred to the storage element of the first digitizing unit.

[0166] 14. The method according to clause 11, further comprising:

[0167] A reset signal is generated from the first digitizing unit to a previous digitizing unit in response to the stored charge at the first digitizing unit reaching the predetermined amount.

[0168] 15. The method according to clause 14, further comprising:

[0169] A previous enable signal from the previous digitizing unit is terminated in response to receiving the reset signal from the first digitizing unit.

[0170] 16. The method of clause 11, further comprising:

[0171] generating a time stamp at a control unit based on the operating status output signal; and

[0172] Select the image pixel sampling period,

[0173] wherein generating the image based on the charge received at the sensing element-level readout circuitry of the charged particle detector comprises:

[0174] assigning detection events to the image pixel sampling periods based on the timestamps; and

[0175] A total number of detection events allocated to the image pixel sampling period is counted.

[0176] 17. The method according to clause 11, further comprising:

[0177] A determination is made based on the operating status signal that a plurality of digitizing units of the sense element stage circuit have completed a charge measurement event.

[0178] 18. The method of clause 1, wherein the sensing element comprises a PIN diode.

[0179] 19. A sensing element level circuit for a charged particle detector, comprising:

[0180] a threshold circuit configured to enter an on-state or an off-state in response to an output of a sensing element of the charged particle detector; and

[0181] A first digitizing unit; wherein

[0182] The on-state allows the threshold circuit to conduct current from the sense element to the first digitizing unit of the sense element stage circuit; and

[0183] The off state prevents the threshold circuit from conducting current from the sense element to the first digitizing unit of the sense element stage circuitry.

[0184] 20. The sense element stage circuit of clause 19, wherein the threshold circuit comprises a solid state current controlled device (SSCCD).

[0185] 21. The sensing element stage circuit of clause 20, wherein the solid-state current control device comprises a thyristor.

[0186] 22. The sensing element stage circuit of clause 20, wherein the threshold circuit is configured to enter an on-state or an off-state by closing an enable switch to couple a control gate of the SSCCD to an anode of the SSCCD in response to receiving a circuit enable signal at the threshold circuit.

[0187] 23. The sense element stage circuit of clause 19, wherein the threshold circuit is configured to enter the on-state in response to a voltage or current from the sense element exceeding a predetermined trigger voltage or current of the threshold circuit.

[0188] 24. The sensing element stage circuit of clause 23, wherein the value of the predetermined trigger voltage is determined based on preventing noise from being passed to the first digitizing unit.

[0189] 25. The sense element stage circuit of clause 19, wherein the threshold circuit is configured to enter the off state in response to a current from the sense element falling below a predetermined holding current of the threshold circuit.

[0190] 26. The sensing element level circuit of clause 19, further comprising:

[0191] A buffer storage device is configured to store charge from the sensing element in the sensing element level circuit and transfer the charge to the digitizing unit of the sensing element level circuit.

[0192] 27. The sense element level circuit of clause 26, wherein the sense element level circuit is further configured to:

[0193] An overflow signal is generated in response to the buffer store exceeding a buffer store threshold.

[0194] 28. The sense element level circuit of clause 27, wherein the sense element level circuit is further configured to:

[0195] A capacitance of the buffer storage element is adjusted in response to the overflow signal.

[0196] 29. The sensing element level circuit of clause 19, further comprising:

[0197] The storage element of the first digitizing unit is configured to store the charge from the sensing element;

[0198] The first digitizing unit is configured to generate an operating status output signal at an operating status output of the first digitizing unit in response to the stored charge reaching a predetermined amount, the operating status signal indicating completion of a charge measurement event at the first digitizing unit.

[0199] 30. The sense element stage circuit of clause 29, wherein the first digitizing unit is configured to:

[0200] In response to the stored charge at the first digitizing unit reaching the predetermined amount, a first unit enable signal is generated from the first digitizing unit to a next digitizing unit of the sensing element stage circuit to enable the next digitizing unit to store charge from the sensing element.

[0201] 31. The sense element stage circuit of clause 29, wherein the first digitizing unit is configured to:

[0202] In response to the stored charge at the first digitizing unit reaching the predetermined amount, a switch in the first digitizing unit is opened to prevent additional charge from being transferred to the storage element of the first digitizing unit.

[0203] 32. The sense element stage circuit of clause 29, wherein the first digitizing unit is configured to:

[0204] A reset signal is generated from the first digitizing unit to a previous digitizing unit in response to the stored charge at the first digitizing unit reaching the predetermined amount.

[0205] 33. The sensing element-level circuit of clause 32, wherein the previous digitization unit is configured to:

[0206] A previous enable signal from the previous digitizing unit is terminated in response to receiving the reset signal from the first digitizing unit.

[0207] 34. The sense element level circuit of clause 29, wherein the sense element level circuit is further configured to:

[0208] generating a time stamp at a control unit based on the operating status output signal; and

[0209] Select the image pixel sampling period, and

[0210] An image is generated based on charge received at the sensing element level circuitry of the charged particle detector by assigning detection events to the image pixel sampling periods based on the timestamps and counting a total number of detection events assigned to the image pixel sampling periods.

[0211] 35. The sense element level circuit of clause 29, wherein the sense element level circuit is further configured to:

[0212] A determination is made based on the operating status signal that a plurality of digitizing units of the sense element stage circuit have completed a charge measurement event.

[0213] 36. The sensing element stage circuit of clause 19, wherein the sensing element comprises a PIN diode.

[0214] 37. A digitizing unit for a charged particle detector, comprising:

[0215] an analog signal input configured to receive charge from the sensing element;

[0216] an enable signal input configured to receive a first unit enable signal for activating the digitizing unit to store charge transferred from the analog signal input;

[0217] an operating status output configured to output an operating status signal representing a charge detection event of the stored charge; and

[0218] an enable signal output configured to output a second enable signal to a further digitizing unit of the charged particle detector; and

[0219] The reset signal input is configured to receive a reset signal, where the reset signal is used to reset the digitizing unit to an initial state.

[0220] 38. The digitizing unit according to clause 37, wherein the digitizing unit is configured to:

[0221] The operating state output signal is generated at the operating state output in response to the stored charge reaching a predetermined amount.

[0222] 39. The digitizing unit according to clause 37, wherein the digitizing unit is further configured to:

[0223] The second enable signal is generated in response to the stored charge reaching a predetermined amount to enable the further digitizing unit to store charge from the sensing element.

[0224] 40. The digitizing unit of clause 37, wherein the digitizing unit is further configured to:

[0225] In response to the stored charge reaching a predetermined amount, a switch in the digitizing unit is opened to prevent additional charge from being transferred to a storage element of the digitizing unit.

[0226] 41. The digitizing unit according to clause 37, further comprising:

[0227] a reset signal output configured to output a second reset signal to the reset signal input of the previous digitizing unit;

[0228] The digitizing unit is further configured to generate the second reset signal in response to the stored charge reaching a predetermined amount.

[0229] 42. The digitization unit of clause 41, wherein the digitization unit is configured to terminate the second enable signal in response to receiving the reset signal at the reset signal input.

[0230] 43. A non-transitory computer-readable medium storing a set of instructions executable by at least one processor of a charged particle beam apparatus to cause the apparatus to perform a method comprising:

[0231] enabling a charged particle detector to cause a threshold circuit of the charged particle detector to enter an on-state or an off-state in response to an output of a sensing element of the charged particle detector; and

[0232] An image is generated based on the charge received at the sensing element level readout circuitry of the charged particle detector, wherein

[0233] The on-state allows the threshold circuit to conduct current from the sense element to a first digitizing unit of the sense element-level readout circuit; and

[0234] The off state prevents the threshold circuit from conducting current from the sense element to the first digitizing unit of the sense element-level readout circuitry.

[0235] It should be understood that the embodiments of the present disclosure are not limited to the exact configurations described above and shown in the accompanying drawings, and that various modifications and changes may be made without departing from the scope thereof. The present disclosure has been described in conjunction with various embodiments, and other embodiments of the present invention will become apparent to those skilled in the art by consideration of the specification and practice of the invention disclosed herein. It is intended that the description and examples be regarded as exemplary only, with the true scope and spirit of the invention being indicated by the following claims.

Claims

1. A sensing element level circuit for a charged particle detector, comprising: a threshold circuit configured to enter an on-state or an off-state in response to an output of a sensing element of the charged particle detector; as well as a first digitization unit; in The on-state allows the threshold circuit to conduct current from the sense element to the first digitizing unit of the sense element stage circuit; as well as The off state prevents the threshold circuit from conducting current from the sense element to the first digitizing unit of the sense element stage circuitry.

2. The sense element stage circuit of claim 1, wherein the threshold circuit comprises a solid state current controlled device (SSCCD). 3 . The sensing element stage circuit of claim 1 , wherein the threshold circuit is configured to enter the on-state in response to a voltage or current from the sensing element exceeding a predetermined trigger voltage or current of the threshold circuit. 4 . The sensing element stage circuit according to claim 3 , wherein a value of the predetermined trigger voltage is determined based on preventing noise from being transferred to the first digitizing unit. 5 . The sense element stage circuit of claim 1 , wherein the threshold circuit is configured to enter the off state in response to a current from the sense element falling below a predetermined holding current of the threshold circuit.

6. The sensing element level circuit according to claim 1 , further comprising: A buffer storage device is configured to store charge from the sensing element in the sensing element level circuit and transfer the charge to the digitizing unit of the sensing element level circuit.

7. The sensing element level circuit of claim 6 , wherein the sensing element level circuit is further configured to: An overflow signal is generated in response to the buffer store exceeding a buffer store threshold.

8. The sensing element level circuit according to claim 1 , further comprising: The storage element of the first digitizing unit is configured to store the charge from the sensing element; The first digitizing unit is configured to generate an operating status output signal at an operating status output of the first digitizing unit in response to the stored charge reaching a predetermined amount, the operating status signal indicating completion of a charge measurement event at the first digitizing unit.

9. The sensing element-level circuit according to claim 8, wherein the first digitizing unit is configured to: In response to the stored charge at the first digitizing unit reaching the predetermined amount, a first unit enable signal is generated from the first digitizing unit to a next digitizing unit of the sensing element stage circuit to enable the next digitizing unit to store charge from the sensing element.

10. The sensing element stage circuit according to claim 8, wherein the first digitizing unit is configured to: In response to the stored charge at the first digitization unit reaching the predetermined amount, a switch in the first digitization unit is opened to prevent additional charge from being transferred to the storage element of the first digitization unit.

11. The sensing element stage circuit according to claim 8, wherein the first digitizing unit is configured to: A reset signal is generated from the first digitizing unit to a previous digitizing unit in response to the stored charge at the first digitizing unit reaching the predetermined amount.

12. The sensing element-level circuit according to claim 11 , wherein the previous digitization unit is configured to: A previous enable signal from the previous digitizing unit is terminated in response to receiving the reset signal from the first digitizing unit.

13. The sensing element level circuit of claim 8, wherein the sensing element level circuit is further configured to: generating a time stamp at a control unit based on the operating status output signal; and Select the image pixel sampling period, and An image is generated based on charge received at the sensing element level circuitry of the charged particle detector by assigning detection events to the image pixel sampling periods based on the timestamps and counting a total number of detection events assigned to the image pixel sampling periods.

14. The sensing element level circuit of claim 8, wherein the sensing element level circuit is further configured to: A determination is made based on the operating status signal that a plurality of digitizing units of the sense element stage circuit have completed a charge measurement event.

15. A non-transitory computer-readable medium storing a set of instructions executable by at least one processor of a charged particle beam apparatus to cause the apparatus to perform a method comprising: enabling a charged particle detector to cause a threshold circuit of the charged particle detector to enter an on-state or an off-state in response to an output of a sensing element of the charged particle detector; as well as An image is generated based on the charge received at the sensing element level readout circuitry of the charged particle detector, wherein The on-state allows the threshold circuit to conduct current from the sense element to a first digitizing unit of the sense element-level readout circuit; and The off state prevents the threshold circuit from conducting current from the sense element to the first digitizing unit of the sense element-level readout circuitry.

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