Solid-state imaging device and imaging device

Abstract

A solid-state imaging device (100) is provided with a pixel array (110) in which a plurality of pixels (111) are arranged in a matrix. The plurality of pixels (111) are provided with: a photoelectric conversion unit (10) that converts received light into signal charges; and capacitance storage units (21, 22, 23, 24, 25), the plurality of pixels (111) being configured so as to be able to output M pixel signals having different gains, and the plurality of pixels (111) being controlled so as to output N (N is an integer of 2 or more and less than M) pixel signals among the M pixel signals.

Description

Technical Field

[0001] The present disclosure relates to a solid-state imaging device. Background Art

[0002] Conventionally, there is known a solid-state imaging device that expands the dynamic range by including a pixel array in which a plurality of pixels outputting a plurality of pixel signals having mutually different gains are arranged in a matrix (see, for example, Patent Documents 1 and 2).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: International Publication No. 2023 / 062947

[0006] Patent Document 2: Japanese Patent Application Laid-Open No. 2022-180791 Summary of the Invention

[0007] Problems to be solved by the invention

[0008] Conventionally, in a solid-state imaging device having the above structure, in order to perform correlated double sampling (also called CDS) processing on multiple pixel signals output from each pixel and generate an image for one frame, a readout time equal to the number of pixel signals × two frames is required.

[0009] On the other hand, solid-state imaging devices are expected to achieve both a higher frame rate and optimal dynamic range control.

[0010] Therefore, the purpose of the present disclosure is to provide a solid-state imaging device, etc., which has a pixel array in which a plurality of pixels are arranged in a matrix and output M (M is an integer greater than 3) pixel signals having different gains, and can achieve a higher frame rate than before.

[0011] Means for solving problems

[0012] A solid-state imaging device according to one embodiment of the present invention comprises a pixel array having a plurality of pixels arranged in a matrix, wherein the plurality of pixels comprises: a photoelectric conversion unit for converting received light into signal charge; and a capacitor storage unit, wherein the plurality of pixels are configured to output M pixel signals having different gains, and the plurality of pixels are controlled to output N (N is an integer greater than 2 and less than M) pixel signals out of the M pixel signals.

[0013] A solid-state imaging device according to one embodiment of the present invention comprises: a pixel array having a plurality of pixels arranged in a matrix; and an AD converter arranged in each column of the pixel array, wherein the plurality of pixels are configured to output M pixel signals having different gains, and the AD converter converts at least one of the M pixel signals into a digital signal having fewer bits than the other pixel signals.

[0014] A solid-state imaging device according to one embodiment of the present invention comprises: a pixel array having a plurality of pixels arranged in a matrix; and an AD converter arranged in each column of the pixel array, the plurality of pixels comprising: a photoelectric conversion unit for converting received light into signal charge; and a capacitor storage unit, the plurality of pixels being configured to output M pixel signals having different gains, the plurality of pixels being controlled to output N (N is an integer greater than 2 and less than M) pixel signals out of the M pixel signals, and the AD converter converting at least one pixel signal out of the N pixel signals into a digital signal having fewer bits than the other pixel signals.

[0015] An imaging device according to one embodiment of the present disclosure is an imaging device including the above-mentioned solid-state imaging device, wherein the solid-state imaging device sequentially outputs image data based on the N pixel signals output by the plurality of pixels, and further includes a system control unit, which sequentially outputs a gain designation signal based on the image data sequentially output from the solid-state imaging device, the gain designation signal designating which N pixel signals are to be output by the plurality of pixels in control of the plurality of pixels by the solid-state imaging device, wherein the solid-state imaging device sequentially controls the plurality of pixels based on the gain designation signal sequentially output from the system control unit.

[0016] An imaging device according to one embodiment of the present disclosure is an imaging device including the above-mentioned solid-state imaging device, wherein the solid-state imaging device sequentially outputs image data based on the N pixel signals output by the plurality of pixels, and further includes a system control unit, which sequentially outputs gain designation signals for each of the plurality of pixel blocks based on the image data sequentially output from the solid-state imaging device, wherein the gain designation signals for each of the plurality of pixel blocks designate which of the N pixel signals is to be output by the first pixel included in each of the plurality of pixel blocks in the control of each of the plurality of pixel blocks performed by the solid-state imaging device, and the solid-state imaging device sequentially controls the first pixel included in each of the plurality of pixel blocks based on the gain designation signals for each of the plurality of pixel blocks sequentially output from the system control unit.

[0017] Effects of the Invention

[0018] According to a solid-state imaging device of one embodiment of the present disclosure, there is provided a solid-state imaging device having a pixel array in which a plurality of pixels are arranged in a matrix and output M pixel signals having different gains, and which is capable of achieving both a high frame rate and optimal dynamic range control. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a block diagram showing a configuration example of the solid-state imaging device according to the first embodiment.

[0020] Figure 2 This is a circuit diagram showing a structural example of a pixel according to the first embodiment.

[0021] Figure 3 This is a correspondence table showing the correspondence between M gains, the on / off states of M-1 connection transistors, and FD holding signal charges corresponding to pixel signals in the first embodiment.

[0022] Figure 4 This is a table showing an example of the time required for outputting pixel signals and the time required for AD conversion in the first embodiment.

[0023] Figure 5 This is a table showing an example of the time required for outputting pixel signals and the time required for AD conversion in the first embodiment.

[0024] Figure 6 This is a graph showing an example of the relationship between the SN of the pixel signal and the dynamic range corresponding to each of N gains in the first embodiment.

[0025] Figure 7 This is a graph showing an example of the relationship between the SN of the pixel signal and the dynamic range corresponding to each of N gains in the first embodiment.

[0026] Figure 8 This is a table showing another example of the time required for outputting pixel signals and the time required for AD conversion according to the first embodiment.

[0027] Figure 9 This is a table showing another example of the time required for outputting pixel signals and the time required for AD conversion according to the first embodiment.

[0028] Figure 10 This is a block diagram showing a configuration example for shortening the time required for AD conversion in the solid-state imaging device according to the first embodiment.

[0029] Figure 11 This is a circuit diagram showing an example of a circuit configuration for shortening the time required for AD conversion according to the first embodiment.

[0030] Figure 12This is a diagram showing the relationship between the illuminance and exposure time in the first embodiment, and the value of a digital signal obtained by AD-converting a pixel signal.

[0031] Figure 13 This is a diagram illustrating an example of a method for improving the SN of a pixel signal according to the first embodiment.

[0032] Figure 14 This is a circuit diagram showing a configuration example of a pixel according to the first embodiment in the case where M=3 and N=2.

[0033] Figure 15 This is a correspondence table showing the correspondence between three gains, the on / off states of two connection transistors, and FD holding signal charges corresponding to pixel signals in the first embodiment when M=3 and N=2.

[0034] Figure 16 This is a timing chart showing an example of pixel control timing according to the first embodiment when M=3 and N=2.

[0035] Figure 17 This is a timing chart showing an example of pixel control timing according to the first embodiment when M=3 and N=2.

[0036] Figure 18 This is a block diagram showing a configuration example of an imaging device according to the first embodiment.

[0037] Figure 19 This is a timing chart showing an example of the timing of exposure control performed by the system control unit in the first embodiment.

[0038] Figure 20 This is a timing chart showing how pixels output pixel signals according to the first embodiment.

[0039] Figure 21 This is a block diagram showing a configuration example of a solid-state imaging device according to a second embodiment.

[0040] Figure 22 This is a circuit diagram showing a structural example of a pixel according to the second embodiment.

[0041] Figure 23 This is a circuit diagram showing a configuration example of a pixel according to Embodiment 2 in the case where M=3 and N=2.

[0042] Figure 24 This is a timing chart showing an example of pixel control timing according to the second embodiment when M=3 and N=2.

[0043] Figure 25 This is a timing chart showing an example of pixel control timing according to the second embodiment when M=3 and N=2.

[0044] Figure 26 This is a block diagram showing a configuration example of a solid-state imaging device according to a third embodiment.

[0045] Figure 27 This is a block diagram showing a configuration example of an imaging device according to a third embodiment. DETAILED DESCRIPTION

[0046] (How one method of the present disclosure was obtained)

[0047] As described above, solid-state imaging devices are expected to achieve both high frame rate and optimal dynamic range control.

[0048] Therefore, the inventors have conducted intensive experiments and studies on a solid-state imaging device having a pixel array in which a plurality of pixels are arranged in a matrix and output M pixel signals having different gains, in order to achieve a balance between optimal dynamic range control and increased frame rate.

[0049] As a result, the inventors have come to the following understanding: by selecting N (N is an integer greater than 2 and less than M) pixel signals less than M from M pixel signals and outputting them to each pixel, it is possible to achieve both optimal dynamic range control and high frame rate speed.

[0050] Furthermore, the inventors conducted further experiments and studies based on this knowledge and conceived of the following solid-state imaging device and the like disclosed herein.

[0051] A solid-state imaging device according to one embodiment of the present invention comprises a pixel array having a plurality of pixels arranged in a matrix, wherein the plurality of pixels comprises: a photoelectric conversion unit for converting received light into signal charge; and a capacitor storage unit, wherein the plurality of pixels are configured to output M pixel signals having different gains, and the plurality of pixels are controlled to output N (N is an integer greater than 2 and less than M) pixel signals out of the M pixel signals.

[0052] According to the solid-state imaging device with the above configuration, the pixel signals output by each pixel are N pixel signals, which are smaller than M. Therefore, the pixel signal readout time is shortened compared to a conventional solid-state imaging device in which each pixel outputs all M pixel signals.

[0053] Therefore, according to the solid-state imaging device with the above configuration, a solid-state imaging device including a pixel array in which a plurality of pixels outputting M pixel signals having different gains are arranged in a matrix can achieve both a higher frame rate and optimal dynamic range control compared to conventional devices.

[0054] Furthermore, the capacitance storage unit may include an overflow capacitance storage unit for storing signal charges overflowing from the photoelectric conversion unit, and a floating diffusion unit for converting the signal charges converted by the photoelectric conversion unit into a voltage.

[0055] According to the solid-state imaging device having the above configuration, signal charges overflowing from the photoelectric conversion portion are accumulated in one or more overflow capacitance accumulation portions.

[0056] Therefore, according to the solid-state imaging device having the above configuration, it is possible to capture an image of a subject with a higher illumination intensity than a solid-state imaging device having a configuration not including one or more overflow capacitance storage units.

[0057] In addition, the multiple pixels may also include: a transfer transistor, one of the source and the drain of the transfer transistor is connected to the photoelectric conversion part, and the other of the source and the drain of the transfer transistor is connected to one of the floating diffusion parts; and a first connection transistor, one of the source and the drain of the first connection transistor is connected to the overflow capacitor storage part, and the other of the source and the drain of the first connection transistor is connected to one of the floating diffusion parts.

[0058] In addition, the control of the multiple pixels may also include shutter control for causing the multiple pixels to perform a shutter action, and the shutter control is performed on the multiple pixels independently of the control for causing the multiple pixels to output N pixel signals out of the M pixel signals, so that the period during which the overflow capacitor storage unit accumulates charge is substantially the same as the period during which the photoelectric conversion unit accumulates charge.

[0059] Furthermore, the plurality of pixels may further include an overflow transistor, one of a source and a drain of the overflow transistor being connected to the photoelectric conversion unit, and the other of the source and the drain of the overflow transistor being connected to the overflow capacitance storage unit.

[0060] Furthermore, there may be a plurality of floating diffusion portions, and each of the plurality of pixels may further include one or more second connection transistors connected to the plurality of floating diffusion portions.

[0061] In addition, the plurality of pixels may further include a first reset transistor, one of the source and the drain of the first reset transistor being connected to the other of the source and the drain of the first connection transistor, and the other of the source and the drain of the first reset transistor being connected to a first pixel power supply.

[0062] In addition, the plurality of pixels may further include a second reset transistor, one of the source and the drain of the second reset transistor being connected to the other of the source and the drain of the first connection transistor, and the other of the source and the drain of the second reset transistor being connected to a second pixel power supply having a voltage different from that of the first pixel power supply.

[0063] Furthermore, the plurality of pixels may be controlled so that the plurality of pixels output N pixel signals consisting of mutually adjacent gains among the M pixel signals.

[0064] A solid-state imaging device according to one embodiment of the present invention comprises: a pixel array having a plurality of pixels arranged in a matrix; and an AD converter arranged in each column of the pixel array, wherein the plurality of pixels are configured to output M pixel signals having different gains, and the AD converter converts at least one of the M pixel signals into a digital signal having fewer bits than the other pixel signals.

[0065] In the solid-state imaging device with the above structure, the AD converter converts at least one of the M pixel signals into a digital signal with a smaller number of bits than the other pixel signals. Therefore, compared to conventional solid-state imaging devices that do not convert at least one pixel signal into a digital signal with a smaller number of bits than the other pixel signals, the AD conversion time is shortened.

[0066] Therefore, according to the solid-state imaging device with the above configuration, a solid-state imaging device including a pixel array in which a plurality of pixels outputting M pixel signals having different gains are arranged in a matrix can achieve both a higher frame rate and optimal dynamic range control compared to conventional devices.

[0067] In addition, it is also possible that there is a selection detection circuit configured in each column of the pixel array, M pixel signals are input from the pixel array to the selection detection circuit, the selection detection circuit detects at least one pixel signal and at least one correction pixel signal from the M pixel signals and outputs them to the AD converter, the AD converter converts the pixel signal into a digital signal, and converts the correction pixel signal into a first correction digital signal having a smaller number of bits than the digital signal.

[0068] In addition, it may also be provided with an HDR (High Dynamic Range) synthesis circuit, the AD converter outputs the digital signal and the first correction digital signal to the HDR synthesis circuit, the HDR synthesis circuit multiplies the value of the first correction digital signal by a coefficient to generate a second correction digital signal, and adds the value obtained by multiplying the value of the digital signal by the first mixing ratio and the value obtained by multiplying the value of the second correction digital signal by the second mixing ratio, and the sum of the first mixing ratio and the second mixing ratio is 1.

[0069] A solid-state imaging device according to one embodiment of the present invention comprises: a pixel array having a plurality of pixels arranged in a matrix; and an AD converter arranged in each column of the pixel array, the plurality of pixels comprising: a photoelectric conversion unit for converting received light into signal charge; and a capacitor storage unit, the plurality of pixels being configured to output M pixel signals having different gains, the plurality of pixels being controlled to output N (N is an integer greater than 2 and less than M) pixel signals out of the M pixel signals, and the AD converter converting at least one pixel signal out of the N pixel signals into a digital signal having fewer bits than the other pixel signals.

[0070] According to the solid-state imaging device with the above configuration, the pixel signals output by each pixel are N pixel signals, which are smaller than M. Therefore, the pixel signal readout time is shortened compared to a conventional solid-state imaging device in which each pixel outputs all M pixel signals.

[0071] Furthermore, in the solid-state imaging device with the above configuration, the AD converter converts at least one of the N pixel signals into a digital signal having fewer bits than the other pixel signals. Therefore, compared to conventional solid-state imaging devices that do not convert at least one pixel signal into a digital signal having fewer bits than the other pixel signals, the AD conversion time is shortened.

[0072] Therefore, according to the solid-state imaging device with the above configuration, a solid-state imaging device including a pixel array in which a plurality of pixels outputting M pixel signals having different gains are arranged in a matrix can achieve both a higher frame rate and optimal dynamic range control compared to conventional devices.

[0073] In addition, the pixel array may also include: a plurality of pixel blocks; and a control circuit, so that each of the plurality of pixel blocks independently selects and outputs N pixel signals among the M pixel signals, the plurality of pixel blocks being composed of a plurality of first pixels arranged in a matrix, and the plurality of first pixels being part of the plurality of pixels.

[0074] An imaging device according to one embodiment of the present disclosure is an imaging device including the above-mentioned solid-state imaging device, wherein the solid-state imaging device sequentially outputs image data based on the N pixel signals output by the plurality of pixels. The imaging device further includes a system control unit, which sequentially outputs a gain designation signal based on the image data sequentially output from the solid-state imaging device, the gain designation signal designating which N pixel signals are to be output by the plurality of pixels in control of the plurality of pixels by the solid-state imaging device, and the solid-state imaging device sequentially controls the plurality of pixels based on the gain designation signal sequentially output from the system control unit.

[0075] According to the imaging device having the above configuration, similar to the solid-state imaging device according to one embodiment of the present disclosure, it is possible to achieve both a higher frame rate and optimal dynamic range control than conventional devices.

[0076] An imaging device according to one embodiment of the present disclosure is an imaging device including the above-mentioned solid-state imaging device, wherein the solid-state imaging device sequentially outputs image data based on the N pixel signals output by the plurality of pixels, and further includes a system control unit, which sequentially outputs gain designation signals for each of the plurality of pixel blocks based on the image data sequentially output from the solid-state imaging device, the gain designation signals for each of the plurality of pixel blocks specifying which N pixel signals are to be output by the first pixel included in each of the plurality of pixel blocks in the control of each of the plurality of pixel blocks performed by the solid-state imaging device, and the solid-state imaging device sequentially controls the first pixel included in each of the plurality of pixel blocks based on the gain designation signals for each of the plurality of pixel blocks sequentially output from the system control unit.

[0077] According to the imaging device having the above configuration, similarly to the solid-state imaging device according to one embodiment of the present disclosure, it is possible to achieve both a higher frame rate and optimal dynamic range control than conventional devices.

[0078] Hereinafter, a specific example of a solid-state imaging device or the like according to one embodiment of the present disclosure will be described with reference to the accompanying drawings. The embodiments shown here each represent a specific example of the present disclosure. Therefore, the numerical values, shapes, constituent elements, configurations and connection methods of constituent elements, as well as steps (processes) and the order of steps shown in the following embodiments are examples and are not intended to limit the present disclosure. In addition, each figure is a schematic diagram and is not necessarily a strict illustration. In each figure, substantially the same structure is marked with the same figure mark, and repeated descriptions are omitted or simplified.

[0079] (Implementation 1)

[0080] <Configuration Example 1 of Solid-State Imaging Device>

[0081] Figure 1 This is a block diagram showing a configuration example of the solid-state imaging device 100 according to the first embodiment.

[0082] like Figure 1 As shown, the solid-state imaging device 100 includes a pixel array 110 , a vertical scanning circuit 120 , a control circuit 130 , an HDR (High Dynamic Range) synthesis circuit 140 , a plurality of vertical signal lines 150 , and a plurality of AD converters 160 .

[0083] The pixel array 110 is configured by arranging a plurality of pixels 111 in a matrix of L (L is an integer greater than or equal to 2) rows and K (K is an integer greater than or equal to 2) columns.

[0084] The pixel 111 includes a photoelectric conversion unit 10 that converts received light into signal charges ( Figure 1 Not shown, see below Figure 2 ), that is, generating and accumulating signal charge according to the received light; and M (M is an integer greater than or equal to 3) capacitor storage units ( Figure 1 Not shown, refer to the following Figure 2 , corresponding to Figure 2 The capacitor storage units 21 to 25 in FIG. 1 are used to store signal charges generated by the photoelectric conversion unit 10, and the pixel 111 is configured to output M pixel signals having different gains. Details of the pixel 111 will be described later.

[0085] The plurality of vertical signal lines 150 are wires extending in the column direction of the pixel array 110. The plurality of vertical signal lines 150 correspond one-to-one to each column of the pixel array 110. That is, there are K vertical signal lines 150.

[0086] The plurality of vertical signal lines 150 are respectively connected to L pixels 111 arranged in the column direction in corresponding columns, and transmit pixel signals output from any one of the L pixels 111 to each of the plurality of AD converters 160 .

[0087] The control circuit 130 controls the vertical scanning circuit 120 , the HDR synthesis circuit 140 , and the plurality of AD converters 160 .

[0088] The vertical scanning circuit 120 is controlled by the control circuit 130 to cause each of the plurality of pixels 111 to output N (N is an integer greater than or equal to 2 and less than M) pixel signals out of M pixel signals.

[0089] At this time, the vertical scanning circuit 120 is controlled by the control circuit 130, so that each of the multiple pixels 111 converts the signal charge corresponding to the reset state of the pixel 111 into a reference voltage corresponding to each gain and outputs a pixel signal representing the converted reference voltage, and converts the signal charge generated by the photoelectric conversion unit 10 during the exposure period into a voltage corresponding to each gain and outputs a pixel signal representing the converted voltage.

[0090] Hereinafter, a series of operations from causing the pixel 111 to convert signal charge into a voltage corresponding to each gain to outputting a pixel signal indicating the converted voltage is referred to as pixel signal readout corresponding to each gain.

[0091] The pixel signal corresponding to each gain includes a reset component and a signal component. In each gain, the pixel signal representing the reference voltage is the reset component, and the pixel signal representing the voltage converted from the signal component generated by the photoelectric converter 10 during the exposure period is the signal component.

[0092] Furthermore, the vertical scanning circuit 120 may have a part or all of the functions of the control circuit 130 .

[0093] The plurality of AD converters 160 correspond one-to-one to the K vertical signal lines 150 . That is, the number of the plurality of AD converters 160 is K.

[0094] The K AD converters 160 are respectively connected to corresponding vertical signal lines 150 .

[0095] The K AD converters 160 AD-convert the K analog pixel signals output from the K pixels 111 into K digital pixel signals in row units via the K vertical signal lines 150 , and output the K digital pixel signals after AD conversion to the HDR synthesis circuit 140 .

[0096] Furthermore, during AD conversion, correlated double sampling processing is performed to remove reset noise during pixel signal readout by calculating the difference between the AD conversion results of the reset component pixel signal and the signal component pixel signal.

[0097] The HDR synthesis circuit 140 generates an image by performing HDR synthesis on the pixel signals output from the plurality of AD converters 160 .

[0098] After the K vertical signal lines 150 converge, the solid-state imaging device 100 with the above structure performs AD conversion in parallel on the K pixel signals output from the K pixels 111 in one row via the K vertical signal lines 150 using K AD converters 160, and outputs the pixel signals of the K digital signals after AD conversion for one row from the K AD converters 160 to the HDR synthesis circuit 140.

[0099] The solid-state imaging device 100 repeats the above operation within one horizontal scanning period until the readout of N pixel signals corresponding to gain x to gain x+N-1 (x is an integer greater than 1 and less than M-N+1) and the AD conversion of the N pixel signals are completed.

[0100] The solid-state imaging device 100 also repeats the above-described operation sequentially row by row from row 1 to row L in the pixel array 110 in units of one horizontal scanning period.

[0101] The solid-state imaging device 100 having the above-described configuration sequentially outputs image data based on N pixel signals outputted from the plurality of pixels 111 .

[0102] In this embodiment, the solid-state imaging device 100 is described as repeating the above-mentioned operation row by row from row 1 to row L in the pixel array 110 in units of one horizontal scanning period. However, the solid-state imaging device 100 may repeat the above-mentioned operation row by row from row 1 to row L in the pixel array 110 for two or more rows at a time, or the solid-state imaging device 100 may operate in a global shutter manner in which pixel signals are read out in the same time period in all rows.

[0103] In addition, in this embodiment, it is assumed that the number of vertical signal lines and the number of AD converters 160 are both K, and the vertical signal lines 150 and the AD converters 160 are described as corresponding one-to-one. However, it is also possible that the number of vertical signal lines 150, or AD converters 160, or both exceeds K, and the correspondence between the vertical signal lines 150 and the AD converters 160 is not one-to-one.

[0104] <Pixel Structure Example 1>

[0105] Figure 2 111 is a circuit diagram showing a structural example of the pixel 111.

[0106] As described above, the pixel 111 includes the photoelectric conversion unit 10 and M capacitor storage units (corresponding to Figure 2 Capacitor storage unit 21 to capacitor storage unit 25).

[0107] The photoelectric conversion unit 10 is realized by, for example, a photodiode having a PN junction.

[0108] The capacitance storage units 21 to 25 as the M capacitance storage units are implemented by, for example, floating diffusion layers.

[0109] The capacitor storage units 21 to 25 as M capacitor storage units are composed of one or more overflow capacitor storage units for storing signal charges overflowing from the photoelectric conversion unit 10, and one or more floating diffusion units other than the one or more overflow capacitor storage units, and the one or more floating diffusion units are used to convert the signal charges converted by the photoelectric conversion unit 10 into voltage.

[0110] Here, the description is given assuming that one or more overflow capacitance storage units are one of the capacitance storage units 25 , and one or more floating diffusion units other than the one or more overflow capacitance storage units are M−1 of the capacitance storage units 21 to 24 .

[0111] Hereinafter, the capacitance storage unit 25 is also referred to as the overflow capacitance storage unit 25 or FD(M), and the capacitance storage units 21 to 24 are also referred to as floating diffusion units 21 to 24 or FD( 1 ) to FD(M−1).

[0112] In addition, if Figure 2 As shown, FD(1) to FD(M) have capacitors C(1) to C(M), respectively.

[0113] like Figure 2 As shown, the pixel 111 further includes a transfer transistor 30 and a first connection transistor 44 .

[0114] One of the source and drain of the transfer transistor 30 is connected to the photoelectric converter 10 , and the other of the source and drain of the transfer transistor 30 is connected to one of one or more floating diffusions (here, the floating diffusion 21 ).

[0115] The transfer transistor 30 is an NMOS transistor, and a gate thereof is driven by a control signal TG output from the vertical scanning circuit 120 .

[0116] The transfer transistor 30 is in a non-conductive state when the gate thereof is at a logic level low, and is in a conductive state when the gate thereof is at a logic level high.

[0117] Hereinafter, a transistor being in a conducting state is also referred to as a transistor being on, and a transistor being in a non-conducting state is also referred to as a transistor being off.

[0118] When the transfer transistor 30 is turned on, the signal charge accumulated in the photoelectric converter 10 is transferred to the floating diffusion 21 via the transfer transistor 30. If there are one or more other floating diffusions electrically connected to the floating diffusion 21, the signal charge accumulated in the photoelectric converter 10 is also transferred to the one or more other floating diffusions.

[0119] One of the source and drain of the first connection transistor 44 is connected to one of the one or more overflow capacitor storage units (here, connected to the overflow capacitor storage unit 25), and the other of the source and drain of the first connection transistor 44 is connected to one of the one or more floating diffusion units (here, connected to the floating diffusion unit 24).

[0120] The first connection transistor 44 is an NMOS transistor, and its gate is driven by the control signal GC(M−1) output from the vertical scanning circuit 120 .

[0121] The first connection transistor 44 is in a non-conductive state when the gate thereof becomes a logic level low, and is in a conductive state when the gate thereof becomes a logic level high.

[0122] When the first connection transistor 44 is turned on, the overflow capacitance storage unit 25 and the floating diffusion 24 are electrically connected.

[0123] like Figure 2 As shown, the pixel 111 further includes an overflow transistor 50 .

[0124] One of the source and the drain of the overflow transistor 50 is connected to the photoelectric conversion unit 10 , and the other of the source and the drain of the overflow transistor 50 is connected to the overflow capacitance storage unit 25 .

[0125] The overflow transistor 50 is an NMOS transistor, and its gate is driven by a control signal OF output from the vertical scanning circuit 120 .

[0126] Therefore, by controlling the voltage of the gate of the overflow transistor 50 , the height of the potential barrier between the photoelectric conversion unit 10 and the overflow capacitance storage unit 25 can be controlled.

[0127] like Figure 2 As shown, the pixel 111 further includes M-2 second connection transistors (here, the second connection transistors 41 to 43 ).

[0128] M−2 second connection transistors (here, the second connection transistors 41 to 43 ) connect M−1 floating diffusions (here, the floating diffusions 21 to 24 ) in series.

[0129] Here, the floating diffusion 24 located at one end of the M-1 floating diffusions connected in series is connected to the other of the source and drain of the first connection transistor 44, and the floating diffusion 21 located at the other end of the M-1 floating diffusions connected in series is connected to the other of the source and drain of the transfer transistor 30.

[0130] The second connection transistors 41 to 43 are NMOS transistors, and their gates are driven by control signals GC( 1 ) to GC(M− 2 ) output from the vertical scanning circuit 120 .

[0131] Each of the second connection transistors 41 to 43 is in a non-conductive state when the gate thereof becomes a logic level low, and is in a conductive state when the gate thereof becomes a logic level high.

[0132] When the second connection transistors 41 to 43 are turned on, the floating diffusion connected to one of the source and drain of the second connection transistor is electrically connected to the floating diffusion connected to the other of the source and drain of the second connection transistor.

[0133] The first connection transistor 44 and the second connection transistors 41 to 43 are examples of transistors for switching gain.

[0134] Hereinafter, when it is not necessary to clearly distinguish between the second connecting transistors 41 to 43 and the first connecting transistor 44, the second connecting transistors 41 to 43 and the first connecting transistor 44 are also referred to simply as connecting transistors. In this case, the second connecting transistors 41 to 43 and the first connecting transistor 44 are also referred to as connecting transistors GC(1) to GC(M-2) and connecting transistor GC(M-1).

[0135] like Figure 2 As shown, the pixel 111 further includes a first reset transistor 61 , an amplifier transistor 81 , and a selection transistor 82 .

[0136] One of the source and drain of the first reset transistor 61 is connected to the other of the source and drain of the first connection transistor 44 , and the other of the source and drain of the first reset transistor 61 is connected to the first pixel power supply 71 .

[0137] The first reset transistor 61 is an NMOS transistor, and its gate is driven by the control signal RS( 1 ) output from the vertical scanning circuit 120 .

[0138] The first reset transistor 61 is in a non-conductive state when the gate thereof becomes a logic level low, and is in a conductive state when the gate thereof becomes a logic level high.

[0139] When the first reset transistor 61 is turned on, the floating diffusion 24 and the floating diffusions 21 to 23 electrically connected thereto, the overflow capacitor storage unit 25 , or the photoelectric converter 10 are reset by the voltage of the first pixel power supply 71 .

[0140] The amplification transistor 81 has a gate connected to the floating diffusion 21 , a drain connected to the first pixel power supply 71 , and a source connected to the drain of the selection transistor 82 .

[0141] The amplifier transistor 81 is an NMOS transistor and forms a source-follower circuit together with a constant current source (not shown) arranged on a vertical signal line 150 connected via a select transistor 82 (described later). Thus, when the select transistor 82 is in the on state, the amplifier transistor 81 outputs a pixel signal corresponding to the voltage of the floating diffusion 24 to the vertical signal line 150.

[0142] The drain of the selection transistor 82 is connected to the source of the amplification transistor 81 , and the source of the selection transistor 82 is connected to the vertical signal line 150 .

[0143] The selection transistor 82 is an NMOS transistor, and its gate is driven by the vertical scanning circuit 120 .

[0144] The selection transistor 82 is in a non-conductive state when the gate thereof becomes a logic level low, and is in a conductive state when the gate thereof becomes a logic level high.

[0145] When the selection transistor 82 is turned on, the pixel signal output from the amplifier transistor 81 is output to the vertical signal line 150 via the selection transistor 82. That is, when the selection transistor 82 is turned on, the pixel 111 is selected.

[0146] Figure 3 It is a correspondence table showing the correspondence between (1) M gains, (2) the on / off states of the connection transistors GC(1) to GC(M-1) when the pixel 111 outputs the pixel signals corresponding to the respective gains, and (3) FD(1) to FD(M) that maintain the signal charges corresponding to the pixel signals.

[0147] like Figure 3 As shown, when the pixel 111 outputs a pixel signal corresponding to a gain of 1, the connection transistors GC(1) to GC(M-1) are in the off state. Furthermore, before the signal charge generated by the photoelectric conversion unit 10 is transferred to the FD(1), the pixel 111 outputs a pixel signal of a reset component. After the signal charge generated by the photoelectric conversion unit 10 is transferred to the FD(1) by the transfer transistor 30, the pixel 111 outputs a pixel signal of a signal component.

[0148] In addition, if Figure 3As shown, when the pixel 111 outputs a pixel signal corresponding to a gain of 2, the connection transistor GC(1) is in the on state, and the connection transistors GC(2) to GC(M-1) are in the off state. Furthermore, before the signal charge generated by the photoelectric conversion unit 10 is transferred to FD(1) and FD(2), the pixel 111 outputs a pixel signal of a reset component. After the signal charge generated by the photoelectric conversion unit 10 is transferred to FD(1) and FD(2) by the transfer transistor 30, the pixel 111 outputs a pixel signal of a signal component.

[0149] In addition, if Figure 3 As shown, when the pixel 111 outputs a pixel signal corresponding to the gain M-1, the connection transistors GC(1) to GC(M-2) are in the on state, and the connection transistor GC(M-1) is in the off state. Furthermore, before the signal charge generated by the photoelectric conversion unit 10 is transferred to FD(1) to FD(M-1), the pixel 111 outputs a pixel signal of a reset component. After the signal charge generated by the photoelectric conversion unit 10 is transferred to FD(1) to FD(M-1) by the transfer transistor 30, the pixel 111 outputs a pixel signal of a signal component.

[0150] In addition, if Figure 3 As shown, when the pixel 111 outputs a pixel signal corresponding to the gain M, the connection transistors GC(1) to GC(M-1) are in the on state. Furthermore, the pixel 111 outputs a pixel signal corresponding to a signal component of the sum of the signal charge generated by the photoelectric conversion unit 10 and transferred to FD(1) to FD(M-1) via the transfer transistor 30, and the signal charge overflowing from the photoelectric conversion unit 10 and accumulated in FD(M). After the signal charge accumulated in FD(1) to FD(M) is discharged to the first pixel power supply 71 via the first reset transistor 61, the pixel 111 outputs a pixel signal of a reset component.

[0151] <Readout Operation Time and Dynamic Range>

[0152] Figure 4 、 Figure 5 This is a table showing an example of the time required for pixel signal output and the time required for AD conversion in a series of actions from when the solid-state imaging device 100 captures a subject, until the pixel 111 outputs pixel signals corresponding to N gains to the vertical signal line 150 and the AD converter 160 performs AD conversion on the output pixel signals.

[0153] Here, Figure 4This table shows the case where the solid-state imaging device 100 captures a subject of relatively low brightness and the pixel 111 outputs pixel signals corresponding to gains 1 to N. Figure 5 This table shows a case where the pixel 111 outputs pixel signals corresponding to gains M-N+1 to M when the solid-state imaging device 100 captures a subject of relatively high brightness.

[0154] Figure 6 、 Figure 7 This is a graph showing an example of the relationship between the SN of the pixel signals corresponding to each N gains and the dynamic range in a series of actions from the pixel 111 outputting pixel signals corresponding to N gains to the vertical signal line 150 and the AD converter 160 performing AD conversion on the output pixel signals when the solid-state imaging device 100 captures a subject.

[0155] Here, Figure 6 This is a graph when the solid-state imaging device 100 captures a subject of relatively low brightness and the pixel 111 outputs pixel signals corresponding to gains 1 to N. Figure 7 This is a graph when the solid-state imaging device 100 captures a subject of relatively high brightness and the pixel 111 outputs pixel signals corresponding to gains M−N+1 to M.

[0156] like Figure 6 and Figure 7 As shown, the vertical scanning circuit 120 controls the pixel 111 so that the pixel 111 outputs N pixel signals composed of adjacent gains among M pixel signals.

[0157] This can reduce the difference in SN between the N pixel signals at the boundaries (transition regions) between the N pixel signals.

[0158] In addition, if Figure 7 As shown, when the pixel 111 outputs a pixel signal corresponding to the gain M-N+1 to the gain M, a pixel signal of a signal component corresponding to the total signal charge of the signal charge transferred in advance to FD(1) to FD(M-1) through the transfer transistor 30 and the signal charge overflowed from the photoelectric conversion unit 10 and accumulated in FD(M) is output. Therefore, compared with a solid-state imaging device having a structure that does not have FD(M) that can accumulate the signal charge overflowed from the photoelectric conversion unit 10, the solid-state imaging device 100 can capture a subject with higher brightness.

[0159] like Figures 4 to 7As shown, in the solid-state imaging device 100, each pixel 111 outputs N pixel signals corresponding to N out of M gains. The AD converter 160 performs AD conversion on the N pixel signals output from each pixel 111, and the HDR synthesis circuit 140 performs HDR synthesis on these pixel signals after the AD conversion by the AD converter 160 to generate an image.

[0160] Thus, in the solid-state imaging device 100 having a pixel array in which a plurality of pixels that output M pixel signals with different gains are arranged in a matrix, the frame rate can be increased at a high speed compared to the conventional solid-state imaging device that reads out all M pixel signals.

[0161] <Reduction of the bit width of AD conversion>

[0162] Figure 8 、 Figure 9 is a table showing another example of the required time for output of pixel signals and the required time for AD conversion in a series of operations from when the pixel 111 outputs pixel signals corresponding to N gains to the vertical signal line 150 and the AD converter 160 performs AD conversion on the output N pixel signals until the solid-state imaging device 100 captures a subject.

[0163] Figure 4 、 Figure 5 is an example of the case where the required time for AD conversion does not exceed the required time for output of pixel signals. In contrast, Figure 8 、 Figure 9 is an example of the case where the required time for AD conversion exceeds the required time for output of pixel signals.

[0164] Here, Figure 8 is a table when the pixel 111 outputs pixel signals corresponding to gains 1 to gain N in the case where the solid-state imaging device 100 captures a low-luminance subject, Figure 9 is a table when the pixel 111 outputs pixel signals corresponding to gains M - N + 1 to gain M in the case where the solid-state imaging device 100 captures a high-luminance subject.

[0165] As Figure 8 shown, in the case where the required time for AD conversion exceeds the required time for output of pixel signals, when the AD converter 160 performs AD conversion on the pixel signal corresponding to gain N, it performs AD conversion with a smaller number of bits than the AD conversion of the pixel signals corresponding to the other N - 1 gains, so that the required time for AD conversion of the pixel signal corresponding to gain N is shorter than the required time for AD conversion of the pixel signals corresponding to the other N - 1 gains.

[0166] This makes it possible to increase the frame rate compared to a case where the time required for AD conversion of a pixel signal corresponding to gain N is not shortened compared to the time required for AD conversion of pixel signals corresponding to other N-1 gains.

[0167] like Figure 9 As shown, when the time required for AD conversion exceeds the time required for outputting the pixel signal, the AD converter 160 performs AD conversion on the pixel signal corresponding to the gain M with a smaller number of bits than the number of bits in the AD conversion of the pixel signals corresponding to the other N-1 gains, thereby making the time required for AD conversion of the pixel signal corresponding to the gain M shorter than the time required for AD conversion of the pixel signals corresponding to the other N-1 gains.

[0168] This makes it possible to increase the frame rate compared to a case where the time required for AD conversion of the pixel signal corresponding to gain M is not shortened compared to the time required for AD conversion of the pixel signals corresponding to the other N-1 gains.

[0169] In this way, when the time required for AD conversion exceeds the time required for output of the pixel signal, the AD converter 160 can achieve a higher frame rate by making the time required for AD conversion of the pixel signal corresponding to one gain shorter than the time required for AD conversion of the pixel signal corresponding to the other N-1 gains, compared with the case where the time required for AD conversion of the pixel signal corresponding to one gain is not shorter than the time required for AD conversion of the pixel signal corresponding to the other N-1 gains.

[0170] Figure 10 This is a block diagram showing a specific configuration example of a solid-state imaging device 100A that converts at least one pixel signal among N pixel signals into a digital signal having a smaller number of bits than other pixel signals.

[0171] like Figure 10 As shown, the solid-state imaging device 100A is Figure 1 The solid-state imaging device 100 shown in the figure has a plurality of selection detection circuits 170 and a plurality of signal lines 180 added thereto.

[0172] Each of the plurality of vertical signal lines 150 transmits a pixel signal output from one of the L pixels 111 arranged in the column direction in the corresponding column to each selection detection circuit 170 .

[0173] Multiple selection detection circuits 170 determine the best pixel signal and the correction pixel signal for correcting the best pixel signal from N pixel signals, and transmit the best pixel signal to multiple AD converters 160 via multiple signal lines 180, and then transmit the correction pixel signal to multiple AD converters 160 via multiple signal lines 180.

[0174] The plurality of AD converters 160 convert the correction pixel signals into digital signals having a smaller number of bits than the optimal pixel signals. The reason for converting the correction pixel signals into digital signals having a smaller number of bits than the optimal pixel signals will be described later.

[0175] The plurality of selection detection circuits 170 correspond one-to-one to the K vertical signal lines 150 and one-to-one to the K AD converters 160. That is, there are K plurality of selection detection circuits 170.

[0176] The plurality of signal lines 180 correspond one-to-one to the K selection detection circuits 170 , and also correspond one-to-one to the K AD converters 160 . That is, there are K signal lines 180 .

[0177] Here, regarding the solid-state imaging device 100A, it is assumed that the number of AD converters 160, selection detection circuits 170, and signal lines 180 is K, and the selection detection circuits 170 correspond one-to-one to the K vertical signal lines 150. However, it is also possible that the number of AD converters 160, or selection detection circuits 170, or signal lines 180, or more than two of them exceeds K, and the correspondence between the vertical signal lines 150 and the selection detection circuits 170 is not one-to-one, and the correspondence between the selection detection circuits 170 and the AD converters 160 may also not be one-to-one.

[0178] Figure 11 This is an example of the detection selection circuit 170 when N=3.

[0179] The detection selection circuit 170 includes a selection circuit 171 for selecting a signal from a plurality of pixel signals including a sample-and-hold circuit SH173 for holding the plurality of pixel signals, and a detection circuit 172 for detecting at least one pixel signal from the plurality of pixel signals.

[0180] First, a plurality of pixel signals from the pixel 111 are held in the sample-and-hold circuit SH173.

[0181] First, an example of the sample and hold circuit SH173 is described.

[0182] In the sample-and-hold circuit SH173, when the switch element SW0 is turned on, the pixel signal is input to the sample-and-hold capacitor elements (C30, C31, C32, C33, C34, and C35) via the vertical signal line 150 and the sample-and-hold switch elements (SH1, SH2, SH3, SH4, SH5, and SH6). Furthermore, the pixel signal is input to the gate of the amplifier transistor SF174 via the readout selection switch elements (SE7, SE8, SE9, SE10, SE11, and SE12). The output of the amplifier transistor SF174 is connected to the signal line 180 via the selection transistor SEL_DET.

[0183] The sample-and-hold switch elements (SH1, SH2, SH3, SH4, SH5, and SH6) are switching transistors that are turned on and off by a sample-and-hold switch control signal ΦSH. When the sample-and-hold switch elements are off, the pixel signals are held in the sample-and-hold capacitor elements (C30, C31, C32, C33, C34, and C35). In other words, the sample-and-hold switch control signal ΦSH selects the address at which the pixel signals are held in the sample-and-hold capacitor elements (C30, C31, C32, C33, C34, and C35).

[0184] The readout selection switch elements (SE7, SE8, SE9, SE10, SE11, SE12) are switching transistors that are turned on and off by signal selection signal 175 (ΦSE). When the readout selection switch elements are turned on, the pixel signals held in the sample-and-hold capacitors (C30, C31, C32, C33, C34, C35) are input to the gate of amplifier transistor SF174. In other words, signal selection signal 175 (ΦSE) selects the address for reading pixel signals from the sample-and-hold capacitors (C30, C31, C32, C33, C34, C35).

[0185] The selection transistor SEL_DET is a switching transistor that is turned on and off according to the selection control signal φSEL_DET. When the selection control signal φSEL_DET is at a logic high level, the selection transistor SEL_DET electrically connects the source of the amplifier transistor SF174 to the signal line 180.

[0186] Here, the sampling and holding capacitor element (C30) holds a reset component of the first pixel signal corresponding to the highest gain among the three pixel signals. On the other hand, the sampling and holding capacitor element (C31) holds a signal component of the first pixel signal.

[0187] The sampling and holding capacitor (C32) holds a reset component of a second pixel signal corresponding to the second highest gain among the three pixel signals. On the other hand, the sampling and holding capacitor (C33) holds a signal component of the second pixel signal.

[0188] The sampling and holding capacitor (C34) holds a reset component of the third pixel signal corresponding to the lowest gain among the three pixel signals. On the other hand, the sampling and holding capacitor (C35) holds a signal component of the third pixel signal.

[0189] Next, detection circuit 172 compares the value obtained by subtracting the reset component (held in C32) from the signal component of the second pixel signal held in sample-and-hold circuit SH173 (held in C33) with the first reference value REF1 at the boundary between the first and second pixel signals, and the second reference value REF2 at the boundary between the second and third pixel signals. Thus, an optimal pixel signal and a correction pixel signal are detected from the three pixel signals, and a signal selection signal 175 (ΦSE) is input to selection circuit 171.

[0190] Here, when the first pixel signal is detected as the optimal pixel signal, the second pixel signal is detected as the correction pixel signal, and when the second pixel signal is detected as the optimal pixel signal, the third pixel signal is detected as the correction pixel signal. When the third pixel signal is detected as the optimal pixel signal, the correction pixel signal is not detected.

[0191] Next, in the selection circuit 171 , the readout selection switch element is controlled based on the signal selection signal 175 (ΦSE).

[0192] For example, if the first pixel signal is the optimal pixel signal, readout selection switch element SE7 is turned on, outputting a reset component to signal line 180 via amplifier transistor SF174 and selection transistor SEL_DET. Similarly, readout selection switch element SE8 is turned on, outputting a signal component to signal line 180. Next, because the second pixel signal becomes the correction pixel signal, readout selection switch element SE9 is turned on, outputting a reset component to signal line 180 via amplifier transistor SF174 and selection transistor SEL_DET. Similarly, readout selection switch element SE10 is turned on, outputting a signal component to signal line 180.

[0193] If the second pixel signal is the optimal pixel signal, readout selection switch element SE9 is turned on, outputting a reset component to signal line 180 via amplifier transistor SF174 and selection transistor SEL_DET. Similarly, readout selection switch element SE10 is turned on, outputting a signal component to signal line 180. Next, since the third pixel signal becomes the correction pixel signal, readout selection switch element SE11 is turned on, outputting a reset component to signal line 180 via amplifier transistor SF174 and selection transistor SEL_DET. Similarly, readout selection switch element SE12 is turned on, outputting a signal component to signal line 180.

[0194] If the third pixel signal is the optimal pixel signal, the readout selection switch element SE11 is turned on to output the reset component to the signal line 180 via the amplifier transistor SF174 and the selection transistor SEL_DET. Similarly, the readout selection switch element SE12 is turned on to output the signal component to the signal line 180.

[0195] Furthermore, since the reset component is subtracted from the signal component by the CDS of the AD conversion circuit, circuit variations of the amplifier transistor SF81, the amplifier transistor SF174, and the like are eliminated.

[0196] The detection circuit 172 includes a comparator 181 , an inverter circuit 182 , a latch circuit 183 , an inverter circuit 184 , an AND circuit 185 , a latch circuit 186 , a latch circuit 187 , a selection control circuit 188 , SW13 , SW14 , SW15 , SW16 , and SW17 .

[0197] The detection circuit 172 controls SW15 and SW16 using the reference value selection signal 176 to switch between the first reference value ( REF1 ) and the second reference value ( REF2 ) in a temporally continuous manner and inputs the values ​​to one input terminal of the comparator 181 .

[0198] Towards the other end, the reset component of the second pixel signal is first input in time to perform automatic zeroing (turning on SW13 and SW17), and then the signal component of the second pixel signal is input (turning on SW14), and analog CDS is performed. The difference between the signal component of the second pixel signal and the reset component of the second pixel signal is compared with the first reference value (REF1) or the second reference value (REF2).

[0199] When the optimal pixel signal is the first pixel signal, when the first reference value (REF1) is input, the output of comparator 181 is at a logic low (L), the output of inverter circuit 182 is at a logic high (H), the output of latch circuit 183 is at a logic high (H), and the output of inverter circuit 184 is at a logic low (L). Next, when the second reference value (REF2) is input, latch circuits 186 and 187 are reset, the output of comparator 181 remains at a logic low (L), the output of inverter circuit 182 remains at a logic high (H), the output of latch circuit 183 remains at a logic high (H), and the output of AND circuit 185 becomes a logic low (L). Consequently, the output of latch circuit 186 becomes a logic low (L), the output of latch circuit 183 becomes a logic high (H), and the output of latch circuit 187 becomes a logic low (L). Based on the outputs of latch circuits 186, 183, and 187, selection control circuit 188 outputs logic-high (H) signals of SE7 and SE8, which are output signals of latch circuit 183, to selection circuit 171 as signal selection signal 175 (φSE). This causes the reset component of the first pixel signal to be output to signal line 180 via amplifier transistor SF174 and selection transistor SEL_DET, and similarly causes the signal component of the first pixel signal to be output to signal line 180. Next, because the second pixel signal becomes the correction pixel signal, selection control circuit 188 outputs logic-high (H) signals of SE9 and SE10, which are output signals of latch circuit 183, to selection circuit 171 as signal selection signal 175 (φSE). This causes the reset component of the second pixel signal to be output to signal line 180 via amplifier transistor SF174 and selection transistor SEL_DET, and similarly causes the signal component of the second pixel signal to be output to signal line 180.

[0200] When the optimal pixel signal is the second pixel signal, when the first reference value (REF1) is input, the output of comparator 181 is at a logic level high (H), the output of inverter circuit 182 is at a logic level low (L), the output of latch circuit 183 is at a logic level low (L), and the output of inverter circuit 184 is at a logic level high (H). Next, when the second reference value (REF2) is input, latch circuits 186 and 187 are reset, the output of comparator 181 remains at a logic level low (L), the output of inverter circuit 182 remains at a logic level high (H), the output of latch circuit 183 remains at a logic level low (L), and the output of AND circuit 185 becomes a logic level high (H). Consequently, the output of latch circuit 186 becomes a logic level low (L), the output of latch circuit 183 becomes a logic level low (L), and the output of latch circuit 187 becomes a logic level high (H). Based on the outputs of latch circuits 186, 183, and 187, selection control circuit 188 outputs logic-high (H) signals of SE9 and SE10, which are output signals of latch circuit 187, to selection circuit 171 as signal selection signal 175 (φSE). This causes the reset component of the second pixel signal to be output to signal line 180 via amplifier transistor SF174 and selection transistor SEL_DET, and similarly causes the signal component of the second pixel signal to be output to signal line 180. Next, because the third pixel signal becomes the correction pixel signal, selection control circuit 188 outputs logic-high (H) signals of SE11 and SE12, which are output signals of latch circuit 187, to selection circuit 171 as signal selection signal 175 (φSE). This causes the reset component of the third pixel signal to be output to signal line 180 via amplifier transistor SF174 and selection transistor SEL_DET, and similarly causes the signal component of the third pixel signal to be output to signal line 180.

[0201] When the optimal pixel signal is the third pixel signal, when the first reference value (REF1) is input, the output of comparator 181 is at a logic high (H), the output of inverter circuit 182 is at a logic low (L), the output of latch circuit 183 is at a logic low (L), and the output of inverter circuit 184 is at a logic high (H). Next, when the second reference value (REF2) is input, latch circuits 186 and 187 are reset, the output of comparator 181 remains at a logic high (H), the output of inverter circuit 182 remains at a logic low (L), the output of latch circuit 183 remains at a logic low (L), and the output of AND circuit 185 becomes a logic low (L). Consequently, the output of latch circuit 186 becomes a logic high (H), the output of latch circuit 183 becomes a logic low (L), and the output of latch circuit 187 becomes a logic low (L). The selection control circuit 188 outputs the logic level high (H) signals of SE11 and SE12, which are the output signals of the latch circuit 186, as the signal selection signal 175 (ΦSE) to the selection circuit 171 based on the outputs of the latch circuit 186, the latch circuit 183 and the latch circuit 187, and outputs the reset component of the third pixel signal to the signal line 180 via the amplifier transistor SF174 and the selection transistor SEL_DET, and similarly outputs the signal component of the third pixel signal to the signal line 180.

[0202] Furthermore, the outputs of latch circuits 186, 183, and 187 are input to AD converter 160 as gain selection signal 189. Based on the value of gain selection signal 189, AD converter 160 adds information identifying the gain corresponding to the optimal pixel signal to a digital signal obtained by AD-converting the optimal pixel signal (hereinafter also referred to as the optimal digital signal), and adds information identifying the gain corresponding to the correction pixel signal to the pixel signal converted into a digital signal obtained by AD-converting the correction pixel signal (hereinafter also referred to as the correction digital signal).

[0203] This eliminates the need for redundant reading of all multiple signals and allows selective reading of at least one pixel signal from multiple pixel signals, thereby enabling faster processing and lower power consumption in subsequent stages including AD converters.

[0204] In this embodiment, the selection detection circuit 170 is described as outputting the correction pixel signal to the signal line 180 after outputting the optimal pixel signal to the signal line 180 , but the selection detection circuit 170 may output the correction pixel signal to the signal line 180 before outputting the optimal pixel signal to the signal line 180 .

[0205] In the case where one pixel signal is selected from a plurality of pixel signals, as shown in FIG. Figure 6 、 Figure 7 As shown in the SN level, there are significant changes in SN at the boundaries between the first and second pixel signals, and between the second and third pixel signals. Therefore, even for the same subject, the SN sense may vary depending on the selected gain.

[0206] As a countermeasure, the HDR synthesis circuit 140 mixes the optimal digital signal and the correction digital signal from immediately before the boundary between the optimal digital signal and the correction digital signal, thereby alleviating the SN step difference in the boundary portion.

[0207] Figure 12 This is a graph showing the relationship between the product of illuminance and exposure time and the values ​​of digital signals (hereinafter also referred to as the first digital signal, the second digital signal, and the third digital signal) obtained by AD-converting the first pixel signal, the second pixel signal, and the third pixel signal, respectively, when the product of illuminance and exposure time is set as the horizontal axis and the value of the digital signal obtained by AD-converting the pixel signal (unit is LSB) is set as the vertical axis. Figure 12 As shown, since the gain corresponding to the correction pixel signal is lower than the gain corresponding to the optimal pixel signal, within the light intensity range in which the optimal pixel signal is not saturated, the value of the digital signal obtained after AD conversion of the correction pixel signal is smaller than the value of the digital signal obtained after AD conversion of the optimal pixel signal.

[0208] For example, when the selection detection circuit 170 determines that the first pixel signal is the optimal pixel signal and the second pixel signal is the correction pixel signal, the optimal digital signal value is the correction digital signal value when A+(LSB) is the maximum value that can be expressed by the number of bits of the optimal digital signal. In other words, the maximum value of the correction digital signal is C(LSB), which is smaller than A+(LSB). Furthermore, when the selection detection circuit 170 determines that the second pixel signal is the optimal pixel signal and the third pixel signal is the correction pixel signal, the optimal digital signal value is the correction digital signal value when A+(LSB) is the maximum value that can be expressed by the number of bits of the optimal digital signal. In other words, the maximum value of the correction digital signal is D(LSB), which is smaller than A+(LSB).

[0209] Therefore, the number of bits of the correction digital signal can be made smaller than the number of bits of the optimal digital signal, and speed increase and power reduction can be achieved in the subsequent stage including the AD converter.

[0210] When a digital signal is input from the AD converter, the HDR synthesis circuit 140 determines whether the digital signal is the first digital signal, the second digital signal, or the third digital signal based on the identification gain information added to the digital signal. If the digital signal is the second digital signal, the digital signal is multiplied by a coefficient of 1 to generate a fourth digital signal. If the digital signal is the third digital signal, the digital signal is multiplied by a coefficient of 2 to generate a fifth digital signal. This allows the optimal digital signal and the correction digital signal to be mixed. Here, the coefficient 1 is equal to the value of the multiplier. Figure 12 The value obtained by dividing the slope of the line segment representing the relationship between the value of the first digital signal and the product of the illuminance and the exposure time by the slope of the line segment representing the relationship between the value of the second digital signal and the product of the illuminance and the exposure time, and the coefficient 2 is equal to Figure 12 The value obtained by dividing the slope of the line segment representing the relationship between the value of the first digital signal and the product of the illuminance and the exposure time by the slope of the line segment representing the relationship between the value of the third digital signal and the product of the illuminance and the exposure time.

[0211] Here, Figure 12 A0 shown on the vertical axis is the value of the boundary between the first digital signal and the fourth digital signal, A- is a digital signal value lower than A0, A+ is a digital signal value higher than A0 and the same as the saturation of the first digital signal, B0 is the value of the boundary between the fourth digital signal and the fifth digital signal, B- is a digital signal value lower than B0, and B+ is a digital signal value higher than B0 and the same as the saturation of the fourth digital signal.

[0212] Next, when the optimal digital signal is the first digital signal and the correction digital signal is the fourth digital signal, the HDR synthesis circuit 140 calculates the first mixing ratio ( Figure 13 The product of the mixing ratio (shown by the thin dotted line) and the value of the optimal digital signal, and the second mixing ratio ( Figure 13 The optimal digital signal and the correction digital signal are mixed by taking the sum of the products of the mixing ratio shown by the thin solid line and the value of the correction digital signal.

[0213] In addition, when the optimal digital signal is the fourth digital signal and the correction digital signal is the fifth digital signal, the HDR synthesis circuit 140 calculates the first mixing ratio ( Figure 13 The product of the mixing ratio shown by the thick solid line) and the value of the optimal digital signal, and the second mixing ratio ( Figure 13 The optimal digital signal and the correction digital signal are mixed by taking the sum of the products of the mixing ratio (represented by the thick dotted line) and the value of the correction digital signal.

[0214] Here, if Figure 13As shown, if the sum of the first mixing ratio and the second mixing ratio is 1 and the value of the first digital signal is less than A-, the value of the first mixing ratio is 1 and the value of the second mixing ratio is 0. If the value of the first digital signal is greater than or equal to A- and less than or equal to A+, the value of the first mixing ratio decreases monotonically with a maximum value of 1 and a minimum value of 0 as the first digital signal increases, and the value of the second mixing ratio increases monotonically with a minimum value of 0 and a maximum value of 1 as the first digital signal increases. If the value of the first digital signal is greater than or equal to A+, the value of the first mixing ratio is 0 and the value of the second mixing ratio is 1.

[0215] Furthermore, if the value of the fourth digital signal is less than B-, the value of the first mixing ratio is 1 and the value of the second mixing ratio is 0. If the value of the fourth digital signal is greater than or equal to B- and less than or equal to B+, the value of the first mixing ratio decreases monotonically with a maximum value of 1 and a minimum value of 0 as the fourth digital signal increases, and the value of the second mixing ratio increases monotonically with a minimum value of 0 and a maximum value of 1 as the fourth digital signal increases. If the value of the fourth digital signal is greater than or equal to B+, the value of the first mixing ratio is 0 and the value of the second mixing ratio is 1.

[0216] Therefore, the HDR synthesis circuit 140 can mitigate the SN step difference in the boundary portion by slowly blending the optimal digital signal and the correction digital signal at their boundary portion, and the above-mentioned effect will not be lost even if the number of bits of the correction digital signal is less than that of the optimal digital signal.

[0217] <Pixel Control Timing Example 1>

[0218] Hereinafter, an example of control timing of the pixel 111 will be described. In order to avoid excessive complexity, the following description will be given assuming that M=3 and N=2.

[0219] Figure 14 : is a circuit diagram showing a configuration example of the pixel 111 in the case where M=3 and N=2.

[0220] Figure 15 It is a correspondence table showing the correspondence between (1) three gains in the case of M=3 and N=2, (2) the on / off states of the connection transistors GC(1) to GC(2) when the pixel 111 outputs the pixel signals corresponding to the respective gains, and (3) FD(1) to FD(3) that maintain the signal charges corresponding to the pixel signals.

[0221] Figure 16 It means to use Figure 14 The timing chart is an example of the control timing of the pixel 111 when the pixel 111 outputs pixel signals corresponding to two gains, namely, gain 1 and gain 2, in the case of M=3 and N=2.

[0222] like Figure 16 As shown, in the readout row, the control signal GC(2) is always at logic level low. Therefore, in the readout row, the first connection transistor 44 is always off.

[0223] At time t1, a read operation period for one row starts.

[0224] At time t2, the vertical scanning circuit 120, under the control of the control circuit 130, changes the control signal RS(1) and the control signal GC(1) from logic low to logic high in the readout row. Consequently, in the pixel 111, the first reset transistor 61 and the second connection transistor 41 change from off to on, and the voltages of FD(1) and FD(2) become equal to the voltage of the first pixel power supply 71. Consequently, a reset component of the pixel signal corresponding to gain 1 and gain 2 is generated in the pixel 111.

[0225] At time t3, the vertical scanning circuit 120 changes the control signal RS(1) from logic high to logic low in the readout row under the control of the control circuit 130. As a result, the first reset transistor 61 in the pixel 111 changes from on to off.

[0226] From time t3 to time t4, in the readout row, the pixel 111 outputs a reset component of a pixel signal corresponding to a gain of 2 via FD(1) and FD(2). The vertical signal line 150 converges before time t4.

[0227] At time t4, the vertical scanning circuit 120 changes the control signal GC(1) from logic level high to logic level low in the readout row under the control of the control circuit 130. As a result, the second connection transistor 41 in the pixel 111 changes from on to off.

[0228] From time t4 to time t5, in the readout row, the pixel 111 outputs, via FD(1), a reset component of a pixel signal corresponding to a gain of 1. The vertical signal line 150 converges before time t5.

[0229] At time t5, the vertical scanning circuit 120, under the control of the control circuit 130, changes the control signal TG from logic low to logic high in the readout row. Consequently, in the pixel 111, the transfer transistor 30 changes from off to on, and the signal charge accumulated in the photoelectric conversion unit 10 is transferred to the FD (1). Consequently, a signal component of a pixel signal corresponding to a gain of 1 is generated in the pixel 111.

[0230] On the other hand, the vertical scanning circuit 120, under the control of the control circuit 130, changes the control signal TG, the control signal GC(1), and the control signal RS(1) from a logic low to a logic high in the shutter row. As a result, in the pixel 111, the transfer transistor 30, the second connection transistor 41, and the first reset transistor 61 change from off to on, and the signal charge accumulated in the photoelectric conversion unit 10, the signal charge accumulated in the FD(1), and the signal charge accumulated in the FD(2) are discharged to the first pixel power supply 71.

[0231] In this specification, the control of the pixels 111 in the shutter row by the vertical scanning circuit 120 is also referred to as shutter control. Furthermore, in this specification, the operation of the vertical scanning circuit 120 causing the pixels 111 in the shutter row to discharge signal charge to the first pixel power supply 71 (or the second pixel power supply 72 described later) is also referred to as shutter operation.

[0232] At time t6, the vertical scanning circuit 120 changes the control signal TG from logic level high to logic level low in the readout row under the control of the control circuit 130. As a result, the transfer transistor 30 in the pixel 111 changes from on to off.

[0233] On the other hand, the vertical scanning circuit 120, under the control of the control circuit 130, changes the control signal TG, the control signal GC(1), and the control signal RS(1) from a logic high level to a logic low level in the shutter row. As a result, in the pixel 111, the transfer transistor 30, the second connection transistor 41, and the first reset transistor 61 change from on to off.

[0234] From time t6 to time t7, in the readout row, the pixel 111 outputs a signal component of a pixel signal corresponding to a gain of 1 via FD(1). The vertical signal line 150 converges before time t7.

[0235] At time t7, the vertical scanning circuit 120, under the control of the control circuit 130, changes the control signal TG and the control signal GC(1) from logic low to logic high in the readout row. Consequently, in the pixel 111, the transfer transistor 30 and the second connection transistor 41 change from off to on. Consequently, a pixel signal component corresponding to a gain of 2 is generated in the pixel 111.

[0236] Furthermore, due to the conduction of the second connection transistor 41, even if the signal charge is not completely transferred from the photoelectric conversion section 10 to FD(1) at time t5, the capacitance of the transfer destination is expanded from capacitance C(1) to capacitance C(1) + capacitance C(2) at time t7, so that the residual signal charge that could not be transferred from the photoelectric conversion section 10 to FD(1) at time t5 is transferred to FD(1) and FD(2).

[0237] At time t8, the vertical scanning circuit 120 changes the control signal TG from logic level high to logic level low in the readout row under the control of the control circuit 130. As a result, the transfer transistor 30 in the pixel 111 changes from on to off.

[0238] From time t8 to time t9, in the readout row, the pixel 111 outputs a signal component of a pixel signal corresponding to a gain of 2 via FD(1) and FD(2). The vertical signal line 150 converges before time t9.

[0239] At time t9, the vertical scanning circuit 120 changes the control signal GC(1) from logic high to logic low in the readout row under the control of the control circuit 130. As a result, the second connection transistor 41 in the pixel 111 changes from on to off.

[0240] On the other hand, the vertical scanning circuit 120, under the control of the control circuit 130, changes the control signal GC(1), the control signal GC(2), and the control signal RS(1) from a logic low to a logic high in the shutter row. As a result, in the pixel 111, the first connection transistor 44, the second connection transistor 41, and the first reset transistor 61 change from off to on, and the signal charge accumulated in the FD(3), the signal charge accumulated in the FD(1), and the signal charge accumulated in the FD(2) are discharged to the first pixel power supply 71.

[0241] That is, in the solid-state imaging device 100, even when the pixel 111 outputs signal charges corresponding to gain 1 and gain 2 in the readout row, which are not based on the signal charges accumulated in the FD (3), the signal charges accumulated in both the photoelectric conversion unit 10 and the FD (3) in the shutter row are discharged to the first pixel power supply 71. Therefore, the charge accumulation times of the photoelectric conversion unit 10 and the FD (3) are substantially the same.

[0242] Therefore, when the types of the two pixel signals output by each pixel 111 are changed from a pixel signal corresponding to gain 1 and a pixel signal corresponding to gain 2 to a pixel signal corresponding to gain 2 and a pixel signal corresponding to gain 3, abnormal image quality of the initial frame after the change can be avoided.

[0243] At time t10, the vertical scanning circuit 120, under the control of the control circuit 130, changes the control signal GC(1), the control signal GC(2), and the control signal RS(1) from a logic high level to a logic low level in the shutter row. As a result, in the pixel 111, the first connection transistor 44, the second connection transistor 41, and the first reset transistor 61 change from on to off.

[0244] At time t11, the read operation period for one row ends.

[0245] Figure 17 It means to use Figure 14 The timing chart is an example of the control timing of the pixel 111 when the pixel 111 outputs pixel signals corresponding to two gains, a gain of 2 and a gain of 3, in the case of M=3 and N=2.

[0246] At time t1, a read operation period for one row starts.

[0247] At time t2, the vertical scanning circuit 120, under the control of the control circuit 130, changes the control signal RS(1) and the control signal GC(1) from logic low to logic high in the readout row. Consequently, in the pixel 111, the first reset transistor 61 and the second connection transistor 41 change from off to on, and the voltages of FD(1) and FD(2) become equal to the voltage of the first pixel power supply 71. Consequently, a reset component of the pixel signal corresponding to gain 1 and gain 2 is generated in the pixel 111.

[0248] Here, the signal charge overflowing from the photoelectric converter 10 during exposure is accumulated in FD (3). Therefore, in the readout row from time t4 to time t5 described later, the pixel 111 can output a reset component of the pixel signal corresponding to a gain of 2 via FD (1) and FD (2).

[0249] Therefore, through the correlated double sampling process, a good SN can be obtained using the pixel signal corresponding to a gain of 2.

[0250] At time t3, the vertical scanning circuit 120 changes the control signal RS(1) from logic high to logic low in the readout row under the control of the control circuit 130. As a result, the first reset transistor 61 in the pixel 111 changes from on to off.

[0251] From time t4 to time t5, in the readout row, the pixel 111 outputs a reset component of a pixel signal corresponding to a gain of 2 via FD(1) and FD(2). The vertical signal line 150 converges before time t5.

[0252] At time t5, the vertical scanning circuit 120, under the control of the control circuit 130, changes the control signal TG from logic low to logic high in the readout row. Consequently, in the pixel 111, the transfer transistor 30 changes from off to on, and the signal charge accumulated in the photoelectric conversion unit 10 is transferred to FD (1) and FD (2). Consequently, a signal component of the pixel signal corresponding to gain 2 is generated in the pixel 111.

[0253] On the other hand, the vertical scanning circuit 120, under the control of the control circuit 130, changes the control signal TG, the control signal GC(1), and the control signal RS(1) from a logic low to a logic high in the shutter row. As a result, in the pixel 111, the transfer transistor 30, the second connection transistor 41, and the first reset transistor 61 change from off to on, and the signal charge accumulated in the photoelectric conversion unit 10, the signal charge accumulated in the FD(1), and the signal charge accumulated in the FD(2) are discharged to the first pixel power supply 71.

[0254] At time t6, the vertical scanning circuit 120 changes the control signal TG from logic level high to logic level low in the readout row under the control of the control circuit 130. As a result, the transfer transistor 30 in the pixel 111 changes from on to off.

[0255] On the other hand, the vertical scanning circuit 120, under the control of the control circuit 130, changes the control signal TG, the control signal GC(1), and the control signal RS(1) from a logic high level to a logic low level in the shutter row. As a result, in the pixel 111, the transfer transistor 30, the second connection transistor 41, and the first reset transistor 61 change from on to off.

[0256] From time t6 to time t7, in the readout row, the pixel 111 outputs a signal component of a pixel signal corresponding to a gain of 2 via FD(1) and FD(2). The vertical signal line 150 converges before time t7.

[0257] At time t8, the vertical scanning circuit 120 switches the control signal GC(2) from logic high to logic low in the readout row under the control of the control circuit 130. As a result, the first connection transistor 44 in the pixel 111 switches from off to on.

[0258] Therefore, at time t8, FD (1) and FD (2) to which the signal charge is transferred from the photoelectric converter 10 are electrically connected to FD (3) which accumulates the signal charge overflowing from the photoelectric converter 10. As a result, a signal component of a pixel signal corresponding to a gain of 3 is generated in the pixel 111.

[0259] From time t8 to time t9, in the readout row, the pixel 111 outputs a signal component of a pixel signal corresponding to a gain of 3 via FD(1), FD(2), and FD(3). The vertical signal line 150 converges before time t9.

[0260] At time t9, the vertical scanning circuit 120, under the control of the control circuit 130, changes the control signal RS(1) from logic low to logic high in the readout row. Consequently, in the pixel 111, the first reset transistor 61 changes from off to on, and the signal charge accumulated in FD(1), FD(2), and FD(3) are discharged to the first pixel power supply 71. Consequently, a reset component of the pixel signal corresponding to a gain of 3 is generated in the pixel 111.

[0261] On the other hand, the vertical scanning circuit 120, under the control of the control circuit 130, changes the control signal GC(1), the control signal GC(2), and the control signal RS(1) from a logic low to a logic high in the shutter row. As a result, in the pixel 111, the first connection transistor 44, the second connection transistor 41, and the first reset transistor 61 change from off to on, and the signal charge accumulated in the FD(3), the signal charge accumulated in the FD(1), and the signal charge accumulated in the FD(2) are discharged to the first pixel power supply 71.

[0262] At time t10, the vertical scanning circuit 120 changes the control signal RS(1) from logic high to logic low in the readout row under the control of the control circuit 130. As a result, the first reset transistor 61 in the pixel 111 changes from on to off.

[0263] On the other hand, the vertical scanning circuit 120, under the control of the control circuit 130, changes the control signal GC(1), the control signal GC(2), and the control signal RS(1) from a logic high level to a logic low level in the shutter row. As a result, in the pixel 111, the first connection transistor 44, the second connection transistor 41, and the first reset transistor 61 change from on to off.

[0264] From time t10 to time t11, in the readout row, the pixel 111 outputs a reset component of a pixel signal corresponding to a gain of 3 via FD(1), FD(2), and FD(3). The vertical signal line 150 converges before time t11.

[0265] At time t11, the read operation period for one row ends.

[0266] According to the solid-state imaging device 100 having the above configuration, the pixel signals output by each pixel 111 are N pixel signals, which are smaller than M. Therefore, compared with a conventional solid-state imaging device having a configuration in which each pixel outputs all M pixel signals, the pixel signal readout time is shortened.

[0267] Therefore, according to the solid-state imaging device 100 having the above configuration, a higher frame rate can be achieved than conventional solid-state imaging devices including a pixel array in which a plurality of pixels outputting M pixel signals having mutually different gains are arranged in a matrix.

[0268] <Exposure Control in Imaging Device>

[0269] Figure 18 This is a block diagram showing a configuration example of the imaging device 200 according to the first embodiment.

[0270] The imaging device 200 is a camera system including the solid-state imaging device 100 .

[0271] like Figure 18 As shown, the imaging device 200 includes the solid-state imaging device 100 , an imaging optical system 202 , a signal processing unit 203 , a driving circuit 204 , and a system control unit 205 .

[0272] The imaging optical system 202 includes a lens and focuses light from a subject onto the surface of the pixel array 110 of the solid-state imaging device 100 .

[0273] As described above, the solid-state imaging device 100 sequentially outputs image data based on the N pixel signals outputted from the plurality of pixels 111 .

[0274] The system control unit 205 sequentially outputs a gain designation signal that designates which N pixel signals the pixels 111 output when the vertical scanning circuit 120 of the solid-state imaging device 100 controls the pixels 111 based on the image data sequentially output from the solid-state imaging device 100 .

[0275] Furthermore, the system control unit 205 performs exposure control on the solid-state imaging device 100 .

[0276] The driving circuit 204 drives the solid-state imaging device 100 based on the gain designation signal sequentially output from the system control unit 205. Thus, the solid-state imaging device 100 sequentially outputs image data based on N pixel signals designated by the gain designation signal.

[0277] The signal processing unit 203 performs various signal processing on the pixels output from the solid-state imaging device 100 .

[0278] Figure 19 1 is a timing chart showing an example of the timing of exposure control performed by the system control unit 205 on the solid-state imaging device 100 .

[0279] like Figure 19 As shown, the system control unit 205 performs exposure control in the same cycle as the vertical scanning period.

[0280] Furthermore, the system control unit 205 also performs vertical retrace control on the solid-state imaging device 100 at the same cycle as the vertical scanning period.

[0281] The vertical retrace control is a control that causes the solid-state imaging device 100 to change N pixel signals selected in the next vertical scanning period.

[0282] According to the imaging device 200 having the above configuration, it is possible to achieve both an increase in frame rate and selection of an appropriate dynamic range.

[0283] Figure 20 This is a timing diagram showing a situation in which, in the imaging device 200, the system control unit 205 controls the solid-state imaging device 100 so that each pixel 111 outputs two pixel signals corresponding to gain 1 and gain 2 for lower illumination from time T1 to T2, and outputs two pixel signals corresponding to gain 2 and gain 3 for higher illumination after time T3.

[0284] like Figure 20 As shown, from time T1 to time T2, the pixel 111 does not output the pixel signal corresponding to the gain 3 by scanning the readout row, but the signal charge accumulated in the FD (3) for generating the pixel signal corresponding to the gain 3 is discharged to the first pixel power supply 71 by scanning the shutter row.

[0285] Thus, the exposure time of the pixel signal corresponding to gain 3 outputted from the pixel 111 from time T3 to time T4 is equal to the exposure time of the pixel signal corresponding to gain 2 outputted from the pixel 111 from time T3 to time T4.

[0286] Therefore, it is possible to avoid abnormal image quality of pixel data after HDR synthesis.

[0287] A solid-state imaging device (hereinafter referred to as a "solid-state imaging device of a comparative example") having a configuration in which signal charges corresponding to pixel signals other than the selected N are not discharged from the capacitor storage unit by a shutter operation prior to the readout operation, discharges these signal charges by a shutter operation after the readout operation. Therefore, the solid-state imaging device of the comparative example has a frame rate that is delayed by one frame compared to the solid-state imaging device 100 of the aforementioned configuration.

[0288] Thus, the solid-state imaging device 100 with the above configuration can solve the problem of one-frame delay in the frame rate in the solid-state imaging device of the comparative example, and can increase the frame rate compared to the solid-state imaging device of the comparative example.

[0289] In addition, in embodiment 1, the solid-state imaging device 100 is described as repeatedly performing the scanning of the readout row and the scanning of the shutter row row by row in units of one horizontal scanning period, but the solid-state imaging device 100 is not necessarily limited to a structure in which the scanning of the readout row and the scanning of the shutter row are repeatedly performed row by row in units of one horizontal scanning period.

[0290] The solid-state imaging device 100 can, for example, scan multiple readout rows and multiple shutter rows in the same time period, or can scan in a global shutter manner, in which the signal charge is discharged to the first pixel power supply 71 in the same time period in all rows to start exposure, and after the exposure is completed, the pixel signal is read out in the same time period in all rows.

[0291] (Implementation Method 2)

[0292] Hereinafter, a solid-state imaging device according to a second embodiment will be described, which has a partially modified configuration from the solid-state imaging device 100 according to the first embodiment.

[0293] Here, regarding the solid-state imaging device of the second embodiment, the same components as those of the solid-state imaging device 100 are given the same reference numerals as those already described, and detailed description thereof is omitted. The description will focus on the differences from the solid-state imaging device 100 .

[0294] Figure 21 This is a block diagram showing a configuration example of a solid-state imaging device 100B according to the second embodiment.

[0295] like Figure 21 As shown, the solid-state imaging device 100B is configured such that the pixel array 110 is changed to a pixel array 110B, and the vertical scanning circuit 120 is changed to a vertical scanning circuit 120B, compared to the solid-state imaging device 100 of the first embodiment.

[0296] The pixel array 110B is configured in contrast to the pixel array 110 except that the pixels 111 are replaced with pixels 111B.

[0297] The vertical scanning circuit 120B is configured to change the pixel to be controlled from the pixel 111 to the pixel 111B relative to the vertical scanning circuit 120 .

[0298] Figure 22 111B is a circuit diagram showing a structural example of the pixel 111B.

[0299] like Figure 22 As shown, the pixel 111B is configured by adding a second reset transistor 62 to the pixel 111 .

[0300] One of the source and drain of the second reset transistor 62 is connected to the other of the source and drain of the first connection transistor 44, and the other of the source and drain of the second reset transistor 62 is connected to the second pixel power supply 72. Here, the voltage of the second pixel power supply 72 is different from the voltage of the first pixel power supply 71.

[0301] The second reset transistor 62 is an NMOS transistor, and its gate is driven by the control signal RS( 2 ) output from the vertical scanning circuit 120B.

[0302] The second reset transistor 62 is in a non-conductive state when the gate thereof becomes a logic level low, and is in a conductive state when the gate thereof becomes a logic level high.

[0303] According to the pixel 111B having the above-described structure, the signal charges accumulated in the floating diffusions 21 to 24 and the photoelectric conversion unit 10 can be discharged to the first pixel power supply 71, that is, reset at the voltage of the first pixel power supply 71, and the signal charges accumulated in the overflow capacitor storage unit 25 can be discharged to the second pixel power supply 72, that is, reset at the voltage of the second pixel power supply 72.

[0304] Here, although it is necessary to make the voltage of the second pixel power supply 72 lower than the voltage of the first pixel power supply 71 so that the voltage applied to the gate of the first connecting transistor 44 is equal to or higher than the voltage of the second pixel power supply 72, by making the voltage applied to the gate of the first connecting transistor 44 lower than the voltage of the first pixel power supply 71, the signal charge accumulated in the overflow capacitor storage unit 25 can be discharged to the second pixel power supply 72.

[0305] Therefore, according to the pixel 111B, compared with the pixel 111 having a structure in which the charges accumulated in the floating diffusion 21 to the floating diffusion 23, the photoelectric conversion unit 10, and the overflow capacitor storage unit 25 are discharged to the first pixel power supply 71, the discharge of the signal charge from the overflow capacitor storage unit 25 during the shutter operation becomes easier.

[0306] Therefore, according to the solid-state imaging device 100B having the above-described structure, compared with the solid-state imaging device 100 , afterimages are reduced when images are continuously captured, and dark signal non-uniformity is improved.

[0307] Furthermore, by making the voltage of the second pixel power supply 72 lower than the voltage of the first pixel power supply 71 , the reliability of the vertical scanning circuit 120B that drives the gate voltage of the first connection transistor 44 can be improved.

[0308] <Pixel Control Timing Example 2>

[0309] Hereinafter, an example of control timing of the pixel 111B will be described. In order to avoid excessive complexity, the following description will be given assuming that M=3 and N=2.

[0310] Figure 23 111B is a circuit diagram showing a configuration example of a pixel 111B in the case where M=3 and N=2.

[0311] Figure 24 It means to use Figure 23 1 is a timing chart showing an example of control timing of the pixel 111B when the pixel 111B outputs pixel signals corresponding to two gains, namely, gain 1 and gain 2, in the case of M=3 and N=2.

[0312] like Figure 24 As shown, in the readout row, the control signal GC(2) and the control signal RS(2) are always at logic low. Therefore, in the readout row, the first connection transistor 44 and the second reset transistor 62 are always turned off.

[0313] like Figure 24 As shown, Figure 24 The control timing of the pixel 111B in the timing diagram shown is the same as that from Figure 16 The control timing of pixel 111 in the timing diagram shown excludes the period from time t9 to time t10, and the control timing is the same after pixel 111 is replaced by pixel 111B, vertical scanning circuit 120 is replaced by vertical scanning circuit 120B, and solid-state imaging device 100 is replaced by solid-state imaging device 100B.

[0314] Therefore, here, about Figure 24 The control timing of the pixel 111B in the timing chart shown will be described mainly with respect to the operation during the period from time t9 to time t10.

[0315] At time t9, the vertical scanning circuit 120 changes the control signal GC(1) from logic high to logic low in the readout row under the control of the control circuit 130. As a result, the second connection transistor 41 in the pixel 111 changes from on to off.

[0316] On the other hand, the vertical scanning circuit 120B is controlled by the control circuit 130 to change the control signal GC(1), the control signal GC(2), and the control signal RS(2) from logic low to logic high in the shutter row. As a result, in the pixel 111B, the first connection transistor 44, the second connection transistor 41, and the second reset transistor 62 are turned from off to on, and the signal charge accumulated in the FD(3), the signal charge accumulated in the FD(1), and the signal charge accumulated in the FD(2) are discharged to the second pixel power supply 72.

[0317] That is, in the solid-state imaging device 100B, even when the pixel 111B outputs signal charges corresponding to gain 1 and gain 2 that are not based on the signal charges accumulated in the FD (3) in the readout row, the signal charges accumulated in both the photoelectric conversion section 10 and the FD (3) in the shutter row are discharged to the second pixel power supply 72. Therefore, the charge accumulation times of the photoelectric conversion section 10 and the FD (3) are substantially the same.

[0318] Therefore, when the types of the two pixel signals output by each pixel 111B are changed from a pixel signal corresponding to gain 1 and a pixel signal corresponding to gain 2 to a pixel signal corresponding to gain 2 and a pixel signal corresponding to gain 3, abnormal image quality of the first frame after the change can be avoided.

[0319] At time t10, the vertical scanning circuit 120B, under the control of the control circuit 130, changes the control signals GC(1), GC(2), and RS(2) from logic high to logic low in the shutter row. Consequently, in the pixel 111B, the first connection transistor 44, the second connection transistor 41, and the second reset transistor 62 change from on to off.

[0320] Figure 25 It means to use Figure 23 1 is a timing chart showing an example of control timing of the pixel 111B when the pixel 111B outputs pixel signals corresponding to two gains, namely, gain 1 and gain 2, in the case of M=3 and N=2.

[0321] like Figure 25 As shown, Figure 25 The control timing of the pixel 111B in the timing diagram shown is the same as that from Figure 17 The control timing of pixel 111 in the timing diagram shown excludes the period from time t9 to time t10, and the control timing is the same after pixel 111 is replaced by pixel 111B, vertical scanning circuit 120 is replaced by vertical scanning circuit 120B, and solid-state imaging device 100 is replaced by solid-state imaging device 100B.

[0322] Therefore, here, about Figure 25 The control timing of the pixel 111B in the timing chart shown will be described mainly with respect to the operation during the period from time t9 to time t10.

[0323] At time t9, the vertical scanning circuit 120B, under the control of the control circuit 130, changes the control signal RS(2) from logic low to logic high in the readout row. Consequently, in the pixel 111, the second reset transistor 62 changes from off to on, and the signal charge accumulated in FD(1), FD(2), and FD(3) are discharged to the second pixel power supply 72. Consequently, a reset component of the pixel signal corresponding to a gain of 3 is generated in the pixel 111B.

[0324] On the other hand, the vertical scanning circuit 120B is controlled by the control circuit 130 to change the control signal GC(1), the control signal GC(2), and the control signal RS(2) from logic low to logic high in the shutter row. As a result, in the pixel 111B, the first connection transistor 44, the second connection transistor 41, and the second reset transistor 62 are turned from off to on, and the signal charge accumulated in the FD(3), the signal charge accumulated in the FD(1), and the signal charge accumulated in the FD(2) are discharged to the second pixel power supply 72.

[0325] At time t10, the vertical scanning circuit 120B switches the control signal RS(2) from logic high to logic low in the readout row under the control of the control circuit 130. As a result, the second reset transistor 62 in the pixel 111 switches from on to off.

[0326] On the other hand, the vertical scanning circuit 120B is controlled by the control circuit 130 to change the control signal GC(1), the control signal GC(2), and the control signal RS(2) from a logic high level to a logic low level in the shutter row. As a result, in the pixel 111, the first connection transistor 44, the second connection transistor 41, and the second reset transistor 62 are turned from on to off.

[0327] (Implementation 3)

[0328] Hereinafter, a solid-state imaging device according to a third embodiment will be described, which has a partially modified configuration from the solid-state imaging device 100 according to the first embodiment.

[0329] Here, regarding the solid-state imaging device of the third embodiment, the same components as those of the solid-state imaging device 100 are given the same reference numerals as those already described, and detailed description thereof is omitted. The description will focus on the differences from the solid-state imaging device 100 .

[0330] Figure 26 This is a block diagram showing a configuration example of a solid-state imaging device 100C according to the third embodiment.

[0331] like Figure 26As shown, the solid-state imaging device 100C is configured such that the pixel array 110 is changed to a pixel array 110B, and the vertical scanning circuit 120 is changed to a first vertical scanning circuit 121, a second vertical scanning circuit 122, a third vertical scanning circuit 123, and a fourth vertical scanning circuit 124 relative to the solid-state imaging device 100 of embodiment 1.

[0332] The pixel array 110B is modified relative to the pixel array 110 to be configured as follows: L and K are even numbers, and a first pixel block 131, a second pixel block 132, a third pixel block 133, and a fourth pixel block 134 are arranged in a matrix. The first pixel block 131 is formed by arranging a plurality of pixels 111 in a matrix with L / 2 rows and K / 2 columns. The second pixel block 132 is formed by arranging a plurality of pixels 111 in a matrix with L / 2 rows and K / 2 columns. The third pixel block 133 is formed by arranging a plurality of pixels 111 in a matrix with L / 2 rows and K / 2 columns. The fourth pixel block 134 is formed by arranging a plurality of pixels 111 in a matrix with L / 2 rows and K / 2 columns.

[0333] That is, the first pixel block 131 is composed of a plurality of pixels 111 arranged in a matrix from row L / 2+1 to row L and from column 1 to column K / 2, the second pixel block 132 is composed of a plurality of pixels 111 arranged in a matrix from row L / 2+1 to row L and from column K / 2+1 to column K, the third pixel block 133 is composed of a plurality of pixels 111 arranged in a matrix from row 1 to row L / 2 and from column 1 to column K / 2, and the fourth pixel block 134 is composed of a plurality of pixels 111 arranged in a matrix from row 1 to row L / 2 and from column K / 2+1 to column K.

[0334] The first pixel block 131 may also be referred to as a first pixel array 131. The second pixel block 132 may also be referred to as a second pixel array 132. The third pixel block 133 may also be referred to as a third pixel array 133. The fourth pixel block 134 may also be referred to as a fourth pixel array 134.

[0335] The first vertical scanning circuit 121 is configured to change the pixels to be controlled by the vertical scanning circuit 120 from the plurality of pixels 111 constituting the pixel array 110 to the plurality of pixels 111 constituting the first pixel block 131 .

[0336] The second vertical scanning circuit 122 is configured to change the pixels to be controlled by the vertical scanning circuit 120 from the plurality of pixels 111 constituting the pixel array 110 to the plurality of pixels 111 constituting the second pixel block 132 .

[0337] The third vertical scanning circuit 123 is configured to change the pixels to be controlled by the vertical scanning circuit 120 from the plurality of pixels 111 constituting the pixel array 110 to the plurality of pixels 111 constituting the third pixel block 133 .

[0338] The fourth vertical scanning circuit 124 is configured to change the pixels to be controlled by the vertical scanning circuit 120 from the plurality of pixels 111 constituting the pixel array 110 to the plurality of pixels 111 constituting the fourth pixel block 134 .

[0339] The solid-state imaging device 100C with the above-mentioned structure is capable of performing the following controls independently of each other: control of which N pixel signals are output by the multiple pixels 111 belonging to the first pixel block 131; control of which N pixel signals are output by the multiple pixels 111 belonging to the second pixel block 132; control of which N pixel signals are output by the multiple pixels 111 belonging to the third pixel block 133; and control of which N pixel signals are output by the multiple pixels 111 belonging to the fourth pixel block 134.

[0340] Therefore, according to the solid-state imaging device 100C having the above-described configuration, it is possible to select a more appropriate dynamic range.

[0341] Figure 27 This is a block diagram showing a configuration example of an imaging device 200C according to the third embodiment.

[0342] like Figure 27 As shown, the imaging device 200C is configured such that, compared to the imaging device 200 of the first embodiment, the solid-state imaging device 100 is replaced by a solid-state imaging device 100C, the system control unit 205 is replaced by a system control unit 205C, and the drive circuit 204 is replaced by a drive circuit 204C.

[0343] Based on the image data successively output from the solid-state imaging device 100C, the system control unit 205C successively outputs a first gain designation signal that specifies which N pixel signals the pixel 111 outputs when the first vertical scanning circuit 121 of the solid-state imaging device 100C controls the pixel 111, successively outputs a second gain designation signal that specifies which N pixel signals the pixel 111 outputs when the second vertical scanning circuit 122 controls the pixel 111, successively outputs a third gain designation signal that specifies which N pixel signals the pixel 111 outputs when the third vertical scanning circuit 123 controls the pixel 111, and successively outputs a fourth gain designation signal that specifies which N pixel signals the pixel 111 outputs when the fourth vertical scanning circuit 124 controls the pixel 111.

[0344] The driving circuit 204C drives the solid-state imaging device 100C based on the first gain designation signal, the second gain designation signal, the third gain designation signal, and the fourth gain designation signal sequentially output from the system control unit 205C.

[0345] Therefore, according to the imaging device 200C having the above configuration, it is possible to achieve both a higher-level increase in frame rate and selection of an appropriate dynamic range.

[0346] Furthermore, in the third embodiment, the plurality of pixels constituting the pixel array 110C are described as being the pixels 111 , but the plurality of pixels constituting the pixel array 110C may be the pixels 111B.

[0347] Furthermore, in the third embodiment, the pixel array 110C is described as including four pixel blocks: the first pixel block 131, the second pixel block 132, the third pixel block 133, and the fourth pixel block 144. However, the pixel array 110C may include any number of pixel blocks and is not necessarily limited to four. For example, the pixel array 110C may include two pixel blocks: the first pixel block 131 and the second pixel block 132, or may include more than four pixel blocks.

[0348] In addition, in embodiment 3, it is described that the pixels 111 controlled by the first vertical scanning circuit 121 are arranged in a matrix within the first pixel block 131, the pixels 111 controlled by the second vertical scanning circuit 122 are arranged in a matrix within the second pixel block 132, the pixels 111 controlled by the third vertical scanning circuit 123 are arranged in a matrix within the third pixel block 133, and the pixels 111 controlled by the fourth vertical scanning circuit 124 are arranged in a matrix within the fourth pixel block 134.

[0349] However, the pixels 111 controlled by the first vertical scanning circuit 121 can be arranged at any position within the pixel array 110C, as long as they are arranged within the pixel array 110C, and are not necessarily limited to being arranged in a matrix within the first pixel block 131. The pixels 111 controlled by the second vertical scanning circuit 122 can be arranged at any position within the pixel array 110C, as long as they are arranged within the pixel array 110C, and are not necessarily limited to being arranged in a matrix within the second pixel block 132. The pixels 111 controlled by the third vertical scanning circuit 123 can be arranged at any position within the pixel array 110C, as long as they are arranged within the pixel array 110C, and are not necessarily limited to being arranged in a matrix within the third pixel block 133. The pixels 111 controlled by the fourth vertical scanning circuit 124 can be arranged at any position within the pixel array 110C, as long as they are arranged within the pixel array 110C, and are not necessarily limited to being arranged in a matrix within the fourth pixel block 134.

[0350] (Replenish)

[0351] As described above, as an illustration of the technology disclosed in this application, embodiments 1 to 3 have been described. However, the present disclosure is not limited to these embodiments. As long as it does not depart from the main purpose of the present disclosure, various modifications that can be thought of by those skilled in the art to the present embodiment, and methods constructed by combining constituent elements in different embodiments or modifications may also be included within the scope of one or more technical solutions of the present disclosure.

[0352] Industrial Applicability]

[0353] The present disclosure can be widely utilized in solid-state imaging devices and the like that capture images.

[0354] Description of Reference Numerals

[0355] 10 Photoelectric conversion unit

[0356] 21, 22, 23, 24 Capacitor storage unit (floating diffusion unit)

[0357] 25 Capacitor storage unit (overflow capacitor storage unit)

[0358] 30 pass transistor

[0359] 41, 42, 43 second connection transistor

[0360] 44 1st connection transistor

[0361] 50 Overflow transistor

[0362] 61 1st reset transistor

[0363] 62 2nd reset transistor

[0364] 71 1st pixel power supply

[0365] 72 2nd pixel power supply

[0366] 81 Amplifier transistor

[0367] 82 Select transistor

[0368] 100, 100A, 100B, 100C solid-state imaging devices

[0369] 110, 110B, 110C pixel arrays

[0370] 111, 111B pixels

[0371] 120, 120B vertical scanning circuit

[0372] 121 1st vertical scanning circuit

[0373] 122 2nd vertical scanning circuit

[0374] 123 3rd vertical scanning circuit

[0375] 124 4th vertical scanning circuit

[0376] 130 Control Circuit

[0377] 131 1st pixel block (1st pixel array)

[0378] 132 2nd pixel block (2nd pixel array)

[0379] 133 3rd pixel block (3rd pixel array)

[0380] 134 4th pixel block (4th pixel array)

[0381] 140 HDR synthesis circuit

[0382] 150 vertical signal lines

[0383] 160 AD converter

[0384] 170 Select detection circuit

[0385] 171 Selection Circuit

[0386] 172 Detection Circuit

[0387] 173 Sample and hold circuit SH

[0388] 174 Amplifier transistor SF

[0389] 175 Signal selection signal

[0390] 176 Reference value selection signal

[0391] 180 signal line

[0392] 181 Comparator

[0393] 182, 184 Inverter Circuit

[0394] 183, 186, 187 latch circuits

[0395] 185 AND Circuit

[0396] 188 Select Control Circuit

[0397] 189 Gain selection signal

[0398] 200, 200C camera device

[0399] 202 Camera Optical System

[0400] 203 Signal Processing Department

[0401] 204, 204C drive circuit

[0402] 205, 205C system control unit

Claims

1. A solid-state imaging device, wherein: A pixel array having a plurality of pixels arranged in a matrix, The plurality of pixels include: a photoelectric conversion unit that converts received light into signal charges; and Capacitor storage unit, The plurality of pixels are configured to output M pixel signals having different gains. The plurality of pixels are controlled to output N pixel signals among the M pixel signals, where N is an integer greater than or equal to 2 and less than M.

2. The solid-state imaging device according to claim 1, wherein The capacitance accumulation section includes an overflow capacitance accumulation section for accumulating signal charges overflowing from the photoelectric conversion section, and a floating diffusion section for converting the signal charges converted by the photoelectric conversion section into a voltage.

3. The solid-state imaging device according to claim 2, wherein The plurality of pixels further comprises: a transfer transistor, one of a source and a drain of the transfer transistor being connected to the photoelectric conversion portion, and the other of the source and the drain of the transfer transistor being connected to one of the floating diffusion portions; as well as A first connection transistor has one of a source and a drain connected to the overflow capacitance storage portion, and the other of a source and a drain connected to one of the floating diffusion portions.

4. The solid-state imaging device according to claim 3, wherein The controlling of the plurality of pixels includes shutter control for causing the plurality of pixels to perform a shutter action, Regardless of control for causing the plurality of pixels to output N pixel signals among the M pixel signals, the shutter control is performed on the plurality of pixels so that a period during which the overflow capacitor storage unit accumulates charge is substantially equal to a period during which the photoelectric conversion unit accumulates charge.

5. The solid-state imaging device according to claim 3 or 4, wherein The plurality of pixels further include an overflow transistor, one of a source and a drain of the overflow transistor being connected to the photoelectric conversion unit, and the other of the source and the drain of the overflow transistor being connected to the overflow capacitance storage unit.

6. The solid-state imaging device according to any one of claims 3 to 5, wherein There are multiple floating diffusion parts. Each of the plurality of pixels further includes one or more second connection transistors connected to the plurality of floating diffusions.

7. The solid-state imaging device according to any one of claims 3 to 6, wherein The plurality of pixels further include a first reset transistor having one of a source and a drain connected to the other of the source and the drain of the first connection transistor, and the other of the source and the drain connected to a first pixel power supply.

8. The solid-state imaging device according to claim 7, wherein The plurality of pixels further include a second reset transistor, one of a source and a drain of the second reset transistor being connected to the other of the source and the drain of the first connection transistor, and the other of the source and the drain of the second reset transistor being connected to a second pixel power supply having a voltage different from that of the first pixel power supply.

9. The solid-state imaging device according to any one of claims 1 to 8, wherein The plurality of pixels are controlled so that the plurality of pixels output N pixel signals composed of mutually adjacent gains among the M pixel signals.

10. A solid-state imaging device, wherein: have: a pixel array having a plurality of pixels arranged in a matrix; and An AD converter is arranged for each column of the pixel array. The plurality of pixels are configured to output M pixel signals having different gains. The AD converter converts at least one pixel signal among the M pixel signals into a digital signal having a smaller number of bits than other pixel signals.

11. The solid-state imaging device according to claim 10, wherein It also includes a selection detection circuit configured for each column of the pixel array, M pixel signals are input from the pixel array to the selection detection circuit, The selection detection circuit detects at least one pixel signal and at least one correction pixel signal from the M pixel signals and outputs the signals to the AD converter. The AD converter converts the pixel signal into a digital signal, and converts the correction pixel signal into a first correction digital signal having a smaller number of bits than the digital signal.

12. The solid-state imaging device according to claim 11, wherein It also has a high dynamic range synthesis circuit, namely the HDR synthesis circuit. The AD converter outputs the digital signal and the first correction digital signal to the HDR synthesis circuit. The HDR synthesis circuit, multiplying the value of the first correction digital signal by a coefficient to generate a second correction digital signal, A value obtained by multiplying the value of the digital signal by the first mixing ratio and a value obtained by multiplying the value of the second correction digital signal by the second mixing ratio are added together. The sum of the first mixing ratio and the second mixing ratio is 1.

13. A solid-state imaging device, wherein: have: a pixel array having a plurality of pixels arranged in a matrix; and An AD converter is arranged for each column of the pixel array. The plurality of pixels include: a photoelectric conversion unit that converts received light into signal charges; and Capacitor storage unit, The plurality of pixels are configured to output M pixel signals having different gains. The plurality of pixels are controlled to output N pixel signals out of the M pixel signals, where N is an integer greater than or equal to 2 and less than M. The AD converter converts at least one pixel signal among the N pixel signals into a digital signal having a smaller number of bits than other pixel signals.

14. The solid-state imaging device according to any one of claims 1 to 9 and 13, wherein The pixel array comprises: multiple pixel blocks; as well as a control circuit to enable the plurality of pixel blocks to independently select and output N pixel signals from the M pixel signals, The plurality of pixel blocks are composed of a plurality of first pixels arranged in a matrix. The plurality of first pixels are a portion of the plurality of pixels.

15. An imaging device comprising the solid-state imaging device according to any one of claims 1 to 9 and 13, wherein: The solid-state imaging device sequentially outputs image data based on the N pixel signals output by the plurality of pixels. The imaging device further includes a system control unit that sequentially outputs a gain designation signal based on the image data sequentially output from the solid-state imaging device, the gain designation signal designating which N pixel signals are to be output by each of the plurality of pixels in control of the plurality of pixels by the solid-state imaging device. The solid-state imaging device sequentially controls the plurality of pixels based on the gain designation signal sequentially output from the system control unit.

16. An imaging device comprising the solid-state imaging device according to claim 14, wherein: The solid-state imaging device sequentially outputs image data based on the N pixel signals output by the plurality of pixels. The imaging device further includes a system control unit that sequentially outputs a gain designation signal for each of the plurality of pixel blocks based on the image data sequentially output from the solid-state imaging device, wherein the gain designation signal for each of the plurality of pixel blocks specifies which N pixel signals are to be output by the first pixel included in each of the plurality of pixel blocks in control of each of the plurality of pixel blocks by the solid-state imaging device. The solid-state imaging device sequentially controls the first pixels included in each of the plurality of pixel blocks based on the gain designation signal for each of the plurality of pixel blocks sequentially output from the system control unit.

Images