Capacitive load driving circuit and liquid ejecting apparatus

Abstract

The invention provides a capacitive load driving circuit and a liquid ejecting apparatus, which can reduce the possibility of distortion in the waveform of a driving signal. The capacitive load drive circuit includes: a first digital amplifier circuit that outputs a first amplified signal to a first output node; a bootstrap circuit that includes a capacitor element connected to the first output node and the second output node, and a diode element having an anode terminal connected to the third transmission node and a cathode terminal connected to the second output node, and outputs a start-up voltage signal to the second output node; the second digital amplification circuit is connected with the first output node and the second output node and outputs a second amplification signal to a third output node; a smoothing circuit that smoothes the second amplified signal and outputs the smoothed second amplified signal as a drive signal; and a voltage limiting circuit which is connected with the third transmission node and the second output node and switches the conduction state of the third transmission node and the second output node according to the potential difference between the third transmission node and the second output node.

Description

Technical Field

[0001] The present invention relates to a capacitive load driving circuit and a liquid ejecting device. Background Art

[0002] Among liquid ejection devices that eject liquid to form images or text on a medium, there are known liquid ejection devices that use piezoelectric elements. In such liquid ejection devices, piezoelectric elements are provided corresponding to the plurality of nozzles that eject the liquid, and are driven according to drive signals. Furthermore, the piezoelectric elements are driven to eject liquid from the nozzles corresponding to the piezoelectric elements. In order to operate such piezoelectric elements, sufficient current must be supplied. Therefore, the drive circuit that outputs the drive signal for driving the piezoelectric elements includes an amplifier circuit that amplifies the source signal that forms the basis of the drive signal.

[0003] Patent document 1 discloses a drive circuit comprising: a pulse modulation circuit for modulating a basic drive signal serving as a basis for a drive signal and outputting a modulated signal; an amplifier circuit for outputting an amplified modulated signal obtained by amplifying the modulated signal from a first output point; a level shift circuit for outputting a level-shifted amplified modulated signal obtained by shifting the potential of the amplified modulated signal from a second output point; and a demodulation circuit for demodulating the level-shifted amplified modulated signal and outputting a drive signal, thereby enabling efficient signal amplification.

[0004] Patent Document 1: Japanese Patent Application Laid-Open No. 2022-057167

[0005] However, in the liquid ejection device described in Patent Document 1, there is a possibility that distortion may occur in the output drive signal waveform depending on the amount of current supplied to the load, and there is room for improvement. Summary of the Invention

[0006] One embodiment of a capacitive load driving circuit according to the present invention is a capacitive load driving circuit that outputs a driving signal, wherein the driving signal drives a capacitive load, and the capacitive load driving circuit includes:

[0007] a first digital amplifier circuit electrically connected to a first transmission node and a second transmission node, outputting a first amplified signal to a first output node, wherein the first transmission node transmits a first voltage signal of a first potential, and the second transmission node transmits a second voltage signal of a second potential;

[0008] A bootstrap circuit is electrically connected to the third transmission node and the first output node, outputting a startup voltage signal to the second output node, and the third transmission node transmits a third voltage signal of a third potential;

[0009] a second digital amplifier circuit connected to the first output node and the second output node, and outputting a second amplified signal to a third output node;

[0010] a smoothing circuit, configured to smooth the second amplified signal and output the smoothed signal as the driving signal; and

[0011] a voltage limiting circuit, electrically connected to the third transmission node and the second output node, for switching the conduction state between the third transmission node and the second output node;

[0012] The bootstrap circuit includes: a capacitor element having one end electrically connected to the first output node and the other end electrically connected to the second output node; and a diode element having an anode terminal electrically connected to the third transmission node and a cathode terminal electrically connected to the second output node.

[0013] The voltage limiting circuit switches the conduction state between the third transmission node and the second output node according to the potential difference between the third transmission node and the second output node.

[0014] One embodiment of the liquid ejection device according to the present invention includes:

[0015] a discharge portion that discharges liquid by being driven by a capacitive load; and

[0016] A capacitive load driving circuit outputs a driving signal, wherein the driving signal drives the capacitive load.

[0017] The capacitive load driving circuit has:

[0018] a first digital amplifier circuit electrically connected to a first transmission node and a second transmission node, outputting a first amplified signal to a first output node, wherein the first transmission node transmits a first voltage signal of a first potential, and the second transmission node transmits a second voltage signal of a second potential;

[0019] A bootstrap circuit is electrically connected to the third transmission node and the first output node, outputting a startup voltage signal to the second output node, and the third transmission node transmits a third voltage signal of a third potential;

[0020] a second digital amplifier circuit connected to the first output node and the second output node, and outputting a second amplified signal to a third output node;

[0021] a smoothing circuit, configured to smooth the second amplified signal and output the smoothed signal as the driving signal; and

[0022] a voltage limiting circuit, electrically connected to the third transmission node and the second output node, for switching the conduction state between the third transmission node and the second output node;

[0023] The bootstrap circuit includes: a capacitor element having one end electrically connected to the first output node and the other end electrically connected to the second output node; and a diode element having an anode terminal electrically connected to the third transmission node and a cathode terminal electrically connected to the second output node.

[0024] The voltage limiting circuit switches the conduction state between the third transmission node and the second output node according to the potential difference between the third transmission node and the second output node. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is a diagram showing an example of the structure of a liquid ejecting device.

[0026] Figure 2 It is a diagram showing the functional structure of the liquid ejecting device.

[0027] Figure 3 This is a diagram showing an example of the arrangement of a plurality of ejection parts in the head unit.

[0028] Figure 4 This is a diagram showing an example of the structure of the ejection portion.

[0029] Figure 5 : is a diagram showing an example of the signal waveform of the driving signal COM.

[0030] Figure 6 This is a diagram showing an example of the functional configuration of a driving circuit.

[0031] Figure 7 It is a diagram for explaining the operation of the driving circuit.

[0032] Figure 8 A diagram schematically showing current flowing in a drive circuit.

[0033] Figure 9 A diagram schematically showing current flowing in a drive circuit.

[0034] Figure 10 A diagram schematically showing current flowing in a drive circuit.

[0035] Figure 11 A diagram schematically showing current flowing in a drive circuit.

[0036] Figure 12 This is a diagram showing an example of the configuration of a boost voltage limiting circuit.

[0037] Figure 13 1 is a diagram showing an example of the configuration of a boost voltage limiting circuit according to a modified example.

[0038] Description of Reference Numerals

[0039] 1...Liquid ejection device, 2...Moving body, 3...Moving unit, 4...Conveying unit, 10...Control unit, 11...Power supply circuit, 13...Capacitor, 20...Head unit, 21...Liquid ejection head, 24...Slide, 31...Slide motor, 32...Slide guide shaft, 33...Timing belt, 40...Paper support unit, 41...Conveying motor, 42...Conveying roller, 50...Drive circuit, 60...Piezoelectric element, 100...Control circuit, 190...Cable, 210...Selection control unit, 23... 0...Selection unit, 510...D / A conversion circuit, 511...Adder, 520...Pulse modulation circuit, 521...Inverter, 530...Gate drive circuit, 531, 532...Gate driver, 550...Amplification circuit, 560...Demodulation circuit, 561...Inductor, 562...Capacitor, 570...Feedback circuit, 600...Ejection unit, 601...Piezoelectric element, 611, 612...Electrodes, 621...Vibration plate, 631...Cavity, 632...Nozzle plate, 641... Reservoir, 651…Nozzle, 710…Level switching signal output circuit, 721…Inverter, 730…Gate drive circuit, 731, 732…Gate driver, 750…Level shift circuit, 760…Boost circuit, 800…Boost voltage limiting circuit, 810…Voltage drop limiting circuit, 811…Transistor, 812…Constant voltage diode, 813…Resistor, 820…Voltage rise limiting circuit, 821…Transistor, 822…Constant voltage diode, 823…Resistor Resistor, 830…voltage rise protection circuit, 831…diode, 840…voltage rise protection circuit, 841…constant voltage diode, 842…resistor, C1, C11–C13…capacitors, D1, D11–D13…diodes, L…nozzle array, M1–M4…transistors, OP1…first output point, OP2…second output point, P…dielectric, Wam1, Wam2, Wbst, Wcom, Wgnd, Wvgd, Wvm1, Wvm2…wiring. DETAILED DESCRIPTION

[0040] The following describes preferred embodiments of the present invention using the accompanying drawings. The accompanying drawings are provided for ease of description. Furthermore, the embodiments described below do not unduly limit the scope of the present invention as described in the claims. Furthermore, not all of the structures described below are necessarily essential components of the present invention.

[0041] In the following description, a consumer inkjet printer, i.e., a serial-mode inkjet printer, is used as an example of the liquid ejection device involved in the present invention. However, the liquid ejection device is not limited to serial-mode inkjet printers; a line-mode inkjet printer may also be used. Furthermore, the liquid ejection device is not limited to inkjet printers; it may also be a colorant ejection device used in the manufacture of color filters for liquid crystal displays, etc., an electrode material ejection device used in forming electrodes for organic EL displays and surface-emitting displays, etc., or a bio-organic material ejection device used in the manufacture of biochips.

[0042] 1. Overview of Liquid Dispensing Device

[0043] Figure 1 1 is a diagram showing an example of the structure of the liquid ejecting device 1. Figure 1 As shown, the liquid ejecting apparatus 1 includes a movable body 2 and a moving unit 3 that reciprocates the movable body 2 in a main scanning direction.

[0044] The moving unit 3 includes: a carriage motor 31 which serves as a driving source for the reciprocating movement of the movable body 2 along the main scanning direction; a carriage guide shaft 32 fixed at both ends; and a timing belt 33 which extends roughly parallel to the carriage guide shaft 32 and is driven by the carriage motor 31.

[0045] The movable body 2 has a carriage 24. The carriage 24 is supported by a carriage guide shaft 32 so as to be reciprocatingly movable and is fixed to a portion of a timing belt 33. The timing belt 33 is moved forward and backward by the carriage motor 31, whereby the movable body 2 having the carriage 24 is guided by the carriage guide shaft 32 and reciprocates. In addition, the head unit 20 is located in a portion of the movable body 2 that is opposite to the medium P. That is, the head unit 20 is mounted on the carriage 24. A plurality of nozzles that eject ink as a liquid are located on the surface of the head unit 20 that is opposite to the medium P. In addition, various control signals for controlling the operation of the head unit 20 are supplied to the head unit 20 via a cable 190. As such a cable 190, a flexible flat cable or the like that can slide to follow the reciprocating movement of the movable body 2 can be used.

[0046] The liquid ejection device 1 also includes a transport unit 4 that transports the medium P along a transport direction on a paper support 40 (platen). The transport unit 4 includes a transport motor 41 that serves as a drive source for transporting the medium P, and a transport roller 42 that rotates with the driving force of the transport motor 41 to transport the medium P along the transport direction.

[0047] In the liquid ejection device 1 configured as described above, the head unit 20 ejects ink onto the medium P in synchronization with the timing of the medium P being transported by the transport unit 4. Thus, the ink ejected by the head unit 20 lands at a desired position on the medium P, forming a desired image or text on the surface of the medium P.

[0048] Next, the functional structure of the liquid ejecting device 1 will be described. Figure 2 1 is a diagram showing the functional structure of the liquid ejection device 1. Figure 2 As shown, the liquid ejecting device 1 includes a control unit 10, a head unit 20, a moving unit 3, a transport unit 4, and a cable 190. The cable 190 electrically connects the control unit 10 and the head unit 20.

[0049] The control unit 10 includes a power supply circuit 11 , a control circuit 100 , and a drive circuit 50 .

[0050] The power supply circuit 11 generates voltage signals VHV, VMV1, VMV2, and VGD having predetermined voltage values ​​from a commercial AC power source supplied externally to the liquid ejection device 1, and outputs these signals to various components of the liquid ejection device 1. Here, the voltage signal VHV is, for example, a 42V DC voltage, the voltage signal VMV1 is, for example, a 20V DC voltage, the voltage signal VMV2 is, for example, an 18V DC voltage, and the voltage signal VGD is, for example, a 7.5V DC voltage. Furthermore, the power supply circuit 11 can output DC voltages of varying voltage values ​​in addition to the voltage signals VHV, VMV1, VMV2, and VGD. In the following description, the voltage value of the voltage signal VHV may be referred to as voltage vhv, the voltage value of the voltage signal VMV1 as voltage vmv1, the voltage value of the voltage signal VMV2 as voltage vmv2, and the voltage value of the voltage signal VGD as voltage vgd.

[0051] Image data is supplied to the control circuit 100 from an external device (not shown) provided outside the liquid ejection device 1, such as a host computer. The control circuit 100 applies various image processing and the like to the supplied image data, thereby generating various control signals for controlling various components of the liquid ejection device 1 and outputting the signals to the various components.

[0052] Specifically, the control circuit 100 generates a control signal Ctrl1 based on image data to control the reciprocating movement of the movable body 2 and outputs it to the carriage motor 31 included in the movable unit 3. Furthermore, the control circuit 100 generates a control signal Ctrl2 based on image data to control the conveyance of the medium P and outputs it to the conveyance motor 41 included in the conveyance unit 4. Thus, the control circuit 100 controls the reciprocating movement of the movable body 2 in the main scanning direction and the conveyance of the medium P in the conveyance direction. Specifically, the head unit 20 can eject ink onto the medium P at a predetermined timing synchronized with the conveyance of the medium P. This allows the ink to land at a desired location on the medium P, allowing the desired image or text to be formed on the medium P.

[0053] In addition, the control circuit 100 can supply the control signal Ctrl1 used to control the reciprocating movement of the movable body 2 to the moving unit 3 after performing signal conversion on the control signal Ctrl1 through the unillustrated slide motor driver. Similarly, it can also supply the control signal Ctrl2 used to control the conveyance of the medium P to the conveying unit 4 after performing signal conversion on the control signal Ctrl2 through the unillustrated conveying motor driver.

[0054] Furthermore, the control circuit 100 outputs a basic drive signal dA to the drive circuit 50. This basic drive signal dA is a digital signal that includes information defining the signal waveform of the drive signal COM supplied to the head unit 20. The drive circuit 50 converts the basic drive signal dA into an analog signal and then amplifies the converted analog signal to generate the drive signal COM. The drive circuit 50 then supplies the generated drive signal COM to the head unit 20. The structure and operation of the drive circuit 50 will be described in detail later.

[0055] The control circuit 100 also generates a drive data signal DATA for controlling the operation of the head unit 20 and outputs the signal to the head unit 20. The head unit 20 includes a selection control unit 210, a liquid ejection head 21, and a plurality of selection units 230. Furthermore, the liquid ejection head 21 includes a plurality of ejection units 600 each including a piezoelectric element 60. Each of the plurality of selection units 230 is provided corresponding to a piezoelectric element 60 included in each of the plurality of ejection units 600 of the liquid ejection head 21.

[0056] The drive data signal DATA is input to the selection control unit 210. In addition, the selection control unit 210 operates using the voltage signal VHV as the drive power. Moreover, based on the drive data signal DATA, the selection control unit 210 generates a signal indicating whether the drive signal COM should be selected or not selected corresponding to each of the selection units 230, and generates a selection signal S obtained by level-shifting the generated signal to a signal based on the high-amplitude logic of the voltage signal VHV, and outputs it to the corresponding selection unit 230. The drive signal COM and the corresponding selection signal S are input to each of the multiple selection units 230. Each of the multiple selection units 230 generates and outputs the drive signal VOUT by selecting or not selecting the drive signal COM based on the selection signal S. That is, the multiple selection units 230 respectively generate the drive signal VOUT based on the drive signal COM, and supply it to one end of the piezoelectric element 60 included in the corresponding ejection unit 600 included in the liquid ejection head 21.

[0057] Furthermore, a reference voltage signal VBS is commonly supplied to the other ends of the piezoelectric elements 60 included in the plurality of ejection units 600. The reference voltage signal VBS serves as a reference potential for driving the piezoelectric elements 60 driven by the drive signal VOUT, and is a signal having a constant potential such as 5.5V, 6V, or 0V.

[0058] The piezoelectric element 60 is provided corresponding to each of the multiple nozzles in the head unit 20. The piezoelectric element 60 is driven based on the potential difference between a drive signal VOUT supplied to one end and a reference voltage signal VBS supplied to the other end. As a result, the ejection unit 600, which includes the piezoelectric element 60, ejects an amount of ink corresponding to the amount the piezoelectric element 60 is driven.

[0059] In addition, Figure 2 , the head unit 20 is shown as having one liquid ejecting head 21. However, the number of liquid ejecting heads 21 included in the head unit 20 is not limited to one. That is, the head unit 20 may include a plurality of liquid ejecting heads 21 depending on the type and amount of ink to be ejected.

[0060] As described above, the liquid ejection device 1 in this embodiment includes: a liquid ejection head 21, which has a plurality of piezoelectric elements 60 driven by being supplied with drive signals COM and VOUT, and ejects ink as an example of liquid by driving the plurality of piezoelectric elements 60; and a drive circuit 50, which outputs the drive signal COM.

[0061] 2. Structure of the ejection part

[0062] Next, an example of the structure of the plurality of ejection portions 600 included in the liquid ejection head 21 and the arrangement of the plurality of ejection portions 600 in the head unit 20 will be described. Figure 3 is a diagram showing an example of the arrangement of the plurality of ejection parts 600 in the head unit 20. Figure 3 exemplified in FIG. 5 is a case where the head unit 20 includes four liquid ejection heads 21 .

[0063] like Figure 3As shown, the four liquid ejection heads 21 each have a plurality of ejection portions 600 arranged in a row in one direction. That is, the liquid ejection head 21 includes a nozzle row L in which the nozzles 651 described later included in the ejection portion 600 are arranged in one direction. In addition, the liquid ejection heads 21 are located side by side in the head unit 20 in a direction intersecting the nozzle row L. That is, the same number of nozzle rows L as the number of liquid ejection heads 21 are formed in the head unit 20. In addition, the arrangement of the nozzles 651 in the nozzle row L is not limited to one row. For example, the nozzles 651 may be arranged in a staggered manner in such a manner that the positions of the even-numbered nozzles 651 counted from one end of the plurality of nozzles 651 and the odd-numbered nozzles 651 counted from one end of the plurality of nozzles 651 are different. Alternatively, one nozzle row L may be formed by arranging the plurality of nozzles 651 in two or more rows.

[0064] Next, an example of the structure of the discharge portion 600 will be described. Figure 4 : is a diagram showing an example of the structure of the ejection portion 600. Figure 4 As shown, the ejection unit 600 includes a piezoelectric element 60, a vibration plate 621, a cavity 631, and a nozzle 651. The vibration plate 621 is provided with Figure 4 The piezoelectric element 60 provided on the upper surface of the cavity 631 is driven to displace the vibrating plate 621. The vibrating plate 621 functions as a diaphragm that expands and contracts the internal volume of the cavity 631. The cavity 631 is filled with ink. The cavity 631 functions as a pressure chamber whose internal volume changes due to the displacement of the vibrating plate 621 caused by the piezoelectric element 60. The nozzle 651 is an opening formed in the nozzle plate 632 and connected to the cavity 631. Furthermore, as the internal volume of the cavity 631 changes, the ink stored in the cavity 631 is ejected from the nozzle 651.

[0065] The piezoelectric element 60 has a structure in which a piezoelectric body 601 is sandwiched between a pair of electrodes 611 and 612. In this structure, the piezoelectric body 601 is configured such that the center of the electrodes 611 and 612 and the vibration plate 621 are symmetrical relative to the end portions, depending on the potential difference between the electrodes 611 and 612. Figure 4 Deflection in the up and down directions.

[0066] Specifically, a drive signal VOUT is supplied to electrode 611, which is one end of the piezoelectric element 60, and a reference voltage signal VBS is supplied to electrode 612, which is the other end. Furthermore, when the piezoelectric element 60 is driven upward in response to a change in the voltage of the drive signal VOUT, the vibration plate 621 is displaced upward. As a result, the internal volume of the cavity 631 expands. Therefore, the ink stored in the reservoir 641 is introduced into the cavity 631. On the other hand, when the piezoelectric element 60 is driven downward in response to a change in the voltage value of the drive signal VOUT, the vibration plate 621 is displaced downward. As a result, the internal volume of the cavity 631 decreases. Therefore, an amount of ink corresponding to the degree of decrease in the internal volume of the cavity 631 is ejected from the nozzle 651.

[0067] As described above, the liquid ejection head 21 includes the piezoelectric element 60 , and ink is ejected onto the medium P by driving the piezoelectric element 60 . The ejection unit 600 and the piezoelectric element 60 included in the ejection unit 600 are not limited to the illustrated configurations, and any configuration may be used as long as the piezoelectric element 60 can be driven based on the drive signal VOUT and ink is ejected from the corresponding nozzle 651 by the drive of the piezoelectric element 60 .

[0068] 3. Drive circuit structure and operation

[0069] Next, the configuration and operation of the drive circuit 50 will be described.

[0070] 3.1 Signal waveform of driving signal COM

[0071] When describing the configuration and operation of the drive circuit 50 , first, an example of the signal waveform of the drive signal COM output by the drive circuit 50 will be described. Figure 5 : is a diagram showing an example of a signal waveform of the drive signal COM. Figure 5 As shown, the drive signal COM includes a trapezoidal waveform Adp in each cycle T. The trapezoidal waveform Adp includes: a period in which the voltage value is constant at voltage vc; a period in which the voltage value is constant at voltage vb, which is lower than voltage vc, follows the period in which the voltage value is constant at voltage vb; a period in which the voltage value is constant at voltage vt, which is higher than voltage vc, follows the period in which the voltage value is constant at voltage vb; and a period in which the voltage value is constant at voltage vt, which is followed by a period in which the voltage value is constant at voltage vc. In other words, the drive signal COM includes a trapezoidal waveform Adp whose voltage value varies between voltage vt and voltage vb and which begins and ends at voltage vc in cycle T.

[0072] The voltage vc corresponds to a potential that serves as a reference for the displacement of the piezoelectric element 60. When the voltage value of the driving signal COM supplied to the piezoelectric element 60 changes from the voltage vc to the voltage vb, the piezoelectric element 60 moves to the Figure 4As a result, the vibration plate 621 moves in the upward direction. Figure 4 Furthermore, the vibration plate 621 is displaced upward. Figure 4 The inner volume of the cavity 631 is expanded, and the ink stored in the reservoir 641 is introduced into the cavity 631. Thereafter, the voltage value of the driving signal COM supplied to the piezoelectric element 60 changes from the voltage vb to the voltage vt, and the piezoelectric element 60 moves to the upper direction. Figure 4 As a result, the vibration plate 621 is driven in the downward direction. Figure 4 Furthermore, the vibration plate 621 is displaced downward. Figure 4 The inner volume of the cavity 631 is reduced by the downward displacement shown, and the ink stored in the cavity 631 is ejected from the nozzle 651 .

[0073] Furthermore, the ink near the nozzle 651 and the vibration plate 621 may continue to vibrate during a constant period after the ink is ejected from the nozzle 651 by driving the piezoelectric element 60. The period during which the voltage value included in the driving signal COM is constant at the voltage vc also serves as a period for stabilizing the vibration generated in the ink and the vibration plate 621 that does not contribute to ink ejection.

[0074] Here, Figure 5 The signal waveform of the driving signal COM shown is an example and is not limited thereto. Signal waveforms of various shapes may be included depending on the physical properties of the ink ejected from the liquid ejection head 21, the length of the period T of the driving signal COM, the conveying speed of the medium P, etc.

[0075] 3.2 Structure of the driving circuit

[0076] Next, the configuration of the drive circuit 50 will be described. Figure 6 1 is a diagram showing an example of the functional structure of the driving circuit 50. Figure 6 As shown, the driving circuit 50 has a D / A conversion circuit 510, an adder 511, a pulse modulation circuit 520, an inverter 521, an amplifier circuit 550, a demodulation circuit 560, a feedback circuit 570, a level switching signal output circuit 710, a level shift circuit 750, a boost circuit 760 and a boost voltage limiting circuit 800.

[0077] The control circuit 100 inputs a digital signal, the basic drive signal dA, to the D / A converter circuit 510. The D / A converter circuit 510 performs digital-to-analog conversion on the basic drive signal dA and outputs the converted analog signal as the basic drive signal aA. Specifically, the D / A converter circuit 510 converts the digital basic drive signal dA, which serves as the basis for the drive signal COM, into an analog basic drive signal aA. The voltage amplitude of the basic drive signal aA is, for example, 1 to 2V. The drive circuit 50 outputs the signal obtained by amplifying the basic drive signal aA as the drive signal COM. In other words, the basic drive signal aA corresponds to the target signal of the drive signal COM before amplification.

[0078] The basic drive signal aA is input to the positive input terminal of the adder 511. The feedback signal VFB, which is the result of feedback of the drive signal COM via the feedback circuit 570 described later, is input to the negative input terminal of the adder 511. The adder 511 then subtracts the feedback signal VFB from the basic drive signal aA and outputs the signal to the pulse modulation circuit 520.

[0079] The pulse modulation circuit 520 generates a modulation signal MS by pulse-modulating the signal output from the adder 511. Specifically, the pulse modulation circuit 520 outputs the modulation signal MS by modulating the analog base drive signal aA. The modulation signal MS is a digital signal consisting of an L-level potential and an H-level potential higher than the L-level. The pulse modulation circuit 520 then outputs the generated modulation signal MS to the amplifier circuit 550. This pulse modulation circuit 520 generates a pulse density modulated signal (PDM signal) by modulating the signal output from the adder 511 using a pulse density modulation (PDM) method, and outputs this PDM signal as the modulation signal MS to the amplifier circuit 550. Specifically, the pulse modulation circuit 520 compares the voltage value of the output signal from the adder 511 with a predetermined reference voltage vref. The pulse modulation circuit 520 outputs a modulation signal MS that becomes H level when the voltage value of the output signal of the adder 511 is larger than the reference voltage vref, and becomes L level when the voltage value of the output signal of the adder 511 is smaller than the reference voltage vref.

[0080] The amplifier circuit 550 includes a gate drive circuit 530, a diode D1, a capacitor C1, and transistors M1 and M2. The amplifier circuit 550 generates a first amplified modulation signal AMS1 obtained by amplifying the modulation signal MS and outputs the amplified signal from a first output point OP1.

[0081] The gate driver circuit 530 outputs gate signals HGD1 and LGD1 based on the modulation signal MS. Specifically, the modulation signal MS is input to a gate driver 531 included in the gate driver circuit 530. The gate driver 531 generates a gate signal HGD1 by level-shifting the modulation signal MS and outputs it to the transistor M1. Furthermore, the modulation signal MS is logic-level-inverted in the inverter 521 and then input to a gate driver 532 included in the gate driver circuit 530. The gate driver 532 generates a gate signal LGD1 by level-shifting the logic-level-inverted modulation signal MS and outputs it to the transistor M2.

[0082] Transistors M1 and M2 are both composed of N-channel MOSFETs. Transistor M1 has its source terminal electrically connected to the first output point OP1, and a voltage signal VMV1 (voltage vmv) is supplied to its drain terminal via wiring Wvm1 as a power supply voltage. It operates based on a gate signal HGD1 input to its gate terminal. Furthermore, transistor M2 has its drain terminal electrically connected to the first output point OP1, and a ground signal GND (ground potential gnd, 0V) is supplied to its source terminal via wiring Wgnd. It operates based on a gate signal LGD1 input to its gate terminal.

[0083] Furthermore, transistor M1 operates based on gate signal HGD1, and transistor M2 operates based on gate signal LGD1. As a result, a first amplified modulated signal AMS1 is generated at first output point OP1, which is obtained by amplifying the modulated signal MS based on ground potential gnd and voltage vmv1. In other words, amplifier circuit 550 outputs first amplified modulated signal AMS1, which is obtained by amplifying the modulated signal MS based on ground potential gnd and voltage vmv1.

[0084] Here, the operation of the gate driver circuit 530 is described. The gate driver circuit 530 includes gate drivers 531 and 532. As described above, the modulation signal MS is input to the gate driver 531, and the signal obtained by inverting the logic level of the modulation signal MS by the inverter 521 is input to the gate driver 532. In other words, the signal input to the gate driver 531 and the signal input to the gate driver 532 are exclusively at the H level. Here, "exclusively at the H level" includes the case where the H level signals are not input to the gate driver 531 and the gate driver 532 at the same time. In other words, the case where the L level signals are input to the gate driver 531 and the gate driver 532 at the same time is not excluded.

[0085] The low-potential power supply terminal of the gate driver 531 is electrically connected to the first output point OP1. Therefore, the signal generated at the first output point OP1 is supplied to the low-potential power supply terminal of the gate driver 531 as a voltage signal HVS1. Furthermore, the high-potential power supply terminal of the gate driver 531 is electrically connected to the cathode terminal of the diode D1 and one end of the capacitor C1. Furthermore, the anode terminal of the diode D1 is supplied with the voltage signal VGD via the wiring Wvgd, and the other end of the capacitor C1 is electrically connected to the first output point OP1. In other words, the diode D1 and the capacitor C1 form a bootstrap circuit, the output voltage of which is supplied to the high-potential power supply terminal of the gate driver 531. Therefore, the high-potential power supply terminal of the gate driver 531 is supplied with a voltage signal HVD1 that is higher than the voltage value of the voltage signal HVS1 input to the low-potential power supply terminal of the gate driver 531 by a voltage value of the voltage signal VGD, i.e., a voltage value of the voltage vgd.

[0086] Therefore, when the gate driver 531 is input with the modulation signal MS of the H level, it outputs the gate signal HGD1 having a voltage value based on the voltage signal HVD1 having a voltage value higher than the voltage value of the first output point OP1 by a voltage vgd. When the gate driver 531 is input with the modulation signal MS of the L level, it outputs the gate signal HGD1 having a voltage value based on the voltage value of the first output point OP1, i.e., the voltage value of the voltage signal HVS1.

[0087] Here, the voltage vgm may be any voltage value capable of driving each of the transistors M1 , M2 and transistors M3 and M4 described later, and is not limited to a DC voltage of 7.5V.

[0088] A ground signal GND at the ground potential gnd is supplied as a voltage signal LVS1 to the low-potential power supply terminal of the gate driver 532. Furthermore, a voltage signal VGD is supplied as a voltage signal LVD1 to the high-potential power supply terminal of the gate driver 532. Therefore, when the gate driver 532 receives an H-level signal obtained by inverting the logic level of the L-level modulation signal MS by the inverter 521, it outputs a gate signal LGD1 based on the voltage value of the voltage signal LVD1 at the voltage vm. When the gate driver 532 receives an L-level signal obtained by inverting the logic level of the H-level modulation signal MS by the inverter 521, it outputs a gate signal LGD1 based on the voltage value of the voltage signal LVS1 at the ground potential gnd.

[0089] The level-switching signal output circuit 710 receives a base drive signal dA as input and generates a level-switching signal LS based on the base drive signal dA. The level-switching signal LS is a digital signal that includes an L-level potential and an H-level potential, which is higher than the L level. Specifically, the level-switching signal output circuit 710 outputs an H-level level-switching signal LS when the value of the base drive signal dA is greater than a predetermined threshold value, and outputs an L-level level-switching signal LS when the value of the base drive signal dA is less than the predetermined threshold value. In other words, the level-switching signal output circuit 710 outputs the level-switching signal LS based on the base drive signal dA.

[0090] The level shift circuit 750 includes a gate drive circuit 730, diodes D11 and D12, capacitors C11 and C12, and transistors M3 and M4. Furthermore, the level shift circuit 750 outputs the first amplified modulation signal AMS1 or a signal obtained by level-shifting the reference potential of the first amplified modulation signal AMS1 as the second amplified modulation signal AMS2 to a second output point OP2.

[0091] The gate driver circuit 730 outputs gate signals HGD2 and LGD2 based on the level-switching signal LS. Specifically, the level-switching signal LS is input to a gate driver 731 included in the gate driver circuit 730. The gate driver 731 generates a gate signal HGD2 by level-shifting the level-switching signal LS and outputs it to the transistor M3. Furthermore, the level-switching signal LS is logic-level-inverted in the inverter 721 and then input to a gate driver 732 included in the gate driver circuit 730. The gate driver 732 generates a gate signal LGD2 by level-shifting the logic-level-inverted signal LS and outputs it to the transistor M4.

[0092] Transistors M3 and M4 are both composed of N-channel MOSFETs. Transistor M3 has its source terminal electrically connected to the second output point OP2, a power supply voltage supplied to its drain terminal via wiring Wbst, and operates based on a gate signal HGD2 input to its gate terminal. Furthermore, transistor M4 has its drain terminal electrically connected to the second output point OP2, a first amplified modulation signal AMS1 supplied to its source terminal via wiring Wam1, and operates based on a gate signal LGD2 input to its gate terminal.

[0093] Furthermore, transistor M3 operates based on gate signal HGD2, and transistor M4 operates based on gate signal LGD2. As a result, at second output point OP2, either the first amplified modulation signal AMS1 or a signal obtained by level-shifting the reference potential of the first amplified modulation signal AMS1 according to the power supply voltage supplied to the drain terminal of transistor M3 is generated as the second amplified modulation signal AMS2. Specifically, level shift circuit 750 selects, based on level switching signal LS, a signal in which the reference potential of the first amplified modulation signal AMS1 is shifted to the power supply voltage input via wiring Wbst, or a signal in which the reference potential of the first amplified modulation signal AMS1 is not shifted, and outputs the signal as the second amplified modulation signal AMS2.

[0094] Here, the power supply voltage supplied to the drain terminal of transistor M3 is supplied from booster circuit 760 via wiring Wbst. Booster circuit 760 includes a diode D13 and a capacitor C13. One end of capacitor C13 is electrically connected to the first output point OP1 via wiring Wam1, to which the first amplified modulated signal AMS1 is supplied. The other end of capacitor C13 is electrically connected to wiring Wbst, which supplies the power supply voltage to the drain terminal of transistor M3. The anode terminal of diode D13 is supplied with voltage signal VMV2 via wiring Wvm2, and the cathode terminal of diode D13, along with the other end of capacitor C13, is electrically connected to wiring Wbst. Furthermore, booster circuit 760 is a connection point connecting the other end of capacitor C13 and the cathode terminal of diode D13, and outputs the signal from wiring Wbst as voltage signal VMV3. Voltage signal VMV3 output by booster circuit 760 is supplied to the drain terminal of transistor M3 as the power supply voltage for transistor M3. That is, the boost circuit 760 includes a capacitor C13 having one end electrically connected to the wiring Wam1 and the other end electrically connected to the wiring Wbst; and a diode D13 having an anode terminal electrically connected to the wiring Wvm2 and a cathode terminal electrically connected to the wiring Wam1.

[0095] In the booster circuit 760 configured as described above, the charge corresponding to the voltage value of the voltage signal VMV2, i.e., voltage vmv2, is accumulated in the capacitor C13. Furthermore, based on the charge accumulated in the capacitor C13, the booster circuit 760 adds the voltage value of the first amplified modulation signal AMS1 to the voltage value across the capacitor C13, i.e., the voltage value corresponding to voltage vmv2, and outputs the signal as voltage signal VMV3 to the drain terminal of the transistor M3. Here, the voltage value across the capacitor C13 is, to be more precise, the value obtained by subtracting the forward voltage of the diode D13 from the voltage value of the voltage signal VMV2, i.e., voltage vmv2. However, in this embodiment, the voltage value across the capacitor C13 is assumed to be equal to the voltage value of the voltage signal VMV2 supplied to the booster circuit 760, i.e., voltage vmv2. Specifically, the booster circuit 760 is electrically connected to the wiring Wvm2 and the wiring Wam1, which transmit the voltage signal VMV2 having a voltage value vmv2, and outputs the voltage signal VMV3 to the wiring Wbst.

[0096] Boosted voltage limiting circuit 800 is electrically connected to wiring Wvm2 that transmits voltage signal VMV2 and wiring Wbst that transmits voltage signal VMV3. Boosted voltage limiting circuit 800 limits the voltage value of voltage signal VMV3 output from boosting circuit 760 based on voltage vmv2, which is the voltage value of voltage signal VMV2. Details of the structure and operation of boosted voltage limiting circuit 800 will be described later.

[0097] Here, the operation of gate driver circuit 730 is described. Gate driver circuit 730 includes gate drivers 731 and 732. As described above, level switching signal LS is input to gate driver 731, and a signal obtained by inverting the logic level of level switching signal LS by inverter 721 is input to gate driver 732. In other words, the signals input to gate driver 731 and the signals input to gate driver 732 are exclusively at the H level. Here, "exclusively at the H level" includes the case where H-level signals are not simultaneously input to gate driver 731 and gate driver 732. In other words, the case where L-level signals are simultaneously input to gate driver 731 and gate driver 732 is not excluded.

[0098] The low-potential-side power supply terminal of the gate driver 731 is electrically connected to the second output point OP2. Therefore, the signal generated at the second output point OP2 is supplied to the low-potential-side power supply terminal of the gate driver 731 as the voltage signal HVS2. Furthermore, the high-potential-side power supply terminal of the gate driver 731 is electrically connected to the cathode terminal of the diode D11 and one end of the capacitor C11. Furthermore, the anode terminal of the diode D11 is supplied with the voltage signal VGD via the wiring Wvgd, and the other end of the capacitor C11 is electrically connected to the second output point OP2. In other words, the diode D11 and the capacitor C11 form a bootstrap circuit, the output voltage of which is supplied to the high-potential-side power supply terminal of the gate driver 731. Therefore, the high-potential-side power supply terminal of the gate driver 731 is supplied with the voltage signal HVD2, which is higher than the voltage value of the voltage signal HVS2 input to the low-potential-side power supply terminal of the gate driver 731 by the voltage value of the voltage signal VGD, i.e., the voltage value of the voltage vgd.

[0099] Therefore, when the level switching signal LS of the H level is input, the gate driver 731 outputs the gate signal HGD2 based on the voltage value of the voltage signal HVD2 which is higher than the voltage value of the second output point OP2 by the voltage vgd. When the level switching signal LS of the L level is input, the gate driver 731 outputs the gate signal HGD2 based on the voltage value of the second output point OP2, that is, the voltage value of the voltage signal HVS2.

[0100] The low-potential-side power supply terminal of the gate driver 732 is electrically connected to the first output point OP1 via wiring Wam1. Therefore, the first amplified modulated signal AMS1 generated at the first output point OP1 is supplied to the low-potential-side power supply terminal of the gate driver 732 as a voltage signal LVS2. Furthermore, the high-potential-side power supply terminal of the gate driver 732 is electrically connected to the cathode terminal of the diode D12 and one end of the capacitor C12. Furthermore, the anode terminal of the diode D12 is supplied with the voltage signal VGD via wiring Wvgd, and the other end of the capacitor C12 is electrically connected to the first output point OP1 via wiring Wam1. In other words, the diode D12 and the capacitor C12 form a bootstrap circuit, the output voltage of which is supplied to the high-potential-side power supply terminal of the gate driver 732. Therefore, the high-potential-side power supply terminal of the gate driver 732 is supplied with a voltage signal LVD2 that is higher than the voltage value of the voltage signal LVS2 input to the low-potential-side power supply terminal of the gate driver 732 by a voltage value of the voltage signal VGD, i.e., a voltage value of the voltage vgd.

[0101] Therefore, when the gate driver 732 is input with an H-level signal in which the logic level of the level switching signal LS of the L level is inverted by the inverter 721, the gate driver 732 outputs a gate signal LGD2 based on the voltage value of the voltage signal LVD2 which is higher than the voltage value of the first output point OP1 by a voltage vgd. When the gate driver 732 is input with an L-level signal in which the logic level of the level switching signal LS of the H level is inverted by the inverter 721, the gate driver 732 outputs a gate signal LGD2 based on the voltage value of the first output point OP1, i.e., the voltage value of the voltage signal LVS2.

[0102] When the level-switching signal LS at an L level, output from the level-switching signal output circuit 710, is input to the level shift circuit 750 configured as described above, the first output point OP1 of the amplifier circuit 550 and the second output point OP2 of the level shift circuit 750 are electrically connected via the transistor M4. Therefore, when the level-switching signal LS at an L level is input, the level shift circuit 750 outputs the first amplified modulated signal AMS1 supplied to the second output point OP2 via the transistor M4 as the second amplified modulated signal AMS2.

[0103] On the other hand, when the level-switching signal LS at an H level, output from the level-switching signal output circuit 710, is input to the level shift circuit 750, the first output point OP1 of the amplifier circuit 550 and the second output point OP2 of the level shift circuit 750 are electrically connected via the boost circuit 760 and the transistor M3. Therefore, when the level-switching signal LS at an H level is input, the level shift circuit 750 outputs a voltage signal VMV3 as the second amplified modulated signal AMS2. This voltage signal VMV3 is a signal obtained by level-shifting the reference potential of the first amplified modulated signal AMS1 by a voltage vmv2, which is the voltage value of the voltage signal VMV2.

[0104] In the following description, the operating mode in which the level shift circuit 750 outputs the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2 is referred to as the first mode MD1, and the operating mode in which the level shift circuit 750 outputs the signal obtained by level-shifting the potential of the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2 is referred to as the second mode MD2. Specifically, the level shift circuit 750 operates in the first mode MD1 when the level switching signal LS is at the L level, and in the second mode MD2 when the level switching signal LS is at the H level.

[0105] Furthermore, as described above, when the value of the base drive signal dA is less than a predetermined threshold, the level-switching signal output circuit 710 outputs the level-switching signal LS at an L level. Therefore, when the value of the base drive signal dA is less than the predetermined threshold, the operation mode of the level shift circuit 750 becomes the first mode MD1. Thereafter, when the value of the base drive signal dA becomes greater than the predetermined threshold, the level-switching signal output circuit 710 switches the level-switching signal LS from an L level to an H level. Thus, the operation mode of the level shift circuit 750 switches from the first mode MD1 to the second mode MD2. Furthermore, immediately after switching the logic level of the level-switching signal LS from an L level to an H level, the level-switching signal output circuit 710 outputs a pulse signal in which the logic level of the output level-switching signal LS is at an L level for a short period of time, one or more times, in order to reduce waveform distortion of the drive signal COM that may occur with the switching of the operation mode of the level shift circuit 750.

[0106] On the other hand, when the value of the basic drive signal dA is greater than a predetermined threshold, the level switching signal output circuit 710 outputs the level switching signal LS at an H level. Therefore, the operating mode of the level shift circuit 750 becomes the second mode MD2. Thereafter, when the value of the basic drive signal dA becomes less than the predetermined threshold, the level switching signal output circuit 710 switches the level switching signal LS from an H level to an L level. Thus, the operating mode of the level shift circuit 750 switches from the second mode MD2 to the first mode MD1. Furthermore, immediately after switching the logic level of the level switching signal LS from an H level to an L level, the level switching signal output circuit 710 outputs a pulse signal in which the logic level of the output level switching signal LS is at an H level for a short period of time, one or more times, in order to reduce waveform distortion of the drive signal COM that may occur with the switching of the operating mode of the level shift circuit 750.

[0107] Here, in the following description, a pulse signal that becomes an L level for a short period of time when the operation mode of the level shift circuit 750 is switched from the first mode MD1 to the second mode MD2, and a pulse signal that becomes an H level for a short period of time when the operation mode of the level shift circuit 750 is switched from the second mode MD2 to the first mode MD1 are sometimes referred to as a counter pulse CP.

[0108] The second amplified modulated signal AMS2 output by the level shift circuit 750 is transmitted through the wiring Wam2 and input to the demodulation circuit 560. The demodulation circuit 560 demodulates the second amplified modulated signal AMS2 output by the level shift circuit 750 by smoothing it, thereby generating the drive signal COM. The drive signal COM generated by the demodulation circuit 560 is transmitted through the wiring Wcom and output from the driver circuit 50.

[0109] The demodulation circuit 560 includes an inductor 561 and a capacitor 562. One end of the inductor 561 is electrically connected to the second output point OP2 via the wiring Wam2. The other end of the inductor 561 is electrically connected to one end of the capacitor 562 via the wiring Wcom. Furthermore, the other end of the capacitor 562 is supplied with a ground signal GND at the ground potential gnd transmitted via the wiring Wgnd. In other words, the inductor 561 and the capacitor 562 form a low-pass filter circuit. This low-pass filter circuit smoothes the second amplified modulation signal AMS2 output from the level shift circuit 750. The demodulation circuit 560 then transmits the smoothed second amplified modulation signal AMS2 via the wiring Wcom as the drive signal COM, which is then output from the drive circuit 50.

[0110] Feedback circuit 570 receives the drive signal COM generated by demodulation circuit 560 and outputs a feedback signal VFB to adder 511. Specifically, feedback circuit 570 supplies feedback signal VFB, which is a voltage-divided version of drive signal COM, to adder 511. This feeds drive signal COM back to pulse modulation circuit 520. As a result, the waveform accuracy of drive signal COM output by drive circuit 50 is improved. Here, feedback circuit 570 may also feed back multiple signals as feedback signal VFB, including a signal obtained by dividing drive signal COM and a signal obtained by extracting the high-frequency component of drive signal COM. In other words, feedback circuit 570 may include multiple feedback circuits, each of which feeds back the signal obtained by dividing drive signal COM and a signal obtained by extracting the high-frequency component of drive signal COM. This allows for the separate feedback of the high-frequency component of drive signal COM. As a result, drive circuit 50 can self-oscillate based on this high-frequency component, increasing the frequency of modulation signal MS to a level sufficient to ensure the accuracy of drive signal COM. Therefore, the waveform accuracy of the driving signal COM output by the driving circuit 50 is further improved.

[0111] As described above, the driving circuit 50 of this embodiment is a capacitive load driving circuit that outputs a driving signal COM. The driving signal COM drives the piezoelectric element 60 as a capacitive load. The driving circuit 50 includes: an amplifier circuit 550 electrically connected to the wiring Wgnd for transmitting the ground signal GND of the ground potential gnd and the wiring Wvm1 for transmitting the voltage signal VMV1 having a voltage value of voltage vm1, and outputting the first amplified modulated signal AMS1 to the wiring Wam1; a booster circuit 760 electrically connected to the wiring Wam1 and the wiring Wvm1 for transmitting the voltage signal VMV1 having a voltage value of voltage vm1; The wiring Wvm2 of the voltage signal VMV2 is electrically connected to the wiring Wvm2, and the voltage signal VMV3 is output to the wiring Wbst; the level shift circuit 750 is connected to the wiring Wam1 and the wiring Wbst, and outputs the second amplified modulated signal AMS2 to the wiring Wam2; the demodulation circuit 560 smoothes the second amplified modulated signal AMS2 and outputs it as the drive signal COM; and the boost voltage limiting circuit 800 limits the voltage value of the voltage signal VMV3 output from the boost circuit 760 based on the voltage value of the voltage signal VMV2, that is, the voltage vmv2.

[0112] 3.3 Operation of the driving circuit

[0113] Next, the operation of the drive circuit 50 will be described. Figure 7 50 is a diagram for explaining the operation of the driving circuit 50. Figure 7 In FIG, only the drive signal COM in an arbitrary period T among the drive signals COM output by the drive circuit 50 is shown. Figure 7 In order to facilitate the illustration and explanation, the signal waveforms in the ideal case without circuit delay and wiring delay are shown. Figure 7 In FIG, a predetermined threshold value of the basic driving signal dA for switching the logic level of the level switching signal LS output by the level switching signal output circuit 710 is shown as a threshold value dvth, and a voltage value of the driving signal COM corresponding to the threshold value dvth is shown as a voltage vth. Figure 7 In FIG, the values ​​of the basic drive signal dA corresponding to the voltages vt, vb, and vc of the drive signal COM are shown as digital values ​​dvt, dvb, and dvc, respectively. Figure 7 In the embodiment, the case where the voltage vth is lower than the voltage vc and the threshold value dvth is smaller than the digital value dvc is illustrated, but the relationship between the voltage vth and the voltage vc and the relationship between the threshold value dvth and the digital value dvc are not limited to this.

[0114] like Figure 7As shown, during the period from time t0 to time t10, the base drive signal dA with the digital value dvc is input to the D / A converter circuit 510. Therefore, the voltage value of the drive signal COM output by the driver circuit 50 becomes voltage vc. At this time, the digital value dvc is greater than the threshold value dvth. Consequently, the level-switching signal output circuit 710 outputs the level-switching signal LS at an H level. Specifically, during the period from time t0 to time t10, the operation mode of the level shift circuit 750 is the second mode MD2. The level shift circuit 750 outputs the signal obtained by level-shifting the reference potential of the first amplified modulated signal AMS1 to voltage vmv2 as the second amplified modulated signal AMS2.

[0115] During the period from time t10 to time t20, the D / A converter circuit 510 receives the base drive signal dA, which decreases from the digital value dvc to the digital value dvb. Consequently, the voltage of the drive signal COM output by the driver circuit 50 decreases from voltage vc to voltage vb. During the period from time t10 to time t20, when the value of the base drive signal dA exceeds the threshold value dvth, the level switching signal output circuit 710 outputs the H-level level switching signal LS. Specifically, during the period from time t10 to time tc1, the level shift circuit 750 maintains the second mode MD2, and the level shift circuit 750 outputs the second amplified modulated signal AMS2, which is a signal obtained by level-shifting the reference potential of the first amplified modulated signal AMS1 to voltage vmv2. On the other hand, during the period from time t10 to time t20, during the period from time tc1 to time t20 when the value of the basic drive signal dA is less than the threshold value dvth, the level switching signal output circuit 710 outputs the level switching signal LS at an L level. As a result, the operation mode of the level shift circuit 750 changes to the first mode MD1, and the level shift circuit 750 outputs the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2.

[0116] When the operating mode of the level shifter circuit 750 transitions from the second mode MD2 to the first mode MD1, the reference potential of the first amplified modulated signal AMS1 output as the second amplified modulated signal AMS2 suddenly changes from voltage vmv2 to ground potential. If the response speed of the driver circuit 50 cannot keep up with this sudden change in the reference potential, distortion may occur in the signal waveform of the drive signal COM. To reduce this potential distortion in the drive signal COM, the driver circuit 50 of this embodiment outputs a counter-pulse CP at time tc1, after the operating mode of the level shifter circuit 750 transitions from the second mode MD2 to the first mode MD1. This counter-pulse CP inverts the logic level of the level switching signal LS for a short period of time. This counter-pulse CP slows the change in the reference potential of the first amplified modulated signal AMS1 output as the second amplified modulated signal AMS2, thereby reducing the possibility of distortion in the signal waveform of the drive signal COM.

[0117] During the period from time t20 to time t30, the base drive signal dA with the digital value dvb is input to the D / A converter circuit 510. Therefore, the voltage value of the drive signal COM output by the driver circuit 50 becomes the voltage vb. At this time, the digital value dvb is less than the threshold value dvth. Consequently, the level switching signal output circuit 710 outputs the level switching signal LS at the low level. That is, during the period from time t20 to time t30, the operation mode of the level shift circuit 750 remains in the first mode MD1, and the level shift circuit 750 outputs the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2.

[0118] During the period from time t30 to time t40, the D / A converter circuit 510 receives the base drive signal dA, which increases from the digital value dvb to the digital value dvt. Consequently, the voltage of the drive signal COM output by the driver circuit 50 increases from voltage vb to voltage vt. During the period from time t30 to time t40, when the value of the base drive signal dA is less than the threshold value dvth, from time t30 to time tc2, the level switching signal output circuit 710 outputs the low-level level switching signal LS. Specifically, during the period from time t30 to time tc2, the level shift circuit 750 maintains the first mode MD1, and the level shift circuit 750 outputs the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2. Meanwhile, during the period from time t30 to time t40, when the value of the base drive signal dA is greater than the threshold value dvth, the level switching signal output circuit 710 outputs the high-level level switching signal LS. As a result, the operation mode of the level shift circuit 750 shifts to the second mode MD2 , and the level shift circuit 750 outputs a signal obtained by level-shifting the reference potential of the first amplified modulated signal AMS1 to the voltage vmv2 as the second amplified modulated signal AMS2 .

[0119] Here, when the operating mode of the level shift circuit 750 transitions from the first mode MD1 to the second mode MD2, the reference potential of the first amplified modulated signal AMS1 output as the second amplified modulated signal AMS2 suddenly changes from the ground potential to the voltage vmv2. If the response speed of the driver circuit 50 cannot keep up with this sudden change in the reference potential, distortion may occur in the signal waveform of the drive signal COM. To reduce this potential distortion in the drive signal COM, the driver circuit 50 of this embodiment outputs a counter-pulse CP at time tc2, after the operating mode of the level shift circuit 750 transitions from the first mode MD1 to the second mode MD2. This counter-pulse CP inverts the logic level of the level switching signal LS for a short period of time. This counter-pulse CP slows the change in the reference potential of the first amplified modulated signal AMS1 output as the second amplified modulated signal AMS2, thereby reducing the possibility of distortion in the signal waveform of the drive signal COM.

[0120] During the period from time t40 to time t50, the base drive signal dA with the digital value dvt is input to the D / A converter circuit 510. Therefore, the voltage value of the drive signal COM output by the driver circuit 50 becomes voltage vt. At this time, the digital value dvt is greater than the threshold value dvth. Consequently, the level switching signal output circuit 710 outputs the level switching signal LS at an H level. Specifically, during the period from time t40 to time t50, the operation mode of the level shift circuit 750 remains in the second mode MD2. The level shift circuit 750 outputs the signal obtained by level-shifting the reference potential of the first amplified modulated signal AMS1 to voltage vmv2 as the second amplified modulated signal AMS2.

[0121] During the period from time t50 to time t60, the D / A converter circuit 510 receives the base drive signal dA, which decreases from the digital value dvt to the digital value dvc. Consequently, the voltage of the drive signal COM output by the driver circuit 50 decreases from voltage vt to voltage vc. At this point, the value of the base drive signal dA exceeds the threshold value dvth. Consequently, the level-switching signal output circuit 710 outputs the level-switching signal LS at an H level. Specifically, during the period from time t50 to time t60, the level shift circuit 750 maintains the second mode MD2, and the level shift circuit 750 outputs the second amplified modulated signal AMS2, a signal obtained by level-shifting the reference potential of the first amplified modulated signal AMS1 to voltage vmv2.

[0122] During the period from time t60 to time t70, the base drive signal dA with the digital value dvc is input to the D / A converter circuit 510. Therefore, the voltage value of the drive signal COM output by the driver circuit 50 is voltage vc. At this time, the digital value dvc is greater than the threshold value dvth. Consequently, the level switching signal output circuit 710 outputs the level switching signal LS at an H level. Specifically, during the period from time t60 to time t70, the operation mode of the level shift circuit 750 remains in the second mode MD2. The level shift circuit 750 outputs a signal obtained by level-shifting the reference potential of the first amplified modulated signal AMS1 to voltage vmv2 as the second amplified modulated signal AMS2.

[0123] 3.4 Structure and Operation of Boost Voltage Limiting Circuit

[0124] In the drive circuit 50 configured as described above, the amount of charge stored in capacitor C13 of the boost circuit 760 fluctuates depending on the waveform of the output drive signal COM and the number of piezoelectric elements 60 driven by the drive signal COM. As a result, the voltage across capacitor C13 may fluctuate. This fluctuation in the voltage across capacitor C13 may distort the waveform of voltage signal VMV3 output by the boost circuit 760 and the waveform of drive signal COM output by the drive circuit 50, resulting in a decrease in the accuracy of ink ejection from the ejection unit 600. Furthermore, if the fluctuation in the voltage across capacitor C13 exceeds the withstand voltage of the various electronic components that comprise the drive circuit 50, these components may malfunction. The boost voltage limiting circuit 800 of the driving circuit 50 of this embodiment reduces the possibility of distortion in the signal waveform of the driving signal COM output by the driving circuit 50 by limiting the variation of the voltage value between the two ends of such a capacitor C13, that is, the variation of the voltage value of the voltage signal VMV3 output by the boost circuit 760, thereby reducing the possibility of deterioration in the ejection accuracy of the ink ejected from the ejection portion 600.

[0125] When describing the configuration and operation of the boost voltage limiting circuit 800 , first, one of the main factors causing the voltage value between both ends of the capacitor C13 to fluctuate, namely, the current flowing through the drive circuit 50 , will be described. Figures 8 to 11 is a diagram for showing an overview of the current flowing in the drive circuit 50. Specifically, Figure 8 FIG shows the direction of the current flowing through the driving circuit 50 when the level shift circuit 750 is in the first mode MD1 and the voltage value of the driving signal COM increases. Figure 9 FIG shows the direction of the current flowing through the driving circuit 50 when the level shift circuit 750 is in the first mode MD1 and the voltage value of the driving signal COM is reduced. Figure 10 FIG shows the direction of the current flowing through the driving circuit 50 when the level shift circuit 750 is in the second mode MD2 and the voltage value of the driving signal COM increases. Figure 11 3 shows the direction of the current flowing through the driving circuit 50 when the level shift circuit 750 is in the second mode MD2 and the voltage value of the driving signal COM is reduced.

[0126] When the level shift circuit 750 is in the first mode MD1, the transistor M3 becomes non-conductive and the transistor M4 becomes conductive. Thus, the first output point OP1 and the second output point OP2 are electrically connected via the transistor M4. Therefore, the first amplified modulation signal AMS1 output from the first output point OP1 is transmitted through the wiring Wam1, Wam2, Wcom and the transistor M4, and is output from the second output point OP2 as the second amplified modulation signal AMS2. Then, the second amplified modulation signal AMS2 output from the second output point OP2 is smoothed in the demodulation circuit 560, whereby the driving circuit 50 outputs the driving signal COM. In such a first mode MD1, when the voltage value of the driving signal COM output by the driving circuit 50 rises, charge is accumulated in the piezoelectric element 60 by the current flowing due to the transmission of the driving signal COM. Therefore, when the level shift circuit 750 is in the first mode MD1 and the voltage value of the driving signal COM rises, as shown in FIG. Figure 8 As shown, in the driving circuit 50 , current flows from the first output point OP1 toward the second output point OP2 , that is, in the order of the wiring Wam1 , the transistor M4 , the wiring Wam2 , and the wiring Wcom.

[0127] On the other hand, in the first mode MD1, when the voltage value of the driving signal COM output by the driving circuit 50 decreases, the charge accumulated in the piezoelectric element 60 is released. Therefore, when the level shift circuit 750 is in the first mode MD1 and the voltage value of the driving signal COM decreases, as shown in FIG. Figure 9 As shown, in the driving circuit 50 , current flows from the second output point OP2 toward the first output point OP1 , that is, in the order of the wiring Wcom, the wiring Wam2 , the transistor M4 , and the wiring Wam1 .

[0128] In addition, when the level shift circuit 750 is in the second mode MD2, the transistor M3 becomes conductive and the transistor M4 becomes non-conductive. Thus, the first output point OP1 and the second output point OP2 are electrically connected via the transistor M4 and the boost circuit 760. Therefore, the first amplified modulation signal AMS1 output from the first output point OP1 is level-shifted to the voltage vmv2 in the boost circuit 760 via the reference potential, and then transmitted in the transistor M3 to be output from the second output point OP2 as the second amplified modulation signal AMS2. Then, the second amplified modulation signal AMS2 output from the second output point OP2 is smoothed in the demodulation circuit 560, whereby the driving circuit 50 outputs the driving signal COM. In such a second mode MD2, when the voltage value of the driving signal COM output by the driving circuit 50 rises, charge is accumulated in the piezoelectric element 60 by the current flowing due to the transmission of the driving signal COM. Therefore, when the level shift circuit 750 is in the second mode MD2 and the voltage value of the driving signal COM rises, as shown in FIG. Figure 10 As shown, in the driving circuit 50 , current flows from the first output point OP1 toward the second output point OP2 , that is, in the order of the wiring Wam1 , the capacitor C13 , the wiring Wbst, the transistor M3 , the wiring Wam2 , and the wiring Wcom.

[0129] On the other hand, in the second mode MD2, when the voltage value of the driving signal COM output by the driving circuit 50 decreases, the charge accumulated in the piezoelectric element 60 is released. Therefore, when the level shift circuit 750 is in the second mode MD2 and the voltage value of the driving signal COM decreases, as shown in FIG. Figure 11 As shown, in the driving circuit 50 , current flows from the second output point OP2 toward the first output point OP1 , that is, in the order of the wiring Wcom, the wiring Wam2 , the transistor M3 , the wiring Wbst, the capacitor C13 , and the wiring Wam1 .

[0130] As described above, in the drive circuit 50 of this embodiment, the capacitor C13 of the boost circuit 760 is provided in the path of the current flowing with the transmission of the output drive signal COM. As a result, the amount of charge stored in the capacitor C13 fluctuates with the transmission of the drive signal COM output by the drive circuit 50, and as a result, the voltage value generated between the two ends of the capacitor C13 is more likely to fluctuate.

[0131] The structure of the boost voltage limiting circuit 800 for limiting the fluctuation of the voltage value that may occur between both ends of the capacitor C13 will be described. Figure 12 800 is a diagram showing an example of the structure of the boost voltage limiting circuit 800. Figure 12 As shown, the boost voltage limiting circuit 800 includes a voltage drop limiting circuit 810 , a voltage increase limiting circuit 820 , and a voltage increase protection circuit 830 .

[0132] The voltage drop limiting circuit 810 includes a transistor 811, a constant voltage diode 812, and a resistor 813. Transistor 811 is an NPN bipolar transistor, with its collector terminal electrically connected to wiring Wvm2 and its emitter terminal electrically connected to wiring Wbst. Furthermore, the base terminal of transistor 811 is electrically connected to the anode terminal of constant voltage diode 812 and one end of resistor 813. Furthermore, the cathode terminal of constant voltage diode 812 is electrically connected to wiring Wvm2, and the other end of resistor 813 is electrically connected to wiring Wbst. The voltage drop limiting circuit 810 configured as described above controls the conduction state of the collector and emitter terminals of transistor 811 based on the potential difference between wiring Wvm2 and wiring Wbst, thereby limiting the reduction in the voltage across capacitor C13.

[0133] The voltage rise limiting circuit 820 includes a transistor 821, a constant voltage diode 822, and a resistor 823. Transistor 821 is an NPN bipolar transistor with its collector terminal electrically connected to wiring Wbst and its emitter terminal electrically connected to wiring Wvm2. Furthermore, the base terminal of transistor 821 is electrically connected to the anode terminal of constant voltage diode 822 and one end of resistor 823. Furthermore, the cathode terminal of constant voltage diode 822 is electrically connected to wiring Wbst, and the other end of resistor 823 is electrically connected to wiring Wvm2. The voltage rise limiting circuit 820 configured as described above controls the conduction state of the collector and emitter terminals of transistor 821 based on the potential difference between wiring Wvm2 and wiring Wbst, thereby limiting the increase in the voltage across capacitor C13.

[0134] Voltage-rise protection circuit 830 includes a diode 831. The anode terminal of diode 831 is electrically connected to wiring Wbst, and a voltage signal VHV is supplied to the cathode terminal. Furthermore, when the voltage value of wiring Wbst exceeds the voltage value of voltage signal VHV, i.e., voltage vhv, the voltage-rise protection circuit 830 discharges the charge of wiring Wbst, i.e., the charge accumulated in capacitor C13 electrically connected to wiring Wbst, via diode 831. This reduces the likelihood that the voltage value of wiring Wbst, i.e., the voltage value at the other end of capacitor C13, will exceed voltage vhv.

[0135] Voltage signal VHV is a voltage value signal used by the selection control unit 210 and other devices to switch whether or not to supply the drive signal COM to the piezoelectric element 60. It is also the highest voltage signal among the voltage values ​​used in various circuits provided in the transmission path that transmits the drive signal COM. The voltage rise protection circuit 830 reduces the likelihood that the voltage value of the wiring Wbst will exceed voltage vhv. This reduces the likelihood that excessive voltage will be applied to circuit elements provided in the transmission path during the transmission of the drive signal COM based on voltage signal VMV3. Consequently, the reliability of the liquid ejection device 1 including the drive circuit 50 is improved.

[0136] A specific example of the operation of limiting the fluctuation of the voltage value that may occur between both ends of the capacitor C13 in the boost voltage limiting circuit 800 configured as described above will be described.

[0137] When charge based on voltage vmv2, the voltage value of voltage signal VMV2, is normally accumulated between the two ends of capacitor C13 included in boost circuit 760, the voltage value at the other end of capacitor C13, i.e., the voltage value of wiring Wbst, becomes the value obtained by adding voltage vmv2 to the voltage value of first amplified modulation signal AMS1. As described above, the voltage value of first amplified modulation signal AMS1 becomes voltage vmv1, based on voltage signal VMV1, when transistor M1 is on, and becomes 0 V, which is ground potential gnd, when transistor M2 is on. Therefore, when charge based on voltage vmv2 is normally accumulated between the two ends of capacitor C13, the voltage value at the other end of capacitor C13 varies between voltage vmv2 and a value obtained by adding voltage vmv1 to voltage vmv2, depending on the first amplified modulation signal AMS1.

[0138] When the charge stored in capacitor C13 is released by the current generated by the transmission of drive signal COM, the voltage across capacitor C13 decreases. Furthermore, as the voltage across capacitor C13 decreases, the voltage of voltage signal VMV3 also decreases. At this point, the voltage of voltage signal VMV2 on transmission wiring Wvm2 remains constant at voltage vmv2. Consequently, as the voltage across capacitor C13 decreases, the potential difference ΔVlow (the value obtained by subtracting the voltage of voltage signal VMV3 from the voltage of voltage signal VMV2)—that is, the potential difference ΔVlow between the voltage of wiring Wvm2 and the voltage of wiring Wbst—increases. When this increased potential difference ΔVlow exceeds the threshold voltage vtz1 defined by the Zener voltage vzd1 of constant-voltage diode 812 and the resistance value of resistor 813, a current corresponding to the difference between potential difference ΔVlow and threshold voltage vtz1 is supplied to the base terminal of transistor 811 via constant-voltage diode 812.

[0139] Transistor 811 controls the conduction state between its collector and emitter terminals based on the amount of current supplied to its base terminal. Specifically, transistor 811 supplies an amount of current corresponding to the amount of current supplied to its base terminal from wiring Wvm2 to wiring Wbst. The current supplied via transistor 811 accumulates charge in capacitor C13, which is electrically connected to wiring Wbst. This limits the drop in the voltage across capacitor C13. Specifically, voltage drop limiting circuit 810 limits the drop in the voltage across capacitor C13 based on the potential difference ΔVlow between the voltage values ​​of wiring Wvm2 and wiring Wbst, which is the value obtained by subtracting the voltage value of voltage signal VMV3 from the voltage value of voltage signal VMV2.

[0140] As described above, the lower limit voltage value of voltage signal VMV3 is defined by threshold voltage vtz1, which is defined by Zener voltage vzd1 of constant voltage diode 812 and the resistance value of resistor 813. Specifically, the lower limit voltage value of voltage signal VMV3 is defined by subtracting threshold voltage vtz1 from voltage vmv2, the voltage value of voltage signal VMV2. The threshold voltage vtz1 used to define the lower limit voltage value of voltage signal VMV3 is set so that, when the voltage value of first amplified modulated signal AMS1 is at ground potential gnd, the voltage value of voltage signal VMV3 remains within an allowable range. For example, the lower limit voltage value of voltage signal VMV3 is set to a value that is at least 80% of voltage vmv2, the voltage value of voltage signal VMV2.

[0141] On the other hand, when charge accumulates in capacitor C13 due to the current generated by the transmission of drive signal COM, the voltage across capacitor C13 increases. Furthermore, as the voltage across capacitor C13 increases, the voltage of voltage signal VMV3 also increases. At this time, the voltage of voltage signal VMV2 transmitted through wiring Wvm2 remains constant at voltage vmv2. Consequently, as the voltage across capacitor C13 increases, the potential difference ΔVhi between wiring Wbst and wiring Wvm2, the value obtained by subtracting the voltage of voltage signal VMV2 from the voltage of voltage signal VMV3, increases. When this increased potential difference ΔVhi exceeds threshold voltage vtz2, which is determined by the Zener voltage vzd2 of constant voltage diode 822 and the resistance value of resistor 823, a current corresponding to the difference between potential difference ΔVhi and threshold voltage vtz2 is supplied to the base terminal of transistor 821 via constant voltage diode 822.

[0142] Transistor 821 controls the conduction state between its collector and emitter terminals based on the amount of current supplied to its base terminal. Specifically, transistor 821 supplies an amount of current corresponding to the amount of current supplied to its base terminal from wiring Wbst to wiring Wvm2. The current flowing through transistor 821 discharges the charge stored in capacitor C13, which is electrically connected to wiring Wbst. As a result, the rise in the voltage across capacitor C13 is limited. Specifically, voltage-rise limiting circuit 820 limits the rise in the voltage across capacitor C13 based on the potential difference ΔVhi between the voltage values ​​of wiring Wbst and wiring Wvm2, which is the value obtained by subtracting the voltage value of voltage signal VMV2 from the voltage value of voltage signal VMV3.

[0143] As described above, the upper limit voltage value of voltage signal VMV3 is defined by the threshold voltage vtz2, which is defined by the Zener voltage vzd2 of constant voltage diode 822 and the resistance value of resistor 823. Specifically, the upper limit voltage value of voltage signal VMV3 is defined by the sum of voltage vmv2, the voltage value of voltage signal VMV2, and the threshold voltage vtz2. The threshold voltage vtz2, which defines the upper limit voltage value of voltage signal VMV3, is set so that, when the voltage value of first amplified modulated signal AMS1 is the voltage value vmv1 of voltage signal VMV1, the voltage value of voltage signal VMV3 fluctuates within an allowable range. For example, the upper limit voltage value of voltage signal VMV3 is set to a value that is no greater than 120% of the sum of voltage vmv2, the voltage value of voltage signal VMV2, and voltage vmv1, the voltage value of voltage signal VMV1.

[0144] Furthermore, in this case, the threshold voltage vtz2, defined by the Zener voltage vzd2 of the constant voltage diode 822 and the resistance value of the resistor 823, is preferably set so that the sum of the voltage vmv2 and the threshold voltage vtz2 is less than the voltage vhv of the voltage signal VHV. Consequently, the voltage rise limiting circuit 820 limits the voltage value of the voltage signal VMV3 to a value lower than the voltage vhv of the voltage signal VHV. As a result, the likelihood of excessive voltage being applied to circuit elements provided in the transmission path during the transmission of the drive signal COM based on the voltage signal VMV3 is further reduced, thereby further improving the reliability of the liquid ejection device 1 including the drive circuit 50.

[0145] As described above, the boost voltage limiting circuit 800 includes the voltage drop limiting circuit 810 and the voltage increase limiting circuit 820 .

[0146] The voltage drop limiting circuit 810 includes a constant voltage diode 812, a resistor 813, and a transistor 811. The cathode terminal of the constant voltage diode 812 is electrically connected to the wiring Wvm2, and the anode terminal is electrically connected to one end of the resistor 813. Furthermore, the other end of the resistor 813 is electrically connected to the wiring Wbst. Furthermore, the base terminal of the transistor 811 is electrically connected to the anode terminal of the constant voltage diode 812 and one end of the resistor 813, the collector terminal is electrically connected to the wiring Wvm2, and the emitter terminal is electrically connected to the wiring Wbst. Furthermore, when the potential of the wiring Wvm2 is greater than the potential of the wiring Wbst, and the potential difference between the wiring Wvm2 and the wiring Wbst is greater than the threshold voltage vtz1, the voltage drop limiting circuit 810 causes conduction between the wiring Wvm2 and the wiring Wbst.

[0147] Furthermore, the voltage rise limiting circuit 820 includes a constant voltage diode 822, a resistor 823, and a transistor 821. The cathode terminal of the constant voltage diode 822 is electrically connected to the wiring Wbst, and the anode terminal is electrically connected to one end of the resistor 823. Furthermore, the other end of the resistor 823 is electrically connected to the wiring Wvm2. Furthermore, the base terminal of the transistor 821 is electrically connected to the anode terminal of the constant voltage diode 822 and one end of the resistor 823, the collector terminal is electrically connected to the wiring Wbst, and the emitter terminal is electrically connected to the wiring Wvm2. Furthermore, when the potential of the wiring Wvm2 is lower than the potential of the wiring Wbst and the potential difference between the wiring Wvm2 and the wiring Wbst is greater than the threshold voltage vtz2, the voltage rise limiting circuit 820 causes conduction between the wiring Wvm2 and the wiring Wbst.

[0148] Specifically, the boosted voltage limiting circuit 800 included in the drive circuit 50 of the liquid ejection device 1 of this embodiment is electrically connected to the wiring Wvm2 and the wiring Wbst. Furthermore, the boosted voltage limiting circuit 800 switches the conductive state between the wiring Wvm2 and the wiring Wbst based on the potential differences ΔVlow and ΔVhi between the voltage values ​​of the wiring Wvm2 and the voltage values ​​of the wiring Wbst.

[0149] The piezoelectric element 60 is an example of a capacitive load, and the drive circuit 50 for outputting the drive signal COM for driving the piezoelectric element 60 corresponds to a capacitive load drive circuit. Furthermore, the D / A converter circuit 510 is an example of a D / A converter circuit, the pulse modulation circuit 520 is an example of a modulation circuit, the amplifier circuit 550 is an example of a first digital amplifier circuit, the demodulation circuit 560 is an example of a smoothing circuit, the level shifter circuit 750 is an example of a second digital amplifier circuit, the booster circuit 760 is an example of a bootstrap circuit, and the boost voltage limiting circuit 800 is an example of a voltage limiting circuit. Furthermore, the capacitor C13 is an example of a capacitor element, the diode D13 is an example of a diode element, the constant voltage diode 812 is an example of a first Zener diode, the constant voltage diode 822 is an example of a second Zener diode, the resistor 813 is an example of a first resistor element, the resistor 823 is an example of a second resistor element, the transistor 811 is an example of a first transistor, and the transistor 821 is an example of a second transistor. Furthermore, the ground signal GND is an example of a first voltage signal, the ground potential gnd is an example of a first potential, the voltage signal VMV1 is an example of a second voltage signal, the voltage vmv1 is an example of a second potential, the voltage signal VMV2 is an example of a third voltage signal, and the voltage vmv3 is an example of a third potential. Furthermore, the first amplified modulation signal AMS1 is an example of a first amplified signal, the second amplified modulation signal AMS2 is an example of a second amplified signal, the voltage signal VMV3 is an example of a startup voltage signal, and the base drive signal aA is an example of an analog base drive signal. Furthermore, the wiring Wgnd is an example of a first transmission node, the wiring Wvm1 is an example of a second transmission node, the wiring Wvm2 is an example of a third transmission node, the wiring Wam1 is an example of a first output node, the wiring Wbst is an example of a second output node, and the wiring Wam2 is an example of a third output node. Furthermore, the threshold voltage vtz1 is an example of a first threshold value, and the threshold voltage vtz2 is an example of a second threshold value.

[0150] 4. Effects

[0151] As described above, in the liquid ejection device 1 of this embodiment, in the drive circuit 50, the amplifier circuit 550 generates a first amplified modulated signal AMS1 by amplifying the modulated signal MS through the switching operation of transistors M1 and M2. The level shift circuit 750, based on the potential of the level switching signal LS, outputs the first amplified modulated signal AMS1 or a signal obtained by shifting the potential of the first amplified modulated signal AMS1 as a second amplified modulated signal AMS2 via transistors M3 and M4. The demodulation circuit 560 demodulates the second amplified modulated signal AMS2 and outputs the drive signal COM. This reduces the voltage values ​​of the voltage signals VMV1 and VMV2 relative to the voltage value of the drive signal COM output by the drive circuit 50. Consequently, the on-resistance of the transistors M1, M2, M3, and M4 can be reduced, thereby reducing the switching loss generated in each of the transistors M1, M2, M3, and M4. Consequently, the power consumption of the drive circuit 50 can be reduced.

[0152] Furthermore, in the liquid ejection device 1 of this embodiment, the boosted voltage limiting circuit 800 included in the drive circuit 50 is electrically connected to the wiring Wvm2 and the wiring Wbst. It switches the conductive state of the wiring Wvm2 and the wiring Wbst based on the potential differences ΔVlow and ΔVhi between the voltage values ​​of the wiring Wvm2 and the wiring Wbst. Consequently, even if the voltage across capacitor C13 fluctuates due to unintended charge accumulation or discharge in the capacitor C13 included in the boosting circuit 760 electrically connected to the wiring Wbst, the voltage across capacitor C13 can be limited based on the voltage vmv2, the voltage value of the voltage signal VMV2 transmitted through the wiring Wvm2. As a result, the signal accuracy of the second amplified modulation signal AMS2 output from the level shifter circuit 750 electrically connected to the wiring Wbst is improved. This improved signal accuracy also improves the signal accuracy of the drive signal COM, which is the result of smoothing the second amplified modulation signal AMS2. That is, the possibility of distortion occurring in the signal waveform of the drive signal COM output by the drive circuit 50 is reduced.

[0153] Furthermore, in the driving circuit 50 included in the liquid ejection device 1 of this embodiment, the boost voltage limiting circuit 800 includes: a voltage drop limiting circuit 810 that provides electrical conduction between the wiring Wvm2 and the wiring Wbst when the potential of the wiring Wvm2 is greater than the potential of the wiring Wbst and the potential difference between the wiring Wvm2 and the wiring Wbst is greater than a threshold voltage vtz1; and a voltage rise limiting circuit 820 that provides electrical conduction between the wiring Wvm2 and the wiring Wbst when the potential of the wiring Wvm2 is less than the potential of the wiring Wbst and the potential difference between the wiring Wvm2 and the wiring Wbst is greater than a threshold voltage vtz2. Thus, the voltage across the capacitor C13 is limited to a predetermined voltage range by the voltage drop limiting circuit 810 and the voltage rise limiting circuit 820. As a result, the signal accuracy of the second amplified modulated signal AMS2 output from the level shift circuit 750 electrically connected to the wiring Wbst is further improved. With this further improvement in the signal accuracy of the second amplified modulated signal AMS2, the signal accuracy of the drive signal COM obtained by smoothing the second amplified modulated signal AMS2 is also further improved. In other words, the possibility of distortion in the signal waveform of the drive signal COM output by the drive circuit 50 is further reduced.

[0154] 5. Modifications

[0155] In the liquid ejection device 1 described above, the boost voltage limiting circuit 800 possessed by the driving circuit 50 is described as having a voltage drop limiting circuit 810, a voltage rise limiting circuit 820 and a voltage rise protection circuit 830, but the boost voltage limiting circuit 800 possessed by the driving circuit 50 only needs to have at least one of the voltage drop limiting circuit 810 and the voltage rise limiting circuit 820. In this case, the possibility of distortion in the signal waveform of the driving signal COM output by the driving circuit 50 can also be reduced.

[0156] Furthermore, in the liquid ejection device 1 described above, Figure 13 As shown, the boost voltage limiting circuit 800 included in the driving circuit 50 may include a voltage increase protection circuit 840 instead of the voltage increase protection circuit 830 . Figure 13 1 is a diagram showing an example of the configuration of a boost voltage limiting circuit 800 according to a modified example.

[0157] The voltage rise protection circuit 840 includes a constant voltage diode 841 and a resistor 842. The cathode terminal of the constant voltage diode 841 is electrically connected to the wiring Wbst, and the anode terminal of the constant voltage diode 841 is electrically connected to one end of the resistor 842. The other end of the resistor 842 is electrically connected to the wiring Wam1.

[0158] In the voltage-rise protection circuit 840 configured as described above, if the potential difference ΔVbst between the voltage values ​​of wiring Wbst and wiring Wam1, that is, the voltage value across capacitor C13, exceeds a threshold voltage vtz3 defined by the Zener voltage vzd3 of constant-voltage diode 841 and the resistance value of resistor 842, a current corresponding to the difference between potential difference ΔVbst and threshold voltage vtz3 flows through wiring Wam1 via constant-voltage diode 841 and resistor 842. This causes the charge stored in capacitor C13, which is electrically connected to wiring Wbst, to be released to wiring Wam1. As a result, the voltage value of wiring Wbst, that is, the voltage value of voltage signal VMV3, is limited based on the voltage value of first amplified modulated signal AMS1 transmitted through wiring Wam1 and threshold voltage vtz3.

[0159] Furthermore, in this case, the threshold voltage vtz3, defined by the Zener voltage vzd3 of the constant voltage diode 841 and the resistance value of the resistor 842, is preferably set so that the sum of the voltage vmv1 and the threshold voltage vtz2 is less than the voltage vhv of the voltage signal VHV. Consequently, the voltage rise limiting circuit 820 limits the voltage value of the voltage signal VMV3 to a value lower than the voltage vhv of the voltage signal VHV. As a result, the likelihood of excessive voltage being applied to circuit elements provided in the transmission path during the transmission of the drive signal COM based on the voltage signal VMV3 is further reduced, thereby further improving the reliability of the liquid ejection device 1 including the drive circuit 50.

[0160] Even if the driving circuit 50 has the boost voltage limiting circuit 800 instead of Figure 12 The voltage rise protection circuit 830 shown or otherwise has Figure 13 In the case of the voltage-rise protection circuit 840 shown in the figure, the same operation and effect as those of the above-described embodiment are achieved.

[0161] Although the embodiments have been described above, the present invention is not limited to these embodiments and can be implemented in various forms within the scope of the present invention. For example, the above-described embodiments and modifications can be appropriately combined.

[0162] The present invention includes structures that are substantially the same as the structures described in the embodiments, for example, structures having the same functions, methods, and results, or structures having the same purposes and effects. Furthermore, the present invention includes structures that replace non-essential parts of the structures described in the embodiments. Furthermore, the present invention includes structures that can achieve the same effects or purposes as the structures described in the embodiments. Furthermore, the present invention includes structures that incorporate known technologies into the structures described in the embodiments.

[0163] The following contents are derived from the above-mentioned embodiment.

[0164] One embodiment of a capacitive load driving circuit is a capacitive load driving circuit that outputs a driving signal, wherein the driving signal drives a capacitive load, and the capacitive load driving circuit includes:

[0165] a first digital amplifier circuit electrically connected to a first transmission node and a second transmission node, outputting a first amplified signal to a first output node, wherein the first transmission node transmits a first voltage signal of a first potential, and the second transmission node transmits a second voltage signal of a second potential;

[0166] A bootstrap circuit is electrically connected to the third transmission node and the first output node, outputting a startup voltage signal to the second output node, and the third transmission node transmits a third voltage signal of a third potential;

[0167] a second digital amplifier circuit connected to the first output node and the second output node, and outputting a second amplified signal to a third output node;

[0168] a smoothing circuit, configured to smooth the second amplified signal and output the smoothed signal as the driving signal; and

[0169] a voltage limiting circuit, electrically connected to the third transmission node and the second output node, for switching the conduction state between the third transmission node and the second output node;

[0170] The bootstrap circuit includes: a capacitor element having one end electrically connected to the first output node and the other end electrically connected to the second output node; and a diode element having an anode terminal electrically connected to the third transmission node and a cathode terminal electrically connected to the second output node.

[0171] The voltage limiting circuit switches the conduction state between the third transmission node and the second output node according to the potential difference between the third transmission node and the second output node.

[0172] In this capacitive load driving circuit, a voltage limiting circuit switches the conductive state of the third transmission node and the second output node based on the potential difference between the third transmission node and the second output node. Consequently, even when the voltage value of the startup voltage signal output by the bootstrap circuit to the second output node increases or decreases, the voltage value of the startup voltage signal is limited by the third voltage signal at the third potential transmitted through the third transmission node. Consequently, the signal accuracy of the second amplified signal output to the third output node by the second digital amplifier circuit connected to the first and second output nodes is improved. Consequently, the likelihood of distortion in the signal waveform of the driving signal output by the smoothing circuit after smoothing the second amplified signal is reduced.

[0173] In one embodiment of the capacitive load driving circuit, it may be that:

[0174] When the potential of the third transmission node is greater than the potential of the second output node and the potential difference between the third transmission node and the second output node is greater than a first threshold, the voltage limiting circuit enables conduction between the third transmission node and the second output node.

[0175] In this capacitive load driving circuit, even if the voltage value of the startup voltage signal output by the bootstrap circuit to the second output node decreases, the voltage limiting circuit limits the voltage value of the startup voltage signal to the third voltage signal having a third potential transmitted through the third transmission node. Consequently, the signal accuracy of the second amplified signal output to the third output node by the second digital amplifier circuit connected to the first and second output nodes is improved, and the likelihood of distortion in the signal waveform of the driving signal output by the smoothing circuit after smoothing the second amplified signal is reduced.

[0176] In one embodiment of the capacitive load driving circuit, it may be that:

[0177] The voltage limiting circuit includes a first Zener diode, a first resistor element, and a first transistor.

[0178] In the first Zener diode, a cathode terminal is electrically connected to the third transmission node, and an anode terminal is electrically connected to one end of the first resistance element.

[0179] In the first resistance element, the other end is electrically connected to the second output node,

[0180] In the first transistor, a base terminal is electrically connected to the anode terminal of the first Zener diode and one end of the first resistor, a collector terminal is electrically connected to the third transfer node, and an emitter terminal is electrically connected to the second output node.

[0181] In one embodiment of the capacitive load driving circuit, it may be that:

[0182] When the potential of the third transmission node is lower than the potential of the second output node and the potential difference between the third transmission node and the second output node is larger than a second threshold, the voltage limiting circuit enables conduction between the third transmission node and the second output node.

[0183] In this capacitive load driving circuit, even if the voltage value of the startup voltage signal output by the bootstrap circuit to the second output node increases, the voltage limiting circuit limits the voltage value of the startup voltage signal to the third voltage signal having a third potential transmitted through the third transmission node. Consequently, the signal accuracy of the second amplified signal output to the third output node by the second digital amplifier circuit connected to the first and second output nodes is improved, and the likelihood of distortion in the signal waveform of the driving signal output by the smoothing circuit after smoothing the second amplified signal is reduced.

[0184] In one embodiment of the capacitive load driving circuit, it may be that:

[0185] The voltage limiting circuit includes a second Zener diode, a second resistance element, and a second transistor,

[0186] In the second Zener diode, a cathode terminal is electrically connected to the second output node, and an anode terminal is electrically connected to one end of the second resistor element.

[0187] In the second resistance element, the other end is electrically connected to the third transmission node,

[0188] In the second transistor, a base terminal is electrically connected to the anode terminal of the second Zener diode and one end of the second resistor, a collector terminal is electrically connected to the second output node, and an emitter terminal is electrically connected to the third transfer node.

[0189] In one embodiment of the capacitive load driving circuit, the capacitive load driving circuit may include:

[0190] A DA conversion circuit converts a basic driving signal, which is a basis of the driving signal, into an analog basic driving signal;

[0191] a modulation circuit, outputting a modulation signal obtained by modulating the analog basic driving signal; and

[0192] A level switching signal output circuit outputs a level switching signal based on the basic driving signal,

[0193] The first digital amplifier circuit outputs the first amplified signal obtained by amplifying the modulated signal based on the first potential and the second potential.

[0194] The second digital amplifier circuit selects, based on the level switching signal, a signal obtained by shifting the reference potential of the first amplified signal based on the third potential or a signal not shifting the reference potential of the first amplified signal, and outputs the signal as the second amplified signal.

[0195] In this capacitive load driving circuit, a first digital amplifier circuit outputs a first amplified signal obtained by amplifying a modulated signal based on a first potential and a second potential. A second digital amplifier circuit, based on a level switching signal, selects a signal in which the reference potential of the first amplified signal is shifted based on a third potential, or a signal in which the reference potential of the first amplified signal is not shifted, to output as a second amplified signal. This reduces the withstand voltage of transistors included in the first and second digital amplifier circuits. This also reduces the on-resistance of the transistors included in the first and second digital amplifier circuits, reducing losses in the transistors. Consequently, power consumption in the capacitive load driving circuit is reduced.

[0196] One embodiment of a liquid ejection device comprises:

[0197] a discharge portion that discharges liquid by being driven by a capacitive load; and

[0198] A capacitive load driving circuit outputs a driving signal, wherein the driving signal drives the capacitive load.

[0199] The capacitive load driving circuit has:

[0200] a first digital amplifier circuit electrically connected to a first transmission node and a second transmission node, outputting a first amplified signal to a first output node, wherein the first transmission node transmits a first voltage signal of a first potential, and the second transmission node transmits a second voltage signal of a second potential;

[0201] A bootstrap circuit is electrically connected to the third transmission node and the first output node, outputting a startup voltage signal to the second output node, and the third transmission node transmits a third voltage signal of a third potential;

[0202] a second digital amplifier circuit connected to the first output node and the second output node, and outputting a second amplified signal to a third output node;

[0203] a smoothing circuit, configured to smooth the second amplified signal and output the smoothed signal as the driving signal; and

[0204] a voltage limiting circuit, electrically connected to the third transmission node and the second output node, for switching the conduction state between the third transmission node and the second output node;

[0205] The bootstrap circuit includes: a capacitor element having one end electrically connected to the first output node and the other end electrically connected to the second output node; and a diode element having an anode terminal electrically connected to the third transmission node and a cathode terminal electrically connected to the second output node.

[0206] The voltage limiting circuit switches the conduction state between the third transmission node and the second output node according to the potential difference between the third transmission node and the second output node.

[0207] In this liquid ejection device, a voltage limiting circuit included in the capacitive load driving circuit switches the conductive state of the third transmission node and the second output node based on the potential difference between the third transmission node and the second output node. Consequently, even when the voltage value of the startup voltage signal output by the bootstrap circuit to the second output node increases or decreases, the voltage value of the startup voltage signal is limited by the third voltage signal at the third potential transmitted through the third transmission node. Consequently, the signal accuracy of the second amplified signal output to the third output node by the second digital amplifier circuit connected to the first and second output nodes is improved. Consequently, the likelihood of distortion in the signal waveform of the driving signal output by the smoothing circuit after smoothing the second amplified signal is reduced.

[0208] In one embodiment of the liquid ejection device,

[0209] When the potential of the third transmission node is greater than the potential of the second output node and the potential difference between the third transmission node and the second output node is greater than a first threshold, the voltage limiting circuit enables conduction between the third transmission node and the second output node.

[0210] In this liquid ejection device, even if the voltage value of the startup voltage signal output to the second output node by the bootstrap circuit of the capacitive load driving circuit decreases, the voltage limiting circuit limits the voltage value of the startup voltage signal to the third voltage signal having a third potential transmitted through the third transmission node. Consequently, the signal accuracy of the second amplified signal output to the third output node by the second digital amplifier circuit connected to the first and second output nodes is improved, and the likelihood of distortion in the signal waveform of the driving signal output by the smoothing circuit after smoothing the second amplified signal is reduced.

[0211] In one embodiment of the liquid ejection device,

[0212] The voltage limiting circuit includes a first Zener diode, a first resistor element, and a first transistor.

[0213] In the first Zener diode, a cathode terminal is electrically connected to the third transmission node, and an anode terminal is electrically connected to one end of the first resistance element.

[0214] In the first resistance element, the other end is electrically connected to the second output node,

[0215] In the first transistor, a base terminal is electrically connected to the anode terminal of the first Zener diode and one end of the first resistor, a collector terminal is electrically connected to the third transfer node, and an emitter terminal is electrically connected to the second output node.

[0216] In one embodiment of the liquid ejection device,

[0217] When the potential of the third transmission node is lower than the potential of the second output node and the potential difference between the third transmission node and the second output node is larger than a second threshold, the voltage limiting circuit enables conduction between the third transmission node and the second output node.

[0218] In this liquid ejection device, even if the voltage value of the startup voltage signal output to the second output node by the bootstrap circuit of the capacitive load driving circuit increases, the voltage value of the startup voltage signal is limited by the third voltage signal having a third potential transmitted through the third transmission node by the voltage limiting circuit. Consequently, the signal accuracy of the second amplified signal output to the third output node by the second digital amplifier circuit connected to the first and second output nodes is improved, and the likelihood of distortion in the signal waveform of the driving signal output by the smoothing circuit after smoothing the second amplified signal is reduced.

[0219] In one embodiment of the liquid ejection device,

[0220] The voltage limiting circuit includes a second Zener diode, a second resistor element, and a second transistor.

[0221] In the second Zener diode, a cathode terminal is electrically connected to the second output node, and an anode terminal is electrically connected to one end of the second resistor element.

[0222] In the second resistance element, the other end is electrically connected to the third transmission node,

[0223] In the second transistor, a base terminal is electrically connected to the anode terminal of the second Zener diode and one end of the second resistor, a collector terminal is electrically connected to the second output node, and an emitter terminal is electrically connected to the third transfer node.

[0224] In one embodiment of the liquid ejection device, the device may include:

[0225] A DA conversion circuit converts a basic driving signal, which is a basis of the driving signal, into an analog basic driving signal;

[0226] a modulation circuit, outputting a modulation signal obtained by modulating the analog basic driving signal; and

[0227] a level switching signal output circuit, which outputs a level switching signal based on the basic driving signal,

[0228] The first digital amplifier circuit outputs the first amplified signal obtained by amplifying the modulated signal based on the first potential and the second potential.

[0229] The second digital amplifier circuit selects, based on the level switching signal, a signal obtained by shifting the reference potential of the first amplified signal based on the third potential or a signal not shifting the reference potential of the first amplified signal, and outputs the signal as the second amplified signal.

[0230] In this liquid ejection device, a first digital amplifier circuit included in a capacitive load driving circuit outputs a first amplified signal obtained by amplifying a modulated signal based on a first potential and a second potential. A second digital amplifier circuit, based on a level switching signal, selects a signal with or without a reference potential shifted based on a third potential to output as a second amplified signal. This reduces the withstand voltage of transistors included in the first and second digital amplifier circuits. This also reduces the on-resistance of the transistors included in the first and second digital amplifier circuits, reducing losses in the transistors. Consequently, power consumption in the capacitive load driving circuit is reduced, and power consumption in the liquid ejection device is reduced.

Claims

1. A capacitive load driving circuit, characterized in that: The capacitive load driving circuit outputs a driving signal, wherein the driving signal drives the capacitive load, and the capacitive load driving circuit comprises: a first digital amplifier circuit electrically connected to a first transmission node and a second transmission node, outputting a first amplified signal to a first output node, wherein the first transmission node transmits a first voltage signal of a first potential, and the second transmission node transmits a second voltage signal of a second potential; A bootstrap circuit is electrically connected to the third transmission node and the first output node, outputting a startup voltage signal to the second output node, and the third transmission node transmits a third voltage signal of a third potential; a second digital amplifier circuit connected to the first output node and the second output node, and outputting a second amplified signal to a third output node; a smoothing circuit, configured to smooth the second amplified signal and output the smoothed signal as the driving signal; as well as a voltage limiting circuit, electrically connected to the third transmission node and the second output node, for switching the conduction state between the third transmission node and the second output node; The bootstrap circuit includes: a capacitor element having one end electrically connected to the first output node and the other end electrically connected to the second output node; and a diode element having an anode terminal electrically connected to the third transmission node and a cathode terminal electrically connected to the second output node, The voltage limiting circuit switches the conduction state between the third transmission node and the second output node according to the potential difference between the third transmission node and the second output node.

2. The capacitive load driving circuit according to claim 1, wherein: When the potential of the third transmission node is greater than the potential of the second output node and the potential difference between the third transmission node and the second output node is greater than a first threshold, the voltage limiting circuit enables conduction between the third transmission node and the second output node.

3. The capacitive load driving circuit according to claim 2, wherein: The voltage limiting circuit includes a first Zener diode, a first resistance element, and a first transistor, In the first Zener diode, a cathode terminal is electrically connected to the third transmission node, and an anode terminal is electrically connected to one end of the first resistance element. In the first resistance element, the other end is electrically connected to the second output node, In the first transistor, a base terminal is electrically connected to the anode terminal of the first Zener diode and one end of the first resistor, a collector terminal is electrically connected to the third transfer node, and an emitter terminal is electrically connected to the second output node.

4. The capacitive load driving circuit according to any one of claims 1 to 3, wherein: When the potential of the third transmission node is lower than the potential of the second output node and the potential difference between the third transmission node and the second output node is larger than a second threshold, the voltage limiting circuit enables conduction between the third transmission node and the second output node.

5. The capacitive load driving circuit according to claim 4, wherein: The voltage limiting circuit includes a second Zener diode, a second resistance element, and a second transistor, In the second Zener diode, a cathode terminal is electrically connected to the second output node, and an anode terminal is electrically connected to one end of the second resistor element. In the second resistance element, the other end is electrically connected to the third transmission node, In the second transistor, a base terminal is electrically connected to the anode terminal of the second Zener diode and one end of the second resistor, a collector terminal is electrically connected to the second output node, and an emitter terminal is electrically connected to the third transfer node.

6. The capacitive load driving circuit according to claim 1, wherein: have: A DA conversion circuit converts a basic driving signal, which is a basis of the driving signal, into an analog basic driving signal; a modulation circuit, outputting a modulation signal obtained by modulating the analog basic driving signal; as well as a level switching signal output circuit, which outputs a level switching signal based on the basic driving signal, The first digital amplifier circuit outputs the first amplified signal obtained by amplifying the modulated signal based on the first potential and the second potential. The second digital amplifier circuit selects, based on the level switching signal, a signal obtained by shifting the reference potential of the first amplified signal based on the third potential or a signal not shifting the reference potential of the first amplified signal, and outputs the signal as the second amplified signal.

7. A liquid ejection device, characterized in that: have: a discharge portion that discharges liquid by being driven by a capacitive load; and A capacitive load driving circuit outputs a driving signal, wherein the driving signal drives the capacitive load. The capacitive load driving circuit has: a first digital amplifier circuit electrically connected to a first transmission node and a second transmission node, outputting a first amplified signal to a first output node, wherein the first transmission node transmits a first voltage signal of a first potential, and the second transmission node transmits a second voltage signal of a second potential; A bootstrap circuit is electrically connected to the third transmission node and the first output node, outputting a startup voltage signal to the second output node, and the third transmission node transmits a third voltage signal of a third potential; a second digital amplifier circuit connected to the first output node and the second output node, and outputting a second amplified signal to a third output node; a smoothing circuit, configured to smooth the second amplified signal and output the smoothed signal as the driving signal; as well as a voltage limiting circuit, electrically connected to the third transmission node and the second output node, for switching the conduction state between the third transmission node and the second output node; The bootstrap circuit includes: a capacitor element having one end electrically connected to the first output node and the other end electrically connected to the second output node; and a diode element having an anode terminal electrically connected to the third transmission node and a cathode terminal electrically connected to the second output node, The voltage limiting circuit switches the conduction state between the third transmission node and the second output node according to the potential difference between the third transmission node and the second output node.

8. The liquid ejection device according to claim 7, wherein: When the potential of the third transmission node is greater than the potential of the second output node and the potential difference between the third transmission node and the second output node is greater than a first threshold, the voltage limiting circuit enables conduction between the third transmission node and the second output node.

9. The liquid ejection device according to claim 8, wherein: The voltage limiting circuit includes a first Zener diode, a first resistance element, and a first transistor, In the first Zener diode, a cathode terminal is electrically connected to the third transmission node, and an anode terminal is electrically connected to one end of the first resistance element. In the first resistance element, the other end is electrically connected to the second output node, In the first transistor, a base terminal is electrically connected to the anode terminal of the first Zener diode and one end of the first resistor, a collector terminal is electrically connected to the third transfer node, and an emitter terminal is electrically connected to the second output node.

10. The liquid ejection device according to any one of claims 7 to 9, wherein: When the potential of the third transmission node is lower than the potential of the second output node and the potential difference between the third transmission node and the second output node is larger than a second threshold, the voltage limiting circuit enables conduction between the third transmission node and the second output node.

11. The liquid ejecting device according to claim 10, wherein: The voltage limiting circuit includes a second Zener diode, a second resistance element, and a second transistor, In the second Zener diode, a cathode terminal is electrically connected to the second output node, and an anode terminal is electrically connected to one end of the second resistor element. In the second resistance element, the other end is electrically connected to the third transmission node, In the second transistor, a base terminal is electrically connected to the anode terminal of the second Zener diode and one end of the second resistor, a collector terminal is electrically connected to the second output node, and an emitter terminal is electrically connected to the third transfer node.

12. The liquid ejection device according to claim 7, wherein: have: A DA conversion circuit converts a basic driving signal, which is a basis of the driving signal, into an analog basic driving signal; a modulation circuit, outputting a modulation signal obtained by modulating the analog basic driving signal; as well as a level switching signal output circuit, which outputs a level switching signal based on the basic driving signal, The first digital amplifier circuit outputs the first amplified signal obtained by amplifying the modulated signal based on the first potential and the second potential. The second digital amplifier circuit selects, based on the level switching signal, a signal obtained by shifting the reference potential of the first amplified signal based on the third potential or a signal not shifting the reference potential of the first amplified signal, and outputs the signal as the second amplified signal.

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