Single-channel and double-channel mainboard switching system, method and device

Abstract

The invention provides a single-path and double-path mainboard switching system, method and device. The system comprises a first processor, a second processor, a bridge chip, a controller, a change-over switch, a single-path flash memory and a double-path flash memory, the first main processor is interconnected with the bridge sheet through a first bus; the second processor is interconnected with the first processor through a second bus; the controller is electrically connected with the change-over switch and is used for detecting a state signal of the change-over switch in real time; in response to the single-path mode signal, executing a single-path operation mode; in response to the two-way mode signal, executing a two-way operation mode; the single-path flash memory is used for receiving read access of the first processor according to a single-path operation mode; and the two-way flash memory is used for receiving common read access of the first processor and the second processor according to the two-way operation mode. By integrating hardware control and software logic, dynamic switching of single-path and double-path modes of a single mainboard is realized, resources are enabled as required, and the hardware cost is remarkably reduced.

Description

Technical Field

[0001] The present application relates to the technical field of computer motherboard design, and in particular to a single-way or dual-way motherboard switching system, method, and device. Background Art

[0002] The motherboard is the connection center for all hardware components in a computer, responsible for transmitting various electronic signals and ensuring communication between components. In recent years, with the advancement of information technology, the technical requirements for motherboards have become increasingly stringent. Existing motherboard designs typically use single- and dual-core CPU configurations to meet different performance requirements.

[0003] However, in the prior art, single-socket and dual-socket motherboards are typically designed independently. When users upgrade from a single-socket to a dual-socket motherboard, they must replace the entire motherboard or redesign the circuits, resulting in redundant hardware investment and increased development costs. Summary of the Invention

[0004] The present invention provides a single- and dual-channel motherboard switching system, switching method, and device. By integrating hardware control and software logic, the system can dynamically switch between single- and dual-channel modes of a single motherboard and enable resources on demand, significantly reducing hardware costs and improving system reliability.

[0005] In a first aspect, the present invention provides a single-way and dual-way motherboard switching system, the system comprising: a first processor, a second processor, a bridge chip, a controller, a switch, a single-way flash memory and a dual-way flash memory;

[0006] The first main processor is interconnected with the bridge chip via a first bus;

[0007] The second processor is interconnected with the first processor via a second bus;

[0008] The controller is electrically connected to the switch and is configured to detect a status signal of the switch in real time; the status signal includes a single-path mode signal and a dual-path mode signal; in response to the single-path mode signal, the controller executes a single-path operation mode; in response to the dual-path mode signal, the controller executes a dual-path operation mode;

[0009] The single-channel flash memory is configured to accept read access from the first processor according to the single-channel operation mode;

[0010] The dual-way flash memory is configured to accept a common read access from the first processor and the second processor according to the dual-way operation mode.

[0011] Preferably, the switch is a physical toggle switch or an electronic signal switching device, configured to send the status signal to the controller.

[0012] Preferably, the single-channel flash memory stores a startup program configured for a single processor, and the dual-channel flash memory stores a startup program for collaborative operation of dual processors. Both the single-channel flash memory and the dual-channel flash memory have independent physical storage space and access channels.

[0013] Preferably, it further comprises a power supply control module configured to simultaneously activate the dual-way power supply control circuits of the first processor and the second processor in the dual-way operation mode; and to only activate the single-way power supply control circuit of the first processor in the single-way operation mode;

[0014] The controller is connected to the power control module via a universal input and output interface.

[0015] In a second aspect, the present invention provides a method for switching between a single-way and a dual-way motherboard, the method being applied to the system as described in the first aspect, the method comprising:

[0016] The controller detects the status signal of the switch in real time; the status signal includes a single-channel mode signal and a dual-channel mode signal;

[0017] In response to the single-channel mode signal, executing a single-channel operation mode;

[0018] In response to the dual-path mode signal, a dual-path operation mode is performed.

[0019] Preferably, in response to the single-path mode signal, executing the single-path operation mode includes:

[0020] In response to the single-channel mode signal, controlling the switch to connect an access channel of the single-channel flash memory;

[0021] Synchronously activate the single-power supply control circuit;

[0022] The first processor is guided to load a startup program from the single-channel flash memory and initialize the system.

[0023] Preferably, in response to the dual-path mode signal, executing the dual-path operation mode comprises:

[0024] In response to the two-way mode signal, establishing a communication link of a second bus between the first processor and the second processor;

[0025] Simultaneously activate the dual power supply control circuit;

[0026] Configure access priority of dual-channel flash memory;

[0027] A startup program synchronous loading mechanism is established between the first processor and the second processor.

[0028] Preferably, establishing a communication link of the second bus between the first processor and the second processor includes:

[0029] sending a bus enable signal to the first processor;

[0030] configuring the second bus to a HyperTransport bus operating mode according to the bus enable signal;

[0031] establishing an interrupt signal handshake protocol between the first processor and the second processor;

[0032] The communication link is established according to the HyperTransport bus operating mode and the interrupt signal handshake protocol.

[0033] In a third aspect, the present invention provides a switching device for a single-way or dual-way motherboard switching system, comprising:

[0034] A status signal detection module is used to detect the status signal of the switch in real time through the controller; the status signal includes a single-channel mode signal and a dual-channel mode signal;

[0035] a single-channel operation mode execution module, configured to respond to the single-channel mode signal and execute the single-channel operation mode;

[0036] The dual-path operation mode execution module is configured to respond to the dual-path mode signal and execute the dual-path operation mode.

[0037] In a fourth aspect, the present invention provides an electronic device comprising a processor and a memory storing execution instructions, wherein when the processor executes the execution instructions stored in the memory, the processor executes any method described in the second aspect.

[0038] The present invention provides a single- and dual-path motherboard switching system, method, and device. By integrating hardware control and software logic, dynamic switching between single- and dual-path modes of a single motherboard and on-demand resource activation are achieved, reducing hardware duplication and material inventory costs. Users can complete mode switching through physical switches or software instructions without disassembly or restarting the machine. Physical isolation of dual flash memories avoids program conflicts, significantly reducing hardware costs and improving system reliability.

[0039] The further effects of the above-mentioned non-conventional preferred embodiment will be described below in conjunction with specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the embodiments of the present invention or the existing technical solutions, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0041] Figure 1 A schematic diagram of the structure of a single- and dual-way motherboard switching system provided by one embodiment of the present invention;

[0042] Figure 2 A schematic diagram of a single-way or dual-way motherboard switching method provided by one embodiment of the present invention;

[0043] Figure 3 A schematic diagram of another single- and dual-way motherboard switching method provided by an embodiment of the present invention;

[0044] Figure 4 A schematic diagram of a single- and dual-way motherboard switching device provided by one embodiment of the present invention;

[0045] Figure 5 A schematic structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0046] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0047] The motherboard is the connection center for all hardware components in a computer, responsible for transmitting various electronic signals and ensuring communication between components. In recent years, with the advancement of information technology, the technical requirements for motherboards have become increasingly stringent. Existing motherboard designs typically use single- and dual-core CPU configurations to meet different performance requirements.

[0048] Single-socket and dual-socket motherboard design is a core technology for balancing performance and cost. However, existing single-socket and dual-socket motherboard technology suffer from the following significant drawbacks: 1. Hardware resource waste and high cost. In existing technology, single-socket and dual-socket motherboards are typically designed separately. When upgrading from a single-socket to a dual-socket motherboard, users must replace the entire motherboard or redesign the circuitry, resulting in duplicate hardware investment and increased development costs. For example, some circuitry on a single-socket motherboard (such as the slave CPU socket and redundant power supply module) can remain idle for extended periods in single-socket mode, resulting in wasted resources. 2. Switching between single-socket and dual-socket modes is complex and lacks flexibility. In existing solutions, switching between single-socket and dual-socket modes requires jumpers, BIOS settings, or physical removal of the slave CPU. This requires professional intervention, lacks dynamic switching, and can easily lead to hardware damage due to misuse. For example, directly plugging in or unplugging a slave CPU without properly powering it off can cause bus signal conflicts or power shorts. 3. The bootloader is separated from power management. Traditional motherboards' single-socket and dual-socket mode switching only controls CPU power supply control and is not integrated with the bootloader loading logic. For example, if the dual-core boot program is not loaded synchronously in dual-core mode, it may cause slave CPU initialization failure or bus communication abnormality.

[0049] In summary, single-socket and dual-socket motherboards typically require separate designs. When users upgrade from a single-socket to a dual-socket motherboard, they must replace the entire motherboard or redesign the circuitry, resulting in redundant hardware investment and increased development costs.

[0050] In view of this, the present invention provides a single-way and dual-way motherboard switching system. Figure 1 The figure shows a specific embodiment of a single-way and dual-way motherboard switching system provided by the present invention. In this embodiment, the switching system includes: a first processor 10, a second processor 20, a bridge chip 30, a controller 40, a switch 50, a single-way flash memory 60, and a dual-way flash memory 70. The first main processor 10 is interconnected with the bridge chip 30 via a first bus; the second processor 20 is interconnected with the first processor 10 via a second bus; the controller 40 is electrically connected to the switch 50 and is configured to detect the status signal of the switch 50 in real time; the status signal includes a single-way mode signal and a dual-way mode signal; in response to the single-way mode signal, the single-way operation mode is executed; in response to the dual-way mode signal, the dual-way operation mode is executed; the single-way flash memory 60 is used to accept read access from the first processor 10 according to the single-way operation mode; and the dual-way flash memory 70 is used to accept joint read access from the first processor 10 and the second processor 20 according to the dual-way operation mode.

[0051] Specifically, the first processor 10 in this embodiment serves as the master processor, and the second processor 20 serves as the slave processor. The first processor 10 and the second processor 20 can be general-purpose processors, including a central processing unit (CPU), a network processor (NP), etc.; they can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gates or transistor logic devices, or discrete hardware components. The first processor 10 and the second processor 20 in this embodiment can specifically adopt the Loongson 3A4000 processor, which is a general-purpose processor for information technology fields such as personal computers and servers, and integrates vulnerability prevention design, hardware national secret algorithms, security and trust modules, and security access control mechanisms.

[0052] Specifically, in this embodiment, the bridge chip 30 can be a bridge chip supporting the Loongson 7A1000 processor. The bridge chip 30 is interconnected with the first processor 10 (3A4000) via the first bus (HT0), converting the original bus signals of the first processor 10 into a variety of standard peripheral interfaces. These include: a storage interface that provides a SATA 2.0 channel (3Gbps) to connect hard disks / solid-state drives; a high-speed expansion interface that supports PCIe 3.0x8 slots for connecting GPUs, network cards, and other devices; and a low-speed peripheral interface that integrates USB 2.0 and Gigabit Ethernet controllers to meet basic I / O requirements. By centrally managing peripherals through the bridge chip 30, the first processor 10 does not need to directly handle the underlying protocol conversion and can focus on computing tasks, reducing the CPU load by approximately 15% to 20%. At the same time, it can form dynamic resource allocation in single- and dual-channel modes. Single-channel operation mode: The bridge chip 30 only responds to the first bus request of the first processor 10, and all peripheral resources (such as PCIe channels and USB ports) are allocated to the first processor 10. Dual-path operation mode: The bridge chip 30 works in conjunction with the first processor 10 to share some peripheral resources (such as PCIe x4 channels) with the second processor 20 through the second bus, thereby achieving dynamic segmentation of peripheral resources.

[0053] Specifically, the switch 50 is a physical toggle switch or an electronic signal switching device configured to send a status signal to the controller 40. For example, the physical toggle switch can be a double-pole double-throw (DPDT) toggle switch with gold-plated contacts and a contact resistance of ≤10mΩ. The electronic signal switching device can be a digital switch with an I2C interface (such as the PCA9557) that supports software-triggered mode switching.

[0054] Specifically, the single-channel flash memory 60 stores the boot program for a single processor configuration, and the dual-channel flash memory 70 stores the boot program for dual processors working together. Both the single-channel flash memory 60 and the dual-channel flash memory 70 have independent physical storage space and access channels. For example, the single-channel flash memory 60 can use GD25Q64 with a capacity of 8MB to store a single-channel UEFI boot program. The dual-channel flash memory 70 can use parallel NAND Flash (MT29F4G08ABA) with a capacity of 512MB to store dual-channel BIOS and CPU collaborative scheduling code.

[0055] Specifically, the switching system also includes a power supply control module configured to simultaneously activate the dual-way power supply control circuits of the first processor 10 and the second processor 20 in the dual-way operation mode; and to activate only the single-way power supply control circuit of the first processor 10 in the single-way operation mode. Exemplarily, the single-way power supply control circuit of the first processor 10 can adopt a multi-phase Buck circuit (IR35201), outputting +12V / 60A and having a conversion efficiency of ≥92%. The power supply of the second processor 20 can be independently deployed with a Buck circuit of the same specifications, which is physically isolated from the power supply of the first processor 10. The dual-way power supply control circuit can be jointly powered by two Buck circuits. The controller 40 is connected to the power supply control module via a universal input and output interface. Single-way operation mode: Controller Pin 1 outputs a high level to enable the single-way power supply control circuit; Pin 2-Pin 8 remain low, turning off the power supply to the second processor 20. Dual-way operation mode: Pin 1-Pin 8 all output a high level, synchronously activating the power supply of the first processor 10 and the second processor 20, starting the dual-way power supply control circuit, and the startup sequence delay is ≤10ms to avoid inrush current.

[0056] Specifically, the controller 40 (CPLD) serves as the control center, receives the signal from the switch 50, controls the flash memory access channel switching, the start and stop of the power control module, and the initialization of the bus communication. The mode switching logic is implemented by programming in a hardware description language (such as Verilog), and the level signal of the switch 50 is detected (high level is dual-channel operation mode, low level is single-channel operation mode). The multiplexer (MUX) is controlled to switch the chip select signal (CS) of the single / dual flash memory. The enable end of the power control module is controlled by the general input and output (GPIO) pin. For example, the controller 40 can use XilinxXC2C256, which has 256 built-in macro units, an operating frequency of 100MHz, and supports JTAG online programming. GPIO configuration: 8 pins are allocated for power control (Pin1-Pin8), 4 pins are used for flash memory chip select (Pin9-Pin12), and 2 pins are used for HT bus enable (Pin13-Pin14). When single-channel operation mode is selected, the CPLD controls the switch to connect a single flash memory channel, activates only a single power supply control circuit, and directs the system to load the boot program from the single flash memory 60. When dual-channel operation mode is selected, the CPLD simultaneously activates the dual power supply control circuits, establishes a second bus (HT1 bus) communication link, configures the PCIe channel to HT bus mode, and simultaneously loads the dual-channel boot program.

[0057] The core technology for balancing performance and cost is the design of a single- and dual-socket motherboard switching system. A single-socket motherboard with a single CPU is suitable for low-load scenarios (such as office servers), while a dual-socket motherboard with a master and slave CPU working together can enhance multi-threaded processing capabilities (such as database clusters).

[0058] It should be noted that the specific types, quantities and combinations of the first processor 10, the second processor 20, the bridge chip 30, the controller 40, the switching switch 50, the single-channel flash memory 60 and the dual-channel flash memory 70 can be adjusted according to the actual needs of the application scenario, and the embodiments of the present application do not limit this.

[0059] It can be seen from the above technical solution that the beneficial effect of this embodiment is: the present invention realizes dynamic switching between single-channel and dual-channel CPU modes and on-demand resource allocation through deep coordination of hardware control and software logic, significantly reduces hardware redundancy costs and improves system reliability.

[0060] The present invention also provides a single-way and dual-way motherboard switching method. Figure 2 The figure shows a specific embodiment of a single-way or dual-way motherboard switching method provided by the present invention. In this embodiment, the method is applied to Figure 1 The system shown, the method includes:

[0061] Step 101: Detecting a status signal of a switch in real time through a controller; the status signal includes a single-channel mode signal and a dual-channel mode signal;

[0062] Specifically, the controller continuously monitors the GPIO input (such as Pin 15) of the switch. The input signal of the GPIO is the status signal. GPIO is a general-purpose input and output interface, a flexible hardware interface that can be configured as input (receiving signal) or output (sending signal) through programming. In this embodiment, the GPIO is configured in input mode to read the status signal of the switch. The single-channel mode signal or dual-channel mode signal selected by the user can be determined by the level state (high / low) of the GPIO pin. For example, when the switch is a physical toggle switch, the physical operation of the switch (such as toggling) is converted into a digital signal that can be recognized by the controller. A high level (3.3V) is a dual-channel mode signal, and a low level (0V) is a single-channel mode signal. When the switch is an electronic switch (such as an I2C digital switch), it communicates with the controller via the I2C bus. The GPIO is used to trigger a mode switching request and can support software remote control (such as switching modes through operating system instructions). Similarly, a high level (3.3V) is a dual-channel mode signal, and a low level (0V) is a single-channel mode signal.

[0063] Step 102: In response to the single-channel mode signal, control the switch to connect the access channel of the single-channel flash memory;

[0064] Specifically, in response to the single-channel mode signal, a single-channel operating mode is executed. This single-channel operating mode may specifically include flash memory switching, power supply control, and startup program loading. For example, when the single-channel mode signal is detected, the controller sets Pin 9 to a low level, selecting the chip select signal (CS0) of the single-channel flash memory. Pins 10-12 are set high to disable access to the dual-channel flash memory.

[0065] Step 103: Synchronously activate the single-channel power supply control circuit;

[0066] The single-power supply control circuit only powers the first processor. This circuit can use a multi-phase buck converter (IR35201) with a +12V / 60A output. When a single-power mode signal is detected, Pin 1 outputs a high level, activating power to the first processor; Pins 2-8 remain low, shutting down power to the second processor.

[0067] Step 104: Instruct the first processor to load a startup program from the single-channel flash memory and initialize the system.

[0068] Specifically, the first processor reads the boot program from a single-channel flash memory address and initializes the memory, bridge chip, and peripherals. The controller (CPLD) monitors the first processor's reset signal and releases system control after confirming the boot is complete. This completes the boot program loading and enters single-channel operation mode.

[0069] Through the above technical solutions, it can be seen that the beneficial effects of this embodiment are: seamless switching, hardware-level control ensures that the switching process is completed within 10ms, and the user is unaware; high reliability, multiple checks (address range, timing matching) to avoid data corruption; energy saving and high efficiency, power consumption is reduced by 40% in single-channel operation mode, which is suitable for low-load scenarios.

[0070] Figure 2 What is shown is only a basic embodiment of the method of the present invention. By performing certain optimization and expansion on this basis, other preferred embodiments of the method can be obtained.

[0071] like Figure 3 FIG. 1 is another specific embodiment of a method for switching between a single-way and a dual-way motherboard according to the present invention. This embodiment further describes the above embodiment. In this embodiment, the method includes the following steps:

[0072] Step 201: Detecting a status signal of the switch in real time through a controller; the status signal includes a single-channel mode signal and a dual-channel mode signal;

[0073] Specifically, the controller continuously monitors the GPIO input (such as Pin 15) of the switch. The input signal of the GPIO is the status signal. GPIO is a general-purpose input and output interface, a flexible hardware interface that can be configured as input (receiving signal) or output (sending signal) through programming. In this embodiment, the GPIO is configured in input mode to read the status signal of the switch. The single-channel mode signal or dual-channel mode signal selected by the user can be determined by the level state (high / low) of the GPIO pin. For example, when the switch is a physical toggle switch, the physical operation of the switch (such as toggling) is converted into a digital signal that can be recognized by the controller. A high level (3.3V) is a dual-channel mode signal, and a low level (0V) is a single-channel mode signal. When the switch is an electronic switch (such as an I2C digital switch), it communicates with the controller via the I2C bus. The GPIO is used to trigger a mode switching request and can support software remote control (such as switching modes through operating system instructions). Similarly, a high level (3.3V) is a dual-channel mode signal, and a low level (0V) is a single-channel mode signal.

[0074] Step 202: Establishing a communication link of a second bus between the first processor and the second processor in response to the dual-mode signal;

[0075] Specifically, in response to the dual-path mode signal, the dual-path operation mode is executed. The dual-path operation mode may specifically include flash memory switching, power supply control, and startup program loading. Since the dual-path operation mode is a joint action of the first processor and the second processor, the first processor and the second processor need to be activated synchronously first. First, a bus enable signal is sent to the first processor, and the second bus is configured to HyperTransport bus operation mode according to the bus enable signal. An interrupt signal handshake protocol is established between the first processor and the second processor, and a communication link is established according to the HyperTransport bus operation mode and interrupt signal handshake protocol. Exemplarily, the controller can send a high level (bus enable signal) to the HT_EN pin of the first processor via Pin13 to activate the second bus (HT1 bus) controller. The PCIe x4 channel of the second processor is configured to HT mode (HyperTransport bus operation mode) by the controller. After the first processor completes HT1 link training, it sends an INIT# interrupt signal to the second processor. After the second processor responds, it returns a TRDY# signal, which the controller monitors to confirm that the communication link is ready.

[0076] Step 203: activating the dual power supply control circuits simultaneously;

[0077] The dual-power supply control circuit can provide power for the first processor and the second processor. When the dual-mode signal is detected, Pin1-Pin8 of the controller are set to a high level, and the dual-power supply control circuit is activated synchronously.

[0078] Step 204: Configure the access priority of the dual-channel flash memory;

[0079] In this embodiment, when two processors need to access the same storage resource, there must be a mechanism to determine which processor's access request is given priority. The dual-channel flash memory may be designed as two independent memory chips, or a shared memory chip, but time-sharing access is required, so it is necessary to configure the access priority. Specifically, the access priority of the dual-channel flash memory can be configured from two directions. The first direction: master-slave processor authority allocation, the first processor: has the highest access priority by default, and is responsible for critical tasks (such as startup program loading, interrupt processing). The second processor: adopts secondary priority in non-critical tasks (such as data cache reading and writing), or dynamically adjusts on demand. The second direction: scenario-based priority strategy, startup phase: the first processor has exclusive access to the dual-channel flash memory, and releases control after loading the dual-channel startup program. During runtime: the first processor has priority access to the configuration table and kernel code, and the second processor accesses the data area on demand.

[0080] Step 205: Establish a startup program synchronous loading mechanism between the first processor and the second processor.

[0081] Specifically, the first processor and the second processor read the boot program from the dual-channel flash memory address to initialize the memory, bridge chip, and peripherals. The first processor sends the initialization code block to the second processor via the second bus. After the second processor verifies the code check value, it completes the loading of the boot program and enters the dual-channel operation mode.

[0082] The above technical solution demonstrates the beneficial effects of this embodiment: single-socket operation meets low power consumption requirements, while dual-socket operation handles sudden high loads. A single motherboard is compatible with both single and dual-socket modes, reducing repetitive development costs, improving hardware resource utilization, and reducing power consumption.

[0083] like Figure 4 The figure shows a specific embodiment of a single-way or dual-way motherboard switching device of the present invention. Figures 2-3 The physical device of the method. Its technical solution is essentially consistent with the above embodiment, and the corresponding description in the above embodiment is also applicable to this embodiment. The device in this embodiment includes:

[0084] The status signal detection module 301 is configured to detect the status signal of the switch in real time through the controller; the status signal includes a single-channel mode signal and a dual-channel mode signal;

[0085] The single-channel operation mode execution module 302 is configured to respond to the single-channel mode signal and execute the single-channel operation mode;

[0086] The dual-path operation mode execution module 303 is configured to respond to the dual-path mode signal and execute the dual-path operation mode.

[0087] Figure 5 : This is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. At the hardware level, the electronic device includes a processor, and optionally also includes an internal bus, a network interface, and a memory. Among them, the memory may include internal memory, such as high-speed random access memory (RAM), and may also include non-volatile memory (non-volatile memory), such as at least one disk storage. Of course, the electronic device may also include hardware required for other services.

[0088] The processor, network interface, and memory can be interconnected through an internal bus, which can be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, or an EISA (Extended Industry Standard Architecture) bus. Buses can be divided into address buses, data buses, control buses, etc. For ease of representation, Figure 5 Only one bidirectional arrow is used in the diagram, but this does not mean that there is only one bus or one type of bus.

[0089] Memory is used to store execution instructions. Specifically, execution instructions are computer programs that can be executed. Memory can include internal memory and non-volatile memory, and provides execution instructions and data to the processor.

[0090] In one possible implementation, a processor reads corresponding execution instructions from non-volatile memory into internal memory and then executes them. Alternatively, the processor can obtain corresponding execution instructions from other devices to logically form a single- or dual-socket motherboard switching device. The processor executes the execution instructions stored in the memory to implement a single- or dual-socket motherboard switching method provided in any embodiment of the present invention.

[0091] The present invention Figure 4 The method performed by a single- and dual-way motherboard switching device provided in the illustrated embodiment can be applied to a processor or implemented by a processor. The processor may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by an integrated logic circuit of hardware in the processor or instructions in the form of software. The above processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The various methods, steps and logic block diagrams disclosed in the embodiments of the present invention can be implemented or executed. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc.

[0092] The steps of the method disclosed in conjunction with the embodiments of the present invention can be directly implemented and executed by a hardware decoding processor, or by a combination of hardware and software modules within the decoding processor. The software modules can be located in a storage medium well-known in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, etc. The storage medium is located in the memory, and the processor reads the information in the memory and, in conjunction with its hardware, completes the steps of the method described above.

[0093] The embodiment of the present invention further provides a readable medium, which stores an execution instruction. When the stored execution instruction is executed by the processor of the electronic device, the electronic device can execute a single-way or dual-way motherboard switching method provided in any embodiment of the present invention, and is specifically used to execute the following Figure 2 、 Figure 3 The method shown.

[0094] The electronic device in each of the aforementioned embodiments may be a computer.

[0095] Those skilled in the art will appreciate that the embodiments of the present invention may be provided as methods or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or a combination of software and hardware.

[0096] The various embodiments of the present invention are described in a progressive manner. Similar portions between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences between the other embodiments. In particular, the device embodiments are described briefly because they are generally similar to the method embodiments. For relevant portions, refer to the description of the method embodiments.

[0097] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not preclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0098] The above are merely embodiments of the present invention and are not intended to limit the present invention. It will be apparent to those skilled in the art that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention are intended to be included within the scope of the claims of the present invention.

Claims

1. A single-way and dual-way motherboard switching system, characterized in that: The system includes: a first processor, a second processor, a bridge chip, a controller, a switch, a single-channel flash memory and a dual-channel flash memory; The first main processor is interconnected with the bridge chip via a first bus; The second processor is interconnected with the first processor via a second bus; The controller is electrically connected to the switch and is configured to detect a status signal of the switch in real time; the status signal includes a single-path mode signal and a dual-path mode signal; in response to the single-path mode signal, the controller executes a single-path operation mode; in response to the dual-path mode signal, the controller executes a dual-path operation mode; The single-channel flash memory is configured to accept read access from the first processor according to the single-channel operation mode; The dual-way flash memory is configured to accept a common read access from the first processor and the second processor according to the dual-way operation mode.

2. The system according to claim 1, wherein: The switch is a physical toggle switch or an electronic signal switching device, configured to send the status signal to the controller.

3. The system according to claim 1, wherein: The single-channel flash memory stores a startup program configured for a single processor, and the dual-channel flash memory stores a startup program for collaborative operation of dual processors. Both the single-channel flash memory and the dual-channel flash memory have independent physical storage space and access channels.

4. The system according to claim 1, wherein: The invention also includes a power supply control module configured to simultaneously activate the dual-way power supply control circuits of the first processor and the second processor in the dual-way operation mode; and to activate only the single-way power supply control circuit of the first processor in the single-way operation mode; The controller is connected to the power control module via a universal input and output interface.

5. A single-way and dual-way motherboard switching method, characterized in that: The method is applied to the system according to claim 1, and the method comprises: The controller detects the status signal of the switch in real time; the status signal includes a single-channel mode signal and a dual-channel mode signal; In response to the single-channel mode signal, executing a single-channel operation mode; In response to the dual-path mode signal, a dual-path operation mode is performed.

6. The method according to claim 5, characterized in that In response to the single-path mode signal, executing the single-path operation mode includes: In response to the single-channel mode signal, controlling the switch to connect an access channel of the single-channel flash memory; Synchronously activate the single-channel power supply control circuit; The first processor is guided to load a startup program from the single-channel flash memory and initialize the system.

7. The method according to claim 5, characterized in that In response to the dual-path mode signal, executing the dual-path operation mode includes: In response to the two-way mode signal, establishing a communication link of a second bus between the first processor and the second processor; Simultaneously activate the dual power supply control circuit; Configure access priority of dual-channel flash memory; A startup program synchronous loading mechanism is established between the first processor and the second processor.

8. The method according to claim 7, characterized in that The establishing of a communication link of the second bus between the first processor and the second processor includes: sending a bus enable signal to the first processor; configuring the second bus to a HyperTransport bus operating mode according to the bus enable signal; establishing an interrupt signal handshake protocol between the first processor and the second processor; The communication link is established according to the HyperTransport bus operating mode and the interrupt signal handshake protocol.

9. A single-way or dual-way motherboard switching system switching device, characterized in that: include: A status signal detection module is used to detect the status signal of the switch in real time through the controller; the status signal includes a single-channel mode signal and a dual-channel mode signal; a single-channel operation mode execution module, configured to respond to the single-channel mode signal and execute the single-channel operation mode; The dual-path operation mode execution module is configured to respond to the dual-path mode signal and execute the dual-path operation mode.

10. An electronic device, characterized in that: The electronic device comprises: processor; a memory for storing instructions executable by the processor; The processor is configured to read the executable instructions from the memory and execute the instructions to implement the method according to any one of claims 5 to 8.

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