Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention provides a semiconductor device, a manufacturing method thereof and electronic equipment, and relates to the technical field of semiconductors. The semiconductor device comprises an HEMT device based on GaN, wherein the HEMT device comprises a substrate, a parasitic channel layer, an epitaxial layer and an electrode layer; the parasitic channel layer and the epitaxial layer are sequentially arranged on the substrate in the thickness direction of the substrate and in the direction far away from the substrate; the electrode layer is arranged on the side, away from the substrate, of the epitaxial layer, the electrode layer comprises a source electrode and a drain electrode, and the source electrode and the drain electrode are arranged at intervals in the first direction; wherein the parasitic channel layer comprises a first part and a second part, the first part and the second part are alternately arranged in the first direction, and the resistivity of the first part is smaller than that of the second part. According to the invention, the transient response capability of the HEMT device can be improved, and the reliability of the HEMT device is ensured.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0002] GaN-based HEMT (High Electron Mobility Transistor) devices have the characteristics of high frequency, high power, high efficiency, and low heat dissipation. They can meet the high power, high frequency, and large bandwidth requirements of radio frequency technology, making GaN-based HEMT devices increasingly used in the field of 5G communications.

[0003] However, when GaN-based HEMT devices are turned off under large drain stress and gate stress, electrons in the HEMT device channel are easily captured by defects in the epitaxial layer, making it difficult for the drain current to recover to its initial state in time after the GaN-based HEMT device is turned off.

[0004] To address the slow drain current recovery problem of HEMT devices during switching, a conductive channel is currently provided in the HEMT device's epitaxial layer to replenish electrons in the channel. This replenishes electrons in the channel and helps quickly recover the drain current. However, while replenishing electrons in the channel, the conductive channel's conductivity can easily increase leakage between the source and drain, thereby reducing the reliability of the HEMT device. Summary of the Invention

[0005] The present application provides a semiconductor device and a manufacturing method thereof, and an electronic device, which can improve the transient response capability of a HEMT device and ensure the reliability of the HEMT device.

[0006] In a first aspect, a semiconductor device is provided, comprising a substrate, a parasitic channel layer, an epitaxial layer and an electrode layer; the parasitic channel layer and the epitaxial layer are sequentially arranged on the substrate along the thickness direction of the substrate and in a direction away from the substrate; the electrode layer is arranged on a side of the epitaxial layer away from the substrate, the electrode layer comprising a source and a drain, the source and the drain being arranged at intervals along a first direction; wherein the parasitic channel layer comprises a first portion and a second portion, the first portion and the second portion being alternately arranged in the first direction, and the resistivity of the first portion is less than the resistivity of the second portion.

[0007] In this embodiment, on the one hand, because the resistivity of the first portion is lower than that of the second portion, the first portion has stronger conductivity than the second portion, thereby enabling the first portion to have movable electrons, so that the first portion can replenish electrons to the epitaxial layer, thereby replenishing electrons in the channel through the epitaxial layer. On the other hand, because the first and second portions are alternately arranged in the first direction, the second portion can be located between two adjacent first portions, so that the second portion blocks the movement of electrons between the two adjacent first portions, thereby forming a discontinuous conductive path in the parasitic channel layer in the first direction, thereby preventing the formation of a leakage path between the source and drain, reducing the leakage current of the HEMT device in the off state, and thus improving the reliability of the HEMT device.

[0008] In some embodiments, the first portion is embedded in the surface of the substrate near the epitaxial layer, and the second portion is formed at the same height as the first portion in the thickness direction of the substrate. This arrangement, on the one hand, allows the length of the first portion in the first direction to be adjusted by adjusting the size of the substrate area where the first portion is embedded, thereby facilitating adjustment of the length of the second portion in the first direction. On the other hand, because the first and second portions are at the same height in the thickness direction of the substrate, the sides of the first and second portions away from the substrate are flush, facilitating the growth of the epitaxial layer on the flush parasitic channel layer and substrate.

[0009] In some embodiments, the material of the first portion comprises an ion-implanted substrate material, and the ion concentration of the first portion is greater than the ion concentration of the second portion. In this configuration, the ion concentration of the first portion is greater than the ion concentration of the second portion, so that the resistivity of the first portion is less than the resistivity of the second portion, thereby making the conductivity of the first portion greater than the conductivity of the second portion.

[0010] In some embodiments, the epitaxial layer includes a nucleation layer disposed on the substrate, the first portion is disposed between the nucleation layer and the substrate, and the portion of the nucleation layer not covering the first portion forms the second portion. With this arrangement, the first portion is first grown on the substrate, and then the nucleation layer is grown simultaneously on the first portion and the substrate. This allows the nucleation layer to continue growing after the first portion has been grown, thereby improving the quality of the generated nucleation layer and facilitating the growth of other layers on top of the nucleation layer.

[0011] In some embodiments, the material of the first portion includes a doped nucleation layer material, and the doping concentration of the first portion is greater than the doping concentration of the second portion. This configuration allows the first portion's doping concentration to be greater than the doping concentration of the nucleation layer, resulting in a lower conductivity of the second portion formed by the nucleation layer than the first portion. Consequently, the second portion formed by the nucleation layer is positioned between adjacent first portions, thereby better blocking electrons from moving between the two adjacent first portions.

[0012] In some embodiments, the epitaxial layer includes a buffer layer disposed on the substrate, the first portion is disposed between the buffer layer and the substrate, and the portion of the buffer layer not covering the first portion forms the second portion. With this arrangement, the first portion is first grown on the substrate, and then the buffer layer is grown simultaneously on both the first portion and the substrate. This replaces the parasitic channel layer with the nucleation layer, eliminating the need for an additional nucleation layer growth step. This allows the buffer layer to be formed in a single growth step, thereby reducing the difficulty of growing the buffer layer.

[0013] In some embodiments, the first portion has an island-like structure comprising a plurality of island-like protrusions arranged along the surface of the substrate near the epitaxial layer. This configuration utilizes the island-like protrusions to increase conductivity, resulting in improved conductivity in the first direction and along the thickness of the substrate. This allows the first portion of the island structure to more quickly replenish electrons through the epitaxial layer to the channel.

[0014] In some embodiments, the material of the first portion includes AlN or AlGaN, and the material of the second portion includes GaN or AlGaN. This arrangement facilitates the growth of a buffer layer using GaN material on the first portion of the AlN material, reducing the number of implantation and doping steps, resulting in a GaN buffer layer with higher crystal quality and better insulation properties, and facilitating greater conductivity of the first portion than the second portion.

[0015] In some embodiments, the surface of the substrate near the buffer layer is provided with an atomic step corresponding to the first portion, so that the surface of the substrate having the atomic step forms the island-shaped first portion, while the surface of the substrate without the atomic step forms the second portion.

[0016] In some embodiments, the parasitic channel layer includes two first portions, and the second portion is disposed between two adjacent first portions. This arrangement allows the second portion to be located between the two first portions, blocking the electron movement path between the two first portions, thereby reducing the movement of electrons in the parasitic channel layer in the first direction, thereby facilitating the first portion to replenish electrons into the channel through the epitaxial layer.

[0017] In some embodiments, in the first direction, the length of the first portion near the source is shorter than the length of the first portion near the drain. This arrangement allows the gate to be positioned closer to the source and farther from the drain due to the withstand voltage design of the HEMT device to improve the withstand voltage capability of the drain. In this embodiment, the length of the first portion near the source is shorter than the length of the first portion near the drain. This ensures that the lengths of the two first portions in the first direction match the gate position for the withstand voltage design, thereby ensuring that the length design of the first portion complies with the withstand voltage design of the HEMT device.

[0018] In some embodiments, the electrode layer further comprises a gate disposed on a side of the epitaxial layer away from the substrate, the gate being positioned between the source and drain. Along the thickness of the substrate, the gate overlaps the second portion, while the source and drain overlap the two first portions, respectively. This arrangement, with the second portion corresponding to the gate and the source and drain corresponding to the two first portions, helps the second portion block the movement of electrons between two adjacent first portions, reducing the movement of electrons in the first portion in the first direction and facilitating the first portion to replenish electrons to the channel through the epitaxial layer along the thickness of the substrate.

[0019] In some embodiments, in the first direction, the length of the second portion is smaller than the length of the first portion. In this way, the length of the first portion is increased, thereby increasing the area of ​​the parasitic channel layer, thereby increasing the amount of electrons supplied to the channel by the parasitic channel layer through the epitaxial layer.

[0020] In a second aspect, a method for manufacturing a semiconductor device is provided, comprising: forming a parasitic channel layer on a substrate; epitaxially growing an epitaxial layer on the parasitic channel layer; forming an electrode layer on the epitaxial layer, the electrode layer comprising a source and a drain, the source and the drain being arranged at intervals along a first direction; wherein the parasitic channel layer comprises a first portion and a second portion, the first portion and the second portion being arranged alternately in the first direction, and the resistivity of the first portion is less than the resistivity of the second portion.

[0021] The method for manufacturing a semiconductor device provided in an embodiment of the present application is used to manufacture the semiconductor device provided in the first aspect. The technical effects brought about can refer to the technical effects brought about by the different implementation methods of the above-mentioned first aspect, and will not be repeated here.

[0022] In some embodiments, forming a parasitic channel layer on a substrate includes: ion implanting a first region of the substrate to form a first portion of the parasitic channel layer; forming a second portion of the parasitic channel layer in a region of the substrate not implanted with ions; and epitaxially growing an epitaxial layer on the parasitic channel layer, including: sequentially epitaxially growing a nucleation layer, a buffer layer, and a barrier layer on the first portion of the parasitic channel layer and the substrate. This configuration, using selective ion implantation to form the first portion of the substrate, helps reduce the resistivity of the first region of the substrate, such that the resistivity of the first portion is less than that of the second portion formed on the substrate.

[0023] In some embodiments, the forming of a parasitic channel layer on a substrate comprises: epitaxially growing an initial parasitic channel layer on the substrate; patterning the initial parasitic channel layer to form first portions spaced apart from each other, with gaps formed between two adjacent first portions; and epitaxially growing an epitaxial layer on the parasitic channel layer comprises: epitaxially growing a nucleation layer on the first portion of the parasitic channel layer and on the substrate, and filling the nucleation layer with the portion to form a second portion of the parasitic channel layer.

[0024] In this way, the first part of the parasitic channel layer, that is, the first nucleation layer, is epitaxially grown on the substrate for the first time, and then the nucleation layer, that is, the second nucleation layer, is epitaxially grown on the first part and the substrate for the second time, so that the nucleation layer is formed through secondary epitaxial growth, thereby improving the crystal quality of the second epitaxial growth of the nucleation layer, thereby improving the insulation of the second nucleation layer.

[0025] In some embodiments, the forming of a parasitic channel layer on the substrate includes: etching a first area of ​​the substrate to form an atomic step; epitaxially growing a first portion of the parasitic channel layer on the atomic step; and epitaxially growing an epitaxial layer on the parasitic channel layer to form an epitaxial layer, including: epitaxially growing a buffer layer on the first portion of the parasitic channel layer and the substrate, wherein a portion of the buffer layer not covering the first portion forms a second portion of the parasitic channel layer.

[0026] In this way, by forming atomic steps on the substrate, the first part of the parasitic channel layer grows into an island-shaped protrusion in the first region of the substrate, and a buffer layer is directly grown on the first part and the substrate, so that the parasitic channel layer is used as a nucleation layer, so that the buffer layer is formed in one epitaxial growth, thereby reducing the difficulty of subsequent epitaxial growth.

[0027] In a third aspect, an electronic device is provided, comprising a circuit board and a semiconductor device, wherein the semiconductor device is the semiconductor device described in the first aspect, and the semiconductor device is disposed on the circuit board.

[0028] The technical effects brought about by any possible implementation of the third aspect can refer to the technical effects brought about by the above-mentioned first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A structural block diagram of a base station with a 5G power amplifier provided in an embodiment of the present application;

[0030] Figure 2 A structural block diagram of a 5G power amplifier for a base station provided in an embodiment of the present application;

[0031] Figure 3 A schematic diagram of the structure of the electrons captured in the HEMT device provided in an embodiment of the present application;

[0032] Figure 4 The semiconductor device provided in the embodiment of the present application is a schematic structural diagram of a GaN-based HEMT device;

[0033] Figure 5 A schematic diagram of the arrangement of the first and second parts provided in an embodiment of the present application;

[0034] Figure 6 A schematic diagram of the effect of selective ion implantation on a substrate provided in an embodiment of the present application;

[0035] Figure 7 A schematic diagram of the corresponding relationship between a parasitic channel layer and a source, gate, and drain provided in an embodiment of the present application;

[0036] Figure 8 A time curve diagram of drain current recovery after the switch of the HEMT device provided in an embodiment of the present application is turned off;

[0037] Figure 9 A graph showing the relationship between the conductive channel and the off-state leakage provided in an embodiment of the present application;

[0038] Figure 10 A schematic diagram of the structure of a HEMT device provided in an embodiment of the present application, in which a parasitic channel layer is located between a substrate and an epitaxial layer;

[0039] Figure 11 A schematic diagram of the structure in which the first portion of the parasitic channel layer provided in an embodiment of the present application is island-shaped;

[0040] Figure 12 A flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0041] Figure 13 A flow chart of a method for manufacturing a parasitic channel layer provided in an embodiment of the present application;

[0042] Figure 14A schematic diagram of a generation process of a parasitic channel layer provided in an embodiment of the present application;

[0043] Figure 15 A flow chart of another method for manufacturing a parasitic channel layer provided in an embodiment of the present application;

[0044] Figure 16 A schematic diagram of another generation process of a parasitic channel layer provided in an embodiment of the present application;

[0045] Figure 17 A flow chart of another method for manufacturing a parasitic channel layer provided in an embodiment of the present application. DETAILED DESCRIPTION

[0046] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0047] The terms "first," "second," and the like (if any) in the description and claims of the present invention and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions, e.g., a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to these processes, methods, products, or apparatus.

[0048] The following is a brief introduction to some concepts that may be involved in the embodiments of the present invention.

[0049] PVD (Physical Vapor Deposition): Physical vapor deposition, a widely used coating technology, has the characteristics of dense and uniform coating layer, strong adhesion and fast deposition speed.

[0050] MBE (Molecular Beam Epitaxy): Molecular beam epitaxy, a crystal growth technology that can produce thin-film semiconductor materials with good surface morphology.

[0051] MOCVD (Metal-Organic Chemical Vapor Deposition): Metal-Organic Chemical Vapor Deposition, a commonly used thin film material growth technology, uses chemical reactions in the reactor to form solid deposits through chemical reactions in the gas phase or at the gas-solid interface.

[0052] The embodiment of the present application provides an electronic device, such as a radar, a 4G or 5G power amplifier (PA) of a base station, etc., which has high power, high frequency, and wide bandwidth functions in the field of radio frequency technology. Figure 1 As shown, Figure 1 This is a structural block diagram of a base station with a 5G power amplifier provided in an embodiment of the present application. The electronic device in this embodiment takes the 5G power amplifier PA of the base station as an example. Figure 1 The base station includes a baseband processing unit (BBU) and a radio remote unit (RRU), which are connected by optical fiber. The RRU is connected to the antenna and mainly completes the reception and transmission of baseband signals. The RRU switches the reception and transmission of RF signals through a duplexer, so that after the duplexer receives the uplink RF signal from the antenna, the low noise amplifier (LNA) amplifies the RF signal and reduces the noise under the power supply of the power module, and then transmits the amplified RF signal to the BBU through the high-speed interface module. The PA is located between the transmission antenna (TXA) and the duplexer in the RRU. The RRU can also transmit the downlink RF signal from the BBU through the high-speed interface module, and the TXA converts the RF signal into a radio signal and transmits it to the PA. The PA then amplifies the RF signal and sends it to the antenna through the duplexer.

[0053] See Figure 2 , Figure 2 This is a structural block diagram of a 5G power amplifier 1000 for a base station provided in an embodiment of the present application. The 5G power amplifier 1000 for the base station may include a circuit board 100 and a semiconductor device 200.

[0054] It should be noted that the semiconductor device 200 of the power amplifier 1000 of a 4G or 5G base station includes a GaN-based HEMT device, which is mounted on a circuit board 100. The HEMT device and the circuit board are applied together to the 5G power amplifier 1000 to achieve the high-power, high-frequency, and wide-bandwidth functions of the 5G power amplifier.

[0055] See Figure 2 and Figure 3 , Figure 3 Schematic diagram of the structure of the electron capture of the HEMT device provided in the embodiment of the present application. The HEMT device generally includes a substrate 210, an epitaxial layer 220, and a source 231, a gate 232, and a drain 233 arranged on the epitaxial layer 220. The epitaxial layer 220 includes a nucleation layer 221, a buffer layer 222, and a barrier layer 223, which are sequentially arranged on the substrate 210, wherein a channel 224 is provided between the buffer layer 222 and the barrier layer 223. However, after the HEMT device is applied to the 5G power amplifier, the HEMT device operates at a high frequency (2GHz-4.9GHz). In the first few seconds after the HEMT device stops working, the current of the drain 233 varies greatly, resulting in poor linearity and unstable gain of the HEMT device, and ultimately unstable output power, which may cause the HEMT device to have insufficient transient response capability.

[0056] See Figure 3 When the HEMT device is turned off under large drain 233 stress and gate 232 stress, the two-dimensional electron gas in the channel 224 is shown as Figure 3 In the sphere in the channel 224, the two-dimensional electron gas is easily captured by defects in the buffer layer 222 and the nucleation layer 221 in the thickness direction of the channel 224, and is also easily captured by defects in the barrier layer 223. Moreover, it takes a long time for the electrons to be released from the defects and participate in conduction, which causes the drain 233 current to decrease while the drain 233 current takes a long time to recover. As a result, it is difficult for the drain 233 current to recover to its initial state in time after the HEMT device is turned off, and it is difficult to meet the application requirements of 5G power amplifiers in RF application scenarios.

[0057] In some embodiments, to shorten the time it takes for the drain 233 current to recover, methods such as adding a conductive channel between the substrate 210 and the epitaxial layer 220 or using a conductive substrate 210 are employed. Electrons carried by the conductive channel or the conductive substrate 210 are used to replenish electrons trapped in the epitaxial layer 220, thereby shortening the time it takes for the drain 233 current to recover. However, whether adding a conductive channel or using a conductive substrate 210, when electrons are replenished to the channel through the epitaxial layer 220, electrons in the conductive channel can move perpendicular to the thickness of the substrate 210, causing leakage in the conductive channel. Electrons in the conductive substrate 210 can also leak along the thickness of the substrate 210, increasing leakage in the substrate 210. Both of these electron replenishment methods can exacerbate leakage, resulting in reduced reliability of the HEMT device.

[0058] To this end, some embodiments of the present application provide a semiconductor device 200, which is mainly a GaN-based HEMT device, which can improve the transient response capability of the HEMT device while also taking into account the reliability of the HEMT device.

[0059] See Figure 4 , Figure 4 The semiconductor device 200 provided in an embodiment of the present application is a schematic structural diagram of a GaN-based HEMT device. The semiconductor device 200 includes a substrate 210, a parasitic channel layer 240, an epitaxial layer 220, and an electrode layer 230. The parasitic channel layer 240 and the epitaxial layer 220 are sequentially arranged on the substrate 210 along the thickness direction of the substrate 210 and away from the substrate 210. The electrode layer 230 is arranged on the side of the epitaxial layer 220 away from the substrate 210. The electrode layer 230 includes a source electrode 231 and a drain electrode 233, which are arranged in a first direction with an interval. The first direction is perpendicular to the thickness direction of the substrate 210.

[0060] The parasitic channel layer 240 includes a first portion 241 and a second portion 242 . The first portion 241 and the second portion 242 are alternately arranged in a first direction. The resistivity of the first portion 241 is smaller than that of the second portion 242 .

[0061] In this embodiment, on the one hand, because the resistivity of the first portion 241 is lower than that of the second portion 242, that is, the conductivity of the first portion 241 is greater than that of the second portion 242, the first portion 241 carries electrons, allowing the first portion 241 to replenish the electrons to the channel through the epitaxial layer 220, so that the electrons in the channel can be replenished after being captured in the epitaxial layer 220. On the other hand, in the first direction, because the first portions 241 and the second portions 242 are alternately arranged in the first direction and the conductivity of the second portions 242 is weaker than that of the first portions 241, the second portions 242 can block the movement of electrons between the source 231 and the drain 233, thereby forming a discontinuous conductive path in the parasitic channel layer 240 in the first direction. This prevents the formation of a leakage path between the source 231 and the drain 233, thereby reducing the leakage current of the HEMT device in the off state and improving the reliability of the HEMT device.

[0062] In some embodiments, the length of the second portion 242 in the first direction is less than the length of the first portion 241. By increasing the length of the first portion 241, the area of ​​the parasitic channel layer 240 is increased, thereby increasing the amount of electrons supplied to the channel by the parasitic channel layer 240 through the epitaxial layer 220. The length of the first portion 241 in the first direction ranges from 1 μm to 10 μm, for example, and the length of the second portion 242 in the first direction ranges from 100 nm to 5 μm, for example.

[0063] In some embodiments, the source electrode 231 and the drain electrode 233 may be made of Ti, Al, Ni, or Au. The substrate may be made of a semi-insulating semiconductor material such as silicon carbide (4H-SiC, 6H-SiC, or 3C-SiC), sapphire, aluminum nitride, or gallium nitride. When the substrate 210 is made of silicon carbide, the resistivity of the substrate 210 may be greater than 1e5 ohm.cm or greater than 1e8 ohm.cm.

[0064] The semiconductor device 200 further includes a gate 232 located between the source 231 and the drain 233. The gate 232 may be made of Au, Ti, Ta or Ti.

[0065] In some embodiments, the semiconductor device 200 further includes a field plate 234 and a dielectric layer 235. The dielectric layer 235 is disposed on a side of the epitaxial layer 220 facing away from the parasitic channel layer 240. The field plates 234 are disposed on both sides of the dielectric layer 235 in a first direction. The gate 232 and one of the field plates 234 are integrally disposed on one side of the dielectric layer 235 in the first direction. In other words, the gate 232, the field plate 234, and the dielectric layer 235 are located between the source 231 and the drain 233. The gate 232 is located above the dielectric layer 235 so that the dielectric layer 235 can reduce leakage of the gate 232. The field plates 234 are used to increase the operating bias voltage and breakdown voltage of the HEMT device. Figure 4 The dotted line between the field plate 234 and the source 231 in FIG. 2 indicates that the field plate 234 connected to the gate 232 and the source 231 are connected to the ground, which helps to improve the withstand voltage capability of the HEMT device.

[0066] In some embodiments, the first portion 241 and the second portion 242 of the parasitic channel layer 240 may be arranged in the following three ways. Figure 5 (a), (b), (c), where Figure 5 The dotted line in is the area where the second portion 242 is located.

[0067] For example, (a) in Figure 5 shows that the parasitic channel layer 240 includes two first parts 241 and a second part 242, and the second part 242 is arranged between the two adjacent first parts 241 to block the mutual movement of electrons between the two adjacent first parts 241 through the second part 242, thereby reducing the electron leakage of the parasitic channel layer 240.

[0068] On this basis, for example, combined Figure 4 and Figure 5In (a), along the thickness direction of the substrate 210, the gate 232 overlaps with the second part 242, and the source 231 and the drain 233 overlap with the two first parts 241 respectively, which helps the second part 242 to block the movement of electrons between the two adjacent first parts 241, thereby reducing the leakage of the parasitic channel layer 240; and it is convenient for the first part 241 to replenish electrons to the channel through the epitaxial layer 220 along the thickness direction of the substrate 210.

[0069] For example, in the first direction, the length of the first portion 241 near the source 231 is shorter than the length of the first portion 241 near the drain 233. Due to the voltage-resistant design of the HEMT device, the gate 232 is positioned closer to the source 231 and farther from the drain 233 to improve the voltage-resistant capability of the drain 233. In this embodiment, the length of the first portion 241 near the source 231 is shorter than the length of the first portion 241 near the drain 233, so that the lengths of the two first portions 241 in the first direction are compatible with the position of the voltage-resistant gate 232.

[0070] For example, Figure 5 (b) in the figure shows that the parasitic channel layer 240 includes two second portions 242 and a first portion 241. The first portion 241 is arranged between two adjacent second portions 242, so that the two second portions 242 block both sides of the first portion 241, thereby reducing the movement of electrons in the first portion 241 in the first direction, thereby reducing the leakage of the parasitic channel layer 240 in the first direction, and thus reducing the off-state leakage of the HEMT device.

[0071] On this basis, for example, in the first direction, the length of the second portion 242 near the source 231 is smaller than the length of the second portion 242 near the drain 233, thereby increasing the distance between the first portion 241 and the drain 233. This allows the length and position of the first portion 241 to be adapted to the withstand voltage design of the HEMT device, thereby reducing the impact of the high voltage on the drain 233 on the first portion 241.

[0072] For example, Figure 5 (c) in the figure shows that the parasitic channel layer 240 includes a first part 241 and a second part 242, the first part 241 is arranged close to the drain 233, and the second part 242 is arranged close to the source 231, so that the first part 241 can directly supplement electrons to the channel close to the drain 233.

[0073] On this basis, for example, in the first direction, the length of the first portion 241 is greater than the length of the second portion 242 , so that the length design of the first portion 241 is more suitable for the withstand voltage design of the HEMT device.

[0074] For another example, in the first direction, the first portion 241 may be disposed close to the source 231 , and the second portion 242 may be disposed close to the drain 233 .

[0075] Regarding the structure of the parasitic channel layer 240 , the formation structure of the parasitic channel layer 240 is described in detail below in combination with three specific implementation methods.

[0076] Example 1:

[0077] Continue reading Figure 4 The first portion 241 is embedded in the surface of the substrate 210 close to the epitaxial layer 220 , and in the thickness direction of the substrate 210 , a portion of the substrate 210 at the same height as the first portion 241 forms the second portion 242 .

[0078] In this embodiment, on the one hand, ions can be implanted into the substrate 210 to form a first portion 241, so that the first portion 241 is embedded in the substrate 210, and a portion of the substrate 210 at the same height as the first portion 241 forms a second portion 242. In this way, the parasitic channel layer 240 and the side of the substrate 210 facing the epitaxial layer 220 are flush, which facilitates the generation of the epitaxial layer 220 and helps to improve the generation quality of the epitaxial layer 220.

[0079] In some possible designs, the length of the first portion 241 in the first direction is adjusted by adjusting the size of the region for ion implantation on the substrate 210 , so as to facilitate adjusting the length of the second portion 242 in the first direction.

[0080] In some possible designs, in the first direction, the length of the second portion 242 is the same as the length of the gate 232 , so that after the gate 232 and the field plate 234 are integrally provided, the length of the second portion 242 is determined according to the length of the field plate 234 .

[0081] Exemplarily, the epitaxial layer 220 includes a nucleation layer 221 disposed on the first portion 241 and the substrate 210, a buffer layer 222 disposed on the nucleation layer 221, and a barrier layer 223 disposed on the buffer layer 222. The nucleation layer is made of AlN, with a thickness ranging from 5 nm to 10 nm. The buffer layer 222 is made of GaN, with a thickness ranging from 100 nm to 2 μm. The barrier layer 223 is made of materials such as AlGaN, InAlN, AlN, and ScAlN.

[0082] When the first portion is formed by ion implantation, the material of the first portion 241 includes the ion-implanted substrate 210 material, and the ion concentration of the first portion 241 is greater than the ion concentration of the second portion 242. It will be understood that the first portion 241 is implanted with ions of elements such as Si and N, while the second portion 242 is the substrate 210 and is not implanted with ions. This results in the ion concentration of the first portion 241 being greater than the ion concentration of the second portion 242, thereby contributing to the resistivity of the first portion 241 being lower than the resistivity of the second portion 242.

[0083] For example, see Figure 5 and 6 , Figure 6 Schematic diagram of the effect of selective ion implantation on the substrate 210 provided in an embodiment of the present application. Figure 6 The shaded area in (a) indicates the local area selected for ion implantation, and the surrounding blank area indicates the area where ions are not implanted. Figure 6 The shaded portion in (b) illustrates a partial view of the first portion 241 after ion implantation. Before ions are implanted into the selected area of ​​substrate 210, the resistivity of the area on substrate 210 corresponding to first portion 241 is greater than 1e12 ohm.cm. After ion implantation, the resistivity of the area on substrate 210 corresponding to first portion 241 is 1e4 ohm.cm. First portion 241 can be activated to reduce the resistivity of the area on substrate 210 corresponding to first portion 241 to 1e2 ohm.cm, thereby further reducing the resistivity of first portion 241 to less than that of second portion 242.

[0084] For example, please also refer to Figure 4 and Figure 7 , Figure 7 A schematic top view of a first portion 241 and a second portion 242 provided in an embodiment of the present application. Figure 7 (a) shows a structure in which the first portion 241 is embedded in the substrate 210 by ion implantation. Figure 7(b) shows a top view of the HEMT device, from which the distribution areas of the two first portions 241 and the second portion 242 can be seen. The distribution areas of the first portion 241 and the second portion 242 in (b) correspond to the distribution areas of the first portion 241 and the second portion 242 in (a), so that in the first direction, the shorter first portion 241 corresponds to the source 231, the longer first portion 241 corresponds to the drain 233, and the middle second portion 242 corresponds to the gate 232. Therefore, in the thickness direction of the substrate 210, the two first portions 241 correspond to the source 231 and the drain 233, respectively, and the second portion 242 corresponds to the gate 232, so that the second portion 242 blocks the movement of electrons between two adjacent first portions 241, thereby reducing leakage of the parasitic channel layer 240 in the first direction.

[0085] For example, in order to more specifically demonstrate the drain current recovery effect of forming a discontinuous conductive channel between the substrate 210 and the epitaxial layer 220 by selective ion implantation in this embodiment, see Figure 8 , Figure 8 This is a time curve diagram of the drain 233 current recovery after the HEMT device switch provided by the embodiment of the present application is turned off. Figure 8 In (a), (b), and (c), the horizontal axis is time, the vertical axis on one side is current density, and the vertical axis on the other side is the electric potential energy difference. The dotted line is the current square wave, and the solid line is the voltage square wave.

[0086] For example, (a) illustrates the current waveform of a HEMT device without a conductive channel. After the HEMT device is turned off, the drain 233 current is shown as the dashed line in (a). The height of the dashed line after the drain 233 current drops compared to the initial height of the dashed line indicates that the remaining drain 233 current is small and the recovery time is greater than 100 seconds.

[0087] For example, (b) illustrates the current waveform of a HEMT device with a continuous conductive channel. After the HEMT device is turned off, the drain 233 current is shown as the dashed line in (b). The height of the dashed line after the drain 233 current drops compared to the initial height of the dashed line indicates that the continuous conductive channel causes the drain 233 current to drop and remain relatively large after the HEMT device is turned off. However, due to leakage in the continuous conductive channel, the drain 233 current recovery time exceeds 40ms.

[0088] For example, (c) illustrates the current waveform of a HEMT device with a heavily doped, thicker, and more conductive conductive channel. After the HEMT device is turned off, the drain 233 current is shown as the dashed line in (c). The height of the dashed line after the drain 233 current drops compared to the initial height of the dashed line indicates that the discontinuous conductive channel causes the drain 233 current to drop after the HEMT device is turned off, with the remaining amount being greater than the remaining drain 233 current in (a) but less than the remaining drain 233 current in (b), resulting in a drain 233 current recovery time of 24 ms.

[0089] As can be seen from (a), (b), and (c), making the conductive channel more conductive can further shorten the recovery time of the drain 233 current. However, the remaining drain 233 current is reduced. As a result, although the drain 233 current recovers quickly, the off-state leakage of the HEMT device increases, which in turn affects the reliability of the HEMT device.

[0090] For example, in order to solve the contradiction between the drain 233 current recovery time and the off-state leakage, refer to Figure 9 , Figure 9 A graph showing the relationship between the conductive channel and the off-state leakage provided in an embodiment of the present application. Figure 9 In (a) and (b), the horizontal axis represents the gate 232 voltage, the vertical axis represents the drain 233 current, the solid line represents the HEMT device transfer curve, and the dotted line represents the drain 233 voltage curve.

[0091] For example, (a) shows the drain 233 current waveform of a HEMT device with a continuous conductive channel. As can be seen from the solid line in (a), after the HEMT device is turned off, the off-state leakage increases. At this time, the transfer curve of the HEMT device is abnormal, and the off-state leakage increases to the mA level.

[0092] For example, (b) shows the waveform of the drain 233 current of a HEMT device with a discontinuous conductive channel. As can be seen from the elliptical box on the solid line in (b), after the HEMT device is turned off, the off-state leakage is small. At this time, the transfer curve of the HEMT device is normal, and the off-state leakage is reduced to a normal range.

[0093] Example 2:

[0094] The difference between this embodiment and the first embodiment is that the parasitic channel layer 240 is disposed between the substrate 210 and the epitaxial layer 220. Figure 10 , Figure 10This is a schematic diagram of the structure of a HEMT device provided in an embodiment of the present application, in which a parasitic channel layer 240 is located between a substrate 210 and an epitaxial layer 220. The epitaxial layer 220 includes a nucleation layer 221 disposed on the substrate 210, a buffer layer 222 disposed on the nucleation layer 221, and a barrier layer 223 disposed on the buffer layer 222. A first portion 241 is disposed between the nucleation layer 221 and the substrate 210, and a portion of the nucleation layer 221 not covering the first portion 241 forms a second portion 242.

[0095] In this embodiment, the substrate 210 is not processed. Instead, spaced first portions 241 are directly formed on the substrate 210. The region between two adjacent first portions 241 is the surface of the substrate 210 facing the epitaxial layer 220, where the nucleation layer 221 is then formed. This results in a portion of the nucleation layer 221 being formed on the substrate 210, while the remaining portion is formed on the first portion 241. The second portion 242 formed on the substrate 210 by the nucleation layer 221 interrupts the continuity of the adjacent first portions 241 in the first direction, resulting in a discontinuous parasitic channel layer 240 in the first direction, thereby achieving a discontinuous conductive path in the HEMT device. Furthermore, after the first portion 241 forms the first nucleation layer, the nucleation layer 221 (i.e., the second nucleation layer) is formed on the first portion 241. This helps improve the quality of the generated nucleation layer 221 and enhances its insulation properties.

[0096] Exemplarily, the material of the first portion 241 includes the doped material of the nucleation layer 221, and the doping concentration of the first portion 241 is greater than the doping concentration of the second portion 242. It is understood that the material generated by the first portion 241 is the same as the material generated by the nucleation layer 221, but the doping concentration of the first portion 241 is greater than the doping concentration of the nucleation layer 221. The doping concentration can adjust the conductivity of the first portion 241 and the nucleation layer 221. The higher the doping concentration, the better the conductivity. Therefore, the conductivity of the first portion 241 is greater than that of the second portion 242 formed by the nucleation layer 221. This allows the first portion 241 to provide electrons to the epitaxial layer 220 while the second portion 242 can block the movement of electrons between two adjacent first portions 241. This allows the parasitic channel layer 240 to form a discontinuous conductive path, thereby reducing leakage in the parasitic channel layer 240 in the first direction.

[0097] Example 3:

[0098] The difference between this embodiment and the second embodiment is that the parasitic channel layer 240 is disposed between the substrate 210 and the buffer layer 222. Figure 11 , Figure 11This is a schematic diagram of an island-shaped first portion 241 of a parasitic channel layer 240 provided in an embodiment of the present application. The epitaxial layer 220 includes a buffer layer 222 disposed on a substrate 210 and a barrier layer 223 disposed on the buffer layer 222. The first portion 241 is disposed between the buffer layer 222 and the substrate 210, and the portion of the buffer layer 222 not covering the first portion 241 forms the second portion 242.

[0099] In this embodiment, after the first part 241 is generated on the substrate 210, the buffer layer 222 is directly generated, so that the parasitic channel layer 240 having the first part 241 directly serves as a nucleation layer, reducing the steps of generating the nucleation layer, so that the parasitic channel layer 240 can not only supplement electrons to the buffer layer 222, but also serve as a nucleation layer to alleviate lattice mismatch, thereby improving the quality of the generated buffer layer 222.

[0100] For example, the first portion 241 has an island-like structure, which includes a plurality of island-like protrusions arranged along the surface of the substrate 210 near the epitaxial layer 220. The shape of the island-like protrusions can improve the conductivity of the first portion 241 in the first direction and the thickness direction of the substrate 210, so that electrons in the first portion 241 can move faster toward the buffer layer 222 along the thickness direction of the substrate 210, thereby improving the efficiency of the first portion 241 in replenishing electrons to the buffer layer 222.

[0101] For example, the material of the first part 241 may include AlN, AlGaN, etc., and the material of the second part 242 may include GaN, AlGaN, etc., so as to reduce the steps of ion injection and doping, and generate the second part 242 of GaN on the first part 241 of AlN, so as to generate the GaN buffer layer 222 of the second part 242 with better crystal quality and better insulation, which is conducive to the conductivity of the first part 241 being greater than the second part 242 formed by the buffer layer 222.

[0102] For another example, in order to form an island-like structure in the first part 241 generated on the substrate 210, an atomic step corresponding to the first part 241 is provided on the surface of the substrate 210 near the buffer layer 222. The atomic step is formed by performing graphical processing on the substrate 210, so that the first part 241 can generate an island-shaped protrusion in the atomic step, so as to restrict the movement of electrons in the first direction inside the first part 241, reduce the leakage of the parasitic channel layer 240 in the first direction, and facilitate the electrons in the first part 241 to be replenished to the channel through the buffer layer 222.

[0103] Based on the semiconductor device 200 of any of the above embodiments, an embodiment of the present application further provides a method for manufacturing the semiconductor device 200 , which will provide a detailed introduction to the manufacturing of the parasitic channel layer 240 .

[0104] See Figure 4 and Figure 12 , Figure 12 A flowchart of a method for manufacturing a semiconductor device 200 provided in an embodiment of the present application is provided. The method for manufacturing the semiconductor device 200 includes:

[0105] S1. Form a parasitic channel layer 240 on a substrate 210 , wherein the parasitic channel layer 240 includes a first portion 241 and a second portion 242 , the first portion 241 and the second portion 242 are alternately arranged in a first direction, and the resistivity of the first portion 241 is smaller than the resistivity of the second portion 242 .

[0106] In this embodiment, the resistivity of the first portion 241 of the parasitic channel layer 240 formed on the substrate 210 is lower than that of the second portion 242, resulting in better conductivity for the first portion 241. The first portion 241 can carry electrons through the epitaxial layer 220 to replenish the channel, facilitating rapid recovery of the drain current. The second portion 242 has good insulation properties, blocking the movement of electrons in the first direction between two adjacent first portions 241. This reduces the movement of electrons in the first direction within the first portions 241, reduces leakage in the parasitic channel layer 240, and thus reduces the off-state leakage of the semiconductor device 200.

[0107] However Figure 12 There are many ways to execute S1, Figure 13-Figure 17 Take this as an example.

[0108] In some embodiments, see Figure 13 and Figure 14 , Figure 13 A flow chart of a method for manufacturing the parasitic channel layer 240 provided in an embodiment of the present application is provided. Figure 14 A schematic diagram of a formation process of the parasitic channel layer 240 provided in an embodiment of the present application is provided. The method for fabricating the parasitic channel layer 240 includes:

[0109] S11 , performing ion implantation on a first region of the substrate 210 to form a first portion 241 of the parasitic channel layer 240 .

[0110] In this embodiment, the parasitic channel layer 240 is formed by ion implantation into the first region of the substrate 210, wherein elements such as Si and N are implanted. The ion implantation dose is 100-500 keV and the dose is 1e10-1E12 cm -2The depth of the ion implantation region ranges from 50 nm to 1 μm. That is, the height of the first portion 241 on the substrate 210 is 50 nm to 1 μm. This allows for localized ion implantation (N-type, P-type) of the substrate 210 to reduce the resistance of the high-resistivity substrate 210. The resistivity of the region with reduced resistance can be controlled (resistivity > 1e4 ohm.cm) by adjusting the implantation dose and energy.

[0111] S12 , forming a second portion 242 of the parasitic channel layer 240 in a region of the substrate 210 where ion implantation is not performed.

[0112] It can be understood that the area where the resistance value is reduced is the first part 241 of the parasitic channel layer 240, and the uninjected and high-resistivity area on the substrate 210 forms the second part 242, so that the resistivity of the first part 241 is lower than the resistivity of the second part 242, so that the electrons in the first part 241 can be blocked from moving in the first direction through the second part 242, thereby reducing leakage in the parasitic channel layer 240.

[0113] In some other embodiments, see Figure 15 and 16 , Figure 15 A flow chart of another method for manufacturing the parasitic channel layer 240 provided in an embodiment of the present application is shown. Figure 16 Another schematic diagram of a process for forming the parasitic channel layer 240 provided in an embodiment of the present application is provided. The method for forming the parasitic channel layer 240 includes:

[0114] S13 , forming an initial parasitic channel layer 240 by epitaxial growth on the substrate 210 .

[0115] In this embodiment, the resistivity of substrate 210 is greater than 1e5 ohm.cm. A thin layer of AlN, namely, first portion 241, is grown on the surface of substrate 210 facing epitaxial layer 220 using PVD sputtering or MBE. Due to the high conductivity of the grown AlN layer, first portion 241 is electronically conductive. The thickness of first portion 241 on substrate 210 ranges from 2 nm to 100 nm.

[0116] S14 , patterning the initial parasitic channel layer 240 to form first portions 241 spaced apart from each other, with a gap formed between two adjacent first portions 241 .

[0117] In this embodiment, the first portion 241 on the surface of the substrate 210 is patterned by etching or photolithography, so that the first portion 241 is cut off to form two first portions 241, and the two first portions 241 are separated to form a gap to accommodate the second portion 242, so as to block the movement of electrons between the two first portions 241 and reduce the leakage of the parasitic channel layer 240 in the first direction.

[0118] In some other embodiments, see Figure 11 and Figure 17 , Figure 17 A flowchart of another method for manufacturing the parasitic channel layer 240 provided in an embodiment of the present application is provided. The method for manufacturing the parasitic channel layer 240 includes:

[0119] S15 , etching the first region of the substrate 210 to form atomic steps.

[0120] In this embodiment, the first area of ​​the substrate 210 is patterned in advance, and a local photolithography mask is made on the surface of the substrate 210 facing the epitaxial layer 220 to expose a part of the substrate 210. The exposed area can be etched by H2 (hydrogen) to realize atomic steps.

[0121] In some other embodiments, ion implantation into the substrate 210 may be used to damage the atomic steps in the implanted area of ​​the substrate 210 , making it difficult to grow the first portion 241 in the implanted area and easy to grow the first portion 241 in the non-implanted area.

[0122] S16 , forming a first portion of the parasitic channel layer 240 by epitaxial growth on the atomic step.

[0123] In this embodiment, multiple island-shaped protrusions are epitaxially grown on the exposed atomic steps to form the first portion 241. The material of the generated first portion 241 includes AlN, which can serve as the nucleation layer 221. This eliminates the need to grow the original nucleation layer 221, allowing the buffer layer 222 to be formed in a single growth step, thereby reducing the difficulty of growing the buffer layer 222. Due to its unique island structure, the first portion 241, which is an island-shaped protrusion, has better conductivity in the first direction and along the thickness direction of the substrate 210. This allows the first portion 241 to more quickly replenish electrons to the channel through the epitaxial layer 220 along the thickness direction of the substrate 210.

[0124] Please return Figure 4 and Figure 12 , after execution Figure 12 After S1, it also includes:

[0125] S2 . Form an epitaxial layer 220 by epitaxial growth on the parasitic channel layer 240 .

[0126] In this embodiment, by growing the epitaxial layer 220 on the parasitic channel layer 240 , the radio frequency performance of the HEMT device can be improved on the one hand, and on the other hand, the parasitic channel layer 240 can supplement electrons to the source 231 and the drain 233 through the epitaxial layer 220 , thereby increasing the number of electrons between the source 231 and the drain 233 and shortening the recovery time of the drain 233 current.

[0127] However Figure 12 There are many ways to execute S2. Figure 13-Figure 17 For example,

[0128] In some embodiments, for Figure 14 For the growth of epitaxial layer 220, please refer to Figure 13 and Figure 14 , the method for manufacturing the epitaxial layer 220 includes:

[0129] S21 , epitaxially growing an epitaxial layer 220 on the parasitic channel layer 240 , including: sequentially epitaxially growing a nucleation layer 221 , a buffer layer 222 and a barrier layer 223 on a first portion 241 of the parasitic channel layer 240 and the substrate 210 .

[0130] In this embodiment, the first portion 241 and the surface of the substrate 210 facing the epitaxial layer 220 are flush with each other, so that a flat nucleation layer 221 , a buffer layer 222 and a barrier layer 223 are sequentially generated on the first portion 241 and the substrate 210 .

[0131] In some other embodiments, Figure 16 For the growth of epitaxial layer 220, please refer to Figure 15 and Figure 16 , the method for manufacturing the epitaxial layer 220 includes:

[0132] S22 , epitaxially growing an epitaxial layer 220 on the parasitic channel layer 240 , including: epitaxially growing a nucleation layer 221 on a first portion 241 of the parasitic channel layer 240 and the substrate 210 , and forming a second portion 242 of the parasitic channel layer 240 in a portion of the nucleation layer 221 that fills gaps.

[0133] In this embodiment, the epitaxial layer 220 further includes a buffer layer 222 located above the nucleation layer 221 and a barrier layer 223 located above the buffer layer 222. The material of the nucleation layer 221 includes AlN. A portion of the AlN nucleation layer 221 is epitaxially grown on the surface of the substrate 210 in the gap facing the first portion 241, while another portion is epitaxially grown on the side of the first portion 241 facing away from the substrate 210 to cover the first portion 241. Furthermore, the AlN thin film of the first portion 241 forms a first nucleation layer, and the AlN nucleation layer 221 forms a second nucleation layer. The nucleation layer 221 grown on the first portion 241 undergoes secondary epitaxial growth using MOCVD, resulting in higher growth quality and better insulation properties for the AlN nucleation layer 221, which facilitates the epitaxial growth of the buffer layer 222 and the barrier layer 223. During the growth of the AlN nucleation layer 221, the doping concentrations of the AlN films in the AlN nucleation layer 221 and the first portion 241 are different. The doping concentration of the AlN film in the first portion 241 is greater than the doping concentration of the AlN nucleation layer 221, so that the resistivity of the AlN film in the first portion 241 is lower than the resistivity of the AlN nucleation layer 221, so that the movement of electrons in the first portion 241 in the first direction is restricted, thereby reducing the leakage of the parasitic channel layer 240 in the first direction.

[0134] In some other embodiments, Figure 11 For the growth of epitaxial layer 220, please refer to Figure 11 and Figure 17 , the method for manufacturing the epitaxial layer 220 includes:

[0135] S23 , epitaxially growing an epitaxial layer 220 on the parasitic channel layer 240 , including: epitaxially growing a buffer layer 222 on the first portion 241 of the parasitic channel layer 240 and the substrate 210 , wherein the portion of the buffer layer 222 not covering the first portion 241 forms the second portion 242 of the parasitic channel layer 240 .

[0136] In this embodiment, the epitaxial layer 220 further includes a barrier layer 223 located above the buffer layer 222. A portion of the GaN buffer layer 222 is epitaxially grown in the unexposed area of ​​the substrate 210 after the photomask process, and another portion is epitaxially grown on the side of the first portion 241 facing away from the substrate 210 to cover the first portion 241. Figure 4 and Figure 12 , after execution Figure 12 After S2, it also includes:

[0137] S3 . Form an electrode layer 230 on the epitaxial layer 220 . The electrode layer 230 includes a source electrode 231 and a drain electrode 233 . The source electrode 231 and the drain electrode 233 are arranged at intervals along the first direction.

[0138] In this embodiment, metallization, etching and deposition processes are used on the side of the generated barrier layer 223 facing away from the substrate 210 to produce a source 231, a gate 232, a drain 233, a field plate 234 and a dielectric layer 235, so that the gate 232 and the field plate 234 are integrally arranged, and the source 231, the gate 232 and the drain 233 are arranged at intervals along the first direction, wherein the dielectric layer 235 material includes SiN, SiO2 and HfO2 and other materials.

[0139] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; The parasitic channel layer and the epitaxial layer are sequentially arranged on the substrate along the thickness direction of the substrate and in a direction away from the substrate; an electrode layer, disposed on a side of the epitaxial layer away from the substrate, the electrode layer comprising a source electrode and a drain electrode, the source electrode and the drain electrode being arranged at intervals along a first direction; The parasitic channel layer includes a first portion and a second portion, the first portion and the second portion are alternately arranged in the first direction, and the resistivity of the first portion is smaller than the resistivity of the second portion.

2. The semiconductor device according to claim 1, wherein The first portion is embedded in a surface of the substrate close to the epitaxial layer, and in a thickness direction of the substrate, a portion of the substrate at the same height as the first portion forms the second portion.

3. The semiconductor device according to claim 2, wherein The material of the first portion includes ion-implanted substrate material, and the ion concentration of the first portion is greater than the ion concentration of the second portion.

4. The semiconductor device according to claim 1, wherein The epitaxial layer includes a nucleation layer disposed on the substrate, the first portion is disposed between the nucleation layer and the substrate, and a portion of the nucleation layer that does not cover the first portion forms the second portion.

5. The semiconductor device according to claim 4, wherein The material of the first portion includes a doped nucleation layer material, and the doping concentration of the first portion is greater than the doping concentration of the second portion. The semiconductor device according to claim 1 , wherein: The epitaxial layer includes a buffer layer disposed on the substrate, the first portion is disposed between the buffer layer and the substrate, and a portion of the buffer layer that does not cover the first portion forms the second portion.

7. The semiconductor device according to claim 6, wherein: The first portion has an island structure, and the island structure includes a plurality of island protrusions arranged along a surface of the substrate close to the epitaxial layer.

8. The semiconductor device according to claim 6 or 7, characterized in that The material of the first portion includes AlN and AlGaN, and the material of the second portion includes GaN and AlGaN.

9. The semiconductor device according to any one of claims 6 to 8, characterized in that: An atomic step corresponding to the first portion is provided on a surface of the substrate close to the buffer layer.

10. The semiconductor device according to any one of claims 1 to 9, wherein: The parasitic channel layer includes two first portions, and the second portion is disposed between two adjacent first portions.

11. The semiconductor device according to claim 10, wherein: In the first direction, a length of the first portion close to the source is smaller than a length of the first portion close to the drain.

12. The semiconductor device according to claim 10 or 11, characterized in that The electrode layer further comprises a gate disposed on a side of the epitaxial layer away from the substrate, wherein the gate is located between the source and the drain; Along the thickness direction of the substrate, the gate overlaps with the second portion, and the source and the drain overlap with two first portions respectively.

13. The semiconductor device according to any one of claims 1 to 12, wherein: In the first direction, the length of the second portion is smaller than the length of the first portion.

14. A method for manufacturing a semiconductor device, characterized in that: include: forming a parasitic channel layer on the substrate; epitaxially growing an epitaxial layer on the parasitic channel layer; forming an electrode layer on the epitaxial layer, wherein the electrode layer comprises a source electrode and a drain electrode, and the source electrode and the drain electrode are arranged at intervals along a first direction; The parasitic channel layer includes a first portion and a second portion, the first portion and the second portion are alternately arranged in the first direction, and the resistivity of the first portion is smaller than the resistivity of the second portion.

15. The method for manufacturing a semiconductor device according to claim 14, wherein: The forming of a parasitic channel layer on the substrate comprises: Performing ion implantation on a first region of the substrate to form a first portion of the parasitic channel layer; The area of ​​the substrate where ion implantation is not performed forms the second part of the parasitic channel layer; The epitaxial growth on the parasitic channel layer to form an epitaxial layer comprises: sequentially epitaxially growing a nucleation layer, a buffer layer and a barrier layer on the first portion of the parasitic channel layer and the substrate.

16. The method for manufacturing a semiconductor device according to claim 14, wherein: The forming of a parasitic channel layer on the substrate comprises: forming an initial parasitic channel layer by epitaxial growth on the substrate; patterning the initial parasitic channel layer to form first portions spaced apart from each other, with a gap formed between two adjacent first portions; The epitaxial growth on the parasitic channel layer to form an epitaxial layer includes: epitaxial growth on the first part of the parasitic channel layer and the substrate to form a nucleation layer, wherein the portion of the nucleation layer that fills the gap forms the second part of the parasitic channel layer.

17. The method for manufacturing a semiconductor device according to claim 14, wherein: The forming of a parasitic channel layer on the substrate comprises: Etching a first region of the substrate to form an atomic step; forming a first portion of the parasitic channel layer by epitaxial growth on the atomic step; The epitaxial growth on the parasitic channel layer forms an epitaxial layer, comprising: epitaxially growing a buffer layer on a first portion of the parasitic channel layer and a substrate, wherein a portion of the buffer layer not covering the first portion forms a second portion of the parasitic channel layer.

18. An electronic device, characterized in that: The invention comprises a circuit board and a semiconductor device according to any one of claims 1 to 13, wherein the semiconductor device is arranged on the circuit board.

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