Voltage stabilizing structure of load in chip, chip and manufacturing method of voltage stabilizing structure

Abstract

The embodiment of the invention provides a voltage stabilization structure of a load in a chip, the chip and a manufacturing method of the voltage stabilization structure, and relates to the technical field of semiconductor chip design, the voltage stabilization structure of the load in the chip comprises a substrate layer which comprises a redundant grid electrode, a redundant active region and a substrate, the redundant grid electrode and the substrate form a redundant MOS tube, and the redundant active region is arranged on the substrate; therefore, the capacitance value of the redundant MOS tube is provided. The redundant active region and the substrate form a PN junction so as to provide a PN junction capacitance value; wherein the redundant MOS tube and the PN junction are connected in parallel with a power supply network of a load of the chip. According to the embodiment of the invention, the problem that the voltage at the two ends of the load of the chip is unstable in the related technology is solved.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of semiconductor chip design, and more specifically, to a voltage stabilizing structure for a load within a chip, a chip, and a method for manufacturing the voltage stabilizing structure. Background Art

[0002] With the rapid development of the internet and AI technologies, and the expansion of data centers, demand for high-performance computing products is growing. Driven by the market, chip clock frequencies are constantly increasing. Advances in manufacturing technology are also driving the integration of individual chips and lowering standard supply voltages.

[0003] This poses a significant challenge to the reliability of the physical design of power integrity in the back-end of integrated circuits, especially in high-speed, large-scale chips. Power integrity primarily refers to the voltage drop (IR drop) and electromigration (EM) issues that exist in the power supply network of the chip's underlying standard cells. This can lead to unstable voltages across the chip's loads. This drop in supply voltage can seriously affect the operating state of the chip's loads. Summary of the Invention

[0004] The embodiments of the present application provide a voltage stabilizing structure for a load within a chip, a chip, and a method for manufacturing the voltage stabilizing structure, so as to at least solve the problem of unstable voltage across the load of the chip in the related art.

[0005] According to one embodiment of the present application, a structure for enhancing power integrity is provided, comprising: a substrate layer including a redundant gate, a redundant active area, and a substrate, wherein the redundant gate and the substrate form a redundant MOS transistor to provide a redundant MOS transistor capacitance value; the redundant active area and the substrate form a PN junction to provide a PN junction capacitance value; wherein the redundant MOS transistor and the PN junction are connected in parallel with the power supply network of the chip load.

[0006] According to another embodiment of the present application, a chip is provided, comprising a power supply, a load, and a voltage stabilizing structure as described in any one of the above items, wherein the voltage stabilizing structure is connected in parallel between the power supply and the load.

[0007] According to another embodiment of the present application, a method for manufacturing a voltage-stabilizing structure for an on-chip load is provided, comprising: obtaining a source file, wherein the source file is a file of the voltage-stabilizing structure after layout and routing; adding redundant graphics to the source file, wherein the redundant graphics include: a redundant metal graphic, a redundant gate graphic, and a redundant active area graphic; determining a metal layer based on the redundant metal graphic, determining a first redundant metal and a second redundant metal based on the metal layer, so that the polarity of the first redundant metal and the second redundant metal are opposite to each other, to obtain a line capacitance, to provide a line capacitance value; determining a base layer based on a base of the source file, forming a redundant MOS transistor based on the redundant gate graphic and the base, to provide a redundant MOS capacitance value; forming a PN junction based on the redundant active area graphic and the base, to provide a PN junction capacitance value; connecting the line capacitance, the redundant MOS transistor, the PN junction, and a power supply network of the chip load in parallel to obtain a corresponding layout file, to obtain the voltage-stabilizing structure based on the layout file.

[0008] In the embodiments of the present application, redundant oxide filling provided on the substrate is utilized as a redundant gate and redundant active area, and the redundant gate and substrate are used to form a redundant MOS transistor. The redundant active area and substrate are used to form a PN junction. The redundant MOS transistor and PN junction are connected in parallel to the power supply network of the chip's load, so that the power supply network of the chip's load is incorporated into an additional capacitor structure. Therefore, the voltage drop generated during the power supply network supplying power to the chip's load can be mitigated by the capacitor structure composed of the redundant MOS transistor and PN junction, thereby achieving voltage stabilization for the chip's load. Secondly, the embodiments of the present application utilize redundant oxide filling of the substrate to obtain redundant MOS transistors and PN junctions, fully utilizing existing structures and achieving cost savings. Finally, because the capacitor structure composed of the redundant MOS transistor and PN junction is an energy storage element, when the chip is powered on, the power supply network is used to charge and store energy in the capacitor structure composed of the redundant MOS transistor and PN junction. When the chip is operating, the capacitor structure composed of the redundant MOS transistor and PN junction can provide current to the standard cell through the power supply network, reducing the current originally required to be provided by the power supply network, thereby reducing the voltage drop on the network and improving the stability of the power supply network. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 Schematic diagram of a capacitor structure composed of a line capacitor, a redundant MOS transistor, and a PN junction according to an embodiment of the present application;

[0010] Figure 2 Schematic diagram of a line capacitor, a redundant MOS transistor, and a PN junction incorporated into a power supply network according to an embodiment of the present application;

[0011] Figure 31 is a flow chart of a method for manufacturing a voltage stabilizing structure of an on-chip load according to an embodiment of the present application;

[0012] Figure 4 is a flow chart of a method for setting a first redundant metal and a second redundant metal based on the hierarchy of a first reference layer to obtain line capacitance according to an embodiment of the present application;

[0013] Figure 5 is a flow chart of a method for obtaining line capacitance by combining a redundant pattern of a first reference layer with a second reference layer according to an embodiment of the present application;

[0014] Figure 6 is a flow chart of a method for obtaining line capacitance based on a redundant pattern of a first reference layer and a polarity network of a second reference layer according to an embodiment of the present application;

[0015] Figure 7 is a flow chart of a method for obtaining line capacitance based on redundant patterns of a first reference layer and a second reference layer according to an embodiment of the present application;

[0016] Figure 8 is a flow chart of a method for obtaining line capacitance based on a redundant pattern of a first reference layer and a polarity network of a second reference layer according to an embodiment of the present application;

[0017] Figure 9 This is a flow chart of a method for connecting a redundant MOS transistor in parallel with a power supply network of a chip load according to an embodiment of the present application;

[0018] Figure 10 It is a hardware structure block diagram of a computer terminal according to the method for manufacturing a voltage stabilizing structure for running an on-chip load according to an embodiment of the present application.

[0019] Explanation of the accompanying drawings: 1. First redundant metal layer; 2. Second redundant metal layer; 3. First redundant metal; 4. Second redundant metal; 5. Redundant gate; 6. Redundant active area; 7. Substrate. DETAILED DESCRIPTION

[0020] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0021] It should be noted that the terms "first", "second", etc. in the description and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0022] In this embodiment, a voltage stabilization structure for a chip load is provided. Figure 1 Schematic diagram of a capacitor structure composed of a line capacitor, a redundant MOS transistor, and a PN junction according to an embodiment of the present application. Figure 2Schematic diagram of the line capacitor, redundant MOS tube, and PN junction incorporated into the power supply network according to an embodiment of the present application. Figure 1 and Figure 2 As shown, the voltage stabilizing structure includes:

[0023] The substrate layer includes a redundant gate 5, a redundant active region 6, and a substrate 7. The redundant gate 5 and the substrate 7 form a redundant MOS transistor to provide a redundant MOS transistor capacitance value; the redundant active region 6 and the substrate 7 form a PN junction to provide a PN junction capacitance value;

[0024] The redundant MOS tube, the PN junction and the power supply network of the chip load are connected in parallel.

[0025] In an exemplary embodiment, the redundant gate 5 and the redundant active area 6 are both redundant oxide fills of the substrate 7 to increase the density of the substrate 7. The redundant gate 5 and the redundant active area 6 are connected to the VDD / VSS of the power supply network, and the substrate 7 is connected to the VSS / VDD of the power supply network. That is, the redundant gate 5 and the redundant active area 6 have the same polarity, which is opposite to the polarity of the substrate 7.

[0026] Through the embodiment of the present application, the redundant oxide filling provided on the substrate 7 is used as a redundant gate 5 and a redundant active area 6, and the redundant gate 5 and the substrate 7 are used to form a redundant MOS transistor, and the redundant active area 6 and the substrate 7 are used to form a PN junction. The redundant MOS transistor and the PN junction are connected in parallel with the power supply network of the chip load, so that the power supply network of the chip load is incorporated into an additional capacitor structure. Therefore, the voltage drop generated in the process of the power supply network supplying power to the chip load can be provided by the capacitor structure composed of the redundant MOS transistor and the PN junction, thereby achieving the effect of stabilizing the voltage of the chip load. Secondly, the embodiment of the present application utilizes the redundant oxide filling of the substrate 7 to obtain the redundant MOS transistor and the PN junction, making full use of the existing structure and achieving the effect of cost saving. Finally, since the capacitor structure composed of the redundant MOS transistor and the PN junction is an energy storage element, when the chip is powered on, the power supply network is used to charge and store energy for the capacitor structure composed of the redundant MOS transistor and the PN junction. When the chip is working, the capacitor structure composed of the redundant MOS transistor and the PN junction can provide current to the standard unit through the power supply network, reducing the current originally required to be provided by the power supply network, thereby reducing the voltage drop on the network to improve the stability of the power supply network.

[0027] In one embodiment, the voltage stabilizing structure further includes:

[0028] A redundant metal layer, comprising a first redundant metal 3 and a second redundant metal 4, wherein the polarities of the first redundant metal 3 and the second redundant metal 4 are opposite to each other, so as to obtain a line capacitance and provide a line capacitance value;

[0029] The line capacitor, the redundant MOS tube, the PN junction and the power supply network of the chip load are connected in parallel.

[0030] In an exemplary embodiment, the first redundant metal 3 and the second redundant metal 4 are both redundant metals used to fill metal within the chip to increase metal density. For example, the metal can be a pad, which serves as a metal area within the chip for connecting the chip to external circuits. The first redundant metal 3 can be connected to the VDD / VSS of the power supply network, and the second redundant metal 4 can be connected to the VSS / VDD of the power supply network. That is, the polarity of the first redundant metal 3 and the second redundant metal 4 are opposite.

[0031] In an exemplary embodiment, Figure 2 As shown in the circuit diagram of the line capacitor, redundant MOS tube, and PN junction incorporated into the power supply network, this circuit diagram is a package-level circuit diagram, mainly composed of the package equivalent resistance, equivalent inductance, equivalent capacitance, as well as the equivalent resistance, equivalent capacitance, decoupling capacitance, and load in the chip. It is a multi-inductor and capacitor parallel model. 电源地 is the parasitic capacitance of the power ground network, C dummy is the capacitance added to the voltage stabilizing structure. net The line capacitance formed by the first redundant metal 3 and the second redundant metal 4, C mos The redundant gate 5 and the substrate 7 form a redundant MOS tube, C pn It is a PN junction formed by the redundant active area 6 and the substrate 7. The line capacitor, redundant MOS tube, and PN junction are connected in parallel to the power supply network to form C dummy Then the C dummy It can ensure that the voltage change across the load will not be too large at a local location, reducing the voltage drop phenomenon. From the perspective of the power ground network, the added capacitance can move the self-resonance point of the RC oscillation circuit to a low frequency, change the anti-resonance point, and greatly reduce the voltage drop caused by the RLC resonance of the package and chip.

[0032] Through the embodiment of the present application, firstly, due to the use of the redundant metal (first redundant metal 3, second redundant metal 4) filled with metal in the chip, and the first redundant metal 3 and the second redundant metal 4 are made into line capacitors. Secondly, due to the use of the redundant oxide filled on the substrate 7 as the redundant gate 5, the redundant active area 6, and the redundant gate 5 and the substrate 7 are used to form a redundant MOS tube, and the redundant active area 6 and the substrate 7 are used to form a PN junction, the line capacitor, the redundant MOS tube, the PN junction and the power supply network of the chip load are connected in parallel, so that the power supply network of the chip load is incorporated into the additional capacitor structure. Therefore, the voltage drop generated in the process of the power supply network supplying power to the chip load can be provided by the capacitor structure composed of the line capacitor, the redundant MOS tube, and the PN junction to achieve the effect of stabilizing the voltage of the chip load. Moreover, the embodiment of the present application utilizes the redundant metal (first redundant metal 3, second redundant metal 4) filled with metal in the chip to obtain line capacitors, and utilizes the redundant oxide filling of the substrate 7 to obtain redundant MOS tubes and PN junctions, making full use of the existing structure and achieving the effect of cost saving. Finally, because the capacitor structure composed of the line capacitor, redundant MOS transistor, and PN junction is an energy storage element, when the chip is powered on, the power network charges and stores energy in this capacitor structure. When the chip is operating, this capacitor structure, composed of the redundant MOS transistor, PN junction, and line capacitor, can provide current to the standard cells through the power network, reducing the current originally required from the power network and thereby reducing the voltage drop across the network, thereby improving the stability of the power network.

[0033] In one embodiment, the redundant gate 5 is connected to the positive terminal or the negative terminal of the power network, and the substrate 7 is connected to the negative terminal or the positive terminal of the power network, so that the polarities of the redundant gate 5 and the substrate 7 are opposite.

[0034] In an exemplary embodiment, the redundant gate 5 is connected to the positive terminal (VDD) of the power supply network, and the substrate 7 is connected to the negative terminal (VSS) of the power supply network, so that the redundant MOS transistor formed by the redundant gate 5 and the substrate 7 is connected in parallel with the power supply network of the chip load. Alternatively, the redundant gate 5 is connected to the negative terminal (VSS) of the power supply network, and the substrate 7 is connected to the positive terminal (VDD) of the power supply network, so that the redundant MOS transistor formed by the redundant gate 5 and the substrate 7 is connected in parallel with the power supply network of the chip load.

[0035] In one embodiment, the redundant gate 5 is connected to the redundant active region 6 , so that the redundant gate 5 and the substrate 7 form a redundant MOS transistor connected in parallel to the power supply network through the redundant active region 6 .

[0036] In an exemplary embodiment, in addition to connecting the redundant gate 5 to the positive or negative terminal of the power supply network and the substrate 7 to the negative terminal (VSS) or positive terminal (VDD) of the power supply network so that the polarity of the redundant gate 5 and the substrate 7 are opposite, and the redundant MOS transistor formed by the redundant gate 5 and the substrate 7 is connected in parallel with the power supply network of the chip load, it is also possible to first connect the PN junction in parallel with the power supply network of the chip load. For example, the redundant active area 6 of the PN junction is connected to the positive terminal (VDD) of the power supply network, the substrate 7 is connected to the negative terminal (VSS) of the power supply network, and the PN junction is connected in parallel with the power supply network of the chip load. The redundant gate 5 is then connected to the redundant active area 6 so that the redundant gate 5 and the substrate 7 form a redundant MOS transistor that is connected in parallel with the power supply network via the redundant active area 6. Alternatively, the redundant active area 6 of the PN junction is connected to the negative terminal (VSS) of the power supply network, the substrate 7 is connected to the positive terminal (VDD) of the power supply network, the PN junction is connected in parallel to the power supply network of the chip load, and the redundant gate 5 is connected to the redundant active area 6, so that the redundant gate 5 and the substrate 7 form a redundant MOS transistor connected in parallel to the power supply network through the redundant active area 6.

[0037] In one embodiment, the redundant metal layer includes a first redundant metal layer 1 , and the first redundant metal 3 and the second redundant metal 4 are located in the first redundant metal layer 1 .

[0038] In one embodiment, the redundant metal layer further includes a second redundant metal layer 2, and the first redundant metal 3 and the second redundant metal 4 are located on an adjacent side of the second redundant metal layer 2, wherein the first redundant metal 3 and the second redundant metal layer 2 have an overlapping surface and are connected by a through hole so that the polarity of the first redundant metal 3 and the second redundant metal layer 2 are the same.

[0039] In an exemplary embodiment, in multi-level interconnect technology, the lower-level metal is typically located at the lower portion of the chip, close to the transistor layer, while the upper-level metal is located at the upper portion of the chip, closer to the chip surface. Accordingly, the lower-level metal is located in a lower-level metal layer, and the upper-level metal is located in a higher-level metal layer. Therefore, because the lower-level metal is covered within the upper-level metal, the upper-level metal can be directly connected to the positive / negative terminals of the power network, while the lower-level metal is connected to the positive / negative terminals of the power network through vias and metal conductors.

[0040] Similarly, redundant metal layers are also divided into upper-level redundant metal layers (first redundant metal layer 1) and lower-level redundant metal layers (second redundant metal layer 2). The upper-level redundant metal layer and the upper-level metal layer are located on the same layer, while the lower-level redundant metal layer and the lower-level metal layer are located on the same layer. When the first redundant metal 3 and the second redundant metal 4 need to be located in the upper-level redundant metal layer, the internal structure of the first redundant metal layer 1 (the upper-level redundant metal layer) can be directly utilized as the first redundant metal 3 and the second redundant metal 4. Based on the connection relationship between the first redundant metal layer 1 (the upper-level redundant metal layer) and the power network, the first redundant metal 3 and the second redundant metal 4 can be connected to the power network. Separate wiring is not required, and there is no need to connect the first redundant metal 3 and the second redundant metal 4 to the power network via wires. Furthermore, when the first redundant metal 3 and the second redundant metal 4 are located near the second redundant metal layer 2 (the lower-level redundant metal layer), the redundant metal on the adjacent side of the lower-level redundant metal layer can be used as the first redundant metal 3 and the second redundant metal 4. The first redundant metal 3 and the second redundant metal 4 are connected to the lower redundant metal layer, so that the lower redundant metal layer is connected to the power network through vias and metal wires. In short, the existing structure in the chip can be fully utilized to reduce costs.

[0041] In one embodiment, multiple groups of the first redundant metal 3 and the second redundant metal 4 are provided to obtain multiple groups of line capacitors, wherein the multiple groups of line capacitors are connected in parallel.

[0042] In an exemplary embodiment, Figure 1 As shown, the first redundant metal 3 and the second redundant metal 4 are located in a middle layer between two lower metal layers (the second redundant metal layer 2). Within this middle layer, the first redundant metal 3 and the second redundant metal 4 are arranged in pairs to form a line capacitor. Multiple pairs of the first redundant metal 3 and the second redundant metal 4 can be arranged within this middle layer to form multiple line capacitors. Multiple line capacitors are connected in parallel to form one or more equivalent capacitors, where the capacitance of each equivalent capacitor is the sum of the capacitances of the multiple parallel line capacitors.

[0043] Furthermore, in an exemplary embodiment, the line capacitance, redundant MOS tube, PN junction and the power supply network of the chip load are connected in parallel, and the sum of all capacitance values ​​can be obtained. The expression of the sum of the capacitance values ​​is: Wherein, ε is the dielectric constant; l is the length of the redundant metal (for example, the first redundant metal 3 and the second redundant metal 4); d is the width of the redundant metal; k is the electrostatic force constant; s is the spacing of the redundant metal; W is the width of the poly (redundant gate 5); L is the channel length; Cox is the gate oxide capacitance per unit area; A is the P / N junction area; Cj is the junction capacitance per unit area, and n is an integer greater than or equal to 1.

[0044] This embodiment further provides a chip, comprising a power supply, a load, and a voltage stabilizing structure as described in any one of the above items, wherein the voltage stabilizing structure is connected in parallel between the power supply and the load.

[0045] This embodiment also provides a method for manufacturing a voltage stabilizing structure of an on-chip load. Figure 3 FIG. 1 is a flow chart of a method for manufacturing a voltage stabilizing structure of a chip load according to an embodiment of the present application. Figure 3 As shown, the process includes the following steps:

[0046] Step S301, obtaining a source file, wherein the source file is a file of the voltage stabilizing structure after layout and routing;

[0047] In an exemplary embodiment, the source file includes a physical design database file or a layout file of the chip.

[0048] Step S302, adding redundant graphics to the source file, wherein the redundant graphics include: redundant metal graphics, redundant gate 5 graphics, and redundant active area 6 graphics;

[0049] In an exemplary embodiment, the redundant pattern may be one or more of a square, a strip, and a T-shape.

[0050] Step S303 , determining a metal layer based on the redundant metal pattern, determining a first redundant metal 3 and a second redundant metal 4 based on the metal layer, and making the polarity of the first redundant metal 3 and the second redundant metal 4 opposite to obtain a line capacitance, thereby providing a line capacitance value;

[0051] Step S304: Determine a substrate layer based on the substrate 7 of the source file, form a redundant MOS transistor based on the pattern of the redundant gate 5 and the substrate 7 to provide a redundant MOS capacitance value; and form a PN junction based on the pattern of the redundant active region 6 and the substrate 7 to provide a PN junction capacitance value.

[0052] Step S305 : connecting the line capacitor, the redundant MOS tube, the PN junction and the power supply network of the chip load in parallel to obtain a corresponding layout file, and obtaining a voltage stabilization structure based on the layout file.

[0053] Through the above steps S301 to S305, the embodiment of the present application adds redundant graphics such as redundant metal, redundant gate 5 and redundant active area 6 to construct voltage-stabilizing structural components such as line capacitors, redundant MOS tubes and PN junctions based on the redundant graphics. These voltage-stabilizing structural components are connected in parallel with the power supply network of the chip's load, which can effectively provide a stable voltage to the chip's load, thereby solving the problem of unstable voltage at both ends of the chip load. By optimizing the design and layout of the voltage-stabilizing structure, problems such as voltage drop and electromigration can be effectively reduced, thereby improving the operating stability and reliability of the chip. Therefore, the embodiment of the present application has significant advantages in solving the problem of unstable voltage at both ends of the chip's load.

[0054] Figure 4 is a flow chart of a method for obtaining line capacitance by setting a first redundant metal and a second redundant metal based on the hierarchy of a first reference layer according to an embodiment of the present application. In one embodiment, as Figure 4 As shown, a metal layer is determined based on a pattern of a redundant metal, a first redundant metal 3 and a second redundant metal 4 are determined based on the metal layer, and the polarities of the first redundant metal 3 and the second redundant metal 4 are made opposite to each other to obtain a line capacitance, thereby providing a line capacitance value, including:

[0055] Step S401, confirming a first reference layer based on a pattern of redundant metal;

[0056] Step S402, identifying the hierarchy of the first reference layer;

[0057] Step S403 : Disposing a first redundant metal 3 and a second redundant metal 4 based on the hierarchy of the first reference layer, wherein the first redundant metal 3 and the second redundant metal 4 have opposite polarities to obtain line capacitance, thereby providing a line capacitance value.

[0058] Through steps S401 to S403, the metal layer is determined based on the pattern of the redundant metal, and the polarity of the first redundant metal 3 and the second redundant metal 4 is determined to be opposite, thereby obtaining the line capacitance and providing the line capacitance value. Such a design can effectively increase the line capacitance of the voltage stabilizing structure of the on-chip load, thereby improving the stability and reliability of the voltage stabilizing structure. At the same time, by setting based on the metal layer, the impact of the line capacitance can be reduced, and the performance and working efficiency of the chip can be improved. Therefore, this technical effect can improve the performance and reliability of the voltage stabilizing structure of the on-chip load.

[0059] In one embodiment, a first redundant metal 3 and a second redundant metal 4 are provided based on the hierarchy of the first reference layer, wherein the polarities of the first redundant metal 3 and the second redundant metal 4 are opposite to each other, so as to obtain a line capacitance and provide a line capacitance value, including:

[0060] When the first reference layer is the first redundant metal layer 1 , a first redundant metal 3 and a second redundant metal 4 are disposed in the first reference layer, wherein the first redundant metal 3 and the second redundant metal 4 have opposite polarities to obtain line capacitance and provide a line capacitance value.

[0061] Figure 5 is a flow chart of a method for obtaining line capacitance by combining a redundant pattern of a first reference layer with a second reference layer according to an embodiment of the present application. In one embodiment, Figure 5 As shown, a first redundant metal 3 and a second redundant metal 4 are set based on the hierarchy of the first reference layer, wherein the polarity of the first redundant metal 3 is opposite to that of the second redundant metal 4 to obtain a line capacitance to provide a line capacitance value, including:

[0062] Step S501 , when the first reference layer is the first redundant metal layer 1 , a first redundant metal 3 and a second redundant metal 4 are provided in the first reference layer;

[0063] In step S502, an AND operation is performed on the redundant pattern of the first reference layer and the second reference layer. When the AND result of the first redundant metal 3 of the first reference layer and the second reference layer is not empty, the first redundant metal 3 of the first reference layer and the second reference layer are assigned the same polarity, so that the polarity of the first redundant metal 3 and the second redundant metal 4 are opposite to obtain a line capacitance to provide a line capacitance value, wherein the second reference layer is an adjacent layer having an overlapping surface with the first reference layer.

[0064] In summary, in step S501 to step S502, by setting the first redundant metal 3 and the second redundant metal 4 in the first reference layer and performing the AND operation on the redundant pattern of the first reference layer and the second reference layer, the following technical effects can be achieved: Providing line capacitance value: By setting the first redundant metal 3 and the second redundant metal 4 and determining that their polarities are opposite, line capacitance can be effectively generated, thereby providing the line capacitance value required for the voltage stabilizing structure. Simplifying the manufacturing process: By setting redundant metals in the first reference layer and the second reference layer and performing the AND operation, the manufacturing process of the voltage stabilizing structure can be simplified without changing the original layout and wiring, thereby improving manufacturing efficiency. Improving the performance of the voltage stabilizing structure: By reasonably designing the polarity of the first redundant metal 3 and the second redundant metal 4, the influence of the line capacitance on the power supply network of the load can be effectively reduced, thereby improving the performance and stability of the voltage stabilizing structure.

[0065] Figure 6 is a flow chart of a method for obtaining line capacitance based on a redundant pattern of a first reference layer and a polarity network of a second reference layer according to an embodiment of the present application. In one embodiment, Figure 6As shown, a first redundant metal 3 and a second redundant metal 4 are set based on the hierarchy of the first reference layer, wherein the polarity of the first redundant metal 3 is opposite to that of the second redundant metal 4 to obtain a line capacitance to provide a line capacitance value, including:

[0066] Step S601 , when the first reference layer is the first redundant metal layer 1 , a first redundant metal 3 and a second redundant metal 4 are provided in the first reference layer;

[0067] In step S602, an AND operation is performed on the redundant pattern of the first reference layer and the polarity network of the second reference layer. When the AND result of the redundant pattern of the first reference layer and the polarity network of the second reference layer is not empty, the first redundant metal 3 of the first reference layer and the polarity network are assigned the same polarity, so that the polarity of the first redundant metal 3 and the second redundant metal 4 are opposite to obtain a line capacitance to provide a line capacitance value, wherein the second reference layer is an adjacent layer having an overlapping surface with the first reference layer.

[0068] In summary, steps S601 to S602 provide line capacitance by disposing first redundant metal 3 and second redundant metal 4 within the first reference layer and performing an AND operation on the redundant pattern of the first reference layer and the polarity network of the second reference layer, so that the polarity of the first redundant metal 3 and the second redundant metal 4 are opposite, thereby obtaining a line capacitance value. This design can effectively increase the value of the line capacitance and improve the stability and reliability of the voltage stabilization structure. Furthermore, the AND operation can realize more complex circuit designs in the voltage stabilization structure of the chip load, improving the flexibility of chip performance and functionality.

[0069] Figure 7 is a flow chart of a method for obtaining line capacitance based on redundant patterns of a first reference layer and a second reference layer according to an embodiment of the present application. In one embodiment, Figure 7 As shown, a first redundant metal 3 and a second redundant metal 4 are set based on the hierarchy of the first reference layer, wherein the polarity of the first redundant metal 3 is opposite to that of the second redundant metal 4 to obtain a line capacitance to provide a line capacitance value, including:

[0070] Step S701, when the first reference layer is a second redundant metal layer 2, a first redundant metal 3 and a second redundant metal 4 are provided in the second reference layer, wherein the second reference layer is an adjacent layer having an overlapping surface with the first reference layer;

[0071] In step S702, the redundant patterns of the first reference layer and the second reference layer are ANDed. When the results of the first redundant metal 3 of the first reference layer and the second reference layer are not empty, the first redundant metal 3 of the first reference layer and the second reference layer are assigned the same polarity, so that the polarity of the first redundant metal 3 and the second redundant metal 4 are opposite to obtain the line capacitance to provide the line capacitance value.

[0072] In summary, steps S701 and S702 implement the arrangement of redundant metal within the first and second reference layers, and through logical operations, reverse the polarity of the first redundant metal 3 and the second redundant metal 4 to obtain line capacitance and provide a line capacitance value. This method effectively increases the line capacitance of the voltage stabilization structure of the chip's internal load, thereby improving voltage stabilization and performance. By increasing the line capacitance value, fluctuations in the chip's internal load can be reduced, improving stability and reliability, while also reducing power supply noise and improving the chip's anti-interference capabilities and operating efficiency.

[0073] Figure 8 is a flow chart of a method for obtaining line capacitance based on a redundant pattern of a first reference layer and a polarity network of a second reference layer according to an embodiment of the present application. In one embodiment, Figure 8 As shown, a first redundant metal 3 and a second redundant metal 4 are set based on the hierarchy of the first reference layer, wherein the polarity of the first redundant metal 3 is opposite to that of the second redundant metal 4 to obtain a line capacitance to provide a line capacitance value, including:

[0074] Step S801, when the first reference layer is the second redundant metal layer 2, a first redundant metal 3 and a second redundant metal 4 are provided in the first reference layer, wherein the second reference layer is an adjacent layer having an overlapping surface with the first reference layer;

[0075] In step S802, the redundant pattern of the first reference layer is ANDed with the polarity network of the second reference layer. When the result of the first redundant metal 3 of the first reference layer and the polarity network of the second reference layer is not empty, the first redundant metal 3 is assigned to the same polarity as the polarity network, so that the polarity of the first redundant metal 3 and the second redundant metal 4 are opposite to obtain the line capacitance to provide the line capacitance value.

[0076] In summary, steps S801 to S802 achieve the goal of matching the polarity network of the first redundant metal 3 with the second reference layer through an AND operation, when the first reference layer is the second redundant metal layer 2. The first redundant metal 3 is assigned the same polarity as the polarity network, thereby making the polarity of the first redundant metal 3 and the second redundant metal 4 opposite, thereby obtaining a line capacitance and providing a line capacitance value. This method can effectively control the value of the line capacitance, improving the stability and performance of the voltage stabilization structure. It can also simplify the manufacturing process and improve production efficiency.

[0077] Furthermore, the poly (redundant gate 5) layer and the OD (redundant active area 6) layer are grouped for power / ground based on the substrate 7 and OD (redundant active area 6) types: the P-type is connected to ground, the N-type is connected to power, and the poly (redundant gate 5) determines power / ground based on the opposite type of the substrate 7. The OD (redundant active area 6) is a P- or N-type active area, and the poly (redundant gate 5) is polysilicon, a polysilicon composite, or a polysilicon-based composite.

[0078] Connect as many dummies (voltage-stabilizing structures) as possible to the power network, following the principle of minimizing floating areas. Adjacent layers of dummies (voltage-stabilizing structures) whose ANDs are not empty can be connected through vias. Adjacent layers of dummies (voltage-stabilizing structures) whose ANDs are empty but can be routed both horizontally and vertically can have their dummies extended within the same layer to short-circuit the nearest power / ground line or a dummy (voltage-stabilizing structure) already connected to the power network. This extension can be either horizontal or vertical. For DP (double mask etch layer) layers that can only route in one direction, short-circuit through vias or broken lines.

[0079] After the connection is completed, calculate whether the sum of the densities of the dummy (voltage-stabilizing structure) exceeds the upper limit of the design rules (for example, the sum of the metal density, the sum of the oxide density, or the sum of the sum of the metal density and the oxide density). If it exceeds the upper limit, capture the dummy (voltage-stabilizing structure) graphics in the excess area and delete the floating dummy (voltage-stabilizing structure) that is not successfully connected to the power / ground network to meet the design rules.

[0080] Figure 9 is a flow chart of a method for connecting a redundant MOS tube in parallel with a power supply network of a chip load according to an embodiment of the present application. In one embodiment, Figure 9 As shown, the production method further includes:

[0081] Step S901, connecting the redundant gate 5 to the positive terminal or the negative terminal of the power supply network;

[0082] Step S902 : Connect the substrate 7 to the negative terminal or the positive terminal of the power supply network so that the polarity of the redundant gate 5 is opposite to that of the substrate 7 , so that the redundant MOS transistor is connected in parallel to the power supply network of the chip load.

[0083] In an exemplary embodiment, the redundant gate 5 is connected to the positive terminal of the power supply network, and the substrate 7 is connected to the negative terminal of the power supply network, so that the redundant MOS transistor formed by the redundant gate 5 and substrate 7 is connected in parallel with the power supply network of the chip load. Alternatively, the redundant gate 5 is connected to the negative terminal of the power supply network, and the substrate 7 is connected to the positive terminal of the power supply network, so that the redundant MOS transistor formed by the redundant gate 5 and substrate 7 is connected in parallel with the power supply network of the chip load.

[0084] In one embodiment, the manufacturing method further includes: when the PN junction is connected in parallel to the power supply network of the chip load, connecting the redundant gate 5 to the redundant active area 6, so that the redundant gate 5 and the substrate 7 form a redundant MOS tube connected in parallel to the power supply network through the redundant active area 6.

[0085] In an exemplary embodiment, in addition to connecting the redundant gate 5 to the positive or negative terminal of the power supply network and the substrate 7 to the negative or positive terminal of the power supply network so that the polarity of the redundant gate 5 and the substrate 7 are opposite, and the redundant MOS transistor formed by the redundant gate 5 and the substrate 7 is connected in parallel with the power supply network of the chip load, it is also possible to first connect the PN junction in parallel with the power supply network of the chip load. For example, the redundant active area 6 of the PN junction is connected to the positive terminal of the power supply network, the substrate 7 is connected to the negative terminal of the power supply network, the PN junction is connected in parallel with the power supply network of the chip load, and the redundant gate 5 is connected to the redundant active area 6 so that the redundant gate 5 and the substrate 7 form a redundant MOS transistor connected in parallel with the power supply network through the redundant active area 6. Alternatively, the redundant active area 6 of the PN junction is connected to the negative terminal of the power supply network, the substrate 7 is connected to the positive terminal of the power supply network, the PN junction is connected in parallel with the power supply network of the chip load, and the redundant gate 5 is connected to the redundant active area 6 so that the redundant gate 5 and the substrate 7 form a redundant MOS transistor connected in parallel with the power supply network through the redundant active area 6.

[0086] In summary, through the embodiments of the present application, the problem of voltage drop within the chip is solved by utilizing the dummy structure (voltage stabilizing structure), thereby achieving the effect of enhancing power integrity while saving area without the need to add additional mask and overhead winding resources. The dummy (redundant structure) is at the same level as each layer of winding meta l (metal) and the base layer, which is a reuse of existing resources. There is no need to add additional mask and overhead winding resources, which saves area and reduces cost. The dummy structure (voltage stabilizing structure) provides an additional capacitor structure consisting of line capacitors, redundant MOS tubes, and PN junctions for the power network by being incorporated into the power network, which increases the total capacitance on the power network and also increases the strength of the power network, which can reduce voltage drop and enhance power integrity. In particular, for a scenario where the natural frequency of the power network is close to the design clock frequency and produces resonance, the increased capacitance can greatly reduce the natural oscillation frequency of the power network, greatly reducing the voltage drop caused by the resonance effect.

[0087] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by adding the necessary general hardware platform with the help of software, of course, it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0088] The method embodiments provided in the embodiments of the present application can be executed in a mobile terminal, a computer terminal or a similar computing device. Taking running on a computer terminal as an example, Figure 10 This is a hardware structure block diagram of a computer terminal of a method for manufacturing a voltage stabilizing structure of a chip load according to an embodiment of the present application. Figure 10 As shown, the computer terminal may include one or more ( Figure 10 Only one is shown) a processor 102 (the processor 102 may include but is not limited to a microprocessor MCU or a programmable logic device FPGA and other processing devices) and a memory 104 for storing data. The computer terminal may also include a transmission device 106 and an input / output device 108 for communication functions. It will be understood by those skilled in the art that Figure 10 The structure shown is only for illustration and does not limit the structure of the above-mentioned computer terminal. For example, the computer terminal may also include Figure 10 More or fewer components than shown, or with Figure 10 Different configurations shown.

[0089] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the method for making the voltage stabilizing structure of the chip load in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, implementing the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include a memory remotely located relative to the processor 102, and these remote memories may be connected to the computer terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0090] The transmission device 106 is used to receive or transmit data via a network. A specific example of the aforementioned network may include a wireless network provided by a computer terminal's communications provider. In one embodiment, the transmission device 106 includes a network interface controller (NIC), which can be connected to other network devices via a server to enable communication with the Internet. In another embodiment, the transmission device 106 may be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0091] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any of the above method embodiments when run.

[0092] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0093] An embodiment of the present application further provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0094] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0095] An embodiment of the present application further provides a computer program product, including a computer program, which implements the steps of any of the above method embodiments when executed by a processor.

[0096] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail here.

[0097] Obviously, those skilled in the art should understand that the modules or steps of the present application described above can be implemented using a general-purpose computing device, they can be concentrated on a single computing device, or distributed across a network composed of multiple computing devices, they can be implemented using program code executable by the computing device, and thus, they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be performed in a different order than herein, or they can be fabricated into separate integrated circuit modules, or multiple modules or steps can be fabricated into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0098] The above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. made within the principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A voltage stabilizing structure for a chip load, characterized in that: include: The substrate layer includes a redundant gate, a redundant active region, and a substrate, wherein the redundant gate and the substrate form a redundant MOS transistor to provide a redundant MOS transistor capacitance value; the redundant active region and the substrate form a PN junction to provide a PN junction capacitance value; The redundant MOS tube, the PN junction and the power supply network of the chip load are connected in parallel.

2. The voltage stabilizing structure according to claim 1, characterized in that: Also includes: A redundant metal layer, comprising a first redundant metal and a second redundant metal, wherein the first redundant metal and the second redundant metal have opposite polarities to obtain a line capacitance to provide a line capacitance value; The line capacitor, the redundant MOS transistor, the PN junction and the power supply network of the chip load are connected in parallel.

3. The voltage stabilizing structure according to claim 2, characterized in that: The redundant gate is connected to the positive terminal or the negative terminal of the power supply network, and the substrate is connected to the negative terminal or the positive terminal of the power supply network, so that the polarity of the redundant gate and the substrate are opposite.

4. The voltage stabilizing structure according to claim 2, characterized in that: The redundant gate is connected to the redundant active region, so that the redundant gate and the substrate form a redundant MOS transistor which is connected in parallel to the power supply network through the redundant active region.

5. The voltage stabilizing structure according to claim 2, characterized in that: The redundant metal layer includes a first redundant metal layer, and the first redundant metal and the second redundant metal are located in the first redundant metal layer.

6. The voltage stabilizing structure according to claim 2, characterized in that: The redundant metal layer also includes a second redundant metal layer, and the first redundant metal and the second redundant metal are located on a side adjacent to the second redundant metal layer, wherein the first redundant metal and the second redundant metal layer have an overlapping surface and are connected by a through hole so that the polarity of the first redundant metal and the second redundant metal layer is the same.

7. The voltage stabilizing structure according to claim 1, characterized in that: The first redundant metal and the second redundant metal are provided in multiple groups to obtain multiple groups of the line capacitors, wherein the multiple groups of line capacitors are connected in parallel.

8. A chip comprising a power supply and a load, characterized in that: It also includes a voltage stabilizing structure according to any one of claims 1 to 7, wherein the voltage stabilizing structure is connected in parallel between the power supply and the load.

9. A method for manufacturing a voltage stabilizing structure of a chip load, characterized in that: include: Obtaining a source file, wherein the source file is a file of the voltage stabilizing structure after layout and routing; Adding redundant graphics to the source file, wherein the redundant graphics include: redundant metal graphics, redundant gate graphics, and redundant active area graphics; Determining a metal layer based on the pattern of the redundant metal, determining a first redundant metal and a second redundant metal based on the metal layer, and making the polarity of the first redundant metal and the second redundant metal opposite to each other to obtain a line capacitance, thereby providing a line capacitance value; Determining a substrate layer based on the substrate of the source file, forming a redundant MOS transistor based on the pattern of the redundant gate and the substrate to provide a redundant MOS capacitance value; forming a PN junction based on the pattern of the redundant active region and the substrate to provide a PN junction capacitance value; The line capacitor, the redundant MOS tube, the PN junction and the power supply network of the chip load are connected in parallel to obtain a corresponding layout file, and the voltage stabilization structure is obtained based on the layout file.

10. The manufacturing method according to claim 9, characterized in that: include: Determining a metal layer based on the pattern of the redundant metal, determining a first redundant metal and a second redundant metal based on the metal layer, and making the polarity of the first redundant metal and the second redundant metal opposite to each other to obtain a line capacitance and provide a line capacitance value, including: confirming a first reference layer based on the pattern of the redundant metal; identifying a hierarchy of the first reference layer; The first redundant metal and the second redundant metal are set based on the hierarchy of the first reference layer, wherein the first redundant metal and the second redundant metal have opposite polarities to obtain line capacitance to provide a line capacitance value.

11. The manufacturing method according to claim 10, characterized in that: The method further comprises: setting the first redundant metal and the second redundant metal based on the hierarchy of the first reference layer, wherein the polarity of the first redundant metal is opposite to that of the second redundant metal, so as to obtain a line capacitance and provide a line capacitance value, comprising: When the first reference layer is a first redundant metal layer, the first redundant metal and the second redundant metal are set in the first reference layer, wherein the first redundant metal and the second redundant metal have opposite polarities to obtain line capacitance to provide a line capacitance value.

12. The manufacturing method according to claim 10, characterized in that: The method further comprises: setting the first redundant metal and the second redundant metal based on the hierarchy of the first reference layer, wherein the polarity of the first redundant metal is opposite to that of the second redundant metal, so as to obtain a line capacitance and provide a line capacitance value, comprising: In a case where the first reference layer is a first redundant metal layer, the first redundant metal and the second redundant metal are disposed in the first reference layer; An AND operation is performed on the redundant pattern of the first reference layer and the second reference layer. When the AND result of the first redundant metal of the first reference layer and the second reference layer is not empty, the first redundant metal of the first reference layer and the second reference layer are assigned the same polarity, so that the polarity of the first redundant metal and the second redundant metal are opposite, so as to obtain a line capacitance to provide a line capacitance value, wherein the second reference layer is an adjacent layer having an overlapping surface with the first reference layer.

13. The manufacturing method according to claim 10, characterized in that: The method further comprises: setting the first redundant metal and the second redundant metal based on the hierarchy of the first reference layer, wherein the polarity of the first redundant metal is opposite to that of the second redundant metal, so as to obtain a line capacitance and provide a line capacitance value, comprising: In a case where the first reference layer is a first redundant metal layer, the first redundant metal and the second redundant metal are disposed in the first reference layer; An AND operation is performed on the redundant pattern of the first reference layer and the polarity network of the second reference layer. When the AND result of the redundant pattern of the first reference layer and the polarity network of the second reference layer is not empty, the first redundant metal of the first reference layer and the polarity network are assigned the same polarity, so that the polarity of the first redundant metal and the second redundant metal are opposite to each other, so as to obtain a line capacitance to provide a line capacitance value, wherein the second reference layer is an adjacent layer having an overlapping surface with the first reference layer.

14. The manufacturing method according to claim 10, characterized in that: The method further comprises: setting the first redundant metal and the second redundant metal based on the hierarchy of the first reference layer, wherein the polarity of the first redundant metal is opposite to that of the second redundant metal, so as to obtain a line capacitance and provide a line capacitance value, comprising: In the case where the first reference layer is a second redundant metal layer, the first redundant metal and the second redundant metal are arranged in the second reference layer, wherein the second reference layer is an adjacent layer having an overlapping surface with the first reference layer; An AND operation is performed on the redundant patterns of the first reference layer and the second reference layer. When the results of the first redundant metal of the first reference layer and the second reference layer are not empty, the first redundant metal of the first reference layer and the second reference layer are assigned the same polarity, so that the polarity of the first redundant metal is opposite to that of the second redundant metal, so as to obtain a line capacitance to provide a line capacitance value.

15. The manufacturing method according to claim 10, characterized in that: The method further comprises: setting the first redundant metal and the second redundant metal based on the hierarchy of the first reference layer, wherein the polarity of the first redundant metal is opposite to that of the second redundant metal, so as to obtain a line capacitance and provide a line capacitance value, comprising: In the case where the first reference layer is a second redundant metal layer, the first redundant metal and the second redundant metal are provided in the first reference layer, wherein the second reference layer is an adjacent layer having an overlapping surface with the first reference layer; The redundant pattern of the first reference layer is ANDed with the polarity network of the second reference layer. When the result of the first redundant metal of the first reference layer and the polarity network of the second reference layer is not empty, the first redundant metal is assigned to the same polarity as the polarity network, so that the polarity of the first redundant metal and the second redundant metal are opposite to each other to obtain line capacitance and provide a line capacitance value.

16. The manufacturing method according to claim 9, characterized in that: Also includes: Connecting the redundant gate to the positive terminal or the negative terminal of the power supply network; The substrate is connected to the negative terminal or the positive terminal of the power supply network so that the polarity of the redundant gate is opposite to that of the substrate, so that the redundant MOS transistor is connected in parallel with the power supply network of the chip load.

17. The manufacturing method according to claim 9, characterized in that: Also includes: When the PN junction is connected in parallel to the power supply network of the chip load, the redundant gate is connected to the redundant active area so that the redundant gate and the substrate form a redundant MOS transistor connected in parallel to the power supply network through the redundant active area.

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