Capacitor series voltage-sharing circuit, control method and power supply equipment

Abstract

The invention provides a capacitor series voltage-sharing circuit, a control method and power supply equipment, and relates to the technical field of circuit design. The capacitor series voltage-sharing circuit comprises a capacitor unit and two groups of switches, each group of switches comprises at least two switch units, and the at least two switch units are respectively connected in series at two ends of the capacitor unit; in the two groups of switches, under the condition that the first group of switches is switched on, the capacitor unit is connected with the first capacitor in the series capacitor in parallel; and under the condition that the second group of switches are switched on, the capacitor unit is connected in parallel with the second capacitor in the series capacitor. Through connection and disconnection of the switch, charges are controlled to be transferred between each series capacitor and the capacitor unit, rapid charging and discharging by using the capacitor unit are realized, the voltage of each series capacitor is adjusted, voltage balance is achieved, and the energy loss of the circuit is reduced. In addition, the voltage-sharing response speed is improved by utilizing the rapid charging and discharging capability of the capacitor units, so that the voltage-sharing capability of the capacitor series voltage-sharing circuit is enhanced.

Description

Technical Field

[0001] The present application relates to the field of circuit design technology, and in particular to a capacitor series voltage balancing circuit, a control method, and a power supply device. Background Art

[0002] In high-voltage applications, connecting capacitors in series is a common method for improving overall voltage withstand capabilities. However, due to differences in leakage current, capacitance, and parasitic parameters among capacitors, voltage distribution across the series capacitors can be unbalanced, potentially damaging the capacitors or affecting the proper operation of the entire circuit.

[0003] In related technologies, a resistive load is connected in parallel across a capacitor to provide a static discharge path for the capacitor, allowing the capacitor with a higher voltage to discharge through the resistor to achieve voltage balance. However, this results in high energy loss. Summary of the Invention

[0004] The capacitor series voltage equalizing circuit, control method and power supply device provided in this application are used to solve the problem of high energy loss existing in the related art.

[0005] In a first aspect, the present application provides a capacitor series voltage balancing circuit, comprising: a capacitor unit and two groups of switches, each group of switches comprising at least two switch units, and the at least two switch units are respectively connected in series at both ends of the capacitor unit;

[0006] In the two groups of switches, when the first group of switches is turned on, the capacitor unit is connected in parallel with the first capacitor in the series capacitors; when the second group of switches is turned on, the capacitor unit is connected in parallel with the second capacitor in the series capacitors.

[0007] In a possible implementation, at least two switch units in the first switch group include a first switch unit and a second switch unit, and at least two switch units in the second switch group include a third switch unit and a fourth switch unit, wherein:

[0008] The first end of the first switch unit is used to be connected to the positive electrode of the first capacitor, and the second end of the first switch unit is commonly connected to one end of the capacitor unit and the first end of the third switch unit;

[0009] The first end of the second switch unit and the second end of the third switch unit are connected to form a common terminal, and the common terminal is used to be connected to the negative electrode of the first capacitor and the positive electrode of the second capacitor;

[0010] The second end of the second switch unit is connected to the other end of the capacitor unit and the first end of the fourth switch unit respectively;

[0011] The second end of the fourth switch unit is used to be connected to the negative electrode of the second capacitor.

[0012] In a possible implementation, the switch unit includes N single-pole single-throw switches connected in series, or the switch unit includes N single-pole single-throw switches connected in parallel, where N is a positive integer greater than or equal to 1.

[0013] In a possible implementation, among the at least two switch units included in each switch group, one switch unit includes two field effect transistors connected in series, and the other switch unit includes a field effect transistor.

[0014] In a possible implementation manner, the field effect transistor is an NMOS transistor.

[0015] In a possible implementation, the capacitor unit includes M electrolytic capacitors. When M is greater than 1, the electrolytic capacitors are connected in parallel.

[0016] In a second aspect, the present application provides a control method for a capacitor series voltage grading circuit, which is applicable to controlling the capacitor series voltage grading circuit of the first aspect. The control method includes:

[0017] Based on the set conduction period, any one of the two groups of switches included in the capacitor series voltage balancing circuit is controlled to be turned on, and the other group of switches is turned off.

[0018] In one possible implementation, based on a set conduction period, controlling one of two groups of switches included in the capacitor series voltage balancing circuit to be turned on and the other group of switches to be turned off includes:

[0019] monitoring a first voltage of a first capacitor and a second voltage of a second capacitor, wherein the first capacitor and the second capacitor are series capacitors;

[0020] If the first voltage is inconsistent with the second voltage, based on the set conduction period, one of the two sets of switches included in the capacitor series voltage balancing circuit is alternately controlled to be turned on and the other set of switches is turned off.

[0021] In one possible embodiment, based on a set on-cycle, any one of the two groups of switches included in the capacitor series voltage equalizing circuit is controlled to be turned on and the other group of switches is turned off, including: monitoring the first voltage of the first capacitor and the second voltage of the second capacitor, where the first capacitor and the second capacitor are series capacitors; if the first voltage is greater than the second voltage, cyclically executing the first control process, the first control process including: based on the set on-cycle, controlling the first group of switches in the two groups of switches to be turned on and the second group of switches to be turned off; based on the set on-cycle, controlling the second group of switches in the two groups of switches to be turned on and the first group of switches to be turned off; if the second voltage is less than the first voltage, cyclically executing the second control process, the second control process including: based on the set on-cycle, controlling the second group of switches in the two groups of switches to be turned on and the first group of switches to be turned off; based on the set on-cycle, controlling the first group of switches in the two groups of switches to be turned on and the second group of switches to be turned off.

[0022] In a third aspect, the present application provides a power supply device, comprising the capacitor series voltage balancing circuit of the first aspect.

[0023] The capacitor series voltage balancing circuit, control method and power supply device provided by the present application include a capacitor unit and two groups of switches, each group of switches includes at least two switch units, and at least two switch units are respectively connected in series at both ends of the capacitor unit; in the two groups of switches, when the first group of switches is turned on, the capacitor unit is connected in parallel with the first capacitor in the series capacitor; when the second group of switches is turned on, the capacitor unit is connected in parallel with the second capacitor in the series capacitor. By turning on and off the switches, the charge is controlled to be transferred between each series capacitor and the capacitor unit, and the capacitor unit is used to quickly charge and discharge, adjust the voltage of each series capacitor, and achieve the effect of voltage balancing. Compared with discharging through a resistance load to achieve voltage balancing, the resistance load consumes energy, thereby reducing circuit energy loss. In addition, the ability of the capacitor unit to quickly charge and discharge is utilized to improve the voltage balancing response speed, thereby enhancing the voltage balancing capability. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0025] Figure 1 A schematic diagram of the structure of a resistive voltage-equalizing circuit provided in the related art;

[0026] Figure 2 Schematic diagram of the structure of the capacitor series voltage equalization circuit provided in the embodiment of the present application Figure 1 ;

[0027] Figure 3 Schematic diagram of the structure of the capacitor series voltage equalization circuit provided in the embodiment of the present application Figure 2 ;

[0028] Figure 4 A schematic diagram of the voltage regulation process of the capacitor series voltage balancing circuit provided in an embodiment of the present application;

[0029] Figure 5 Schematic diagram of the structure of the capacitor series voltage equalization circuit provided in the embodiment of the present application Figure 3 .

[0030] The above drawings illustrate specific embodiments of the present application, which will be described in more detail below. These drawings and the textual description are not intended to limit the scope of the present application in any way, but rather to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0031] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0032] The terms "first", "second" etc. in the specification and claims of the present application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable in appropriate circumstances, so that the embodiments of the present application described herein can, for example, be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, the process, system, product or equipment comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or that are inherent to these processes, products or equipment.

[0033] Figure 1 This is a schematic diagram of the structure of a resistive voltage balancing circuit provided in the related art, such as Figure 1 As shown, capacitors C1 and C2 are connected in series. Due to differences in leakage current or capacitance between capacitors C1 and C2, this difference can lead to an imbalanced voltage distribution (i.e., mismatch) between capacitors C1 and C2. When the input voltage (Vin) is high and exceeds the capacitor's withstand voltage or the device's operating voltage range, this mismatch can cause some capacitors to experience excessive voltage, damaging the capacitors or affecting the normal operation of the entire circuit. Therefore, resistors R1, R2, and R3 are connected in parallel across capacitors C1 and C2. By turning switches Q1 and Q2 on and off, the higher voltage on capacitor C1 or C2 is discharged through the resistors, thereby regulating the voltages of capacitors C1 and C2 using resistors R1, R2, and R3. However, during this process, a certain amount of current will flow through resistors R1, R2, and R3, resulting in significant energy loss (such as heating).

[0034] To address the above technical issues, the present application provides a capacitor series voltage-equalizing circuit. By turning on and off a switch, the circuit controls the transfer of charge between each series capacitor and the capacitor unit, transferring the charge of the first capacitor with a higher voltage to the second capacitor with a lower voltage, thereby achieving voltage balancing. By replacing resistor discharge with charge transfer, the circuit energy loss during the voltage regulation process is reduced.

[0035] Figure 2 Schematic diagram of the structure of the capacitor series voltage equalization circuit provided in the embodiment of the present application Figure 1 ,like Figure 2 As shown, the capacitor series voltage equalizing circuit includes: a capacitor unit and two groups of switches, each group of switches includes at least two switch units, and the at least two switch units are respectively connected in series at both ends of the capacitor unit; in the two groups of switches, when the first group of switches is turned on, the capacitor unit is connected in parallel with the first capacitor in the series capacitor; when the second group of switches is turned on, the capacitor unit is connected in parallel with the second capacitor in the series capacitor.

[0036] The two switch groups are staggered, complementing each other. That is, when the first switch group (such as the first and second switch units in the figure) is on, the second switch group (such as the third and fourth switch units in the figure) is off; when the first switch group is off, the second switch group is on. Each switch group contains at least two switch units, each of which is used to control the connection between capacitor unit C3 and the series capacitor. The first and second capacitors C1 and C2 are capacitors that require voltage balancing, and the capacitor units can be considered auxiliary capacitors that provide voltage balancing capabilities.

[0037] By alternately controlling the on and off states of the two sets of switches, capacitor unit C3 is alternately connected in parallel with the first capacitor C1 and the second capacitor C2. When capacitor unit C3 is connected in parallel with the first capacitor C1, charge is redistributed between capacitor unit C3 and the first capacitor C1, shifting from high voltage to low voltage, thus balancing the voltage of the first capacitor C1. When capacitor unit C3 is connected in parallel with the second capacitor C2, charge is redistributed between capacitor unit C3 and the second capacitor C2, shifting from high voltage to low voltage, thus balancing the voltage of the second capacitor C2. After multiple alternations and charge redistributions, the voltages of the first capacitor C1 and the second capacitor C2 are ultimately the same, preventing damage caused by capacitor overvoltage.

[0038] The switch must be able to quickly open and close. The switch unit can be composed of semiconductor switches such as field-effect transistors, diodes, and insulated gate bipolar transistors. Semiconductor switches have high voltage ratings. Mechanical switches (such as single-pole single-throw switches) can also be used. Mechanical switches are simple to control, have a low failure rate, and are low cost. This application does not restrict the switch type.

[0039] It should be noted that the capacitor series voltage balancing circuit provided in the embodiment of the present application can be expanded to voltage balancing scenarios with three or more capacitors in series, simply by increasing the number of switch groups and capacitor units. The embodiment of the present application does not limit the number of switch units in each switch group or the connection form.

[0040] It should also be noted that the two groups of switches can be controlled by a control unit other than the capacitor series voltage balancing circuit, and each switch unit in the two groups of switches is turned on or off under the control signal of the control unit.

[0041] In the embodiment of the present application, the charge transfer between each series capacitor and the capacitor unit is controlled by turning on and off the switch, so as to realize rapid charging and discharging by the capacitor unit, adjust the voltage of each series capacitor, and achieve voltage balancing. Under ideal conditions, lossless voltage balancing can be achieved. Compared with discharging through a resistive load to achieve voltage balancing, energy consumption by the resistive load is avoided, thereby reducing circuit energy loss.

[0042] In addition, the method of achieving voltage equalization through resistive loads in related technologies is only applicable to static or slowly changing voltage imbalances, cannot cope with transient shocks, and has a slow voltage equalization response; and, due to the energy limitation of resistors, their voltage equalization capabilities are limited. The embodiment of the present application utilizes the ability of capacitor units to quickly charge and discharge through rapid switching of switches to dynamically adjust charge redistribution, thereby improving the voltage equalization response speed and thereby enhancing the voltage equalization capability.

[0043] In some embodiments, at least two switch units in the first switch group include a first switch unit and a second switch unit, and at least two switch units in the second switch group include a third switch unit and a fourth switch unit. Figure 3 Schematic diagram of the structure of the capacitor series voltage equalization circuit provided in the embodiment of the present application Figure 2 , it should be noted that, Figure 3 Just an example, Figure 3 Each switch unit includes a switch, and each capacitor unit includes a capacitor. Figure 3 The structure described does not constitute a specific limitation on the capacitor series voltage grading circuit described in the embodiment of the present application. Figure 3 As shown:

[0044] A first end of the first switch unit S1 is used to connect to the positive electrode of the first capacitor C1, and a second end of the first switch unit S1 is commonly connected to one end of the capacitor unit C3 and a first end of the third switch unit S3;

[0045] The first end of the second switch unit S2 and the second end of the third switch unit S3 are connected to form a common terminal, and the common terminal is used to be connected to the negative electrode of the first capacitor C1 and the positive electrode of the second capacitor C2;

[0046] The second end of the second switch unit S2 is connected to the other end of the capacitor unit C3 and the first end of the fourth switch unit S4 respectively;

[0047] The second end of the fourth switch unit S4 is configured to be connected to the negative electrode of the second capacitor C2.

[0048] Figure 4 The voltage regulation flow diagram of the capacitor series voltage equalizing circuit provided in the embodiment of the present application is combined with Figure 3 and Figure 4 , the voltage regulation principle of the capacitor series voltage equalizing circuit is explained in detail.

[0049] For example, Figure 3 The power supply V1 is used to supply power to the capacitor series voltage equalization circuit. After the power supply V1 supplies power, there may be a voltage mismatch between the first capacitor C1 and the second capacitor C2. The charge is transferred from the capacitor with a high voltage to the capacitor with a low voltage through the capacitor unit C3 to achieve voltage balance between the first capacitor C1 and the second capacitor C2. Among them, the first group of switches SWA includes a first switch unit S1 and a second switch unit S2, and the second group of switches SWB includes a third switch unit S3 and a fourth switch unit S4. The first group of switches SWA and the second group of switches SWB are complementary and out of phase, that is, when the first group of switches SWA is turned on, the second group of switches SWB is turned off; when the first group of switches SWA is turned off, the second group of switches SWB is turned on. After the power supply V1 supplies power, the first capacitor C1 and the second capacitor C2 are charged and divided, resulting in uneven voltage. The voltage regulation process may involve at least the following situations:

[0050] In the first case, the first capacitor C1 is larger than the second capacitor C2.

[0051] Phase 1: The first set of switches SWA is turned on (S1 & S2 ON), and the second set of switches SWB is turned off (S3 & S4 OFF). The first capacitor C1 and the capacitor unit C3 are connected in parallel, and charge is transferred from the first capacitor C1 to the capacitor unit C3. In other words, the first capacitor C1 charges the capacitor unit C3. After a certain charging time, the voltages of the first capacitor C1 and the capacitor unit C3 are equal.

[0052] Phase 2: The first set of switches SWA is disconnected (S1 & S2 OFF), and the second set of switches SWB is turned on (S3 & S4 ON). The second capacitor C2 and the capacitor unit C3 form a parallel relationship. Charge is transferred from the capacitor unit C3 to the second capacitor C2. That is, the capacitor unit C3 charges the second capacitor C2. After a certain charging time, the voltage of the second capacitor C2 and the capacitor unit C3 are equal.

[0053] Through stages 1 and 2, charge is transferred from the high-voltage first capacitor C1 to the low-voltage second capacitor C2, thereby reducing the voltage of the first capacitor C1 and increasing the voltage of the second capacitor C2, thereby adjusting the voltage balance between the first capacitor C1 and the second capacitor C2. It should be noted that in the actual adjustment process, multiple cycles of adjustment, stage 1-stage 2-stage 1...-stage 2, may be required to achieve final voltage balance, i.e., equal voltages between the first capacitor C1 and the second capacitor C2.

[0054] In the second case, the first capacitor C1 is smaller than the second capacitor C2.

[0055] Phase 1: The second set of switches SWB is turned on (S3 & S4 are on), and the first set of switches SWA is turned off (S1 & S2 are off). The second capacitor C2 and the capacitor unit C3 are connected in parallel, and charge is transferred from the second capacitor C2 to the capacitor unit C3. That is, the second capacitor C2 charges the capacitor unit C3. After a certain charging time, the voltage of the second capacitor C2 and the capacitor unit C3 are equal.

[0056] Phase 2: The second set of switches SWB is disconnected (S3 & S4 are OFF), and the first set of switches SWA is turned on (S1 & S2 are ON). The first capacitor C1 and the capacitor unit C3 are connected in parallel, and charge is transferred from the capacitor unit C3 to the first capacitor C1. That is, the capacitor unit C3 charges the first capacitor C1. After a certain charging time, the voltages of the first capacitor C1 and the capacitor unit C3 are equal.

[0057] Through stages 1 and 2, charge is transferred from the second capacitor C2 (with a higher voltage) to the first capacitor C1 (with a lower voltage). This increases the voltage of the first capacitor C1 and decreases the voltage of the second capacitor C2, thereby balancing the voltages between the first capacitor C1 and the second capacitor C2. It should be noted that the actual regulation process may involve multiple cycles of stage 1, stage 2, stage 1, and stage 2 to achieve final voltage balancing, i.e., equal voltages between the first capacitor C1 and the second capacitor C2.

[0058] A third type is that the first capacitor C1 is equal to the second capacitor C2.

[0059] The voltages of the first capacitor C1, the second capacitor C2, and the capacitor unit C3 are consistent. At this time, when the first set of switches SWA is turned on or the second set of switches SWB is turned on, the capacitor unit C3 does not participate in charge transport (transfer), and the first capacitor C1 and the second capacitor C2 maintain the same voltage.

[0060] In some embodiments, the capacitor unit includes M electrolytic capacitors. When M is greater than 1, the electrolytic capacitors are connected in parallel.

[0061] For example, if some capacitors in a parallel connection fail, the remaining capacitors can still maintain circuit functionality, achieving redundancy and improving circuit reliability. Furthermore, multiple parallel capacitors can provide more charge reserves, enhancing the circuit's ability to suppress transient voltage fluctuations and improving stability.

[0062] In practical applications of capacitor series voltage balancing circuits, high voltage and high current scenarios may be involved, and a single switch may not be able to withstand the full voltage or current. Therefore, in some embodiments, the switch unit includes N single-pole single-throw switches connected in series, or the switch unit includes N single-pole single-throw switches connected in parallel, where N is a positive integer greater than or equal to 1.

[0063] When N is greater than 1, and the switch unit includes N series-connected single-pole, single-throw (SPST) switches, the on / off state of the switch unit is determined by the logical "AND" relationship of all the SPST switches. The switch unit is on only when all the SPST switches are closed, and it is off when any SPST switch is open. By connecting multiple SPST switches in series, the voltage on the line can be distributed, thereby protecting individual switches and improving safety and reliability.

[0064] When the switch unit includes N parallel single-pole single-throw switches, the on / off state of the switch unit is determined by the logical "OR" relationship of all the single-pole single-throw switches. When any single-pole single-throw switch is closed, the switch unit is turned on.

[0065] In some embodiments, among the at least two switch units included in each switch group, one switch unit includes two field effect transistors connected in series, and the other switch unit includes a field effect transistor.

[0066] The field effect transistor may be an NMOS transistor or a PMOS transistor.

[0067] In this embodiment, field-effect transistors (FETs) are used as switches. These FETs have low on-resistance, reducing power consumption in capacitor-series voltage-balancing circuits. Furthermore, FETs offer fast switching speeds, supporting high-frequency on and off switching, making them suitable for high-frequency circuits and enabling rapid response to voltage changes, thus improving voltage-balancing capabilities.

[0068] In order to simplify the circuit structure and reduce the complexity of circuit implementation, in some embodiments, the field effect transistor is an NMOS transistor.

[0069] For example, Figure 5 Schematic diagram of the structure of the capacitor series voltage equalization circuit provided in the embodiment of the present application Figure 3 As shown. Figure 5As shown, the first switch unit consists of an NMOS transistor M2, the second switch unit consists of two NMOS transistors connected in series (M1 and M5), the third switch unit consists of two NMOS transistors connected in series (M4 and M6), and the fourth switch unit consists of an NMOS transistor M3. The gates of each NMOS transistor are simultaneously connected to an external control unit, and each NMOS transistor is turned on or off by a control signal from the control unit. The drain of NMOS transistor M2 is connected to the positive electrode of the first capacitor C1, and the source of NMOS transistor M2 is connected to one end of capacitor C3 and the drain of NMOS transistor M4. The drain of NMOS transistor M1, the other end of capacitor C3, and the drain of NMOS transistor M3 are connected to each other. The source of NMOS transistor M1 is connected to the source of NMOS transistor M5, and the drain of NMOS transistor M5, the drain of NMOS transistor M6, the negative electrode of the first capacitor C1, and the positive electrode of the second capacitor C2 are connected to each other. The source of NMOS transistor M6 is connected to the source of NMOS transistor M4. The source of the NMOS transistor M3 is connected to the negative electrode of the second capacitor C2.

[0070] In order to enable those skilled in the art to more clearly understand the capacitor series voltage equalization circuit solution proposed in the embodiment of the present application, Figure 5 Further analysis is made on the implementation principle of the capacitor series voltage equalizing circuit.

[0071] The power supply V1 is used to supply power to the capacitor series voltage equalization circuit. Assume that the power supply output voltage V1 is 20V. The rated working voltage of the first capacitor C1 and the second capacitor C2 is 12V, the capacity is 100uF, and the accuracy is plus or minus 20%. The capacitor unit C3 is a multi-layer ceramic capacitor (MLCC) with a capacity of 1uF and a rated working voltage of 25V. If the accuracy of the first capacitor C1 is 20% positive, the capacity is 120uF, and the accuracy of the second capacitor C2 is 20% negative, the capacity is 80uF. The first capacitor C1 and the second capacitor C2 are connected in series, and the voltage is inversely proportional to the capacity. Therefore, the voltage of the first capacitor C1 is , the voltage of the second capacitor C2 As a result, a mismatch occurs between the first capacitor and the second capacitor, requiring voltage balancing.

[0072] Phase 1: When the first set of switches (M1, M2, and M5) are turned off and the second set of switches (M3, M4, and M6) are turned on, capacitor unit C3 and second unit C2 form a parallel relationship, and charge is transferred from second capacitor 2 to capacitor unit C3. Second capacitor C2 charges capacitor unit C3. After a certain charging time, the voltage of second capacitor C2 and capacitor unit C3 are equal. .

[0073] Phase 2: When the first set of switches (M1, M2, and M5) are turned on and the second set of switches (M3, M4, and M6) are turned off, capacitor unit C3 forms a parallel relationship with first unit C1, and charge is transferred from capacitor unit C3 to first capacitor C1. Capacitor unit C3 charges first unit C1. After a certain charging time, the voltage of first capacitor C1 and capacitor unit C3 are equal. At this time, the first capacitor and the second capacitor are still mismatched, but the voltage difference gradually decreases.

[0074] Phase 3: When the first set of switches (M1, M2, and M5) are turned off and the second set of switches (M3, M4, and M6) are turned on, the capacitor unit C3 and the second capacitor C3 form a parallel relationship, and the second capacitor C2 continues to charge the capacitor unit C3. .

[0075] Phase 4: When the first set of switches (M1, M2, and M5) are turned on and the second set of switches (M3, M4, and M6) are turned off, the capacitor unit C3 forms a parallel relationship with the first unit C1, and the capacitor unit C3 continues to charge the first unit C1. .

[0076] At this time, the voltage difference between the first capacitor C1 and the second capacitor C2 is further reduced. It can be seen that by alternately controlling the conduction and disconnection of the two sets of switches, the capacitor unit C3 is connected in parallel with the first capacitor C1 and the second capacitor C2 in turn, that is, continuously repeating the cycle of stage 1 to stage 4, and finally achieving voltage balance between the first capacitor C1 and the second capacitor C2.

[0077] Next, the present application also provides a control method for a capacitor series voltage equalizing circuit, which is suitable for controlling the capacitor series voltage equalizing circuit in the above embodiment. The control method includes: based on a set conduction period, controlling any one of the two groups of switches included in the capacitor series voltage equalizing circuit to be turned on and the other group of switches to be turned off.

[0078] The first and second sets of switches are complementary and staggered. At any given moment, only one set of switches is on while the other is off. This periodic switching achieves capacitor voltage balancing. For example, when the first set of switches is on, the second set of switches is off, and when the first set of switches is off, the second set of switches is on.

[0079] For example, the control method is performed by a control unit connected to the capacitor series voltage grading circuit, such as a microcontroller, an analog control circuit, a field programmable gate array, a digital signal processor, etc. The control unit inputs a control signal to the switch unit in the capacitor series voltage grading circuit, wherein the control signal includes a set on-period, such as 5 milliseconds, 10 milliseconds, 10 microseconds, etc. The control signal is, for example, a high-level signal and a low-level electrical signal of 5 milliseconds, thereby controlling the switch units included in the first group of switches to be on for 5 milliseconds and the switch units included in the second group of switches to be off for 5 milliseconds.

[0080] The on-cycle of the switch directly affects the charging and discharging speed of the capacitor, which in turn determines the balancing effect of the capacitor voltage. The shorter the on-cycle, the higher the switching frequency and the finer the voltage regulation, but the switching loss increases. It should be noted that in actual applications, the on-cycle can be set based on various factors such as application scenario requirements, capacitor specifications, voltage balancing accuracy, switching loss, etc. By selecting an appropriate on-cycle, the efficiency and reliability of the capacitor series voltage balancing circuit can be improved.

[0081] The embodiment of the present application realizes capacitor series voltage balancing in a simple and efficient manner by alternately controlling the conduction of two sets of switches, thereby ensuring efficient and stable operation of the capacitor series voltage balancing circuit, and is suitable for application scenarios with various series capacitor voltage imbalances.

[0082] In some embodiments, based on a set conduction cycle, any one of the two groups of switches included in the capacitor series voltage balancing circuit is controlled to be turned on, and the other group of switches is turned off, including: monitoring a first voltage of the first capacitor and a second voltage of the second capacitor, where the first capacitor and the second capacitor are series capacitors; if the first voltage is inconsistent with the second voltage, based on the set conduction cycle, alternately controlling any one of the two groups of switches included in the capacitor series voltage balancing circuit to be turned on, and the other group of switches to be turned off.

[0083] For example, the first voltage of the first capacitor and the second voltage of the second capacitor are collected in real time by a voltage sensor, and the control unit obtains the first voltage and the second voltage from the voltage sensor. When it is detected that the first voltage and the second voltage are inconsistent, that is, there is a voltage mismatch problem in the series capacitors, at this time, the voltage balancing control mechanism is triggered, that is, by alternately controlling one set of switches in the two groups to be turned on and the other set of switches to be turned off, the capacitor unit is connected in parallel with the first capacitor and the second capacitor in turn, and finally the voltage balance of the first capacitor and the second capacitor is achieved. When it is detected that the first voltage and the second voltage are consistent, that is, there is no voltage mismatch problem in the series capacitors, the voltage balancing control mechanism is not triggered or stops being triggered.

[0084] The embodiments of the present application improve the accuracy and flexibility of dynamic pressure equalization through real-time monitoring and feedback control.

[0085] Before performing voltage regulation control, the voltage magnitude relationship between the first capacitor and the second capacitor can be determined, and based on the magnitude relationship, it is determined which of the two sets of switches is turned on first. This allows for more accurate voltage balancing. In some embodiments, based on a set on-cycle, controlling any one of the two sets of switches included in the capacitor series voltage balancing circuit to be turned on and the other set of switches to be turned off includes: monitoring the first voltage of the first capacitor and the second voltage of the second capacitor, the first capacitor and the second capacitor being series capacitors; if the first voltage is greater than the second voltage, looping through a first control process, the first control process including: based on a set on-cycle, controlling the first set of switches in the two sets of switches to be turned on and the second set of switches to be turned off; based on a set on-cycle, controlling the second set of switches in the two sets of switches to be turned on and the first set of switches to be turned off; if the second voltage is less than the first voltage, looping through a second control process, the second control process including: based on a set on-cycle, controlling the second set of switches in the two sets of switches to be turned on and the first set of switches to be turned off; based on a set on-cycle, controlling the first set of switches in the two sets of switches to be turned on and the second set of switches to be turned off.

[0086] For example, see Figure 3 As shown, when it is detected that the first voltage is greater than the second voltage, for example, the first voltage is 12V and the second voltage is 5V, the first process is: first, based on a set conduction period (such as 5 milliseconds), the first set of switches (S1 and S2) are turned on, the first capacitor C1 is connected in parallel with the capacitor unit C3, and the first capacitor C1 charges the capacitor unit C3; then the first set of switches (S1 and S2) are turned off, and the second set of switches (S3 and S4) are turned on, the second capacitor C2 is connected in parallel with the capacitor unit C3, and the capacitor unit C3 discharges to the second capacitor C2; and the above first process is repeated. When it is detected that the first voltage is lower than the second voltage, for example, the first voltage is 5V and the second voltage is 12V, the second process is as follows: first, the second set of switches (S3 and S4) are turned on based on a set conduction period (e.g., 5 milliseconds), the second capacitor C2 is connected in parallel with the capacitor unit C3, and the second capacitor C2 charges the capacitor unit C3; then, the second set of switches (S3 and S4) are turned off, and the first set of switches (S1 and S2) are turned on, the first capacitor C1 is connected in parallel with the capacitor unit C3, and the capacitor unit C3 discharges to the first capacitor C1; and the above second process is repeated.

[0087] When the first voltage is equal to the second voltage, there is no voltage mismatch between the first capacitor C1 and the second capacitor C2, and the voltage equalization adjustment mechanism is not triggered.

[0088] The present application also provides a power supply device, comprising the capacitor series voltage balancing circuit described in the above embodiment.

[0089] For example, the power supply device is a high-voltage direct current power supply device, a pulse function rate device (such as a laser, an electromagnetic gun, etc.), a high-voltage circuit breaker, a supercapacitor energy storage device, etc.

[0090] In power supply equipment, the application of the capacitor series voltage balancing circuit provided in this application can significantly improve the voltage balancing efficiency, reduce the loss during the voltage balancing process, and ensure the stable operation of the power supply equipment.

[0091] Finally, it should be noted that other embodiments of the present invention will readily occur to those skilled in the art after considering the specification and practicing the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present invention that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. It is not limited to the precise structure described above and shown in the drawings, and various modifications and variations may be made without departing from the scope of this application. The scope of this application is limited solely by the appended claims.

Claims

1. A capacitor series voltage equalizing circuit, characterized in that: include: A capacitor unit and two groups of switches, each group of switches including at least two switch units, and the at least two switch units are respectively connected in series at both ends of the capacitor unit; In the two groups of switches, when the first group of switches is turned on, the capacitor unit is connected in parallel with the first capacitor in the series capacitors; when the second group of switches is turned on, the capacitor unit is connected in parallel with the second capacitor in the series capacitors.

2. The capacitor series voltage grading circuit according to claim 1, wherein: At least two switch units in the first group of switches include a first switch unit and a second switch unit, and at least two switch units in the second group of switches include a third switch unit and a fourth switch unit, wherein: The first end of the first switch unit is used to be connected to the positive electrode of the first capacitor, and the second end of the first switch unit is commonly connected to one end of the capacitor unit and the first end of the third switch unit; The first end of the second switch unit and the second end of the third switch unit are connected to form a common end, and the common end is used to be connected to the negative electrode of the first capacitor and the positive electrode of the second capacitor; The second end of the second switch unit is connected to the other end of the capacitor unit and the first end of the fourth switch unit respectively; The second end of the fourth switch unit is used to be connected to the negative electrode of the second capacitor.

3. The capacitor series voltage grading circuit according to claim 1 or 2, characterized in that: The switch unit includes N single-pole single-throw switches connected in series, or the switch unit includes N single-pole single-throw switches connected in parallel, where N is a positive integer greater than or equal to 1.

4. The capacitor series voltage grading circuit according to claim 1 or 2, characterized in that: Among the at least two switch units included in each switch group, one switch unit includes two field effect transistors connected in series, and the other switch unit includes a field effect transistor.

5. The capacitor series voltage grading circuit according to claim 4, characterized in that: The field effect tube is an NMOS tube.

6. The capacitor series voltage grading circuit according to claim 1 or 2, characterized in that: The capacitor unit includes M electrolytic capacitors. When M is greater than 1, the electrolytic capacitors are connected in parallel.

7. A control method for a capacitor series voltage balancing circuit, characterized in that: The method for controlling the capacitor series voltage balancing circuit according to any one of claims 1 to 6 comprises: Based on the set conduction period, any one of the two groups of switches included in the capacitor series voltage balancing circuit is controlled to be turned on, and the other group of switches is controlled to be turned off.

8. The control method of the capacitor series voltage grading circuit according to claim 7, characterized in that: The controlling, based on the set conduction period, of the two groups of switches included in the capacitor series voltage balancing circuit to be turned on and the other group of switches to be turned off includes: monitoring a first voltage of a first capacitor and a second voltage of a second capacitor, wherein the first capacitor and the second capacitor are connected in series; If the first voltage is inconsistent with the second voltage, based on a set conduction period, any one of the two switch groups included in the capacitor series voltage balancing circuit is alternately controlled to be turned on and the other switch group is turned off.

9. The control method of the capacitor series voltage grading circuit according to claim 7, characterized in that: The controlling, based on the set conduction period, of the two groups of switches included in the capacitor series voltage balancing circuit to be turned on and the other group of switches to be turned off includes: monitoring a first voltage of a first capacitor and a second voltage of a second capacitor, wherein the first capacitor and the second capacitor are connected in series; If the first voltage is greater than the second voltage, a first control process is cyclically executed, the first control process comprising: controlling the first set of switches of the two sets of switches to be turned on and the second set of switches to be turned off based on the set on-cycle; controlling the second set of switches of the two sets of switches to be turned on and the first set of switches to be turned off based on the set on-cycle; If the second voltage is less than the first voltage, a second control process is executed in a loop, wherein the second control process includes: controlling the second group of switches in the two groups of switches to be turned on and the first group of switches to be turned off based on the set on-cycle; and controlling the first group of switches in the two groups of switches to be turned on and the second group of switches to be turned off based on the set on-cycle.

10. A power supply device, characterized in that: The method comprises the capacitor series voltage grading circuit according to any one of claims 1 to 6.

Images