Network device with traffic control

Abstract

The invention discloses a network device with flow control, and relates to the technical field of network devices. The network device comprises: a receiving packet buffer comprising a first register, wherein a first value stored in the first register indicates the amount of data to be processed of the receiving packet buffer; the receiving processor is used for receiving the first packet and storing the first packet to a receiving packet buffer; the transmission control circuit comprises a plurality of registers, determines whether to transmit a pause frame according to the second numerical value and the third numerical value in the plurality of registers and configures pause time in the pause frame; and the transmission processor transmits the pause frame to the external device based on the control of the transmission control circuit, so that the external device stops transmitting the data before the pause time expires based on the pause frame. The first numerical value is provided for a processor, so that the processor configures the second numerical value and the third numerical value when the first numerical value is not less than the critical value to trigger the emission control circuit to emit a pause frame.

Description

Technical Field

[0001] The present application relates to the technical field of network devices, and in particular to a network device with flow control. Background Art

[0002] Existing network devices often employ flow control mechanisms to prevent receive buffer overflows. Generally, existing hardware-implemented flow control mechanisms send pause frames based on the amount of data in the receive buffer, requesting external devices to pause data transmission. However, when a network device's central processing unit (CPU) experiences an abnormality such as a system crash or a system failure, the receive buffer remains full, potentially causing the network device to continuously send pause frames, preventing external devices from resuming transmission. On the other hand, existing software-implemented flow control mechanisms, while offering increased control flexibility, often require high CPU load when issuing pause frames. Furthermore, these pause frames must be queued in a packet transmission queue, potentially causing delays in their transmission and preventing timely flow control from being effective. Therefore, it can be understood that existing flow control mechanisms suffer from at least one of the following drawbacks: processor anomalies can cause the continuous sending of pause frames, paralyzing the external network; significantly increasing the CPU load, resulting in reduced system performance; and delays in the transmission of pause frames, which reduces the real-time nature of flow control. Summary of the Invention

[0003] In some embodiments, one of the purposes of the present application, but not limited to, is to provide a network device with flow control that can improve the real-time performance of flow control.

[0004] In some embodiments, a network device includes a receive packet buffer, a receive processor, a transmit control circuit, and a transmit processor. The receive packet buffer includes a first register storing a first value indicating the amount of data to be processed in the receive packet buffer. The receive processor receives a first packet and stores the first packet in the receive packet buffer via a receive direct memory access controller. The transmit control circuit includes a second register and a third register, wherein the transmit control circuit determines whether to issue a pause frame based on a second value stored in the second register and configures a pause time in the pause frame based on a third value stored in the third register. The transmit processor, under control of the transmit control circuit, transmits the pause frame to an external device, causing the external device to stop sending data to the receive processor before the pause time expires based on the pause frame. The first value is provided to a processor, which, when the first value is not less than a first threshold, configures the second value and the third value to trigger the transmit control circuit to control the transmit processor to issue the pause frame.

[0005] The features, implementation and effects of the present application are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0007] Figure 1 A schematic diagram of a network device according to some embodiments of the present application is provided;

[0008] Figure 2 According to some embodiments of the present application Figure 1 An operational flow chart of a flow control process of a network device;

[0009] Figure 3 According to some embodiments of the present application Figure 1 A flowchart of operations related to determining a pause time in a pause frame by a network device;

[0010] Figure 4 According to some embodiments of the present application Figure 1 a schematic diagram of a partial circuit of a network device; and

[0011] Figure 5 According to some embodiments of the present application Figure 1Flow chart of related operations of a network device determining a pause time in a pause frame.

[0012] Reference numerals:

[0013] 100: network device;

[0014] 110: Network controller;

[0015] 111: Transmitter control circuit;

[0016] 111A, 111B: registers;

[0017] 112: Transmit processor;

[0018] 113: Transmitting direct memory access controller;

[0019] 114: receiving control circuit;

[0020] 115: receiving processor;

[0021] 115A: processing circuit;

[0022] 115B: First-in-first-out circuit;

[0023] 115C: register;

[0024] 116: receiving direct memory access controller;

[0025] 120: transmit packet buffer;

[0026] 130: Receive packet buffer;

[0027] 131: register;

[0028] 140: processor;

[0029] 150: memory interface unit;

[0030] PF: Pause frame;

[0031] R1, R2, R3, R4: value;

[0032] S210, S212, S214, S216, S218, S220, S222, S224: operation;

[0033] S310, S312, S314, S316, S318, S320: operation;

[0034] S510, S512, S514, S516, S518, S520: operation;

[0035] SP1, SP2: Packet;

[0036] T1min, T2min: preset values;

[0037] TH1, TH2: critical values. DETAILED DESCRIPTION

[0038] All terms used in this application have their ordinary meanings. The definitions of the aforementioned terms in commonly used dictionaries, including any examples of their use in this application, are intended to be illustrative only and should not limit the scope and meaning of this application. Similarly, this application is not limited to the various embodiments described herein.

[0039] As used herein, the terms "coupled" or "connected" may refer to direct physical or electrical contact between two or more components, or indirect physical or electrical contact between two or more components, or to the mutual operation or action of two or more components. As used herein, the term "circuit" may refer to a device comprised of at least one transistor and / or at least one active or passive component connected in a specific manner to process signals.

[0040] Figure 1 A schematic diagram of a network device 100 is provided according to some embodiments of the present application. In some embodiments, the network device 100 may be coupled to an external device (not shown) via, but not limited to, an Ethernet network to transmit packets to the external device or receive packets from the external device.

[0041] In some embodiments, network device 100 includes a network controller 110, a transmit packet buffer 120, a receive packet buffer 130, and a processor 140. Network controller 110 is primarily used to perform operations related to packet transmission and reception. In some embodiments, network controller 110 may be a media access control (MAC) controller. Network controller 110 includes a transmit control circuit 111, a transmit processor 112, a transmit direct memory access (DMA) controller 113, a receive control circuit 114, a receive processor 115, and a receive DMA controller 116.

[0042] The receive processor 115 can receive packet SP1 from the aforementioned external device and store it in the receive packet buffer 130 via the receive direct memory access controller 116. The receive processor 115 can decapsulate packet SP1 and verify its legitimacy. If packet SP1 passes the verification, the receive processor 115 can store it in the receive packet buffer 130 via the receive direct memory access controller 116. The receive control circuit 114 can determine whether packet SP1 is a pause frame. If packet SP1 is a pause frame, the receive control circuit 114 can control the transmit processor 112 to pause sending packets to the aforementioned external device. In some embodiments, a pause frame is a flow control mechanism in Ethernet networks. Its function is to request a transmitter (e.g., network device 100) to pause data transmission when a receiving device (e.g., the aforementioned external device) is unable to process received data (e.g., packet SP2 sent by network device 100) in time to prevent data loss.

[0043] The transmit processor 112 can obtain the to-be-transmitted packet SP2 from the transmit packet buffer 120 via the transmit direct memory access controller 113, encapsulate the packet SP2, and transmit the packet SP2 to the aforementioned external device. Similarly, if the network device 100 is unable to process the received packet SP1 in time, the transmit control circuit 111 can control the transmit processor 112 to output a pause frame PF as packet SP2, thereby transmitting the pause frame PF to the aforementioned external device, causing the external device to suspend data transmission (e.g., packet SP1).

[0044] Specifically, in some embodiments, the receive packet buffer 130 includes a register 131 for storing a value R1, which indicates the amount of data to be processed in the receive packet buffer 130. In some embodiments, the transmit control circuit 111 includes a register 111A and a register 111B. Register 111A stores a value R2 for indicating whether to issue a pause frame PF, and register 111B stores a value R3 for indicating the pause duration of the pause frame PF. A main control circuit (not shown) within the transmit control circuit 111 can determine whether to control the transmit processor 112 to output the pause frame PF as packet SP2 based on the value R2, and configure the pause duration of the pause frame PF based on the value R3.

[0045] Value R1 is provided to processor 140. In some embodiments, processor 140 may be, but is not limited to, a central processing unit (CPU). Processor 140 may read value R1 in register 131 to determine whether the amount of data pending in receive packet buffer 130 is excessive. For example, processor 140 may compare value R1 with threshold TH1 and determine that the amount of data pending in receive packet buffer 130 is excessive when value R1 is not less than (i.e., greater than or equal to) threshold TH1. This condition indicates that receive processor 115 may not have enough time to process subsequent received packets. Therefore, when value R1 is not less than threshold TH1, processor 140 may configure value R2 in register 111A and value R3 in register 111B to trigger transmit control circuit 111 to control transmit processor 112 to issue a pause frame PF. This allows an external device to temporarily stop sending data to receive processor 115 before the aforementioned pause time expires based on the pause frame PF.

[0046] In some embodiments, the processor 140 may configure the value R3 to be a fixed value so that the pause time in the pause frame PF has the same value. Alternatively, in some embodiments, the processor 140 may adjust the value R3 according to the actual operating conditions of the network device 100, thereby dynamically adjusting the length of the pause time in each pause frame PF issued. Figure 3 、 Figure 4 and Figure 5 illustrate.

[0047] Figure 2 According to some embodiments of the present application Figure 1 , a flow chart of the flow control process of the network device 100. In operation S210, the network device 100 begins receiving packets. In operation S212, the processor 140 determines whether the value R1 is not less than the threshold TH1. If so, operation S214 is executed; otherwise, operation S216 is executed. In operation S214, the processor 140 configures the values ​​R2 and R3 to trigger the transmit control circuit 111 to control the transmit processor 112 to issue a pause frame PF. In operation S216, the network device 100 reports the relevant information to the protocol layer. In operation S220, the network device 100 begins transmitting packets. In operation S222, the network device 100 stores the packet SP2 to be transmitted into the transmit packet buffer 120, thereby entering the transmit queue. In operation S224, the network device 100 triggers the transmit direct memory access controller 113, causing the transmit processor 112 to obtain the packet SP2 from the transmit packet buffer 120 and transmit the packet SP2.

[0048] based on Figure 2As can be seen, during packet reception operations, if the value R1 is detected to be too high (indicating an excessive amount of data to be processed in the receive packet buffer 130), the processor 140 can directly set the values ​​R2 and R3 in registers 111A and 111B, thereby directly triggering the transmit control circuit 111 to issue a pause frame PF. This allows for more immediate issuance of the pause frame PF, improving overall system processing efficiency. This eliminates the need for the processor 140 to execute an additional thread to monitor the operating status of the network controller 110's receiver, nor does it require the processor 140 to store the entire pause frame PF in the transmit packet buffer 120, effectively reducing the processor 140's load. On the other hand, if the processor 140 itself or its peripheral bus circuits experience an error such as an abnormality or termination, not only will the processor 140 be unable to perform packet reception operations, but it will also be unable to configure registers 111A and 111B. This configuration prevents the transmit control circuit 111 from being erroneously triggered and continuously issuing pause frames PF when the aforementioned error occurs, thereby preventing network downtime.

[0049] Figure 3 According to some embodiments of the present application Figure 1 The network device 100 determines the pause time in the pause frame PF. Figure 2 In operation S210), the network device 100 starts to receive packets. Figure 2 The processor 140 checks whether the value R1 is not less than the threshold value TH1. If so, the processor 140 performs an operation S314; otherwise, the processor 140 performs an operation S316 (corresponding to Figure 2 In operation S216, processor 140 determines a difference between a first time difference and a pause time parameter, and confirms whether this difference is less than a first predetermined value, where the first time difference is the time difference between multiple time periods associated with value R1. If not, operation S318 is executed; conversely, if yes, operation S316 is executed. In operation S318, processor 140 determines value R3 based on this difference, with the difference being inversely proportional to value R3. In operation S320, processor 140 configures value R2 to trigger transmit control circuit 111 to control transmit processor 112 to issue a pause frame PF. In operation S316, network device 100 reports the relevant information to the protocol layer.

[0050] In this example, when value R1 is greater than threshold TH1, processor 140 further determines whether to adjust value R3 based on the first time difference between multiple time periods associated with value R1, the pause time parameter, and a preset value T1min (i.e., the first preset value in operation S314), thereby adjusting the pause time in the pause frame PF or preventing transmit control circuit 111 from issuing the pause frame PF. Specifically, the multiple time periods may include a first time period and a second time period. The first time period is the period from the last pause frame PF issued by transmit processor 112 to the time when value R1 is no less than (i.e., greater than or equal to) threshold TH1 again. The second time period is the period from the last pause frame PF issued by transmit processor 112 to the time when value R1 is no less than (i.e., greater than or equal to) threshold TH1 again. The pause time parameter is the pause time set by transmit processor 112 in the last pause frame PF issued. It should be understood that the last pause frame PF issued and the last pause frame issued are, respectively, the later and earlier frames of the consecutive transmissions. That is, the pause frame PF sent most recently is the next pause frame sent after the pause frame PF sent previously.

[0051] For example, after the network device 100 is powered on, the transmit processor 112 issues a pause frame PF for the first time. The period from when the pause frame PF takes effect until the value R1 is again no less than the threshold value TH1 is the aforementioned second period. Next, the transmit processor 112 issues a pause frame PF for the second time, and the period from when the pause frame PF takes effect until the value R1 is again no less than the threshold value TH1 is the aforementioned first period. The pause time in the first issued pause frame PF is the pause time parameter. The first issued pause frame PF and the second issued pause frame PF are two consecutive pause frames PF, and the first issued pause frame PF is sent earlier than the second issued pause frame PF. That is, at the current moment, the second issued pause frame PF is the pause frame PF that was sent most recently, while the first issued pause frame PF is the pause frame PF that was sent earlier. The processor 140 can record this information and determine a difference value based on this difference (operation S312), which can be expressed as the following mathematical formula:

[0052] T=T2-T1-T PF ;

[0053] Wherein, T2 is the aforementioned first time period, T1 is the aforementioned second time period, T PF is the aforementioned pause time parameter.

[0054] Using the above formula, processor 140 can evaluate the speed at which the amount of data to be processed in receive packet buffer 130 reaches threshold TH1. When difference T is greater than a preset value T1min, processor 140 determines value R3 based on difference T (operation S318). Generally speaking, a larger difference T indicates a slower rate at which the amount of data to be processed in receive packet buffer 130 reaches threshold TH1. In this case, value R3 can be adjusted to a smaller value to reduce the pause time, allowing the external device to start sending data earlier to avoid impacting the network bandwidth between the two devices. Alternatively, a smaller difference T indicates a faster rate at which the amount of data to be processed in receive packet buffer 130 reaches threshold TH1. In this case, value R3 can be adjusted to a larger value to increase the pause time, allowing the external device to pause sending data for a longer period of time. Therefore, in general, difference T and value R3 are inversely proportional. In some embodiments, processor 140 may include a lookup table that records the mapping between difference T and value R3, and executes operation S316 based on this lookup table.

[0055] On the other hand, if the difference T is too low (e.g., not greater than the preset value T1min), it indicates that the processor 140 is overloaded and cannot process the packets in the receive packet buffer 130. In this case, the processor 140 may forgo issuing a pause frame PF (i.e., not triggering the transmit control circuit 111 to issue a pause frame PF) and directly report the result to the protocol layer. In this way, the network device 100 will forgo receiving packets, and the transmit control circuit 111 will not issue a pause frame PF, thereby ensuring the normal operation of external devices.

[0056] In some embodiments, the pause frame PF takes effect when the transmit processor 112 issues the pause frame PF. In some embodiments, the pause frame PF takes effect when the other device (e.g., the external device described above) parses the received pause frame PF and begins to suspend data transmission. The above definition of the pause frame PF taking effect is merely an example and the present application is not limited thereto.

[0057] In practical applications, the pause time of the pause frame PF should not be too short to prevent the network device 100 from frequently sending pause frames PF. If the network device 100 frequently sends pause frames PF to the external device, the network bandwidth of both parties will be occupied and the processor load in the external device may be too high. On the other hand, the pause time of the pause frame PF should not be too long. If the pause time is too long, the external device will be unable to send data for a long time. Figure 3In other words, the network device 100 can dynamically and adaptively configure the pause time in the pause frame PF according to the current network operation status to avoid the above problem.

[0058] Figure 4 According to some embodiments of the present application Figure 1 In this example, the receiving processor 115 includes a processing circuit 115A, a first-in-first-out (FIFO) circuit 115B, and a register 115C. The network device 100 also includes a memory interface unit 150 and an interrupt processing circuit 152.

[0059] Processing circuit 115A is configured to verify the received packet SP1 and, if the packet SP1 passes verification, store the packet SP1 in a first-in-first-out circuit 115B. First-in-first-out circuit 115B may be coupled to receive direct memory access controller 116 via memory interface unit 150, which in turn is coupled to receive packet buffer 130 via receive direct memory access controller 116. In other words, receive processor 115 may first store the received packet SP1 in first-in-first-out circuit 115B, and then transfer the packet SP1 to receive packet buffer 130 via receive direct memory access controller 116 and memory interface unit 150. In some embodiments, memory interface unit 150 may serve as a control unit for data exchange between each direct memory access controller in the system and a main memory (not shown).

[0060] The value R4 stored in register 115C indicates the amount of data to be processed by FIFO circuit 115B. The interrupt processing circuit 152 sets a flag signal to an initial value (e.g., but not limited to, a value of 0). After packet SP1 is transferred from FIFO circuit 115B to receive packet buffer 130, the interrupt processing circuit 152 determines whether the value R4 is less than a threshold value TH2. If the value R4 is less than the threshold value TH2, the flag signal is set to a predetermined value (e.g., but not limited to, a value of 1). If the value R4 is not less than the threshold value TH2 and the flag signal is the predetermined value, the interrupt signal SU is issued and the flag signal is set back to the initial value. In some embodiments, the flag signal is a parameter stored in an internal register (not shown) within the interrupt processing circuit 152, and the interrupt processing circuit 152 can read the value R4 based on the transfer of the packet by the receive direct memory access controller 116. In this example, when the processor 140 receives the interrupt signal SU twice in a row, the processor 140 can determine whether to adjust the value R3 to update the pause time or to prevent the transmission control circuit 111 from sending the pause frame PF according to a time difference related to the interrupt signal SU, the pause time parameter, and a second preset value (e.g., the preset value T2min). The detailed operation here will be referred to later. Figure 5 illustrate.

[0061] Figure 5 According to some embodiments of the present application Figure 1 The network device 100 determines the pause time in the pause frame PF. Figure 2In operation S210, the network device 100 begins receiving packets. In operation S512, the interrupt processing circuit 152 sets the flag signal to an initial value. In operation S512, the first-in-first-out circuit 115B transfers the packet to the receive packet buffer 130 via the memory interface unit 150 and the receive direct memory access controller 116. In operation S514, the interrupt processing circuit 152 determines whether the value R4 is less than the threshold value TH2. If so, operation S516 is executed; otherwise, operation S518 is executed. In operation S516, the interrupt processing circuit 152 sets the flag signal to a predetermined value and executes operation S512 again. In operation S518, the interrupt processing circuit 152 determines whether the flag signal is the predetermined value. If so, operation S520 is executed; otherwise, operation S512 is executed again. In operation S520, the interrupt processing circuit 152 sends an interrupt signal SU to the processor 140. In operation S522, the interrupt processing circuit 152 sets the flag signal to the initial value and executes operation S512 again. In operation S524, when the processor 140 receives the interrupt signal SU twice consecutively, the processor 140 determines a difference between a time difference associated with the interrupt signal SU and a pause time parameter, and confirms whether this difference is not greater than a second predetermined value, where the time difference is the time interval between the two consecutive interrupt signals SU received by the processor 140. If so, operation S530 is executed; if not, operation S526 is executed. In operation S526, the processor 140 determines a value R3 based on the difference, with the difference being inversely proportional to the value R3. In operation S528, the processor 140 configures the value R2 to trigger the transmit control circuit 111 to control the transmit processor 112 to issue a pause frame PF. In operation S530, the network device 100 reports the relevant information to the protocol layer.

[0062] In this example, when the interrupt signal SU is received twice, the processor 140 further determines whether to adjust the value R3 based on the time difference associated with the interrupt signal SU, the pause time parameter, and the preset value T2min (i.e., the second preset value in operation S524), thereby adjusting the pause time in the pause frame PF, or preventing the transmit control circuit 111 from issuing the pause frame PF. In some embodiments, the aforementioned time difference may be the time interval between two consecutive interrupt signals SU received by the processor 140. Figure 5As can be seen from the flow, after the flag signal is set to the initial value, if the interrupt processing circuit 152 detects that the value R4 is less than the threshold value TH2 (i.e., the amount of data to be processed in the FIFO circuit 115B is less than the threshold value TH2), the interrupt processing circuit 152 will set the flag signal to a predetermined value (which is different from the initial value; for example, the initial value may be 0, while the predetermined value may be 1). Alternatively, if the interrupt processing circuit 152 detects that the value R4 is greater than or equal to the threshold value TH2, the interrupt processing circuit 152 will check whether the flag signal is the predetermined value. If the flag signal is the predetermined value, the first interrupt signal SU is issued. If the flag signal is not the predetermined value, the interrupt processing circuit 152 continues to monitor whether the value R4 drops below the threshold value TH2 again. Subsequently, when the value R4 rises again to be no less than the threshold value TH2 and the flag signal is the predetermined value, the interrupt processing circuit 152 issues a second interrupt signal SU. In the above flow, the flag signal is required to be set to the predetermined value during the period between the issuance of the two interrupt signals SU. This indicates that during the period between the two interrupt signals SU, the amount of data to be processed in the FIFO circuit 115B has dropped below the threshold TH2, thereby confirming that the data in the FIFO circuit 115B has been successfully read (i.e., transferred to the receive packet buffer 130) during this period.

[0063] Accordingly, the processor 140 may record the time interval between two consecutive receipts of the interrupt signal SU to determine the aforementioned time difference, and determine a difference value based on the time difference and the pause time (i.e., the pause time parameter) set in the most recently sent pause frame (operation S514), which can be expressed as the following mathematical formula:

[0064] T=T2-T1-T PF ;

[0065] Among them, T2 is the time point when the interrupt signal SU is received for the second time, T1 is the time point when the interrupt signal SU is received for the first time, T PF is the aforementioned pause time parameter.

[0066] Using the above equation, processor 140 can evaluate the speed at which the amount of data to be processed in FIFO circuit 115B reaches threshold TH2. When difference T is greater than a preset value T2min, processor 140 determines value R3 based on difference T (operation S526). A larger difference T indicates that the amount of data to be processed in FIFO circuit 115B reaches threshold TH2 more slowly. In this case, value R3 can be adjusted to a smaller value to reduce the duration of the pause, allowing the external device to start sending data earlier to avoid affecting the network bandwidth between the two devices. Alternatively, a smaller difference T indicates that the amount of data to be processed in FIFO circuit 115B reaches threshold TH2 more quickly. In this case, value R3 can be adjusted to a larger value to increase the duration of the pause, allowing the external device to pause sending data for a longer period of time. In some embodiments, as described above, difference T and value R3 are inversely proportional. In some embodiments, processor 140 may include a lookup table that records the mapping between difference T and value R3, and executes operation S516 based on this lookup table.

[0067] On the other hand, if the difference T is too low (for example, not greater than the preset value T2min), it indicates that the memory interface unit 150 is overloaded and cannot process the packet in the FIFO circuit 115B in time. Under this condition, the processor 140 may forgo issuing the pause frame PF (i.e., not triggering the transmit control circuit 111 to issue the pause frame PF). In this way, the network device 100 will forgo receiving the packet, and the transmit control circuit 111 will not issue the pause frame PF, thereby ensuring normal operation of the external device. As previously mentioned, the aforementioned process requires that the data in the FIFO circuit 115B be successfully read within the time period between two interrupt signals SU. Therefore, when the memory interface unit 150 is overloaded, the memory interface unit 150 cannot promptly process the data in the FIFO circuit 115B, resulting in the amount of data to be processed in the FIFO circuit 115B not decreasing. This, in turn, prevents the interrupt processing circuit 152 from issuing the second interrupt signal SU. This prevents the transmit control circuit 111 from frequently issuing the pause frame PF.

[0068] In summary, the network devices provided by some embodiments of the present application can determine whether to issue a pause frame based on the actual network status and dynamically configure the pause duration within the pause frame, thereby improving the real-time performance of traffic control. Furthermore, the network devices provided by some embodiments of the present application can prevent the CPU from erroneously issuing multiple pause frames consecutively due to CPU anomalies or excessive load, thereby preventing network paralysis.

[0069] Although the embodiments of the present application are described above, these embodiments are not intended to limit the present application. Technicians in this technical field may change the technical features of the present application based on the explicit or implicit content of the present application. All such changes may fall within the scope of patent protection sought by the present application. The scope of patent protection of the present application shall be based on the scope of the patent application defined in this specification.

Claims

1. A network device, characterized in that: include: a receiving packet buffer comprising a first register, wherein a first value stored in the first register indicates an amount of data to be processed in the receiving packet buffer; a receiving processor that receives a first packet and stores the first packet in the receiving packet buffer via a receiving direct memory access controller; a transmission control circuit comprising a second register and a third register, wherein the transmission control circuit determines whether to issue a pause frame according to a second value stored in the second register, and configures a pause time in the pause frame according to a third value stored in the third register; as well as a transmitting processor that transmits the pause frame to an external device based on the control of the transmitting control circuit, so that the external device stops sending data to the receiving processor before the pause time expires based on the pause frame; The first value is provided to a processor, so that when the first value is not less than a first threshold, the processor configures the second value and the third value to trigger the transmit control circuit to control the transmit processor to send the pause frame.

2. The network device according to claim 1, wherein: When the first value is greater than the first threshold, the processor determines whether to adjust the third value or to prevent the transmit control circuit from sending the pause frame based on a time difference between multiple time periods associated with the first value, a pause time parameter, and a first preset value.

3. The network device according to claim 2, wherein: The multiple time periods include: a first time period, the first time period being a time period from the moment the pause frame most recently sent by the transmit processor takes effect to the moment the first value becomes equal to the first threshold; and a second time period, the second time period being a time period from when the pause frame previously sent by the transmitting processor takes effect to when the first value becomes equal to the first threshold value; The pause frame sent previously and the pause frame sent most recently are respectively an earlier frame and a later frame sent continuously, the pause time parameter is the pause time set in the pause frame sent most recently, and the time difference is a difference between the first time period and the second time period.

4. The network device according to claim 2, wherein: When a difference between the time difference and the pause time parameter is greater than the first preset value, the processor determines the third value according to the difference, and the difference is in inverse proportion to the third value.

5. The network device according to claim 2, wherein: When a difference between the time difference and the pause time parameter is not greater than the first preset value, the transmission control circuit does not send the pause frame.

6. The network device according to claim 1, wherein: The receiving processor further includes a first-in-first-out circuit and a fourth register. The first-in-first-out circuit temporarily stores the first packet. A fourth value stored in the fourth register indicates an amount of data to be processed by the first-in-first-out circuit. The processor further determines, based on the fourth value and a second threshold, whether to configure the second value and the third value to trigger the transmit control circuit to issue the pause frame.

7. The network device according to claim 6, wherein: When the fourth value is greater than the second threshold, the processor determines whether to adjust the third value to update the pause time or to prevent the transmit control circuit from sending the pause frame based on a time difference between multiple time periods associated with the fourth value, a pause time parameter, and a second preset value.

8. The network device according to claim 7, wherein: The multiple time periods include: a first time period, which is a time period from the moment the pause frame most recently sent by the transmit processor takes effect to the moment the fourth value becomes equal to the second threshold; and a second time period, which is the time period from when the pause frame previously sent by the transmitting processor takes effect to when the fourth value becomes equal to the second threshold value; The pause frame sent previously and the pause frame sent most recently are respectively an earlier frame and a later frame sent continuously, the pause time parameter is the pause time set in the pause frame sent most recently, and the time difference is a difference between the first time period and the second time period.

9. The network device according to claim 7, wherein: When a difference between the time difference and the pause time parameter is greater than the second preset value, the processor determines the third value according to the difference, and the difference is in inverse proportion to the third value.

10. The network device according to claim 7, wherein: When a difference between the time difference and the pause time parameter is not greater than the second preset value, the transmission control circuit does not send the pause frame.

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