Video processing method, device, equipment and program product

Abstract

The invention relates to the field of video processing, in particular to a video processing method and device, equipment and a program product. The method comprises the following steps: receiving a video to be processed through a first protocol conversion module or through the first protocol conversion module and a second protocol conversion module; determining a code rate type of the to-be-processed video, and determining a conversion mode of the first protocol conversion module and a gating path of the multi-channel video gating module according to the code rate type; and according to the conversion mode of the first protocol conversion module and the gating path of the multi-channel video gating module, the video to be processed is converted and output to the image processing chip for image processing. According to the image processing method, the input pins of the image processing chip are multiplexed, the processing requirements of videos of different code rate types can be met only through single equipment, topological connection is simpler, the use of the pins of the image processing chip can be effectively reduced, the specification of the image processing chip is reduced, and the image processing cost is reduced.

Description

Technical Field

[0001] The present application relates to the field of video processing, and in particular to video processing methods, devices, equipment, and program products. Background Art

[0002] A two-in-one LED sending card typically integrates the functions of a splicing controller and an LED sending card. The splicing controller typically has multiple input and output interfaces. The video input from these multiple input interfaces undergoes image processing, scaling, and splicing before being output through multiple output interfaces. An LED sending card typically has one or more input interfaces and multiple network ports. These interfaces split the input image data according to the network port display area, package it according to specific protocol rules, and transmit the data to the receiving card via the Ethernet physical layer.

[0003] Two-in-one LED transmitter cards typically feature multiple input interfaces (such as HDMI and DVI) and multiple network output ports. To facilitate FPGA processing, a protocol conversion module is often used to convert the input video protocol, such as HDMI to MIPI, LVDS, or parallel port formats. This module converts a single HDMI interface into one or more MIPI / LVDS / parallel port interfaces. The higher the input image bitrate, the more interface groups are converted, and the corresponding number of output interfaces increases.

[0004] As can be seen from the above, a single high-bitrate video input interface or multiple low-bitrate video input interfaces both require multiple sets of MIPI / LVDS / parallel port video output interfaces. In this case, if both requirements are to be compatible, the number of FPGA pins is very high. To meet the requirements of high-rate HDMI interface input and multiple low-rate HDMI interface inputs, the following solutions are usually used:

[0005] Solution 1: The sending card only supports multiple low-rate input interfaces. When high-rate interface input is required, an external splicing controller device is required to split the single high-rate HDMI image into multiple low-rate images, and then connect them to the sending card through multiple low-rate input interfaces.

[0006] Solution 2: The sending card only supports a single high-speed input interface. When multiple low-speed interface inputs are required, an external splicing controller device is required to splice multiple low-speed images into a single high-speed HDMI image, which is then connected to the sending card through a single adjustable rate input interface.

[0007] Solution 3: Improve FPGA specifications and use FPGA chips with more pins.

[0008] Since options 1 and 2 require multiple devices, the topology connection is more complex and prone to compatibility issues. Option 3 requires increasing the number of pins of the FPGA chip, which is not conducive to reducing equipment costs. Summary of the Invention

[0009] In view of this, the embodiments of the present application provide a video processing method, apparatus, equipment and program product to solve the problem in the prior art that video processing requires multiple devices, the topology connection is relatively complex, compatibility issues are prone to occur, or it is not conducive to reducing equipment costs.

[0010] A first aspect of an embodiment of the present application provides a video processing method, wherein a device for video processing includes a first protocol conversion module, a second protocol conversion module, a multi-channel video strobe module, and an image processing chip, wherein: a first output end of the first protocol conversion module is connected to a first input end of the image processing chip, a second output end of the first protocol conversion module is connected to a first input end of the multi-channel video strobe module, an output end of the second protocol conversion module is connected to a second input end of the multi-channel video strobe module, and an output end of the multi-channel video strobe module is connected to a second input end of the image processing chip;

[0011] The method comprises:

[0012] Receiving the video to be processed through the first protocol conversion module, or through the first protocol conversion module and the second protocol conversion module;

[0013] Determine the bit rate type of the video to be processed, and determine the conversion mode of the first protocol conversion module and the gating path of the multi-channel video gating module according to the bit rate type;

[0014] The video to be processed is converted according to the conversion mode of the first protocol conversion module and the preset conversion mode of the second protocol conversion module. The second output end of the first protocol conversion module or the output end of the second protocol conversion module is determined to be selected through the selection path of the multi-channel video selection module. The converted video is output to the image processing chip for image processing through the first output end of the first protocol conversion module and the output end of the multi-channel video selection module.

[0015] In combination with the first aspect, in a first possible implementation of the first aspect, determining the conversion mode of the first protocol conversion module and the gating path of the multi-channel video gating module according to the bit rate type includes:

[0016] When the bit rate type of the to-be-processed video is a preset first bit rate type, the first protocol conversion module converts the to-be-processed video of the first bit rate type to obtain a plurality of groups of converted videos, wherein a first portion of the plurality of groups of converted videos is transmitted to a first input end of the image processing chip via a first output end of the first protocol conversion module, and a second portion of the plurality of groups of converted videos is transmitted to a first input end of the multi-channel video gating module via a second output end of the first protocol conversion module, wherein the bit rate of the first bit rate type is greater than the bit rate of the second bit rate type;

[0017] Furthermore, the multi-channel video gating module selects the path between the first input end of the multi-channel video gating module and the output end of the multi-channel video gating module, and the second part of the multiple groups of converted videos are transmitted to the second input end of the image processing chip through the output end of the multi-channel video gating module.

[0018] In conjunction with the first possible implementation of the first aspect, in a second possible implementation of the first aspect, the image processing chip performs image processing, including:

[0019] detecting a synchronization time difference between a first video inputted via a first input terminal of the image processing chip and a second video inputted via a second input terminal of the image processing chip;

[0020] Delay compensation is performed on the first video or the second video according to the synchronization time difference, so that the first video and the second video are synchronously aligned.

[0021] In conjunction with the first possible implementation of the first aspect, in a third possible implementation of the first aspect, the first part of the multiple groups of converted videos includes multiple channels of video, which are converted and processed by multiple first protocol conversion modules and then output to the first input end of the image processing chip respectively;

[0022] The second part of the multiple groups of converted videos includes group-channel videos, and the multiple groups of videos are selected by the multi-channel video selection module and transmitted to the second input end of the image processing chip.

[0023] In combination with the first possible implementation method of the first aspect, in a fourth possible implementation method of the first aspect, the number of interfaces for videos of the first bit rate type accessed by the first protocol conversion module is m, the number of channels after the m videos of the first bit rate type are converted by the first protocol conversion module is x, the number of channels after the m videos of the first bit rate type are converted by the second protocol conversion module is y, and xm≤y, where m, y, and x are natural numbers greater than 0.

[0024] With reference to the first aspect, in a fifth possible implementation of the first aspect, when the bit rate type of the to-be-processed video is a multi-channel preset second bit rate type, the first protocol conversion module performs protocol conversion processing on the first portion of the to-be-processed video of the second bit rate type, and then outputs the converted data to the first input end of the image processing chip through the first output end of the first protocol conversion module;

[0025] Furthermore, after the second protocol conversion module performs protocol conversion processing on the second part of the second bit rate type of the to-be-processed video, based on selecting the path between the second input end of the multi-channel video gating module and the output end of the multi-channel video gating module, the converted video is output to the second input end of the image processing chip through the output end of the multi-channel video gating module.

[0026] In combination with the first aspect, in a sixth possible implementation of the first aspect, after receiving the video to be processed by the first protocol conversion module, or by the first protocol conversion module and the second protocol conversion module, the method further includes:

[0027] Determining the bit rate and bit rate type of the video to be processed;

[0028] When the bit rate type of the video to be processed is a preset first bit rate type, the number of channels of the video converted by the first protocol conversion module is determined according to the bit rate of the video to be processed.

[0029] A second aspect of an embodiment of the present application provides a video processing device, wherein the device for video processing includes a first protocol conversion module, a second protocol conversion module, a multi-channel video strobe module, and an image processing chip, wherein: a first output end of the first protocol conversion module is connected to a first input end of the image processing chip, a second output end of the first protocol conversion module is connected to a first input end of the multi-channel video strobe module, an output end of the second protocol conversion module is connected to a second input end of the multi-channel video strobe module, and an output end of the multi-channel video strobe module is connected to a second input end of the image processing chip;

[0030] The device comprises:

[0031] a to-be-processed video receiving unit, configured to receive the to-be-processed video through the first protocol conversion module, or through the first protocol conversion module and the second protocol conversion module;

[0032] a conversion mode determining unit, configured to determine a bit rate type of the video to be processed, and determine a conversion mode of the first protocol conversion module and a gating path of the multi-channel video gating module according to the bit rate type;

[0033] The conversion processing unit is configured to convert the video to be processed according to the conversion mode of the first protocol conversion module and the conversion mode of the preset second protocol conversion module, determine to select the second output end of the first protocol conversion module or the output end of the second protocol conversion module through the selection path of the multi-channel video selection module, and output the converted video to the image processing chip for image processing through the first output end of the first protocol conversion module and the output end of the multi-channel video selection module.

[0034] A third aspect of an embodiment of the present application provides a video processing device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the video processing device implements a method as described in any one of the first aspects.

[0035] A fourth aspect of the embodiments of the present application provides a computer program product, which, when executed on a computer, enables the computer to execute the method in the above-mentioned first aspect or its various implementations.

[0036] A fifth aspect of an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method described in any one of the first aspects are implemented.

[0037] A sixth aspect of the present application provides a chip for implementing the methods described in each implementation of the first aspect. Specifically, the chip includes a processor configured to retrieve and execute a computer program from a memory, causing a device equipped with the chip to execute the methods described in the first aspect or its implementations.

[0038] The beneficial effects of the embodiments of the present application compared with the prior art are as follows: the embodiments of the present application, by designing multiple video input interfaces and connecting the protocol conversion module, combine the collaborative work of the multi-way selection chip and the image processing chip, and are compatible with the functions of high-rate interface decoding and multiple low-rate interface decoding without basically increasing the FPGA specifications and adding the splicing controller. Compared with the prior art, the image processing method in the embodiments of the present application reuses the input pins of the image processing chip, and only a single device is required to complete the processing requirements of videos of different bit rate types. Compared with the method of using an external splicing controller, the topological connection used in this method is simpler, and can effectively reduce the use of pins of the image processing chip, reduce the specifications of the image processing chip, and reduce the image processing cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0040] Figure 1 is a schematic diagram of a device for video processing provided in an embodiment of the present application;

[0041] Figure 2 This is a schematic diagram of an implementation flow of a video processing method provided in an embodiment of the present application;

[0042] Figure 3 is a schematic diagram of an image processing chip provided in an embodiment of the present application;

[0043] Figure 4 is a schematic diagram of a video processing device provided in an embodiment of the present application;

[0044] Figure 5 This is a schematic diagram of a video processing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0045] In the following description, specific details such as specific system structures and techniques are provided for purposes of illustration rather than limitation to facilitate a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid obscuring the description of the present application with unnecessary detail.

[0046] In order to illustrate the technical solution described in this application, specific embodiments are provided below.

[0047] A two-in-one LED sending card integrates the functions of a splicing controller (splicing controller) and an LED sending card. The splicing controller is equipped with multiple input and output interfaces, capable of receiving multiple video signals. After image processing, scaling, and splicing, it outputs the processed video signals through multiple output interfaces. The LED sending card, on the other hand, typically includes one or more input interfaces and multiple network interfaces. Its primary function is to split the input image data according to the display areas of different network ports, then package the data according to specific protocol rules and transmit it to the receiving card via the Ethernet physical layer.

[0048] Two-in-one LED transmitter cards typically feature multiple input interfaces (such as HDMI and DVI) and multiple network output ports. To facilitate FPGA (field programmable gate array) processing, a protocol conversion module is often used to convert the input video signal protocol (such as HDMI) into a format more suitable for FPGA processing, such as MIPI, LVDS, or parallel interface protocols. The protocol conversion module converts a single input interface into one or more MIPI, LVDS, or parallel interface groups based on the input image bit rate. The higher the input image bit rate, the greater the number of interface groups after conversion, and the corresponding number of output interfaces.

[0049] Therefore, whether it is a single high-bitrate video input interface or multiple low-bitrate video input interfaces, multiple sets of MIPI interfaces, LVDS interfaces, or parallel interfaces are required to meet the output requirements. Therefore, to simultaneously meet these two input requirements, the number of FPGA pins is required to be high. To achieve this compatibility, there are usually three solutions:

[0050] Solution 1: The sending card only supports multiple low-rate input interfaces. If you need to process high-rate input signals, you need to add an external splicing controller to split the single high-rate HDMI signal into multiple low-rate signals, and then connect them to the sending card through multiple low-rate input interfaces.

[0051] Solution 2: The sending card only supports a single high-speed input interface. If you need to process multiple low-speed input signals, you need to add an external splicing controller to splice the multiple low-speed signals into a single high-speed HDMI signal, and then connect it to the sending card through the single high-speed input interface.

[0052] Solution 3: Improve the FPGA specifications and use FPGA chips with more pins to meet the high pin count requirements.

[0053] However, both options 1 and 2 require additional controllers, which complicates system connectivity and can easily lead to compatibility issues. While option 3 solves the problem, it requires an FPGA chip with more pins, increasing equipment costs and hindering cost control.

[0054] In order to solve the above problems, the present invention proposes a video processing method. Figure 1 A structural diagram of a device for video processing is shown in FIG. Figure 1As shown, the device for video processing includes a first protocol conversion module, a second protocol conversion module, a multi-channel video gating module and an image processing chip. Among them, the input end of the first protocol conversion module can input a video of a preset first bit rate type (such as 4Kx2K@60Hz, 4Kx1K@60Hz), and can also input a video of a preset second bit rate type (such as a video of a 1080P image). The first output end of the first protocol conversion module is connected to the first input end of the image processing chip, the second output end of the first protocol conversion module is connected to the first input end of the multi-channel video gating module, the output end of the second protocol conversion module is connected to the second input end of the multi-channel video gating module, the input end of the second protocol conversion module can input a video of a preset second bit rate type, and the output end of the multi-channel video gating module is connected to the second input end of the image processing chip. The first protocol conversion module and the second protocol conversion module output a format of a preset second bit rate type adapted for processing by the image processing chip, including videos of protocols such as multiple groups of MIPI, LVDS or parallel ports. The bitrate of a video of the preset first bitrate type is greater than a preset first bitrate threshold, and the bitrate of a video of the preset second bitrate type is less than a preset second bitrate threshold. For example, videos of the 4Kx2K@60Hz and 4Kx1K@60Hz types belong to the first bitrate type, while videos of 1080P images belong to the second bitrate type.

[0055] Among them, the image processing chip or other control chip can detect the bit rate type of the video to be processed input by the first protocol conversion module. If it is the first bit rate type, the first protocol conversion module is controlled to convert the video to be processed, such as converting it into multiple groups of videos with protocols such as MIPI, LVDS or parallel port, to obtain multiple groups of videos with the second bit rate type. Through the first output end of the first protocol conversion module, the first part of the multiple groups of videos with the second bit rate type is output to the image processing chip, such as output to an FPGA or other image processing chip. Through the second output end of the first protocol conversion module, the second part of the multiple groups of videos with the second bit rate type is output to the first input end of the multi-channel video selection module. At the same time, the first input end of the multi-channel video selection module and the output end of the multi-channel video selection module are selected, so that the second part of the multiple groups of videos with the second bit rate type are output to the image processing chip through the output end of the multi-channel video selection module.

[0056] When the image processing chip or other control chip detects that the input video to be processed is a multi-channel video of the second bit rate type, the first protocol conversion module and the second protocol conversion module can each input a portion of the video to be processed. After the first protocol conversion module converts the first portion of the multi-channel video, it outputs the converted video through the first output terminal of the first protocol conversion module, and the second output terminal of the first protocol conversion module may not output the video. After the second protocol conversion module converts the second portion of the multi-channel video, it selects the second input terminal and the output terminal of the multi-channel video selection module, so that the second portion of the multi-channel video after protocol conversion is output to the image processing chip.

[0057] The input and output terminals of the first and second protocol conversion modules may include one or more interfaces. The first input, second input, and output terminals of the multi-channel video selection module may include one or more interfaces.

[0058] Figure 2 A schematic diagram of the implementation flow of a video processing method provided in an embodiment of the present application, which is based on Figure 1 The device for video processing shown in FIG. 1 includes:

[0059] In S201, a video to be processed is received by a first protocol conversion module, or by a first protocol conversion module and a second protocol conversion module.

[0060] The first protocol conversion module in the embodiment of the present application can be used to input a video to be processed of a first bit rate type, and can also input a video to be processed of a second bit rate type. The second protocol conversion module can be used to input a video to be processed of a second bit rate type. For example, the first protocol conversion module can input a single-channel video to be processed of a first bit rate type, including HDMI videos such as 4Kx2K@60Hz and 4Kx1K@60Hz. The first protocol conversion module and the second protocol conversion module can input multiple channels of videos to be processed of a second bit rate type, such as HDMI videos of 1080P images.

[0061] The inputs of the first protocol conversion module and the second protocol conversion module may include one or more input interfaces for inputting one or more channels of video to be processed. Alternatively, one or more first protocol conversion modules and one or more second protocol conversion modules may be included to meet the processing requirements of different channels of video to be processed, including image content processing, scaling, splicing, and other processing requirements.

[0062] In S202, the bit rate type of the video to be processed is determined, and the conversion mode of the first protocol conversion module and the gating path of the multi-channel video gating module are determined according to the bit rate type.

[0063] The bitrate type of the video to be processed in the embodiment of the present application can include a first bitrate type and a second bitrate type, i.e., a high bitrate type and a low bitrate type. In a preset connection relationship, the video to be processed of the first bitrate type can be input into the first protocol conversion module through the input end of the first protocol conversion module, and the video to be processed of the second bitrate type can be input into the first protocol conversion module and the second protocol conversion module.

[0064] When determining the conversion mode of the first protocol conversion module and the selection path of the multi-channel video selection module according to the bit rate type, it can include determining the conversion mode of the first protocol conversion module and the selection path of the multi-channel video selection module according to the first bit rate type, and determining the conversion mode of the first protocol conversion module, the conversion mode of the second protocol conversion module and the selection path of the multi-channel video selection module according to the second bit rate type.

[0065] When the first protocol conversion module inputs a video to be processed of a first bit rate type, the first protocol conversion module converts the video to be processed of the first bit rate type into multiple groups of videos in a format compatible with the image processing chip (such as MIPI, LVDS, or parallel port protocol format), and outputs a first portion of the multiple groups of videos to the first input terminal of the image processing chip via the first output terminal of the first protocol conversion module, and outputs a second portion of the multiple groups of videos to the second input terminal of the image processing chip via the second output terminal of the first protocol conversion module and the multi-channel video selection module. At this time, the multi-channel video selection module selects the first input terminal.

[0066] When the video to be processed is a video of the second bit rate type, the first protocol conversion module and the second protocol conversion module are used to convert the video to a format compatible with the image processing chip (such as MIPI, LVDS or parallel port protocol format). The video converted by the first protocol conversion module is directly transmitted to the first input of the image processing chip via the first output of the first protocol conversion module. The video converted by the second protocol conversion module is transmitted to the second input of the image processing chip via the multi-channel video selection module. At this time, the second input of the multi-channel video selection module connected to the output of the second protocol conversion module is selected.

[0067] In S203, the video to be processed is converted according to the conversion mode of the first protocol conversion module and the preset conversion mode of the second protocol conversion module. The second output end of the first protocol conversion module or the output end of the second protocol conversion module is selected through the selection path of the multi-channel video selection module. The converted video is output to the image processing chip for image processing through the first output end of the first protocol conversion module and the output end of the multi-channel video selection module.

[0068] When the bit rate type of the video to be processed is the first bit rate type, the first protocol conversion module converts the video to be processed of the first bit rate type to obtain multiple sets of converted videos. The first portion of the multiple sets of converted videos is transmitted to the image processing chip through the first output end of the first protocol conversion module, and the second portion of the multiple sets of converted videos is transmitted to the first input end of the multi-channel video selection module through the second output end of the first protocol conversion module, wherein the bit rate of the first bit rate type is greater than the bit rate of the second bit rate type. The multi-channel video selection module selects the path between the first input end of the multi-channel video selection module and the output end of the multi-channel video selection module, and the second portion of the multiple sets of converted videos is transmitted to the second input end of the image processing chip through the output end of the multi-channel video selection module.

[0069] For example, the video to be processed is a single-channel 4Kx2K@60Hz HDMI video. The first protocol conversion module converts the HDMI video into multiple groups of videos with MIPI, LVDS or parallel port protocols. The first part of the multiple groups of converted videos, such as 2 groups of videos, are directly transmitted to the image processing chip through the first output end of the first protocol conversion module. The second part of the multiple groups of converted videos, such as 2 groups of videos, are transmitted to the first input end of the multiplexer chip through the second output end of a protocol conversion module. After controlling the first input end of the multiplexer chip to be the selection end, the second part of the video can be transmitted to the second input end of the image processing chip through the output end of the multiplexer chip.

[0070] The first protocol conversion module in the embodiment of the present application may include multiple input interfaces, which can be used to receive multiple videos to be processed of the first bit rate type, or multiple first protocol conversion modules can be set to receive multiple videos to be processed of the first bit rate type.

[0071] The first input of the multi-channel video gating module can include multiple interfaces for inputting multiple sets of converted videos. Multiple interfaces can be selected to transmit the multiple sets of videos to the second input of the image processing chip. Alternatively, multiple multi-channel video gating modules can be provided to meet the gating requirements of multiple sets of videos.

[0072] In a possible implementation, assume that the number of interfaces for videos of the first bit rate type accessed by the first protocol conversion module is m, the number of channels after the m videos of the first bit rate type are converted by the first protocol conversion module is x, the number of channels after the m videos of the first bit rate type are converted by the second protocol conversion module is y, and xm≤y, where m, y, and x are natural numbers greater than 0. Since xm is the difference between the total number of channels converted by the first protocol conversion module and the number of input channels, this difference is the number of channels that need to be gated and transmitted through the multi-channel video gating module. If this difference is the same as the number of channels converted by the second protocol conversion module, the interface at the output end of the multi-channel video gating module can be shared to the greatest extent, thereby improving product performance.

[0073] In an embodiment of the present application, for a single-channel video of the first bit rate type to be processed, after being converted into multiple groups of videos by a first protocol conversion module, the videos are transmitted to the image processing chip via different transmission paths. Due to the different transmission paths, the time at which different groups of videos arrive at the image processing chip may also be different. In order to improve the reliability of image processing, an embodiment of the present application can perform synchronization alignment processing on the video converted from the video of the first bit rate type to be processed. The synchronization performance can be improved by optimizing the signal path, or the synchronization alignment can be performed based on the signal content.

[0074] like Figure 3 As shown, the image processing chip includes a timing detection module, an adaptive timing compensation module, an image processing unit and an image fusion module. Among them, the timing detection module can be used to detect the frame synchronization signal and the line synchronization signal of the input video, and calculate the synchronization time difference based on the frame synchronization signal and the line synchronization signal. For example, the frame synchronization of the first video A0 input at the first input end of the image processing chip is 50ns earlier than the second video A1 input at the second input end, and the timing detection module outputs the time difference Δt=50ns. The adaptive compensation module can dynamically adjust the data stream delay based on the timing detection results to eliminate the physical path difference. The image processing unit can perform content optimization and other processing on the images input from the two input ends, and the image fusion module can perform operations such as splicing on the images to adapt to different playback requirements.

[0075] In a possible implementation, the first bitrate type of video to be processed may include multiple bitrates, such as 4Kx2K@60Hz, 4Kx1K@60Hz, and other HDMI videos. To adapt to image processing requirements, the number of channels of the converted video can be adaptively determined based on the bitrate and bitrate type of the image to be processed. For example, a 4Kx2K@60Hz HDMI video corresponds to a 2-channel MIPI video or a 4-channel LVDS video, and a 4Kx1K@60Hz HDMI video corresponds to a 1-channel MIPI video or a 2-channel LVDS video.

[0076] In a possible implementation, the video to be processed can be a multi-channel video of the second bit rate type. For example, the video to be processed is a 4-channel 1080P image HDMI video. The multi-channel video can be input into the input end of the first protocol conversion module and the second protocol conversion module respectively, and the video to be processed can be converted into a video of a protocol such as MIPI, LVDS or parallel port. At this time, the first output end of the first protocol conversion module can directly output the converted video to the first input end of the image processing chip. After the second protocol conversion module converts the video to be processed, it selects the second input end of the multi-channel video selection module, so that the video processed by the second protocol conversion module is delivered to the second input end of the image processing chip.

[0077] That is to say, using Figure 1 The video processing device shown is compatible with the processing requirements of videos of the first bit rate type and the second bit rate type, and does not require additional pins of the image processing chip, effectively simplifying the connection structure of the image processing device and reducing the device cost.

[0078] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0079] Figure 4 This is a schematic diagram of an image processing device provided in an embodiment of the present application. The device for video processing includes a first protocol conversion module, a second protocol conversion module, a multi-channel video gating module, and an image processing chip, wherein: a first output end of the first protocol conversion module is connected to a first input end of the image processing chip, a second output end of the first protocol conversion module is connected to a first input end of the multi-channel video gating module, an output end of the second protocol conversion module is connected to a second input end of the multi-channel video gating module, and an output end of the multi-channel video gating module is connected to a second input end of the image processing chip. The device includes:

[0080] The video to be processed receiving unit 401 is configured to receive the video to be processed through the first protocol conversion module, or through the first protocol conversion module and the second protocol conversion module;

[0081] A conversion mode determining unit 402 is configured to determine a bit rate type of the video to be processed, and determine a conversion mode of the first protocol conversion module and a gating path of the multi-channel video gating module according to the bit rate type;

[0082] The conversion processing unit 403 is configured to convert the video to be processed according to the conversion mode of the first protocol conversion module and the preset conversion mode of the second protocol conversion module, determine to select the second output end of the first protocol conversion module or the output end of the second protocol conversion module through the selection path of the multi-channel video selection module, and output the converted video to the image processing chip for image processing through the first output end of the first protocol conversion module and the output end of the multi-channel video selection module.

[0083] Figure 4 The image processing device shown, and Figure 2 The image processing method shown corresponds to.

[0084] Figure 5 Schematic diagram of a video processing device provided in an embodiment of the present application. Figure 5 As shown, the video processing device 5 of this embodiment includes: a processor 50, a memory 51, and a computer program 52, such as an image processing program, stored in the memory 51 and executable on the processor 50. When the processor 50 executes the computer program 52, the steps of the above-described image processing method embodiments are implemented. Alternatively, when the processor 50 executes the computer program 52, the functions of the modules / units in the above-described apparatus embodiments are implemented.

[0085] For example, the computer program 52 may be divided into one or more modules / units, which are stored in the memory 51 and executed by the processor 50 to implement the present application. The one or more modules / units may be a series of computer program instruction segments capable of implementing specific functions, and the instruction segments are used to describe the execution process of the computer program 52 in the video processing device 5.

[0086] The video processing device may include, but is not limited to, a processor 50 and a memory 51. Those skilled in the art will understand that Figure 5 It is only an example of a video processing device 5 and does not constitute a limitation of the video processing device 5. It may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, the video processing device may also include input and output devices, network access devices, buses, etc.

[0087] The processor 50 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0088] The memory 51 can be an internal storage unit of the video processing device 5, such as a hard disk or memory of the video processing device 5. The memory 51 can also be an external storage device of the video processing device 5, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) card, a Flash Card, etc. equipped on the video processing device 5. Furthermore, the memory 51 can also include both an internal storage unit of the video processing device 5 and an external storage device. The memory 51 is used to store the computer program and other programs and data required by the video processing device. The memory 51 can also be used to temporarily store data that has been output or is about to be output.

[0089] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0090] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0091] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0092] In the embodiments provided in this application, it should be understood that the disclosed devices / terminal equipment and methods can be implemented in other ways. For example, the device / terminal equipment embodiments described above are merely illustrative. For example, the division of the modules or units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0093] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0094] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0095] If the integrated module / unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the process in the above-mentioned embodiment method, and can also be completed by hardware related to computer program instructions. The computer program can be stored in a computer-readable storage medium, and the computer program, when executed by the processor, can implement the steps of the above-mentioned various method embodiments. Wherein, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form, etc. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, U disk, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electric carrier signal, telecommunication signal and software distribution medium, etc.

[0096] In addition, an embodiment of the present application also provides a computer program product, which, when running on a computer, enables the computer to execute the methods in the above-mentioned implementation manners.

[0097] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A video processing method, characterized in that: The device for video processing includes a first protocol conversion module, a second protocol conversion module, a multi-channel video strobe module, and an image processing chip, wherein: a first output end of the first protocol conversion module is connected to a first input end of the image processing chip, a second output end of the first protocol conversion module is connected to a first input end of the multi-channel video strobe module, an output end of the second protocol conversion module is connected to a second input end of the multi-channel video strobe module, and an output end of the multi-channel video strobe module is connected to a second input end of the image processing chip; The method comprises: Receiving the video to be processed through the first protocol conversion module, or through the first protocol conversion module and the second protocol conversion module; Determine the bit rate type of the video to be processed, and determine the conversion mode of the first protocol conversion module and the gating path of the multi-channel video gating module according to the bit rate type; The video to be processed is converted according to the conversion mode of the first protocol conversion module and the preset conversion mode of the second protocol conversion module. The second output end of the first protocol conversion module or the output end of the second protocol conversion module is determined to be selected through the selection path of the multi-channel video selection module. The converted video is output to the image processing chip for image processing through the first output end of the first protocol conversion module and the output end of the multi-channel video selection module.

2. The method according to claim 1, characterized in that Determining a conversion mode of the first protocol conversion module and a gating path of the multi-channel video gating module according to the bit rate type includes: When the bit rate type of the to-be-processed video is a preset first bit rate type, the first protocol conversion module converts the to-be-processed video of the first bit rate type to obtain a plurality of groups of converted videos, wherein a first portion of the plurality of groups of converted videos is transmitted to a first input end of the image processing chip via a first output end of the first protocol conversion module, and a second portion of the plurality of groups of converted videos is transmitted to a first input end of the multi-channel video gating module via a second output end of the first protocol conversion module, wherein the bit rate of the first bit rate type is greater than the bit rate of the second bit rate type; Furthermore, the multi-channel video gating module selects the path between the first input end of the multi-channel video gating module and the output end of the multi-channel video gating module, and the second part of the multiple groups of converted videos are transmitted to the second input end of the image processing chip through the output end of the multi-channel video gating module.

3. The method according to claim 2, characterized in that The image processing chip performs image processing, including: detecting a synchronization time difference between a first video inputted via a first input terminal of the image processing chip and a second video inputted via a second input terminal of the image processing chip; Delay compensation is performed on the first video or the second video according to the synchronization time difference, so that the first video and the second video are synchronously aligned.

4. The method according to claim 2, characterized in that The first part of the plurality of groups of converted videos includes multiple channels of video, which are converted and processed by the plurality of the first protocol conversion modules and then output to the first input end of the image processing chip respectively; The second part of the multiple groups of converted videos includes group-channel videos, and the multiple groups of videos are selected by the multi-channel video selection module and transmitted to the second input end of the image processing chip.

5. The method according to claim 2, characterized in that The number of interfaces for videos of the first bit rate type accessed by the first protocol conversion module is m, the number of channels after the m videos of the first bit rate type are converted by the first protocol conversion module is x, the number of channels after the m videos of the first bit rate type are converted by the second protocol conversion module is y, and xm≤y, where m, y, and x are natural numbers greater than 0.

6. The method according to claim 1, characterized in that When the bit rate type of the video to be processed is a multi-channel preset second bit rate type, the first protocol conversion module performs protocol conversion processing on the first portion of the video to be processed of the second bit rate type, and outputs the converted data to the first input end of the image processing chip through the first output end of the first protocol conversion module; Furthermore, after the second protocol conversion module performs protocol conversion processing on the second part of the second bit rate type of the to-be-processed video, based on selecting the path between the second input end of the multi-channel video gating module and the output end of the multi-channel video gating module, the converted video is output to the second input end of the image processing chip through the output end of the multi-channel video gating module.

7. The method according to claim 1, characterized in that After receiving the video to be processed through the first protocol conversion module, or through the first protocol conversion module and the second protocol conversion module, the method further includes: Determining the bit rate and bit rate type of the video to be processed; When the bit rate type of the video to be processed is a preset first bit rate type, the number of channels of the video converted by the first protocol conversion module is determined according to the bit rate of the video to be processed.

8. A video processing device, characterized in that: The device for video processing includes a first protocol conversion module, a second protocol conversion module, a multi-channel video strobe module, and an image processing chip, wherein: a first output end of the first protocol conversion module is connected to a first input end of the image processing chip, a second output end of the first protocol conversion module is connected to a first input end of the multi-channel video strobe module, an output end of the second protocol conversion module is connected to a second input end of the multi-channel video strobe module, and an output end of the multi-channel video strobe module is connected to a second input end of the image processing chip; The device comprises: a to-be-processed video receiving unit, configured to receive the to-be-processed video through the first protocol conversion module, or through the first protocol conversion module and the second protocol conversion module; a conversion mode determining unit, configured to determine a bit rate type of the video to be processed, and determine a conversion mode of the first protocol conversion module and a gating path of the multi-channel video gating module according to the bit rate type; The conversion processing unit is configured to convert the video to be processed according to the conversion mode of the first protocol conversion module and the conversion mode of the preset second protocol conversion module, determine to select the second output end of the first protocol conversion module or the output end of the second protocol conversion module through the selection path of the multi-channel video selection module, and output the converted video to the image processing chip for image processing through the first output end of the first protocol conversion module and the output end of the multi-channel video selection module.

9. A video processing device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the video processing device implements the method according to any one of claims 1 to 7.

10. A computer program product comprising computer program instructions, characterized in that When the computer program is executed, the method according to any one of claims 1 to 7 is performed.

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