Readout circuit for improving dynamic range of composite dielectric gate photodetector

Abstract

The application discloses a readout circuit for improving dynamic range based on a composite medium grid photosensitive detector and belongs to the field of integrated circuits. An overflow electron discharge circuit is designed for the composite medium grid photosensitive detector pixel in the readout circuit, which is used for discharging the overflow electrons of the collection area of the composite medium grid photosensitive detector after saturation, so as to improve the equivalent full well capacity. A special timing is designed, and the same pixel is read out twice in the analog domain and the digital domain to improve the equivalent full well capacity or reduce the readout noise, so as to improve the dynamic range. The composite medium grid photosensitive detector can obtain better detection effect in scenes such as astronomical observation and remote sensing monitoring which need to capture high-brightness and weak-light targets at the same time.

Description

Technical Field

[0001] This invention relates to a readout circuit for improving dynamic range based on a composite dielectric gate photodetector, belonging to the field of integrated circuits. Background Technology

[0002] Currently, CCD and CMOS-APS are the two mainstream imaging devices, but they each have obvious technical limitations. CCD devices require complex timing control and high voltage driving, resulting in slow operating speed and difficulty in improving integration density; while CMOS-APS, although having higher integration density, suffers from a low pixel fill factor and limited full-well charge capacity due to its photodiode structure.

[0003] To address these issues, Chinese Patent Publication No. CN102938409A proposes an innovative composite dielectric gate dual-transistor photodetector. This device integrates reset, photosensitive, and readout functions into a single unit, forming a complete pixel cell. This design not only significantly improves the pixel fill factor but also boasts advantages such as high operating speed, high fill factor, and large full-well charge capacity, while remaining fully compatible with CMOS processes. In particular, its use of a threshold-variable MOSFET signal readout region gives it a significant inherent performance advantage over traditional CCDs and CMOS-APS.

[0004] Although composite dielectric gate dual-transistor photodetectors have significant advantages over traditional CCDs and CMOS-APSs in terms of integration density, fill factor, and response speed, several key technical bottlenecks still need to be overcome in practical applications. For example, under strong light imaging conditions (such as daytime outdoor scenes), the full-well charge capacity of existing devices is still insufficient, making it difficult to effectively handle high-intensity signals from direct sunlight or strong background skylight. This not only leads to premature saturation of the photoelectric signal but also significantly compresses the dynamic range of the device, affecting image quality. This deficiency is particularly evident in scenarios such as astronomical observation and remote sensing monitoring, where both bright and low-light targets need to be captured simultaneously. In addition, the readout noise level of this device is still relatively high. High readout noise not only reduces the signal-to-noise ratio of the image but also limits the detection sensitivity of the device in low-light environments, making it difficult to meet the stringent requirements of high-end scientific imaging, low-light night vision, and other fields. Summary of the Invention

[0005] To further improve the full-well charge capacity, this invention considers both device-level and circuit-level approaches. However, increasing the full-well charge capacity of a single device at the device level presents significant challenges in terms of pixel area, dark current, thermal noise, and process compatibility. From a circuit-level perspective, this invention examines existing CMOS-APS solutions and finds that one way to improve the effective full-well capacity is through delayed reset. That is, after the exposure stage, the floating diffusion (FD) node is not immediately reset, but rather a partial charge transfer is performed first to prevent premature FD saturation, thereby increasing the effective full-well capacity. CMOS-APS can also transfer the charge in the photodiode (PD) to the FD node in multiple stages through the transmission gate (TX), using multi-stage charge transfer to avoid FD saturation caused by a single charge transfer. This technique requires multi-pulse transmission gate control and multi-phase clocks within the pixel, increasing circuit design complexity. However, considering that the device structure of composite dielectric gate photodetectors differs from CMOS-APS, and their simplified pixel structure does not have an FD node, this approach cannot be applied to composite dielectric gate photodetectors.

[0006] This invention addresses the unique structure of composite dielectric grating photodetectors by designing a readout circuit to improve dynamic range. It incorporates an overflow electron discharge circuit for the composite dielectric grating photodetector pixels to discharge electrons overflowing from the saturated collection region, thereby increasing the equivalent full-well capacity. Furthermore, a specific timing sequence is designed to perform two consecutive readouts of the same pixel in both the analog and digital domains, further enhancing the equivalent full-well capacity or reducing readout noise to improve dynamic range. The specific solution is as follows:

[0007] A readout circuit for improving dynamic range based on a composite dielectric grating photodetector, the circuit comprising a composite dielectric grating photodetector pixel, an overflow electron discharge circuit, a clamping circuit, a switch S1, a precharge circuit, a comparator, a ramp generator, an AND gate, and a counter;

[0008] The overflow electron discharge circuit includes an external capacitor C. ext and reset transistor M Rst The external capacitor C ext The positive terminal is connected to the drain terminal of the composite dielectric gate photodetector pixel, and the negative terminal is connected to a negative voltage, the value of which is the same as the substrate voltage of the composite dielectric gate photodetector pixel; the reset transistor M Rst Parallel connection to external capacitor C ext At both ends, the reset transistor M Rst The drain terminal is connected to an external capacitor C. ext The positive terminal and the source terminal are connected to an external capacitor C. ext The negative terminal of the electrode has its gate end supplied with an external reset voltage V. Reset As the gate voltage.

[0009] Optionally, the clamping circuit includes an amplifier and a first transistor M1. The gate terminal of the first transistor M1 is connected to the output terminal of the amplifier, the drain terminal of the composite dielectric gate photodetector pixel is connected to the negative input terminal of the amplifier, and the positive input terminal of the amplifier is provided with a clamping voltage V externally. REF,CLAMP The source terminal of the first transistor M1 is connected to the drain terminal of the pixel of the composite dielectric gate photodetector, forming a feedback loop.

[0010] Optionally, the pre-charge circuit includes an integrating capacitor C. INT The second transistor M2; the drain of the first transistor M1 in the clamping circuit is connected to one end of switch S1, and the other end of switch S1 is connected to the integrating capacitor C. INT The source terminal of the second transistor M2 is connected to the positive input terminal of the comparator; in the pre-charge circuit, the gate terminal of the second transistor M2 is connected to the externally provided pre-charge voltage V. Precharge Connected, with the drain terminal connected to the external power supply V. DD Connected, the source terminal is connected to the integrating capacitor C INT The positive terminal is connected; the integrating capacitor C INT The negative terminal is grounded.

[0011] Optionally, the negative input of the comparator is provided with an external reference voltage V. REF,COMP Its output voltage V COMPOUT The input of the AND gate is used together with the read enable signal EN_READ; the output of the AND gate is connected to the input of the counter.

[0012] The comparator's output voltage V COMPOUT The result of the AND operation with the read enable signal EN_READ is used as the counting basis for the counter: when the enable signal of the counter is logic 1, the counter is enabled. During the timer's counting process, at the end of each clock cycle, the value of the counter output port increases by 1.

[0013] The present invention also provides a high-gain readout method for a composite dielectric grating photodetector, the method being implemented based on the above-described readout circuit, the high-gain readout method comprising:

[0014] Pre-exposure reset stage: Reset transistor M Rst Gate voltage V Reset Connect to high level Reset transistor M Rst Close and connect the capacitor C EXT Perform a reset;

[0015] Exposure stage: Switch S1 is open, and the current signal path of the composite dielectric grating photodetector pixel does not pass through the integrating capacitor C. INTThe comparator and counter, along with the clamping circuit amplifier, remain on the signal path, ensuring that the drain voltage of the composite dielectric gate photodetector pixel remains constant, at a stable voltage V. REF,CLAMP Pre-charge voltage V Precharge Being at a high level VDD does not affect the integrating capacitor C. INT ; Disabling the readout signal and enabling EN_READ disables the counter; Under the action of the gate-substrate forward bias, the MOS-C signal collection region of the composite dielectric gate photodetector pixel generates a depletion region in the substrate, realizing the collection of photogenerated carriers and achieving exposure;

[0016] Reset transistor M Rst In the on state, the reset transistor M Rst Gate voltage V Reset When connected to a low-level voltage V = 0, if the composite dielectric grating photodetector saturates under illumination, the external capacitor C... EXT Collect the overflowing electrons that cannot be collected after saturation; if the light is strong enough, the external capacitor C EXT After charging is complete, the amount of charge stored is:

[0017]

[0018] Among them, V REF,CLAMP The clamping voltage, V SUB For the substrate voltage of the composite dielectric grating photodetector, This refers to the capacitance value of the external capacitor.

[0019] Readout stage: Switch S1 is closed, pre-charge voltage V Precharge Pulling down the integrating capacitor C INT Precharge to external voltage V DD After that, the pre-charge voltage V Precharge Pulling the EN_READ signal high enables the readout, and the ramp generator provides the pixel gate of the composite dielectric gate photodetector with power from V... RampStart The voltage begins to rise gradually until it reaches V. RampEnd At this point, the read signal is turned off and EN_READ is enabled to read the data.

[0020] Reset Phase: After the readout phase ends, switch S1 is opened, and the circuit is in the reset phase. The drain voltage of the composite dielectric gate photodetector pixel remains constant, at a stable voltage V. REF,CLAMP .

[0021] This invention also provides a low-noise readout method for a composite dielectric grating photodetector, the method being implemented by the aforementioned readout circuit, wherein the low-noise readout method averages two consecutive readout results in the digital domain; the low-noise readout method includes:

[0022] Step S1.1: The composite dielectric grating photodetector pixel performs an exposure operation, utilizing an external capacitor C. EXT The electrons that cannot be collected after saturation are collected; at this point, the integrating capacitor C... INT Charging; the ramp generator applies a ramp voltage to the gate of the composite dielectric gate photodetector pixel, and a counter starts counting simultaneously. When the ramp voltage applied to the gate reaches the threshold of the readout transistor of the composite dielectric gate photodetector, the readout transistor turns on, and the integrating capacitor C... int Discharge, the discharge rate is determined by the number of photoelectrons collected by the composite dielectric grating photodetector and the external capacitance C. EXT The amount of stored charge is determined by the integrating capacitance C. INT After the discharge is completed, the counter stops counting synchronously, and the value of the counter at this time is recorded as the pixel grayscale value DN1;

[0023] Step S1.2, reduce the ramp generator voltage to the starting voltage V. RAMP Then, the integrating capacitor C INT Recharge and perform a second readout; the counter output value is recorded as the pixel grayscale value DN2.

[0024] Step S1.3, the pixel output grayscale value DN of the composite dielectric grating photodetector is: .

[0025] This invention also provides a low-noise readout method for a composite dielectric grating photodetector, the method being implemented based on the aforementioned readout circuit, wherein the low-noise readout method averages two readout results in the analog domain; the low-noise readout method includes:

[0026] Step S2.1: The composite dielectric grating photodetector pixel performs an exposure operation, utilizing an external capacitor C. EXT Collect the overflowing electrons that cannot be collected after saturation, and simultaneously adjust the integrating capacitor C. INT Charge;

[0027] Step S2.2: The ramp generator applies a constant voltage greater than the threshold voltage of the readout transistor of the composite dielectric gate photodetector pixel to the gate of the composite dielectric gate photodetector, and applies a voltage to the integrating capacitor C. INT Discharge is completed within a fixed time and then stopped by applying a constant voltage to the gate of the composite dielectric grating photodetector pixel.

[0028] Step S2.3: Reset the exposure signal within the pixel of the composite dielectric grating photodetector and perform a new exposure;

[0029] Step S2.4: Repeat the readout operation of step S2.2 once, with the discharge time being the same as S2.2;

[0030] Step S2.5, read the integrating capacitor C INT The remaining charge in the sample, and the average charge released during the two discharges, is denoted as the gray value DN.

[0031] The present invention also provides a method for reading out high full-well charge of a composite dielectric grating photodetector. The method is based on the above-mentioned readout circuit and the high full-well charge readout method sums the results of two consecutive readouts in the analog or digital domain.

[0032] The beneficial effects of this invention are:

[0033] By designing an overflow electron discharge circuit for the pixels of the composite dielectric grating photodetector in the readout circuit, electrons overflowing after the collection area of ​​the composite dielectric grating photodetector becomes saturated are discharged, thereby improving the equivalent full-well capacity. In addition, a special timing is designed to read out the same pixel twice in the analog and digital domains to improve the equivalent full-well capacity or reduce readout noise to improve the dynamic range. This enables the composite dielectric grating photodetector to achieve better detection results in scenarios such as astronomical observation and remote sensing monitoring that require simultaneous capture of bright and weak light targets. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a schematic diagram of the readout circuit based on a composite dielectric grating photodetector.

[0036] Figure 2 This is a timing diagram of the high-gain readout circuit based on a composite dielectric grating photodetector during its operation.

[0037] Figure 3 This is a timing diagram of the two readout stages of a digital domain sequential readout circuit based on a composite dielectric grating photodetector.

[0038] Figure 4 This is a timing diagram of the two readout stages of an analog domain sequential readout circuit based on a composite dielectric grating photodetector. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0040] Example 1

[0041] This embodiment provides a readout circuit for improving dynamic range based on a composite dielectric grating photodetector, such as... Figure 1 As shown, the circuit includes a composite dielectric grating photodetector pixel, an overflow electron discharge circuit, a clamping circuit, a switch S1, a pre-charge circuit, a comparator, a ramp generator, an AND gate, and a counter. The specific structure of the composite dielectric grating photodetector can be found in Chinese Patent Publication No. CN102938409A. The gate terminal of the composite dielectric grating photodetector pixel is connected to the ramp generator, the source terminal is grounded, and the drain terminal is connected to the input terminal of the clamping circuit.

[0042] The overflow electron discharge circuit includes an external capacitor C. ext and reset transistor M Rst External capacitor C ext The positive terminal is connected to the drain terminal of the composite dielectric gate photodetector pixel, and the negative terminal is connected to a negative voltage, the value of which is the same as the substrate voltage of the composite dielectric gate photodetector pixel; the reset transistor M Rst Parallel connection to external capacitor C ext At both ends, the reset transistor M Rst The drain terminal is connected to an external capacitor C. ext The positive terminal and the source terminal are connected to an external capacitor C. ext The negative terminal of the electrode has its gate end supplied with an external reset voltage V. Reset .

[0043] The clamping circuit consists of an amplifier and a transistor (hereinafter referred to as the first transistor M1); the pre-charge circuit consists of an integrating capacitor CINT and a transistor (hereinafter referred to as the second transistor M2).

[0044] In the clamping circuit, the gate terminal of the first transistor M1 is connected to the output terminal of the amplifier, the drain terminal of the composite dielectric gate photodetector pixel is connected to the negative input terminal of the amplifier, and the positive input terminal of the amplifier is provided with a clamping voltage V externally. REF,CLAMP The source terminal of the first transistor M1 is connected to the drain terminal of the pixel of the composite dielectric gate photodetector, forming a feedback loop.

[0045] The drain of the first transistor M1 is connected to one end of the switch S1, and the other end of the switch S1 is connected to the integrating capacitor C. INT The source terminal of the second transistor M2 is connected to the positive input terminal of the comparator; in the pre-charge circuit, the gate terminal of the second transistor M2 is connected to the externally provided pre-charge voltage V. Precharge Connected, with the drain terminal connected to the external power supply V. DD Connected, the source terminal is connected to the integrating capacitor C INT The positive terminal is connected; the integrating capacitor C INT The negative terminal is grounded.

[0046] The other input of the comparator is provided with an external reference voltage V. REF,COMP Its output voltage V COMPOUT The input of the AND gate is used together with the read enable signal EN_READ; the output of the AND gate is connected to the input of the counter, and the output voltage V of the comparator is... COMPOUT The result of the AND operation with the read enable signal EN_READ is used as the counting basis for the counter: when the enable signal of the counter is logic 1, the counter is enabled. During the timer's counting process, at the end of each clock cycle, the value of the counter output port increases by 1.

[0047] Typically, a readout circuit has three operating stages: exposure, readout, and reset. This embodiment, however, features a specially designed timing sequence for an additional overflow electron discharge circuit to achieve high-gain readout and improve dynamic range. This sequence comprises four stages: pre-exposure reset, exposure, readout, and reset. Specifically, a pre-exposure reset stage is added before the exposure stage to accommodate the external capacitor C. EXT Perform a reset so that the external capacitor C can be used during the exposure stage. EXT Electrons overflowing from the collection region of the composite dielectric grating photodetector after saturation, such as... Figure 2 As shown:

[0048] 1. During the pre-exposure reset stage, the reset transistor M is used. Rst Gate voltage V Reset Change from low level connection to high level connection Reset transistor M Rst Close and connect the capacitor C EXT Perform a reset.

[0049] 2. Exposure Stage: When switch S1 is open, the circuit is in the exposure stage, and the current signal path of the composite dielectric grating photodetector pixel does not pass through the integrating capacitor C. INT The comparator and counter circuits, along with the clamping circuit's amplifier, remain on the signal path, ensuring that the drain voltage of the composite dielectric gate photodetector pixel remains constant, at a stable voltage V. REF,CLAMP Pre-charge voltage V Precharge Being at a high level VDD does not affect the integrating capacitor C. INT Disabling the readout signal and enabling EN_READ disables the counter. Under the forward bias of the gate-substrate forward voltage, the MOS-C signal collection region of the composite dielectric gate photodetector pixel generates a depletion region in the substrate, enabling the collection of photogenerated carriers and achieving exposure.

[0050] During this stage, the reset transistor M Rst If the composite dielectric grating photodetector is saturated under illumination, the external capacitor C... EXTIt can collect the overflowing electrons that cannot be collected after saturation. If the light is strong enough, the external capacitor C... EXT After charging is complete, the amount of charge stored is: , where V REF,CLAMP The clamping voltage, V SUB For the substrate voltage of the composite dielectric grating photodetector, This refers to the capacitance value of the external capacitor.

[0051] 3. Readout Stage: When switch S1 is closed, the circuit is in the readout stage, and the pre-charge voltage V... Precharge Pulling down the integrating capacitor C INT Precharge to external voltage V DD The pre-charge voltage V thereafter Precharge Pulling the EN_READ signal high enables the readout, and the ramp generator provides the pixel gate of the composite dielectric gate photodetector with power from V... RampStart The voltage begins to rise gradually until it reaches V. RampEnd At this point, the read signal is turned off and EN_READ is enabled to read the data.

[0052] The drain voltage of the pixel in the composite dielectric grating photodetector is stabilized at V under the negative feedback of the clamping circuit. REF,CLAMP The ramp generator is maintained at the initial voltage V. RampStart The pre-charge voltage V remains unchanged. Precharge Pulling low, the second transistor M2 turns on and the integrating capacitor C... INT Precharged to V DD At this time, the voltage V on the upper plate of the integrating capacitor is X = V DD >V REF,COMP Therefore, the comparator outputs V COMPOUT The voltage is high. The pre-charge voltage V is high after pre-charging is complete. Precharge Raise to V DD At the same time, the read enable signal EN_READ is turned on, and V, which is also logic 1, is also enabled. COMPOUT The EN_READ signal is ANDed with the counter via an AND gate, enabling the counter to start counting. Simultaneously, the ramp generator produces a ramp voltage from V... RampStart The pixel-to-integrating capacitance C of the composite dielectric grating photodetector begins to rise. INT Discharge occurs, and the voltage V on the upper plate of the integrating capacitor... X Gradually decrease, when V X Drops below comparator reference level V REF,COMP When, the comparator outputs V COMPOUT The value is flipped from logic 1 to logic 0. This value, after being ANDed with EN_READ, outputs a logic 0 bit, which serves as the enable signal for the counter, stopping the counter from counting. The count value is V. OUT,CNTSubsequently, when the ramp voltage provided by the ramp generator reaches V... RampEnd When the read signal is turned off, EN_READ is enabled to read the data.

[0053] 4. Reset Phase: After the readout phase ends, switch S1 is opened, and the circuit is in the reset phase. The drain voltage of the composite dielectric gate photodetector pixel remains constant, at a stable voltage V. REF,CLAMP .

[0054] During this stage, a suitable negative bias voltage V is applied between the gate and the substrate of the composite dielectric gate photodetector pixel. Reset In a MOS-C chip, photoelectrons collected at the P-type substrate interface leak out through the electrodes connected to the substrate under the influence of an electric field. Disabling the read enable signal EN_READ ensures the counter enable signal remains at logic 0 via an AND gate, maintaining the counter's count value at V. OUT,CNT constant.

[0055] Example 2

[0056] This embodiment achieves low-noise or high full-well charge readout based on the dynamic range-enhancing readout circuit of the composite dielectric grating photodetector provided in Embodiment 1. Under the circuit structure described in Embodiment 1, the readout noise is reduced by averaging the results of two consecutive readouts in the digital domain, and the equivalent full-well charge is increased by repeatedly exposing the same pixel.

[0057] In step S1.1, the composite dielectric grating photodetector pixel performs an exposure operation. The composite dielectric grating photodetector collects photoelectrons, and the overflowing electrons that cannot be collected after saturation are handled by the external capacitor C. EXT Collection, at this time, for the integrating capacitor C INT Charging; The ramp generator applies a ramp voltage to the gate of the composite dielectric gate photodetector pixel, and a counter starts counting simultaneously. When the ramp voltage applied to the gate reaches the threshold of the composite dielectric gate photodetector readout transistor, the transistor turns on, and the integrating capacitor C... INT Discharge, the discharge rate is determined by the number of photoelectrons collected by the composite dielectric grating photodetector and the external capacitance C. EXT The amount of stored charge determines the integrating capacitance C. INT After the discharge is complete, the counter stops counting synchronously, and the value of the counter at this time is the gray value DN1 of that pixel;

[0058] Step S1.2, reduce the ramp generator voltage to the starting voltage V. RAMP Then, the integrating capacitor C INT Recharge and perform a second readout; the counter output value is the grayscale value DN2 of that pixel.

[0059] Step S1.3: Output grayscale value DN;

[0060] Step S1.3.1: Averaging the two consecutive readout results to reduce readout noise, the pixel output grayscale value DN of the composite dielectric grating photodetector is: .

[0061] The timing sequence of the readout circuit that reads twice consecutively in the digital domain is as follows: Figure 3 As shown, the circuit has four operating stages: exposure stage, first readout stage, second readout stage, and reset stage. The exposure stage, first readout stage, and reset stage are the same as those described in Example 1. A second readout stage is added after the first readout stage to perform a second continuous readout without resetting or re-exposure. The readout signal is sampled twice independently, and random timing noise is reduced by digital domain averaging, with a noise power reduction ratio of [percentage missing]. times.

[0062] Step S1.3.2, read the integrating capacitor C INT The remaining charge DN2 in the image, and the amount of charge released by the integrating capacitor during the two discharges, are recorded as the grayscale value accumulated from the two exposures. To achieve high full-well charge readout.

[0063] During the second readout phase, switch S1 is opened, disabling the read enable signal EN_READ. This, along with an AND gate, keeps the counter enable signal at logic 0, maintaining the counter's count value at V. OUT,CNT The slope voltage generated by the slope generator remains unchanged from V. RampEnd Reduce to V RampStart At this time, switch S1 is closed, and the read enable signal EN_READ is simultaneously activated, with V, which is also logic 1. COMPOUT The EN_READ signal is used as the enable signal for the counter through an AND gate, and the counter starts counting, enabling the circuit to perform the second continuous readout.

[0064] Averaging the two readouts in the analog domain can also reduce readout noise, as shown in the following scheme:

[0065] In step S2.1, the composite dielectric grating photodetector pixel performs an exposure operation. The composite dielectric grating photodetector collects photoelectrons, and the overflowing electrons that cannot be collected after saturation are handled by the external capacitor C. EXT Collect, and simultaneously integrate capacitor C INT Charge;

[0066] Step S2.2: The ramp generator applies a constant voltage greater than the threshold voltage of the readout transistor of the composite dielectric gate photodetector pixel to the gate of the composite dielectric gate photodetector, and applies a voltage to the integrating capacitor C. INTDischarge is completed within a fixed time and then stopped by applying a constant voltage to the gate of the composite dielectric grating photodetector pixel.

[0067] Step S2.3: Reset the exposure signal within the pixel of the composite dielectric grating photodetector and perform a new exposure;

[0068] Step S2.4: Repeat the readout operation of step S2.2 once, with the discharge time being the same as S2.2;

[0069] Step S2.5, output the grayscale value DN;

[0070] Step S2.5.1, read the integrating capacitor C INT The remaining charge in the sample, and the average charge released by the two discharges, are recorded as the gray value DN to achieve low-noise readout;

[0071] Step S2.5.2, read the integrating capacitor C INT The remaining charge in the well, and the amount of charge released by the two discharges, are recorded as the gray value DN accumulated by the two exposures to achieve high full-well charge readout.

[0072] The timing sequence of the readout circuit that reads twice consecutively in the analog domain is as follows: Figure 4 As shown, this circuit has six operating stages: first exposure stage, first readout stage, first reset stage, second exposure stage, second readout stage, and second reset stage. The first exposure stage is the same as the exposure stage in Embodiment 1; the second readout stage and the second readout stage are the same as the readout stage in Embodiment 1; the first reset stage and the second reset stage are the same as the reset stage in Embodiment 1. The ramp voltage of the ramp generator in the second exposure stage is V after the first reset stage. Reset Gradually increase to the ramp-start voltage V RampStart .

[0073] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A readout circuit for improving dynamic range based on a composite dielectric grating photodetector, characterized in that, The circuit comprises a composite material gate photosensitive detector pixel, an overflow electron discharge circuit, a clamping circuit, a switch S1, a pre-charge circuit, a comparator, a slope generator, an AND gate and a counter; The overflow electron discharge circuit comprises an external capacitor C ext and a reset transistor M Rst , wherein the positive pole of the external capacitor C ext is connected with the drain end of the compound medium gate photosensitive detector pixel, and the negative pole is connected with a negative voltage, the voltage value of the negative voltage being the same as the substrate voltage of the compound medium gate photosensitive detector pixel; the reset transistor M Rst is connected in parallel between the two poles of the external capacitor C ext , wherein the drain end of the reset transistor M Rst is connected with the positive pole of the external capacitor C ext , the source end is connected with the negative pole of the external capacitor C ext , and the gate end is provided with a reset voltage V Reset as the gate voltage by the outside. The pre-charge circuit comprises an integrating capacitor C INT and a second transistor M2; the drain of the first transistor M1 of the clamping circuit is connected with one end of a switch S1, the other end of the switch S1 is connected with the integrating capacitor C INT , the source of the second transistor M2 and the positive input of the comparator; in the pre-charge circuit, the gate of the second transistor M2 is connected with a pre-charge voltage V Precharge provided externally, the drain is connected with an external power supply V DD , and the source is connected with the positive pole of the integrating capacitor C INT ; the negative pole of the integrating capacitor C INT is grounded.

2. The readout circuit according to claim 1, characterized in that The clamping circuit comprises an amplifier and a first transistor M1, the gate end of the first transistor M1 is connected to the output end of the amplifier, the drain end of the composite dielectric gate photosensitive detector pixel is connected to the negative input end of the amplifier, the positive input end of the amplifier is provided with a clamping voltage V REF,CLAMP by an external source; the source end of the first transistor M1 is connected to the drain end of the composite dielectric gate photosensitive detector pixel, forming a feedback loop.

3. The readout circuit according to claim 2, characterized in that The negative input of the comparator is supplied with a reference voltage V REF,COMP The output voltage V COMPOUT The output of the AND gate is connected to the input of the counter. The output voltage V of the comparator COMPOUT The AND result of the read enable signal EN_READ and the comparator output voltage V is the basis of the counter count: when the counter enable signal is logic 1, the counter is enabled, and during the timer counting process, the counter output port value increases by 1 at the end of each clock cycle.

4. A high-gain readout method of a composite material gate photosensitive detector, the method being implemented based on the readout circuit for improving dynamic range of a composite material gate photosensitive detector according to any one of claims 1-3, the high-gain readout method comprising: Exposure reset stage: the gate voltage V Rst of the reset transistor M Reset is connected to the high level , the reset transistor M Rst is closed and the external hanging capacitor C EXT is reset; Exposure stage: switch S1 is off, the current signal path of the composite dielectric gate photosensitive detector pixel does not pass through the integration capacitor C INT and the comparator and the counter, while the amplifier of the clamping circuit is still in the signal path, so that the drain voltage of the composite dielectric gate photosensitive detector pixel remains constant at the stable voltage V REF,CLAMP ; the precharge voltage V Precharge is at a high level VDD, which does not affect the integration capacitor C INT ; turning off the readout signal enable EN_READ makes the counter not work; under the action of the gate-substrate forward bias of the MOS-C signal collection area of the composite dielectric gate photosensitive detector pixel, a depletion region is generated in the substrate to realize the collection of photo-generated carriers and exposure. Reset transistor M Rst In the open state, reset transistor M Rst Gate voltage V Reset Connect low voltage V = 0, if the composite dielectric gate photodetector is saturated under light, external capacitor C EXT Collect the overflow electrons that cannot be collected after saturation; if the light is strong enough, the external capacitor C EXT After charging, the amount of stored charge is: Wherein, V REF,CLAMP is a clamping voltage, V SUB is a compound dielectric gate photodetector substrate voltage, is a capacitance value of an external capacitor; Readout stage: switch S1 is closed, pre-charge voltage V Precharge pulls down the integration capacitor C INT pre-charged to the external voltage V DD , and then the pre-charge voltage V Precharge pulls up, opens the readout enable signal EN_READ, and the ramp generator provides a voltage from V RampStart starts to gradually rise until the voltage value reaches V RampEnd , at which time the readout signal enable EN_READ is closed to realize readout; Reset stage: after the readout stage, switch S1 is disconnected, the circuit is in the reset stage, the drain voltage of the composite dielectric grating photodetector pixel remains constant, and is in a stable voltage V REF,CLAMP .

5. A low-noise readout method for a composite-mediategated photodetector, characterized in that, The method is implemented based on the readout circuit for improving dynamic range of a composite material gate photosensitive detector according to any one of claims 1-3, the low-noise readout method comprising averaging the results of two consecutive readouts in the digital domain; The low-noise readout method comprises: Step S1.1, the composite medium gate photosensitive detector pixel is exposed, and an external capacitor C is used EXT overflow electrons which cannot be collected after saturation are collected, and the integral capacitor C INT is discharged; a slope generator applies a slope voltage to the gate of the composite medium gate photosensitive detector pixel, and a counter starts counting; when the slope voltage applied to the gate reaches the threshold value of the read transistor of the composite medium gate photosensitive detector, the read transistor is turned on, the integral capacitor C int is discharged, and the discharge rate is determined by the number of photoelectrons collected by the composite medium gate photosensitive detector and the external capacitor C EXT stores the amount of charge; the integral capacitor C INT is discharged, and the counter stops counting synchronously; at this time, the value of the counter is recorded as the pixel gray value DN1; Step S1.2, the ramp generator voltage is lowered to a start voltage V RAMP After, the integral capacitor C INT Recharge and the second readout, the counter output value is recorded as the pixel gray value DN2; Step S1.3, the composite medium gate photosensitive detector pixel output gray value DN is: .

6. A low-noise readout method for a composite-mediategated photodetector, characterized in that, The method is implemented based on the readout circuit for improving dynamic range of a composite material gate photosensitive detector according to any one of claims 1-3, the low-noise readout method comprising averaging the results of two consecutive readouts in the digital domain; Step S2.1, the composite medium gate photosensitive detector pixel is exposed, and the external capacitor C is used EXT overflow electrons which cannot be collected after saturation are collected, and the integral capacitor C INT is charged; Step S2.2, the ramp generator applies a constant voltage greater than the threshold of the readout transistor of the composite medium gated photodetector pixel to the gate of the composite medium gated photodetector pixel and integrates the charge on the integration capacitor C INT discharging, the discharging is stopped by stopping the application of the constant voltage on the gate of the composite medium gated photodetector pixel after the fixed time of discharging is completed; Step S2.3, resetting the exposure signal in the composite material gate photosensitive detector pixel and re-exposing once; Step S2.4, repeating the readout operation of step S2.2 once, the discharge time being the same as that of S2.2; Step S2.5, read the remaining charge amount in the integrating capacitor C INT The average of the charge amounts released by the two discharges is recorded as the gray value DN.

7. A method for reading out a high full-well capacity of a compound medium gate photodetector, characterized in that, The method is implemented based on the readout circuit for improving dynamic range of a composite material gate photosensitive detector according to any one of claims 1-3, the high-full-charge readout method comprising summing the results of two consecutive readouts in the analog or digital domain.

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