Semiconductor device and method of manufacturing the same

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. In one embodiment, a method includes forming a fin including a first material over a second material; a sacrificial gate is formed above the fin portion, and a channel region of the fin portion comprising the first material and the second material is directly located below the sacrificial gate and located between two non-channel regions of the fin portion comprising the first material and the second material; removing a non-channel region of the fin part; performing a process to replace the second material in the channel region of the fin with a third material; forming a source / drain feature in the non-channel region; removing the sacrificial grid electrode; removing the third material; and forming a gate over the fin portion.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having strained nanosheet channels and a method for manufacturing the same. Background Art

[0002] The electronics industry has an increasing demand for smaller and faster electronic devices that simultaneously support a wide range of increasingly complex and sophisticated functions. Consequently, there is a continuing trend within the semiconductor industry toward lower-cost manufacturing, higher-performance, and lower-power integrated circuits (ICs). To date, this demand has been met largely by reducing the size of semiconductor integrated circuits (e.g., minimum component size), thereby increasing production efficiency and reducing associated costs. However, such size reductions also increase the complexity of semiconductor manufacturing processes. Consequently, achieving continued advancements in semiconductor integrated circuits and devices requires similar advancements in semiconductor manufacturing processes and technologies.

[0003] Multi-gate devices are designed to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effects (SCEs). The fin field-effect transistor (FinFET) is one type of multi-gate device that has been proposed. FinFET gets its name from the fin-shaped structure that extends from the substrate on which it is formed to form the FET channel. Another multi-gate device is the gate-all-around (GAA) transistor, which is a multi-gate device developed to address the performance challenges associated with FinFETs. GAA devices are named for their gate structure, which extends completely around the channel and provides better electrostatic control than FinFETs. FinFET devices and GAA devices are compatible with traditional complementary metal-oxide-semiconductor (CMOS) processes. In addition, the three-dimensional structure of these devices allows them to be aggressively scaled down while maintaining gate control and reducing short-channel effects (SCEs). Summary of the Invention

[0004] An object of the present invention is to provide a semiconductor device and a method for manufacturing the same to solve at least one of the above problems.

[0005] Some embodiments of the present disclosure provide a method for manufacturing a semiconductor device, including forming a fin, the fin including a first material located above a second material; forming a sacrificial gate above the fin, wherein a channel region of the fin including the first material and the second material is directly below the sacrificial gate and between two non-channel regions of the fin including the first material and the second material; removing the non-channel region of the fin; performing a process to replace the second material in the channel region of the fin with a third material; forming a source / drain component in the non-channel region; removing the sacrificial gate; removing the third material; and forming a gate above the fin.

[0006] Some embodiments of the present disclosure further provide a method for manufacturing a semiconductor device. The method includes forming a first material layer above a second material layer; etching the first material layer and the second material layer to form a raised structure, the raised structure including a remaining portion of the first material layer and a remaining portion of the second material layer, wherein the remaining portion of the second material layer has a second volume; replacing or converting the second material layer to form a third material layer below the first material layer, wherein the third material layer has a third volume smaller than the second volume, wherein the third material layer strains the first material layer to form a strained first material layer; removing the third material layer; and forming a fourth material layer below the strained first material layer.

[0007] Some embodiments of the present disclosure provide a semiconductor device comprising a first source / drain component spaced apart from a second source / drain component in a first direction; a fin structure comprising a semiconductor nanosheet channel spaced apart from a mesa portion in a second direction, wherein an upper surface of the mesa portion defines a side plane perpendicular to the second direction; a gate structure located above the fin structure, wherein a lower portion of the gate structure is located between the mesa portion of the fin structure and the semiconductor nanosheet channel; a first inner spacer separating the first source / drain component from the lower portion; and a second inner spacer separating the second source / drain component from the lower portion; wherein the semiconductor nanosheet channel has a bottom surface adjacent to the first inner spacer, the lower portion of the gate structure, and the second inner spacer, wherein the bottom surface has a highest point at a maximum vertical distance from the side plane and a lowest point at a minimum vertical distance from the side plane; wherein a difference between the maximum vertical distance and the shortest vertical distance is less than 3 nanometers. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The following detailed description, taken in conjunction with the accompanying drawings, will provide a better understanding of the embodiments of the present invention. It should be emphasized that, in accordance with standard industry practice, many features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0009] Figure 1 is a plan view of a layout of a semiconductor device according to some embodiments of the present disclosure.

[0010] Figure 2 The flowchart of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure is shown.

[0011] Figure 3-30 The semiconductor device of some embodiments of the present disclosure is shown in FIG. Figure 2 perspective views or schematic cross-sectional views during various process stages of a method.

[0012] Figure 31 The flowchart of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure is shown.

[0013] Figures 32-45 31 shows a perspective view or schematic cross-sectional view of a semiconductor device according to some embodiments of the present disclosure during multiple process stages of the method according to FIG. 31 .

[0014] The reference numerals are as follows:

[0015] 10:Semiconductor substrate

[0016] 11: Unit Cell

[0017] 20: Active Zone

[0018] 30: Gate line

[0019] 100: Semiconductor devices (multi-gate devices, GAA devices)

[0020] 202: Base

[0021] 212: Epitaxial stacking

[0022] 214: epitaxial layer

[0023] 2141: Laterally concave surface

[0024] 216: epitaxial layer (isolation layer)

[0025] 217,225,226,227: Mask layer

[0026] 218: First mask layer

[0027] 219: Second mask layer

[0028] 220: semiconductor fin (fin)

[0029] 220a: Fin part

[0030] 221: Shallow Trench Isolation (STI)

[0031] 222: Sacrificial (dummy) gate structure

[0032] 223:Sacrificial gate dielectric

[0033] 224: Sacrificial gate electrode

[0034] 228: Platform (Platform part)

[0035] 230: spacer

[0036] 230g: Gate sidewall spacer

[0037] 230f: Fin sidewall spacer

[0038] 300:Nanosheet (semiconductor nanosheet channel)

[0039] 301: Lowest Nanosheet

[0040] 302: Middle nanosheet

[0041] 303: Top nanosheet (top semiconductor nanosheet channel)

[0042] 311:Top surface

[0043] 3110: Side plane

[0044] 312:lower surface

[0045] 313: First end surface

[0046] 314: Second end surface

[0047] 350: Gap (concave)

[0048] 360: Shoulders

[0049] 410: Barrier lining

[0050] 420,430: Intermediary material (intermediary layer)

[0051] 431: Concave surface

[0052] 350,450: concave part

[0053] 500: Internal spacer

[0054] 600: Source / drain component

[0055] 700: Interlayer dielectric material

[0056] 710: Etching stop layer

[0057] 712: Gate cavity

[0058] 722: Gate

[0059] 729: Lower part of the film

[0060] 731: Interface layer

[0061] 732: dielectric layer (gate dielectric layer)

[0062] 733: Gate electrode material

[0063] 1000,2000:Method

[0064] S1010,S1020,S1030,S1040,S1050,S1060,S1070,S1080,S1090,S1100,S1110,S1120,S1130,S1140,S1150,S1160,S1170,S1180,S1190,S2080,S2110,S2120,S2130,S2140,S2150,S2160,S2170,S2180,S2190: Operation

[0065] D1: Maximum vertical distance

[0066] D2: Shortest vertical distance

[0067] D3: Difference

[0068] T1, T2, T3, T5: Height (vertical thickness)

[0069] T4: Height Difference

[0070] H1, H2: Height (vertical distance)

[0071] W1, W2, W3, W5: width DETAILED DESCRIPTION

[0072] The following content provides many different embodiments or examples for implementing different components of the embodiments of the present invention. Specific examples of components and configurations are described below to simplify the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, if the description refers to a first component being formed on or located on a second component, it may include an embodiment in which the first component and the second component are in direct contact, and it may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component and the second component are not in direct contact. In addition, the embodiments of the present invention may repeat component symbols and / or letters in many examples. These repetitions are for the purpose of simplicity and clarity and do not in themselves represent a specific relationship between the various embodiments and / or configurations discussed.

[0073] In addition, spatially relative terms such as "over," "overlying," "above," "upper," "top," "under," "underlying," "beneath," "below," "lower," "bottom," "side," and / or other similar terms may be used herein to describe the relationship of one element or component to other elements or components as shown in the figures. Such spatially relative terms encompass not only the orientations shown in the figures, but also different orientations of the device in use or operation. The device may be rotated (e.g., 90 degrees or to other orientations), and the spatially relative descriptions used herein should be interpreted based on the rotated orientation.

[0074] In some embodiments herein, a "material layer" is a layer comprising at least 50% by weight of an identified material, such as at least 60% by weight of an identified material, at least 75% by weight of an identified material, at least 90% by weight of an identified material, or substantially 100% by weight of an identified material; and a layer that is itself a "material" comprising at least 50% by weight of an identified material, such as at least 60% by weight of an identified material, at least 75% by weight of an identified material, at least 90% by weight of an identified material, or substantially 100% by weight of an identified material. For example, in some embodiments, a titanium nitride layer and a titanium nitride layer are each a layer comprising at least 50% by weight of titanium nitride, a layer comprising at least 60% by weight of titanium nitride, a layer comprising at least 75% by weight of titanium nitride, a layer comprising at least 90% by weight of titanium nitride, or a layer comprising substantially 100% by weight of titanium nitride.

[0075] For the sake of brevity, conventional techniques associated with conventional semiconductor device fabrication may not be described in detail herein. In addition, the various tasks and processes described herein may be incorporated into more comprehensive processes or processes having additional functionality not described in detail herein. Specifically, the various processes in semiconductor device fabrication are well known, and therefore, for the sake of brevity, many conventional processes will be only briefly mentioned herein or will be omitted entirely without providing well-known process details. It will be more readily understood by those skilled in the art after reading this disclosure in its entirety that the structures disclosed herein can be used with a variety of technologies and can be integrated into a variety of semiconductor devices and products. In addition, it should be noted that the semiconductor device structure includes a varying number of components, and a single component shown in the diagram may also represent multiple components.

[0076] Figure 1 A unit cell 11, a portion of a semiconductor substrate 10 in a semiconductor device 100, is shown. As shown, parallel active regions 20 are spaced apart from one another and extend along the X-direction. Furthermore, parallel gate lines 30 are spaced apart from one another and extend along the Y-direction, which is perpendicular to the X-direction. Gate lines 30 can be formed of a conductive material, such as metal, and form the gate structure of device 100.

[0077] The semiconductor device 100 may be a multi-gate device 100. In various embodiments, the multi-gate device 100 may include a FinFET device, a GAA transistor, or other types of multi-gate devices. The multi-gate device 100 is formed over a substrate 10.

[0078] The multi-gate device 100 may include a P-type metal oxide semiconductor device 100 or an N-type metal oxide semiconductor multi-gate device 100. Specific examples may be presented herein and referred to as FinFET devices 100 due to their fin-like structures. An embodiment of a multi-gate transistor referred to as a GAA device 100 is also presented herein. The GAA device 100 includes any device having a gate structure (e.g., surrounding a portion of a channel region) or a portion of a gate structure formed on four sides of a channel region. The devices presented herein also include embodiments having a channel region disposed in a nanosheet channel, a nanowire channel, a strip channel, and / or other suitable channel structures. As used herein, the term "nanosheet channel" is intended to include nanowire channel and strip channel structures.

[0079] In some embodiments, the substrate 10 may be a semiconductor substrate, such as a silicon substrate. The substrate 10 may include various layers, including a conductive layer or an insulating layer formed on the semiconductor substrate. As is known in the art, the substrate 10 may include various doping configurations, depending on the design requirements. The substrate 10 may also include other semiconductors, such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, the substrate 10 may include a compound semiconductor and / or an alloy semiconductor. In addition, the substrate 10 may optionally include an epitaxial layer, may be strained to enhance performance, the substrate 10 may include a silicon-on-insulator (SOI) structure, and / or have other suitable enhancement features.

[0080] The embodiments presented herein are devices that may have one or more channel regions (e.g., nanosheets) associated with a gate structure. For example, a stack of vertically spaced nanosheet channels may be provided. However, one of ordinary skill will appreciate that these teachings may be applied to a single channel (e.g., a single nanosheet) or any number of channels. One of ordinary skill will appreciate other examples of semiconductor devices that may benefit from aspects of the present disclosure.

[0081] In some embodiments, an interposer layer is used to apply stress to a nanosheet channel to form a strained nanosheet channel. In some embodiments, an interposer layer is used during the formation of a gate cavity around the nanosheet channel before gate metal deposition to prevent or reduce damage to the nanosheet channel. In some embodiments, it can also prevent or reduce diffusion of semiconductor nanosheets.

[0082] As described herein, in some embodiments, processes are performed to provide strained nanosheet channels. Specifically, some processes involve applying stress to the nanosheet channels to form the strained nanosheet channels. In some embodiments, a sacrificial layer beneath the semiconductor nanosheet, or sacrificial layers beneath and above the semiconductor nanosheet, is at least partially removed. The remaining portion of the sacrificial layer and / or the newly introduced intervening layer are then treated to induce volume expansion. This expansion applies stress to the semiconductor nanosheet.

[0083] In some embodiments, an interposer is formed below the semiconductor nanosheet, or above and below the semiconductor nanosheet. The interposer is then removed. In some embodiments, the interposer is removed using a highly selective process such that little or no semiconductor nanosheet is removed by the highly selective process.

[0084] Furthermore, the interposer can prevent diffusion of semiconductor nanosheets. For example, the sacrificial layer can be a germanium source, such as silicon germanium (SiGe). When a germanium source is present during subsequent processing of an n-type gate, such as during a thermal process, germanium can diffuse from the sacrificial layer into the phosphorus-doped n-type source / drain components and enhance phosphorus diffusion from the n-type source / drain components into the sacrificial layer. Consequently, n-type mobility may be reduced. High n-type doping levels may result in increased interdiffusion.

[0085] In the embodiments herein, this diffusion and mobility loss are avoided by removing the germanium source prior to the thermal process. Specifically, some embodiments remove a sacrificial layer of silicon germanium from the channel region. A germanium-free interposer layer can then be formed to replace the silicon germanium layer. In some other embodiments, the silicon germanium layer can be converted into a silicon germanium oxide layer. For example, in some embodiments, a material with a higher dielectric value can be formed to replace the original silicon germanium layer. This conversion or replacement can reduce diffusion.

[0086] The embodiments of the present disclosure provide advantages over the prior art, although it is understood that other embodiments may provide different advantages. Not all advantages are necessarily discussed herein, and not all embodiments are required to have a particular advantage.

[0087] Reference Figure 2 , which illustrates a method 1000 for fabricating a semiconductor device 100 (e.g., a multi-gate device) according to various embodiments. The method 1000 is discussed below with reference to a GAA device having a channel region, which may be referred to as a nanosheet or a nanosheet channel, and may include various geometries (e.g., cylindrical, bar-shaped) and various sizes. However, it will be understood that aspects of the method 1000 may be equally applicable to other types of multi-gate components without departing from the scope of the present disclosure. In some embodiments, the method 1000 may be used to fabricate the multi-gate devices described above with reference to FIG. Figure 1 The multi-gate device 100 is described. Therefore, one or more aspects discussed above with reference to the multi-gate device 100 may also be applied to the method 1000. It will be appreciated that the method 1000 includes steps characteristic of a complementary metal oxide semiconductor (CMOS) technology process flow and, therefore, is only briefly described herein. Furthermore, additional steps may be performed before, after, and / or during the method 1000.

[0088] Method 1000 is referenced below Figure 3-30 Provide a description. Figure 3-30 A perspective view of a multi-gate device 100 is provided, taken along a plane generally parallel to Figure 1A schematic cross-sectional view of a plane of the multi-gate device 100 defined by the X-axis and the Z-axis in FIG. Figure 1 1 is a schematic cross-sectional view of a plane of the multi-gate device 100 defined by the Y-axis and the Z-axis in FIG. 1 , illustrating various manufacturing stages according to the method 1000 .

[0089] Furthermore, the semiconductor device 100 may include various other devices and components, such as other types of devices, such as additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, static random access memory (SRAM), and / or other logic circuits, but is simplified for a better understanding of the concepts of the present disclosure. In some embodiments, the semiconductor device 100 includes a plurality of semiconductor devices (e.g., transistors), including PFETs, NFETs, etc., that may be interconnected. In addition, it should be noted that the process steps of the method 1000, including any description provided with reference to the accompanying drawings, are merely exemplary and are not intended to be limiting beyond what is specifically recited in the appended claims.

[0090] In operation S1010, the method 1000 provides a substrate 202, such as Figure 3 As shown. In some embodiments, substrate 202 may be a semiconductor substrate, such as a silicon (Si) substrate. Substrate 202 may include various layers, including conductive layers or insulating layers formed on the semiconductor substrate. As is known in the art, substrate 202 may include various doping configurations depending on design requirements. For example, different doping profiles (e.g., p-type wells, n-type wells) may be formed in regions on substrate 202 designed for different device types (e.g., n-type field effect transistors (NFETs) and p-type field effect transistors (PFETs)). Suitable doping may include ion implantation and / or diffusion processes of dopants, such as boron (B) for p-type wells and phosphorus (P) for n-type wells. In some embodiments, substrate 202 includes a single crystalline semiconductor layer on at least a portion of its surface. Substrate 202 may include a single crystalline semiconductor material, such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. Alternatively, substrate 202 may include a compound semiconductor and / or an alloy semiconductor. In the illustrated embodiment, substrate 202 is made of crystalline Si.

[0091] like Figure 3 As shown, at operation S1020, method 1000 ( Figure 2) is to form one or more epitaxial layers above the substrate 202. In some embodiments, an epitaxial stack 212 is formed above the substrate 202. The epitaxial stack includes a plurality of epitaxial layers 214 of a first composition, and epitaxial layers 216 of a second composition interposed between the epitaxial layers 214. The first composition and the second composition may be different. Possible embodiments include providing a first composition and a second composition having different oxidation rates and / or etching selectivities. In one embodiment, the epitaxial layer 214 is silicon germanium (SiGe) and the epitaxial layer 216 is silicon. In embodiments where the epitaxial layer 214 includes SiGe and the epitaxial layer 216 includes silicon, the oxidation rate of silicon is less than the oxidation rate of silicon germanium. Note that, Figure 3 Three epitaxial layers 214 and three epitaxial layers 216 are shown for illustrative purposes only and are not intended to limit the scope of the invention beyond the scope of the claims. It will be appreciated that any number of epitaxial layers may be formed in epitaxial stack 212; the number of epitaxial layers depends on the desired number of channel regions for GAA device 100. In some embodiments, the number of epitaxial layers 216 is between 2 and 10, such as 6 or 7 layers.

[0092] In some embodiments, the epitaxial layer 214 has a thickness ranging from about five nanometers to about fifteen nanometers. The epitaxial layer 214 can have a substantially uniform thickness. In some embodiments, the epitaxial layer 216 has a thickness ranging from about five nanometers to about fifteen nanometers. In some embodiments, the stacked epitaxial layer 216 has a substantially uniform thickness. As described in more detail below, the epitaxial layer 216 can serve as a channel region of a subsequently formed multi-gate device, and the epitaxial layer 216 has a thickness selected based on device performance considerations. The epitaxial layer 214 can be used to define the spacing between adjacent channel regions of a subsequently formed multi-gate device, and the epitaxial layer 214 has a thickness selected based on device performance considerations.

[0093] For example, epitaxial growth of epitaxial stack 212 can be performed by a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth process. In some embodiments, the epitaxially grown layers, such as epitaxial layer 216, comprise the same material as substrate 202. In some embodiments, epitaxial layer 214 and the epitaxially grown layers of epitaxial layer 216 comprise a different material than substrate 202. As described above, in at least some examples, epitaxial layer 214 comprises epitaxially grown Si. 1-x Ge xlayer (where x is from about 10% to about 55%), and epitaxial layer 216 includes an epitaxially grown silicon (Si) layer. Alternatively, in some embodiments, either epitaxial layer 214 or epitaxial layer 216 may include other materials such as germanium, a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP, or a combination thereof. As discussed, the materials of epitaxial layer 214 and epitaxial layer 216 may be selected based on characteristics that provide different oxidation characteristics, etching selectivities, and the like. In various embodiments, epitaxial layer 214 and epitaxial layer 216 are substantially free of dopants (i.e., have a dopant density from about 0 cm2 to about 10 cm3). -3 to about 1×10 17 cm -3 extrinsic doping concentration), where, for example, no intentional doping is performed during epitaxial layer 214 and epitaxial layer 216. In some embodiments, the bottom and top layers of epitaxial stack 212 are SiGe layers (not shown). In alternative embodiments, the bottom layer of epitaxial stack 212 is a Si layer and the top layer of epitaxial stack 212 is a SiGe layer (not shown).

[0094] In some embodiments, the method includes forming a mask layer 217 over the epitaxial stack 212, such as Figure 3 As shown. The mask layer 217 includes a first mask layer 218 and a second mask layer 219. The first mask layer 218 can be a pad oxide layer made of silicon oxide, which can be formed by thermal oxidation. The second mask layer 219 can be made of silicon nitride (SiN), which can be formed by chemical vapor deposition (CVD), including low-pressure CVD (LPCVD) and plasma-assisted CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other suitable processes.

[0095] like Figure 4 As shown, in operation S1030, method 1000 ( Figure 2 ) is to pattern the epitaxial stack 212 to form the semiconductor fin 220. For example, the mask layer 217 can be patterned into a mask pattern using a patterning step including optical lithography and etching. According to operation S1030, the epitaxial stack 212 is then patterned through the opening defined in the patterned mask layer 217 in an etching process, such as dry etching (e.g., reactive ion etching), wet etching, and / or other suitable processes. The stacked epitaxial layers 214 and 216 are thereby patterned into the fin 220. Although Figure 4The formation of two fins 220 is shown, but any suitable number of fins may be formed.Trenches are etched between adjacent fins 220.

[0096] In various embodiments, each fin 220 includes an upper portion of the interleaved epitaxial layer 214 and the epitaxial layer 216, and a bottom portion formed by the etched substrate 202. Each fin 220 protrudes upward from the substrate 202 in the Z direction and extends longitudinally in the X direction. The sidewalls of each fin 220 can be straight or sloped (not shown). Figure 4 The other fins may be spaced apart in the Y direction. The fins 220 may have the same width or different widths.

[0097] like Figure 5 As shown, according to operation S1040, method 1000 ( Figure 2 ) A shallow trench isolation (STI) component (also referred to as an STI component) 221 is formed in a trench adjacent to each fin 220 using a dielectric layer. The STI component 221 can be formed by first filling the trench around each fin 220 with a dielectric material layer to cover the top surface and sidewalls of the fin 220 (not shown). The dielectric material layer may include one or more dielectric materials. Suitable dielectric materials for forming the dielectric layer may include silicon oxide, silicon nitride, silicon carbide, fluorosilicate glass (FSG), low-K dielectric materials, and / or other suitable dielectric materials. The dielectric material may be deposited by any suitable technique, such as thermal growth, flowable CVD (FCVD), HDP-CVD, PVD, ALD, and / or spin coating. The dielectric material layer is then planarized by using, for example, a chemical mechanical planarization (CMP) process until the top surface of the mask layer 217 is exposed, and the dielectric material layer is recessed to form a shallow trench isolation (STI) component (also referred to as an STI component) 221, such as Figure 5 As shown. In the embodiment shown, STI features 221 are formed on substrate 202. Any suitable etching technique, including dry etching, wet etching, RIE, and / or other etching methods, can be used to recess the isolation features 221. In some embodiments, an anisotropic dry etch is used to selectively remove the dielectric material of the isolation features 221 without etching the fins 220. The mask layer 217 (e.g., Figure 4 The mask layer 217 may also be removed before, during, and / or after recessing the isolation features 221. In some embodiments, the mask layer 217 is removed before recessing the isolation features 221. In some embodiments, the mask layer 217 is removed by the etchant used to recess the isolation features 221.

[0098] like Figure 6As shown, in operation S1050, method 1000 ( Figure 2 ) to form a sacrificial (dummy) gate structure 222. Figure 6 One half of the sacrificial gate structure 222 is shown. Figure 6 The formation of one sacrificial gate structure 222 is shown, but any suitable number of sacrificial gate structures may be formed. Each sacrificial gate structure 222 protrudes upward from the substrate 202 in the Z direction and extends longitudinally in the Y direction. Figure 6 In the embodiment, other sacrificial gate structures are spaced apart along the X direction.

[0099] Sacrificial gate structures 222 are formed over portions of the fins 220 that will become the channel regions. The sacrificial gate structures 222 may extend over multiple adjacent fins 220. The sacrificial gate structures 222 are located directly over and define the channel region of the GAA device to be formed. Each sacrificial gate structure 222 includes a sacrificial gate dielectric 223 and a sacrificial gate electrode 224 overlying the sacrificial gate dielectric 223.

[0100] A sacrificial gate structure 222 is formed by first blanket depositing a sacrificial gate dielectric layer over the fin 220. Then, a sacrificial gate electrode layer is blanket deposited over the sacrificial gate dielectric layer and over the fin 220. The sacrificial gate dielectric layer comprises silicon oxide, silicon nitride, or a combination thereof. In some embodiments, the thickness of the sacrificial gate electrode layer is in a range of about one hundred nanometers to about two hundred nanometers. The sacrificial gate electrode layer comprises silicon, such as polycrystalline silicon or amorphous silicon. In some embodiments, the thickness of the sacrificial gate dielectric layer is in a range of about 1 nanometer to about 5 nanometers. In some embodiments, the sacrificial gate electrode layer is subjected to a planarization process. The sacrificial gate dielectric layer and the sacrificial gate electrode layer are deposited using CVD, including LPCVD and PECVD, PVD, ALD or other suitable processes. A mask layer 225 is formed over the sacrificial gate electrode layer. The mask layer 225 may include a mask layer 226, such as silicon oxide, and a mask layer 227, such as silicon nitride. Subsequently, as Figure 6 As shown, the mask layer 225 is patterned to pattern the sacrificial gate electrode layer and the sacrificial gate dielectric layer into a sacrificial gate structure 222 . The sacrificial gate structure 222 includes a sacrificial gate dielectric 223 and a sacrificial gate electrode 224 .

[0101] After forming the sacrificial gate structure 222, each fin 220 is partially uncovered or exposed on opposite sides of the sacrificial gate structure 222, thereby defining a source / drain (S / D) region. In this disclosure, "source / drain region" or "source / drain feature" may refer to a source or a drain, individually or collectively, depending on the context.

[0102] Now refer to Figure 7 In operation S1060, method 1000 ( Figure 2 ) A spacer material is deposited and then etched to form spacers 230 on the sidewalls of the sacrificial gate structure 222 and the sidewalls of the fin 220. The spacers 230 may include a spacer material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN film, silicon oxycarbide, SiOCN film, and / or combinations thereof. In some embodiments, each spacer 230 may include multiple layers, such as a liner layer and a main spacer layer on the liner layer.

[0103] For example, the spacer 230 may be formed by depositing a spacer material including a liner material layer and a dielectric material layer over the sacrificial gate structure 222 using, for example, a subatmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, or other suitable processes.

[0104] like Figure 8 As shown, in operation S1070, after depositing the liner material layer and the dielectric material layer, etching back (e.g., anisotropically) is performed to expose and remove a portion 220a of the fin 220 adjacent to the sacrificial gate structure 222 and not covered by the sacrificial gate structure 222 (e.g., the source / drain region). Figure 9 yes Figure 8 , along a single fin 220 and across a central sacrificial gate 222 located between the illustrated portions of two adjacent sacrificial gates 222 .

[0105] Also refer to Figure 8 and Figure 9The liner material layer and the dielectric material layer may remain on the sidewalls of the sacrificial gate structure 222 as gate sidewall spacers 230g and on the sidewalls of the fin as fin sidewall spacers 230f. In some embodiments, the etch-back process may include a wet etch process, a dry etch process, a multi-step etch process, and / or a combination thereof. The spacer 230 may have a thickness ranging from approximately five nanometers to approximately twenty nanometers.

[0106] The method 1000 continues with operation S1080 to remove the epitaxial layer 214, ie, the silicon germanium (SiGe) layer 214, such as Figure 10 shown. Figure 11 yes Figure 10 , which is a cross-sectional view of an X-section of the manufacturing stage along a single fin 220 and spanning a central sacrificial gate structure 222 between the shown portions of two adjacent sacrificial gate structures 222. Figure 12 yes Figure 11 , which is a cross-sectional view of the Y section of the manufacturing stage along the sacrificial gate structure 222 and across the two fins 220.

[0107] Also refer to Figure 10-12 After epitaxial layer 214 is removed, epitaxial layer 216 remains in fin 220. In embodiments where epitaxial layer 214 is formed of silicon germanium (SiGe) and epitaxial layer 216 is formed of silicon (Si), epitaxial layer 214 can be removed, for example, by an NMOS silicon germanium removal process. In some embodiments, the removal process can use an etchant that etches silicon germanium at a higher etch rate than silicon, such as NH4OH:H2O2:H2O (ammonia peroxide mixture, APM), H2SO4+H2O2 (sulfuric acid peroxide mixture, SPM), or the like. Other suitable processes and materials may be used. This etching process removes epitaxial layer 214.

[0108] Nanosheets 300 are formed from isolation layer 216 and define fins 220, for example, for an n-type device. The illustrated nanosheets 300 include a lowermost nanosheet 301 adjacent to the terrace portion, a middle nanosheet 302, and an uppermost nanosheet 303. In some embodiments, there may be no or more than one middle nanosheet 303 in each fin 220. In some embodiments, there may be only a single nanosheet 300 in each fin 220. Voids 350 are formed between vertically adjacent nanosheets 300. Each void 350 is bounded by an uppermost surface 311 (the upper surface of terrace 228 of each nanosheet 300) and a lowermost surface 312 (the lower surface of each nanosheet 300). Each surface 311 and 312 extends in the X-direction from a first end surface 313 to a second end surface 314.

[0109] The method 1000 may continue to operation S1090 where a barrier liner 410 is formed over the structure of the partially fabricated device 100, such as Figure 13 1 is a cross-sectional view of an X-section at a next manufacturing stage, which is a cross-sectional view of the central sacrificial gate structure 222 along a single fin 220 and across the illustrated portions of two adjacent sacrificial gate structures 222 .

[0110] like Figure 13 As shown, the barrier liner 410 covers each uppermost surface 311, each lowermost surface 312, each first end surface 313 and each second end surface 314 of the nanosheet 300 and covers the platform portion 228. The exposed surface of the fin 220 may be covered by the barrier liner 410. The barrier liner 410 may further cover the gate sidewall spacer 230g. In some embodiments, the barrier liner 410 is blanket deposited in an isotropic process. The barrier liner 410 may be formed of any suitable material. The material forming the barrier liner 410 may be selected to minimize expansion during a subsequent process. For example, the material forming the barrier liner 410 may not be affected by subsequent processes, such as oxidation processes such as thermal oxidation processes. Figure 13 As shown, barrier liner 410 does not fill void 350 .

[0111] The method 1000 also continues with operation S1100 to form an interposer material 420 on the barrier liner 410, such as Figure 14 shown. Figure 14 ,and Figure 13 Similarly, an X-cut cross-sectional view at a next stage of fabrication is shown, which is a cross-sectional view along a single fin 220 and across the central sacrificial gate structure 222 between the illustrated portions of two adjacent sacrificial gate structures 222 .

[0112] like Figure 14 As shown, interposing material 420 covers each uppermost surface 311, each lowermost surface 312, each first end surface 313, and each second end surface 314 of nanosheet 300, as well as barrier liner 410 above mesa portion 228, and interposing material 420 is located above gate sidewall spacer 230g. In some embodiments, interposing material 420 fills gap 350 such that interposing material 420 merges, for example, from uppermost surface 311 to lowermost surface 312.

[0113] In some embodiments, interposer material 420 is blanket deposited using an isotropic process. Interposer material 420 can be formed from any suitable material. Interposer material 420 can be selected to provide a desired expansion during subsequent processing. For example, interposer material 420 can be selected based on its response to an oxidation process. In some embodiments, interposer material 420 is silicon (Si) or silicon germanium (SiGe).

[0114] Reference Figure 15 Specifically, the method 1000 may include performing a process at operation S1110 to expand the intermediary material 420 and apply stress to the nanosheets 300 (301-303). For example, an oxidation process may be performed to convert the intermediary material 420 into an oxidized material.

[0115] In other words, the interposer material 420 is converted to a processed interposer material 430 , such as an oxidized interposer material 430 . In some embodiments, the barrier liner 410 remains between the processed interposer material 430 and the semiconductor material of the nanosheet 300 and the mesa portion 228 of the fin 220 .

[0116] As shown, in the unconfined region, the treated intermediary material 430 grows to a greater thickness than the original intermediary material 420. This is limited by the barrier liner 410 on the nanosheet 300. In the confined region of the void 350, the increase in thickness is limited by the barrier liner 410 on the nanosheet 300 or the terrace portion 228. As a result, a compressive stress can be applied to the nanosheet 300 and the terrace portion 228 through the treated intermediary material 430. As a result, the nanosheet 300 and the terrace portion 228 are strained.

[0117] Reference Figure 16 At operation S1120 , the method 1000 may include recessing the processed interposer material 430 . Figure 16 FIG. 2 is a cross-sectional view of an X-section at a next manufacturing stage, which is a cross-sectional view of the central sacrificial gate structure 222 along a single fin 220 and spanning between the illustrated portions of two adjacent sacrificial gate structures 222 . Figure 17 yes Figure 16 , which is a cross-sectional view of the Y section of the manufacturing stage along the sacrificial gate 222 and across the two fins 220.

[0118] Also refer to Figure 16 and Figure 17, the treated interposer material 430 can be removed from the gate sidewall spacer 230g, from the end surface 313 of the nanosheet 300 and the mesa portion 228, from the end surface 314 of the nanosheet 300 and the mesa portion 228, from a portion of the uppermost surface 311, and from a portion of the lowermost surface 312. Specifically, the treated interposer material 430 and the barrier liner 410 can be laterally etched to form recesses 450 between the uppermost surface 311 and the lowermost surface 312.

[0119] Reference Figure 18 In operation S1130 , the method 1000 may include forming inner spacers 500 . Figure 19 yes Figure 18 , which is a cross-sectional view of the central sacrificial gate structure 222 along a single fin 220 and spanning between the shown portions of two adjacent sacrificial gate structures 222.

[0120] Also refer to Figure 18 and Figure 19 , an inner spacer 500 is formed in the recess 450 and adjacent to the remaining processed interposer material 430 and barrier liner 410. In some embodiments, the inner spacer 500 can be formed of silicon oxide, silicon nitride, silicon carbide, silicon carbon nitride, silicon oxycarbide, silicon carbon oxynitride, and / or other suitable dielectric materials. The inner spacer 500 can be formed by atomic layer deposition (ALD) or any other suitable method. As shown in the figure, after depositing the material forming the inner spacer 500, the material can be trimmed from the ends of the nanosheet 300.

[0121] exist Figure 20 In operation S1140 , the method 1000 further includes forming source / drain features 600 . Furthermore, in operation S1150 , the method 1000 further includes forming an inter-layer dielectric (ILD) material 700 .

[0122] Figure 21 yes Figure 20 , and is a cross-sectional view of the central sacrificial gate structure 222 along a single fin 220 and spanning between the illustrated portions of two adjacent sacrificial gate structures 222 .

[0123] Also refer to Figure 20 and Figure 21Source / drain features 600 are formed above fin 220 and between inner spacers 500. Source / drain features 600 may be grown epitaxially. For an n-channel FET, the epitaxial material may include one or more layers of Si, SiP, SiC, and SiCP, or for a p-channel FET, the epitaxial material may include one or more layers of Si, SiGe, or Ge. For a p-channel FET, the source / drain may also include boron (B). The source / drain epitaxial layers may be formed by an epitaxial growth method using CVD, ALD, or molecular beam epitaxy (MBE).

[0124] In addition, an interlayer dielectric (ILD) material 700 is formed over the source / drain features 600. As shown, an etch stop layer 710 may be formed over the source / drain features 600 before forming the ILD material 700.

[0125] exist Figure 22 In operation S1160 , the method 1000 further includes removing the sacrificial gate structure 222 to form gate cavities 712 . Figure 23 yes Figure 22 , which is a cross-sectional view of the X-section of the manufacturing stage along a single fin 220 and spanning a central gate cavity 712 between the shown portions of two adjacent gate cavities 712, as shown, the gate sidewall spacer 230g defines the gate cavity 712.

[0126] Reference Figure 24 In operation S1170 , method 1000 also includes removing the treated interposer material 430 and remaining portions of barrier liner 410 . Figure 25 yes Figure 24 , which is a cross-sectional view of an X-section of the manufacturing stage of , which is a cross-sectional view along a single fin 220 and spanning the central gate cavity 712 between the shown portions of two adjacent gate cavities 712. Figure 26 yes Figure 24 , which is a cross-sectional view of the Y section of the manufacturing stage along the single gate cavity 712 and across the two fins 220.

[0127] Also refer to Figure 24-26 After removing the processed interposer material 430 and the barrier liner 410 , the gate cavity 712 extends downward and surrounds the nanosheet 300 and is bounded by the inner spacer 500 in the X direction.

[0128] Reference Figure 27 In operation S1180 , the method 1000 further includes forming a gate 722 in the gate cavity 712 . Figure 28 yes Figure 27, which is a cross-sectional view of an X-section of the manufacturing stage of , which is a cross-sectional view along a single fin 220 and spanning a central gate 722 between the shown portions of the two gates 722. Figure 29 yes Figure 24 , which is a cross-sectional view along a single gate 722 and across two fins 220 .

[0129] Also refer to Figure 27-Figure 29 , the gate 722 can be formed according to a replacement metal gate process. In some embodiments, the replacement metal gate process includes forming an interfacial layer 731 on the uppermost surface 311 and the lowermost surface 312. The interfacial layer 731 may include a silicon monoxide (SiO2) layer. Alternatively, the interfacial layer 731 may selectively include HfSiO or SiON. The interfacial layer 731 can be formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), thermal oxidation, wet oxidation, radical oxidation (RadOx), or a combination of the foregoing. In some embodiments, the interfacial layer 731 is selectively formed on the semiconductor material of the nanosheet 300 and the platform portion 228, and is not formed on the internal spacer 500.

[0130] In some embodiments, the replacement metal gate process includes forming a dielectric layer 732 over the interface layer 731. According to some embodiments, the gate dielectric layer 732 includes silicon oxide, silicon nitride, or a combination thereof. In some embodiments, the gate dielectric layer 732 is a high-k dielectric material, and in these embodiments, the gate dielectric layer 732 may have a k value greater than approximately 7.0 and may include a metal oxide or silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The gate dielectric layer 732 may be formed by molecular beam deposition (MBD), ALD, CVD, PECVD, metal organic CVD (MOCVD), PVD, thermal oxidation, combinations thereof, or other suitable techniques.

[0131] In some embodiments, the gate dielectric layer 732 is formed on the interfacial layer 731 of semiconductor material covering the nanosheets 300 and the mesa portion 228 , as well as on the inner spacers 500 and the shallow trench isolation (STI) features 221 .

[0132] In some embodiments, the replacement metal gate process includes forming a gate electrode material 733 over the gate dielectric layer 732 to fill the gate cavity 712. The gate electrode material 733 is deposited on the gate dielectric layer 732 and fills the remaining portion of the gate cavity 712. The gate electrode material 733 can be a metal-containing material such as TiN, TaN, TaC, Co, Ru, Al, combinations thereof, or multiple layers thereof. For example, although a single layer of gate electrode material is shown, any number of work function regulating layers can be deposited.

[0133] After the replacement metal gate process is completed, each semiconductor nanosheet 300 is wrapped in a gate dielectric 732 and surrounded by a gate electrode material 733 .

[0134] Method 1000 may continue to operation S1190, where further processing may be performed. Generally speaking, further processes may form various components and regions known in the art. For example, subsequent processes may form contact openings, contact metal, and various contacts / vias / conductors and multilayer interconnect components (e.g., metal layers and interlayer dielectrics) above substrate 202, which are configured to connect various components to form a functional circuit, and this functional circuit may include one or more multi-gate elements. In this example, the multilayer interconnect components may include vertical interconnect components such as vias or contacts and horizontal interconnect components such as metal lines. The various interconnect components may be made of various conductive materials, including copper, tungsten and / or silicide. In one example, a copper-related multilayer interconnect structure is formed using a damascene and / or dual damascene process. In addition, additional process steps may be performed before, during, and after method 1000, and some of the above-mentioned process steps may be replaced or eliminated according to various embodiments of method 1000.

[0135] Method 1000 may produce a device 100 having certain characteristics. For example, Figure 30 , which is a schematic diagram showing the channel region of the fin 220 and the gate 722 . Figure 30 yes Figure 28 A magnified view of a portion of the .

[0136] In some embodiments, this method provides nanosheets with reduced height differences by reducing or not etching the top or bottom surfaces of the nanosheets during processing. For example, the channels of the uppermost nanosheet 303 have a lowermost surface (or bottom surface) 312 with reduced height differences.

[0137] For example, Figure 30As shown, the uppermost surface 311 of the mesa portion 228 defines a lateral plane 3110 perpendicular to a vertical Z-direction. The lower portion 729 of the gate structure 722 is located between the mesa portion 228 and the uppermost semiconductor nanosheet channel 303 of the fin structure 220. The uppermost semiconductor nanosheet channel 303 has a lowermost or bottom surface 312. The lowermost or bottom surface 312 has a highest point at a maximum vertical distance D1 from the lateral plane 3110 and a lowest point at a minimum vertical distance D2 from the lateral plane 3110. The difference D3 between the maximum vertical distance D1 and the shortest vertical distance D2 is less than 3 nanometers. For example, the difference D3 can be zero, or can be at least 0.05 nanometers, e.g., at least 0.1, at least 0.2, at least 0.3, at least 0.4, at least 0.5, at least 0.6, at least 0.7, at least 0.8, at least 0.9, at least 1, at least 1.1, at least 1.2, at least 1.3, at least 1.4, at least 1.5, at least 1.6, at least 1.7, at least 1.8, at least 1.9, at least 2.0, at least 2.1, at least 2.2, at least 2.3, at least 2.4, at least 2.5, at least 2.6, at least 2.7, at least 2.8, or at least 2.9 nanometers. The difference D3 can be less than 3 nanometers, for example, less than 2.9, less than 2.8, less than 2.7, less than 2.6, less than 2.5, less than 2.4, less than 2.3, less than 2.2, less than 2.1, less than 2.0, less than 1.9, less than 1.8, less than 1.7, less than 1.6, less than 1.5, less than 1.4, less than 1.3, less than 1.2, less than 1.1, less than 1.0, less than 0.9, less than 0.8, less than 0.7, less than 0.6, less than 0.5, less than 0.4, less than 0.3, less than 0.2, or less than 0.1 nanometers.

[0138] In some embodiments, each uppermost surface 311 is planar, and each lowermost surface 312 is planar.

[0139] In some embodiments, each semiconductor nanosheet channel 300 has a vertical thickness or height T1 of 3 to 8 nanometers from the uppermost surface 311 to the lowermost surface 312. For example, each vertical thickness T1 can be at least 3.0, such as at least 3.5, at least 4, at least 4.5, at least 5, at least 5.5, at least 6, at least 6.5, at least 7, or at least 7.5 nanometers. Furthermore, each vertical thickness T1 can be no more than 8.0 nanometers, such as no more than 7.5 nanometers, no more than 7 nanometers, no more than 6.5 nanometers, no more than 6 nanometers, no more than 5.5 nanometers, no more than 5 nanometers, no more than 4.5 nanometers, no more than 4 nanometers, no more than 3.5 nanometers, or no more than 3 nanometers.

[0140] exist Figure 2-Figure 30In an embodiment, the stress applied by the treated interposer material is less than the stress applied if the interposer material 420 fills the volume between each pair of adjacent nanosheets 300. The nanosheets are separated by a vertical distance or height H1. Accordingly, when the epitaxial layer 214 is removed, the gaps 350 have the same vertical distance or height H1. Adding the barrier liner 410 reduces the height of the gaps 350 to a reduced height H2, as shown in FIG. Figure 13 As shown. Therefore, in operation S1100, the amount of interposer material 420 added to fill gap 350 is limited by the reduced height H2. In other words, the volume of interposer material 420 is limited in the Z direction. As the amount of interposer material 420 decreases, the amount of stress applied by the processed interposer material 420 also decreases.

[0141] exist Figures 31-45 In the embodiment of , the amount of stress applied by the treated intervening material is also less than the amount of stress that would be applied if the intervening material 420 filled the volume between each pair of adjacent nanosheets 300. Figures 31-45 In the embodiment, the volume is limited in the X direction, rather than Figure 2-Figure 30 Limited in the Z direction.

[0142] Figure 31 is a flow chart of a method 2000 for fabricating a semiconductor device 100 (e.g., a multi-gate device) according to various embodiments. The method 2000 is discussed below with reference to a GAA device having a channel region, which may be referred to as a nanosheet or nanosheet channel and may include various geometries (e.g., cylindrical, bar-shaped) and sizes. However, it should be understood that aspects of the method 2000 may be equally applicable to other types of multi-gate devices without departing from the scope of the present disclosure. In some embodiments, the method 2000 may be used to fabricate a device as described above with reference to FIG. Figure 1 The multi-gate device 100 described above is described. Therefore, one or more aspects discussed above with reference to the multi-gate device 100 may also be applied to the method 2000. It should be understood that the method 2000 includes steps that are part of a complementary metal oxide semiconductor (CMOS) technology process flow and is therefore only briefly described herein. Furthermore, additional steps may be performed before, after, and / or during the method 2000.

[0143] Method 2000 is referenced below Figures 32-45 Provide a description. Figures 32-45 A perspective view of a multi-gate device 100 is provided, and a perspective view of a multi-gate device 100 is provided, along a plane substantially parallel to Figure 1 2 is a schematic cross-sectional view of a multi-gate device 100 taken along a plane defined by an X-axis and a Z-axis in FIG. 2 , illustrating various stages of fabrication according to the method 2000 .

[0144] Furthermore, the semiconductor device 100 may include various other devices and components, such as other types of devices, such as additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, static random access memory (SRAM), and / or other logic circuits, but is simplified for a better understanding of the concepts of the present disclosure. In some embodiments, the semiconductor device 100 includes a plurality of semiconductor devices (e.g., transistors), including PFETs, NFETs, etc., that may be interconnected. In addition, it should be noted that the process steps of the method 2000, including any description provided with reference to the accompanying drawings, are exemplary only and are not intended to be limiting beyond what is specifically recited in the appended claims.

[0145] The method 2000 includes operations S1010 to S1070, as described above. In operation S1070, the portion 220a of the fin 220 adjacent to and not covered by the sacrificial gate structure 222 (eg, the source / drain region) is removed, and Figure 8-9 As shown, in operation S2080, the method 2000 includes removing only a portion of the epitaxial layer 214, that is, a portion of the silicon germanium (SiGe) layer 214, as shown in FIG. Figure 32 shown. Figure 33 yes Figure 32 , which is a cross-sectional view of the central sacrificial gate structure 222 along a single fin 220 and spanning between the shown portions of two adjacent sacrificial gate structures 222.

[0146] Also refer to Figure 32 and Figure 33 After removing a portion of epitaxial layer 214, each epitaxial layer 214 is recessed to a laterally recessed surface 2141. In embodiments where epitaxial layer 214 is formed of silicon germanium (SiGe) and epitaxial layer 216 is formed of silicon (Si), epitaxial layer 214 may be recessed, for example, by an NMOS silicon germanium removal process. In some embodiments, the removal process may use an etchant that etches silicon germanium at a higher etch rate than silicon, such as NH4OH:H2O2:H2O (ammonia peroxide mixture, APM), H2SO4+H2O2 (sulfuric acid peroxide mixture, SPM), or the like. Other suitable processes and materials may be used. This etching process removes a side portion of epitaxial layer 214 to form a recess 350 at each laterally recessed surface.

[0147] As shown, the portion of epitaxial layer 216 adjacent to recess 350 can be etched in the Z direction. For example, the portion of epitaxial layer 216 covered by the non-recessed portion of epitaxial layer 214 has an original vertical thickness T2. The portion of epitaxial layer 216 not covered by the non-recessed portion of epitaxial layer 214, i.e., the portion adjacent to recess 350, has a reduced vertical thickness T3. Each of surfaces 311 and 312 adjacent to recess 350 can have a height difference (thickness) T4. Each of surfaces 311 and 312 forms a shoulder 360 where thickness T3 and thickness T4 intersect.

[0148] The laterally recessed surface 2141 of the epitaxial layer 214 may be separated from the original end portion 313 or 314 by a lateral distance or width W1. Thus, the recess 350 may have a lateral width W1 in the X-direction.

[0149] As shown, the nanosheet 300 (and the epitaxial layer 214 before recessing) has a lateral width W2 in the X-direction.

[0150] In some embodiments, the ratio of width W1 to width W2 is 1:100 to 49:100. For example, the ratio of W1:W2 can be at least 1:100, 2:100, 5:100, 10:100, 15:100, 20:100, 25:100, 30:100, 35:100, 40:100, or 45:100. Furthermore, the ratio of W1:W2 can be no more than 49:100, 45:100, 40:100, 35:100, 30:100, 25:100, 20:100, 15:100, 10:100, 5:100, or 2:100.

[0151] Reference Figure 34 In operation S1110, method 2000 may include performing a process to expand the recessed epitaxial layer 214 and apply stress to the nanosheets 300 (301-303). FIG34 is a cross-sectional view of an X-section at a next manufacturing stage, showing a cross-section of a central sacrificial gate structure 222 along a single fin 220 and spanning between the illustrated portions of two adjacent sacrificial gate structures 222. The aforementioned process may be an oxidation process to convert the epitaxial layer 214 into an oxidized material. As shown, the oxidation process may also oxidize portions of the epitaxial layer 216.

[0152] In other words, the recessed epitaxial layer 214 is transformed into a processed intermediate material 430, such as an oxidized intermediate material 430. As shown, in unrestricted directions, such as lateral directions, the processed intermediate material 430 grows to a greater thickness than the original recessed epitaxial layer 214. In the vertical direction, which is restricted by the recess 350, the increase in thickness in the Z direction is restricted by the epitaxial layer 216 (or nanosheet 300) or the terrace portion 228. Therefore, a compressive stress can be applied to the nanosheet 300 and the terrace portion 228 by the processed intermediate material 430. As a result, the nanosheet 300 and the terrace portion 228 are stretched.

[0153] Specifically, referring to a single segment of treated interposer material 430, the topmost nanosheet 303 is strained in the vertical direction, as indicated by arrow A1, and in the lateral directions, as indicated by arrows A2 and A3. Similarly, the middle nanosheet 302 is strained in the vertical direction, as indicated by arrow A4, and in the lateral directions, as indicated by arrows A5 and A6. Due to the volume expansion of the interposer, additional strain is applied and n-mobility is increased.

[0154] Reference Figure 35 In operation S1120 , the method 2000 may include recessing the processed interposer material 430 . Figure 35 2 is a cross-sectional view of an X-section at a next manufacturing stage, which is a cross-sectional view of a central sacrificial gate structure 222 along a single fin 220 and spanning between the illustrated portions of two adjacent sacrificial gate structures 222 .

[0155] exist Figure 35 In. Figure 35 As shown, the processed interposer material 430 is laterally recessed to a recessed surface 431 to form a recess 450. In some embodiments, the recessed surface 431 is located between the shoulder 360 and the nearest corresponding end 313 or end 314. In other words, the lateral width W3 of the recess 450 is less than the lateral width W1 of the recess 350 (refer to FIG. Figure 33 ).

[0156] Reference Figure 36 , in operation S2130 , the method 2000 may include forming an inner spacer 500 . Figure 36 FIG. 2 is a cross-sectional view of an X-section at a next manufacturing stage, which is a cross-sectional view of the central sacrificial gate structure 222 along a single fin 220 and spanning between the illustrated portions of two adjacent sacrificial gate structures 222 .

[0157] like Figure 36As shown, inner spacers 500 are formed in recesses 450 adjacent to the remaining processed interposer material 430. In some embodiments, inner spacers 500 can be formed from silicon oxide, silicon nitride, silicon carbide, carbon nitride siliconide, carbon oxysilicide, carbon oxynitride siliconide, and / or other suitable dielectric materials. Inner spacers 500 can be formed by atomic layer deposition (ALD) or any other suitable method. After depositing the material forming inner spacers 500, the material can be trimmed from the ends of nanosheets 300, as shown.

[0158] Figure 37 is a perspective view of the device 100, showing that in operation S1140, the method 2000 further includes forming source / drain features 600. Furthermore, the method 2000 further includes forming an inter-layer dielectric (ILD) material 700 in operation S1150.

[0159] Figure 38 yes Figure 37 , which is a cross-sectional view of the central sacrificial gate structure 222 along a single fin 220 and spanning between the shown portions of two adjacent sacrificial gate structures 222.

[0160] Also refer to Figure 37 and Figure 38 The source / drain features 600 are formed above the fins 220 and between the inner spacers 500. The source / drain features 600 can be epitaxially grown. For an n-channel FET, the epitaxial material can include one or more layers of Si, SiP, SiC, and SiCP, or for a p-channel FET, the epitaxial material can include Si, SiGe, or Ge. For a p-channel FET, the source / drain can also include boron (B). The source / drain epitaxial layers can be formed using epitaxial growth methods such as CVD, ALD, or molecular beam epitaxy (MBE).

[0161] In addition, an interlayer dielectric (ILD) material 700 is formed over the source / drain features 600. As shown in the figure, before forming the interlayer dielectric (ILD) material 700, an etch stop layer 710 may be formed over the source / drain features 600.

[0162] Reference Figure 39 In operation S1160 , the method 2000 further includes removing the sacrificial gate structure 222 to form a gate cavity 712 . Figure 40 yes Figure 39, which is a cross-sectional view of a central gate cavity 712 along a single fin 220 and spanning between the shown portions of two adjacent gate cavities 712. As shown, gate sidewall spacers 230g define the gate cavity 712.

[0163] Reference Figure 41 In operation S1170 , the method 2000 further includes removing the treated interposer material 430 and the remaining portion of the barrier liner 410 . Figure 42 yes Figure 41 , which is a cross-sectional view of the X-section of the manufacturing stage of , which is a cross-sectional view along a single fin 220 and spanning the central gate cavity 712 between the shown portions of two adjacent gate cavities 712.

[0164] Also refer to Figure 41-42 After removing the processed interposer material 430 and the barrier liner 410 , the gate cavity 712 extends downward and surrounds the nanosheet 300 and is bounded by the inner spacer 500 in the X direction.

[0165] 43 , in operation S1180 , the method 2000 further includes forming a gate 722 in the gate cavity 712 . Figure 44 yes Figure 43 , which is a cross-sectional view of an X-section of the manufacturing stage of , which is a cross-sectional view along a single fin 220 and spanning a central gate 722 between the shown portions of the two gates 722.

[0166] Also refer to Figure 43-44 , the gate 722 can be formed according to a replacement metal gate process. In some embodiments, the replacement metal gate process includes forming an interface layer 731 on the uppermost surface 311 and the lowermost surface 312. The interface layer 731 may include a silicon monoxide (SiO2) layer. Alternatively, the interface layer 731 may selectively include HfSiO or SiON. The interface layer 731 can be formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), thermal oxidation, wet oxidation, radical oxidation (RadOx), or a combination of the foregoing. In some embodiments, the interface layer 731 is selectively formed on the semiconductor material of the nanosheet 300 and the platform portion 228, and is not formed on the internal spacer 500.

[0167] In some embodiments, the replacement metal gate process includes forming a dielectric layer 732 over the interface layer 731. According to some embodiments, the gate dielectric layer 732 includes multiple layers of silicon oxide, silicon nitride, or a combination thereof. In some embodiments, the gate dielectric layer 732 is a high-k dielectric material, and in these embodiments, the gate dielectric layer 732 may have a k value greater than about 7.0 and may include metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The gate dielectric layer 732 may be formed by molecular beam deposition (MBD), ALD, CVD, PECVD, metal organic CVD (MOCVD), PVD, thermal oxidation, combinations thereof, or other suitable techniques.

[0168] In some embodiments, a gate dielectric layer 732 is formed on the interfacial layer 731 of semiconductor material covering the nanosheets 300 and the mesa portion 228 , as well as on the inner spacers 500 and shallow trench isolation (STI) features.

[0169] In some embodiments, the replacement metal gate process includes forming a gate electrode material 733 over the gate dielectric layer 732 to fill the gate cavity 712. The gate electrode material 733 is deposited on the gate dielectric layer 732 and fills the remaining portion of the gate cavity 712. The gate electrode material 733 can be a metal-containing material such as TiN, TaN, TaC, Co, Ru, Al, combinations thereof, or multiple layers thereof. For example, although a single layer of gate electrode material is shown, any number of work function regulating layers can be deposited.

[0170] After the replacement metal gate process is completed, each semiconductor nanosheet 300 is wrapped in a gate dielectric 732 and surrounded by a gate electrode material 733 .

[0171] Method 2000 may continue to operation S1190, where further processing may be performed. Generally speaking, further processing may form various components and regions known in the art. For example, subsequent processing may form contact openings, contact metal, and various contacts / vias / lines and multilayer interconnect components (e.g., metal layers and interlayer dielectrics) above substrate 202, which are configured to connect various components to form a functional circuit, and this functional circuit may include one or more multi-gate elements. In this example, the multilayer interconnect components may include vertical interconnects such as vias or contacts and horizontal interconnect components such as metal lines. The various interconnect components may be made of various conductive materials, including copper, tungsten and / or silicide. In one example, a copper-related multilayer interconnect structure is formed using a damascene and / or dual damascene process. In addition, additional process steps may be performed before, during, and after method 2000, and some of the above-mentioned process steps may be replaced or eliminated according to various embodiments of method 2000.

[0172] Method 2000 can produce a device 100 having certain characteristics. For example, referring to Figure 45 , which is a schematic diagram showing the channel region of the fin 220 and the gate 722 . Figure 45 yes Figure 44 A magnified view of a portion of the .

[0173] In some embodiments, this method provides nanosheets with reduced height differences by reducing or not etching the top or bottom surfaces of the nanosheets during processing. For example, the channels of the uppermost nanosheet 303 have a lowermost surface (or bottom surface) 312 with reduced height differences.

[0174] For example, Figure 45As shown, the uppermost surface 311 of the platform portion 228 at ends 313 and 314 defines a side plane 3110 perpendicular to a vertical Z-direction. The lower portion 729 of the gate structure 722 is located between the platform portion 228 and the uppermost semiconductor nanosheet channel 303 of the fin structure 220. The uppermost semiconductor nanosheet channel 303 has a lowermost or bottom surface 312 having a highest point at a maximum vertical distance D1 from the side plane 3110 and a lowest point at a minimum vertical distance D2 from the side plane 3110. The difference D3 between the maximum vertical distance D1 and the shortest vertical distance D2 is less than 3 nanometers. For example, the difference D3 can be zero, or can be at least 0.05 nanometers, e.g., at least 0.1, at least 0.2, at least 0.3, at least 0.4, at least 0.5, at least 0.6, at least 0.7, at least 0.8, at least 0.9, at least 1, at least 1.1, at least 1.2, at least 1.3, at least 1.4, at least 1.5, at least 1.6, at least 1.7, at least 1.8, at least 1.9, at least 2.0, at least 2.1, at least 2.2, at least 2.3, at least 2.4, at least 2.5, at least 2.6, at least 2.7, at least 2.8, or at least 2.9 nanometers. The difference D3 can be less than 3 nanometers, for example, less than 2.9, less than 2.8, less than 2.7, less than 2.6, less than 2.5, less than 2.4, less than 2.3, less than 2.2, less than 2.1, less than 2.0, less than 1.9, less than 1.8, less than 1.7, less than 1.6, less than 1.5, less than 1.4, less than 1.3, less than 1.2, less than 1.1, less than 1.0, less than 0.9, less than 0.8, less than 0.7, less than 0.6, less than 0.5, less than 0.4, less than 0.3, less than 0.2, or less than 0.1 nanometers.

[0175] In some embodiments, each semiconductor nanosheet channel 300 has outer terminal regions adjacent to end 313 and end 314, having a vertical thickness or height T1 of 3 to 8 nanometers from uppermost surface 311 to lowermost surface 312. For example, each vertical thickness T1 can be at least 3.0, such as at least 3.5, at least 4, at least 4.5, at least 5, at least 5.5, at least 6, at least 6.5, at least 7, or at least 7.5 nanometers. Furthermore, each vertical thickness T1 can be no more than 8.0 nanometers, such as no more than 7.5 nanometers, no more than 7 nanometers, no more than 6.5 nanometers, no more than 6 nanometers, no more than 5.5 nanometers, no more than 5 nanometers, no more than 4.5 nanometers, no more than 4 nanometers, no more than 3.5 nanometers, or no more than 3 nanometers.

[0176] As further shown, each semiconductor nanosheet channel 300 has an inner region from shoulder 360 to shoulder 360 having a vertical thickness or height T5 that increases from uppermost surface 311 to lowermost surface 312. Vertical thickness or height T5 can be more than 6 nanometers greater than vertical thickness or height T1. That is, each shoulder 360 can have a vertical length of 3 nanometers. For example, each vertical thickness T5 can be at least 0.5 nanometer greater than vertical thickness T1, such as at least 1, at least 1.5, at least 2, or at least 2.5, at least 3, at least 3.5, at least 4, at least 4.5, at least 5, or at least 5.5 nanometers greater than vertical thickness T1. Furthermore, each vertical thickness T5 can be no more than 6 nanometers, such as no more than 5.5, 5, 4.5, 4, 3.5, 3, 2.5, 2, 1.5, 1, or 0.5 nanometers greater than vertical thickness T1.

[0177] like Figure 45 As shown, each shoulder 360, i.e., the interface between the end region and the central region, is located at a lateral distance or width W5 from the end 313 in the X-direction. In some embodiments, width W5 is between six and twelve nanometers. For example, width W5 can be at least 6 nanometers, such as at least 6.5, at least 7, at least 7.5, at least 8, at least 8.5, at least 9, at least 9.5, at least 10, at least 10.5, at least 11, or at least 11.5 nanometers. Furthermore, width W5 can be at most 12 nanometers, such as at most 11.5, at most 11, at most 10.5, at most 10, at most 9.5, at most 9, at most 8.5, at most 8, at most 7.5, at most 7, or at most 6.5 nanometers.

[0178] exist Figures 31-45 In some embodiments, the stress applied by the treated intervening material is less than the stress applied if the intervening material 420 fills the volume between each pair of adjacent nanosheets 300. Figure 33 As shown, nanosheet 300 has a lateral width W2, and the lateral width of the recessed epitaxial layer 214 is equal to the difference between width W2 and twice the recess width W1 (= W2 - 2(W1)). Therefore, the volume of each recessed epitaxial layer 214 is smaller than the original volume of each epitaxial layer 214. Specifically, the lateral width of each recessed epitaxial layer 214 is smaller than the original width of each recessed epitaxial layer 214. In other words, the volume of the second layer 216 converted into the interposer material 430 is limited in the X direction. As the amount of epitaxial layer 216 is reduced, the stress exerted by the processed epitaxial layer 216 is also reduced to a desired level.

[0179] In the embodiments herein, negative effects caused by the presence of germanium in epitaxial layer 214 can be avoided. Specifically, when germanium is present in epitaxial layer 214 after forming source / drain features 600, thermal treatment can cause germanium to diffuse from epitaxial layer 214 into phosphorus-doped silicon n-type source / drain features 600, and can enhance the diffusion of phosphorus from source / drain features 600 into epitaxial layer 214. Consequently, n-type mobility may be reduced. To avoid such negative effects, in some embodiments, epitaxial layer 214 is removed and replaced with interposer 430. Interposer 430 can block such diffusion.

[0180] Therefore, one embodiment of the present disclosure describes a method for manufacturing a semiconductor device, comprising forming a fin, the fin comprising a first material located above a second material; forming a sacrificial gate above the fin, wherein a channel region of the fin comprising the first material and the second material is directly below the sacrificial gate and between two non-channel regions of the fin comprising the first material and the second material; removing the non-channel region of the fin; performing a process to replace the second material in the channel region of the fin with a third material; forming a source / drain component in the non-channel region; removing the sacrificial gate; removing the third material; and forming a gate above the fin.

[0181] In some embodiments, the method further includes straining the first material and the third material together to form a strained first material.

[0182] In some embodiments of the method, performing the process of replacing the second material with the third material includes: removing the second material; forming a third material precursor below the first material; and processing the third material precursor to form the third material.

[0183] In some embodiments of the method, replacing the second material with the third material includes: removing the second material to form a void below a bottom surface of the first material; forming a liner on the bottom surface; and forming the third material below the liner.

[0184] In some embodiments of the method, performing the process of replacing the second material with the third material includes: removing a portion of the second material, wherein a remaining portion of the second material remains beneath the first material; and converting the remaining portion of the second material into the third material.

[0185] In some embodiments of this method, after removing the portion of the second material, a covered surface portion of the first material is covered by the remaining portion of the second material, and an uncovered surface portion of the first material is uncovered by the remaining portion of the second material; converting the remaining portion of the second material to the third material includes performing an oxidation process; the oxidation process oxidizes the uncovered surface portion of the first material to form a first oxide material. The method further includes removing at least a portion of the first oxide material and at least a portion of the third material before forming the source / drain features in the non-channel region.

[0186] In some embodiments of the method, the second material is silicon germanium (SiGe) and wherein the third material does not contain germanium.

[0187] In some embodiments of this method, the fin extends along a first direction; after removing the non-channel region of the fin, the second material contacts the first material along an interface having a first length in the first direction; the process of replacing the second material with a third material includes removing at least a portion of the second material; after the process of replacing the second material with the third material, the third material in the channel region has a third width in the first direction; and the third width is less than the first length.

[0188] In some embodiments of this method, the fin extends along a first direction; the first material is located above the second material in a second direction perpendicular to the first direction; before performing the process of replacing the second material with the third material, the second material in the channel region has a second vertical thickness in the second direction; after performing the process of replacing the second material with the third material, the third material in the channel region has a third vertical thickness in the second direction; and the third vertical thickness is less than the second vertical thickness.

[0189] In another embodiment, a method for manufacturing a semiconductor device includes forming a first material layer above a second material layer; etching the first material layer and the second material layer to form a raised structure, the raised structure including a remaining portion of the first material layer and a remaining portion of the second material layer, wherein the remaining portion of the second material layer has a second volume; replacing or converting the second material layer to form a third material layer below the first material layer, wherein the third material layer has a third volume smaller than the second volume, wherein the third material layer strains the first material layer to form a strained first material layer; removing the third material layer; and forming a fourth material layer below the strained first material layer.

[0190] In some embodiments of this method, the protruding structure extends vertically in the second direction; the remaining portion of the second material layer has a second vertical height in the second direction; before removing the third material layer, the third material layer has a third vertical height in the second direction; and the third vertical height is less than the second vertical height.

[0191] In some embodiments of this method, the raised structure extends laterally in the first direction; the remaining portion of the second material layer has a second width in the first direction; and before removing the third material layer, the third material layer has a third width in the first direction, and the third width is smaller than the second width.

[0192] In some embodiments, the method includes removing the second material layer to form a void below the first material layer; forming a third material precursor in the void below the first material layer; and processing the third material precursor to form a third material layer.

[0193] In some embodiments, the method includes removing a portion of the second material layer, wherein the remaining portion of the second material layer remains below the first material layer; and converting the remaining portion of the second material layer into a third material layer.

[0194] In another embodiment, a semiconductor device includes a first source / drain component separated from a second source / drain component in a first direction; a fin structure including a semiconductor nanosheet channel separated from a mesa portion in a second direction, wherein an upper surface of the mesa portion defines a side plane perpendicular to the second direction; a gate structure located above the fin structure, wherein a lower portion of the gate structure is located between the mesa portion of the fin structure and the semiconductor nanosheet channel; a first inner spacer separating the first source / drain component from the lower portion; and a second inner spacer separating the second source / drain component from the lower portion; wherein the semiconductor nanosheet channel has a bottom surface adjacent to the first inner spacer, the lower portion of the gate structure, and the second inner spacer, wherein the bottom surface has a highest point at a maximum vertical distance from the aforementioned side plane and a lowest point at a shortest vertical distance from the aforementioned side plane; wherein a difference between the maximum vertical distance and the shortest vertical distance is less than 3 nanometers.

[0195] In some embodiments of the semiconductor device, the difference between the maximum vertical distance and the shortest vertical distance is less than one nanometer.

[0196] In some embodiments of the semiconductor device, the semiconductor nanosheet channel has a central region, a first terminal region between the central region and a first inner spacer, and a second terminal region between the central region and a second inner spacer, wherein a vertical thickness of the central region is greater than a vertical thickness of the first terminal region and greater than a vertical thickness of the second terminal region.

[0197] In some embodiments of the semiconductor device, a vertical thickness of the central region is 0.1 to 6 nanometers greater than a vertical thickness of the first terminal region, and 0.1 to 6 nanometers greater than a vertical thickness of the second terminal region.

[0198] In some embodiments of the semiconductor device, the semiconductor nanosheet channel has a central region, a first terminal region between the central region and a first inner spacer, and a second terminal region between the central region and the second inner spacer; a first interface located between the central region and the first terminal region, and the first interface is located at a first distance from the first source / drain component in a first direction; the first distance is six nanometers to twelve nanometers; a second interface located between the central region and the second terminal region, and the second interface is located at a second distance from the second source / drain component in the first direction; the second distance is six nanometers to twelve nanometers.

[0199] In some embodiments of the semiconductor device, the fin structure includes at least two semiconductor nanosheet channels; the gate structure includes at least two sub-chip portions, wherein each sub-chip portion is located directly below a corresponding semiconductor nanosheet channel; and the vertical thickness of each semiconductor nanosheet channel is 3 nanometers to 8 nanometers.

[0200] The above summarizes the components of several embodiments so that those skilled in the art can better understand the viewpoints of the embodiments of the present invention. Those skilled in the art should understand that they can easily design or modify other processes and structures based on the embodiments of the present invention to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of the present invention, and they can make various changes, substitutions and replacements without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be as defined by the appended claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: forming a fin comprising a first material overlying a second material; forming a sacrificial gate over the fin, wherein a channel region of the fin comprising the first material and the second material is directly below the sacrificial gate and between two non-channel regions of the fin comprising the first material and the second material; removing the plurality of non-channel regions of the fin; performing a process to replace the second material in the channel region of the fin with a third material; forming source / drain features in a plurality of the non-channel regions; removing the sacrificial gate; removing the third material; as well as A gate is formed above the fin. 2 . The method for manufacturing a semiconductor device as claimed in claim 1 , further comprising straining the first material and the third material together to form a strained first material.

3. The method for manufacturing a semiconductor device according to claim 1 , wherein the process of replacing the second material with the third material comprises: removing the second material; forming a third material precursor below the first material; and The third material precursor is processed to form the third material.

4. The method for manufacturing a semiconductor device according to claim 1 , wherein the process of replacing the second material with the third material comprises: removing the second material to form a void below a bottom surface of the first material; forming a lining layer on the bottom surface; as well as The third material is formed under the liner.

5. The method for manufacturing a semiconductor device according to claim 1 , wherein the process of replacing the second material with the third material comprises: removing a portion of the second material, wherein a remaining portion of the second material remains beneath the first material; and The remaining portion of the second material is converted to the third material. 6 . The method for fabricating a semiconductor device as claimed in claim 1 , wherein the second material is silicon germanium, and wherein the third material does not contain germanium.

7. The method for manufacturing a semiconductor device according to claim 1, wherein: The fin extends along a first direction; After removing the plurality of non-channel regions of the fin, the second material contacts the first material along an interface having a first length in a first direction; Performing the process of replacing the second material with the third material includes removing at least a portion of the second material; After performing the process of replacing the second material with the third material, the third material in the channel region has a third width in the first direction; and The third width is smaller than the first length.

8. The method for manufacturing a semiconductor device according to claim 1, wherein: The fin extends along a first direction; The first material is located above the second material in a second direction perpendicular to the first direction; Before performing the process of replacing the second material with the third material, the second material in the channel region has a second vertical thickness in the second direction; After performing the process of replacing the second material with the third material, the third material in the channel region has a third vertical thickness in the second direction; and The third vertical thickness is smaller than the second vertical thickness.

9. A method for manufacturing a semiconductor device, characterized in that: forming a first material layer on a second material layer; etching the first material layer and the second material layer to form a protruding structure, the protruding structure including a remaining portion of the first material layer and a remaining portion of the second material layer, wherein the remaining portion of the second material layer has a second volume; replacing or converting the second material layer to form a third material layer below the first material layer, wherein the third material layer has a third volume smaller than the second volume, wherein the third material layer strains the first material layer to form a strained first material layer; removing the third material layer; and A fourth material layer is formed below the strained first material layer.

10. A semiconductor device, characterized in that: a first source / drain component, located away from a second source / drain component in a first direction; A fin structure comprising a semiconductor nanosheet channel, the semiconductor nanosheet channel being away from a mesa portion in a second direction perpendicular to the first direction, wherein an upper surface of the mesa portion defines a side plane perpendicular to the second direction; a gate structure disposed above the fin structure, wherein a lower portion of the gate structure is disposed between the mesa portion of the fin structure and the semiconductor nanosheet channel; a first inner spacer separating the first source / drain feature from the lower portion of the chip; and a second inner spacer separating the second source / drain feature from the lower portion of the chip; wherein the semiconductor nanosheet channel has a bottom surface adjacent to the first inner spacer, the lower portion of the gate structure, and the second inner spacer, wherein the bottom surface has a highest point at a maximum vertical distance from the side plane and a lowest point at a shortest vertical distance from the side plane; and A difference between the maximum vertical distance and the shortest vertical distance is less than 3 nanometers.

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